Low-power-consumption and low-jitter digital injection-locked phase-locked loop

Abstract

The invention belongs to the technical field of digital-analog hybrid integrated circuit design, and particularly discloses a low-power-consumption and low-jitter digital injection-locked phase-locked loop which comprises an injection pulse path, a pulse width calibration path, a pulse time calibration path and a double-injection numerically-controlled oscillator. The low power consumption of the digital injection locked phase-locked loop is realized through the synergistic effect of the pulse width calibration path, the pulse time calibration path and the double-injection numerically-controlled oscillator; the injection pulse path, the pulse width calibration path and the pulse time calibration path process reference signals, the time sequence and the pulse width of injection pulses are adjusted under the change of the technology, the voltage and the temperature through the self-calibration technology, the injection pulses are injected into the double-injection-number control oscillator, and the minimum jitter is achieved while the maximum injection intensity is obtained.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of digital-analog hybrid integrated circuit design, and particularly relates to a low-power and low-jitter digital injection-locked phase-locked loop. BACKGROUND

[0002] As a key module in a wireless biosensor system, a phase-locked loop provides a local oscillator signal for a wireless and wired communication electronic system in the sensor, and its performance directly affects the power consumption, frequency and communication quality of the entire sensor system. At present, wireless biosensors mainly use an energy harvesting system for power supply, which can effectively reduce the battery replacement frequency and achieve large-scale deployment. However, the energy harvesting system faces two challenges: low power supply voltage and insufficient energy conversion efficiency, which puts strict power requirements on the electronic system. In addition, with the continuous improvement of the data transmission rate of biosensors, the jitter requirement of the phase-locked loop also becomes more stringent.

[0003] In order to solve these problems, various low-power and low-jitter phase-locked loops have been proposed, such as all-digital phase-locked loops, sub-sampling phase-locked loops and injection-locked phase-locked loops. However, in the all-digital phase-locked loop, the quantization noise generated by the time-to-digital converter with limited resolution reduces the in-band phase noise of the all-digital phase-locked loop, while the traditional sub-sampling phase-locked loop and injection-locked phase-locked loop are often based on analog architecture, which has high power consumption, large area and poor anti-interference ability, and is difficult to meet the requirements of wearable health management applications. SUMMARY

[0004] In view of the problems existing in the prior art, the application provides a low-power and low-jitter digital injection-locked phase-locked loop, which comprises: an injection pulse path, an input end of which is connected to a reference signal, and an output end of which outputs an injection pulse signal; a pulse width calibration path, which comprises a first phase detector and a successive approximation register; an input end of the first phase detector is connected to the injection pulse signal and a clock signal, and an output end of the first phase detector is connected to an input end of the successive approximation register; an output end of the successive approximation register outputs a second control signal to the injection pulse path, for regulating the pulse width of the injection pulse signal; a pulse time calibration path, which comprises a second phase detector and an accumulator; an input end of the second phase detector is connected to the injection pulse signal and the clock signal, and an output end of the second phase detector is connected to an input end of the accumulator; an output end of the accumulator outputs a first control signal to the injection pulse path, for regulating the injection time of the injection pulse signal; The double injection digitally controlled oscillator comprises a first injection end and a second injection end; the first injection end is connected to the positive end of the injection pulse signal, and the second injection end is connected to the negative end of the injection pulse signal; and the output end of the double injection digitally controlled oscillator outputs a clock signal. The time and pulse width of the injection pulse signal are regulated through the pulse time calibration path and the pulse width calibration path respectively, so as to realize low jitter of the digital injection locking phase-locked loop; and the low power consumption of the digital injection locking phase-locked loop is realized through the synergistic effect of the pulse width calibration path, the pulse time calibration path and the double injection digitally controlled oscillator.

[0005] Further, the injection pulse path comprises a first controllable delay line, a second controllable delay line and an AND gate. The first input end of the first controllable delay line is connected to a reference signal, the second input end of the first controllable delay line is connected to the first control signal, the output end of the first controllable delay line is connected to the second input end of the AND gate and the first input end of the second controllable delay line. The second input end of the second controllable delay line is connected to the second control signal, and the output end of the second controllable delay line is connected to the first input end of the AND gate. The output end of the AND gate is connected to the first injection end and the second injection end of the double injection digitally controlled oscillator, and an injection pulse signal is output.

[0006] Further, the digital injection locking phase-locked loop further comprises a frequency-locked loop, the first input end of the frequency-locked loop is connected to a reference signal, the second input end of the frequency-locked loop is connected to a frequency control signal, and the output end of the frequency-locked loop is connected to the input end of the double injection digitally controlled oscillator.

[0007] Further, the digital injection locking phase-locked loop further comprises a time-to-digital converter, a digital filter, a buffer and a frequency divider. The first input end of the time-to-digital converter is connected to a reference signal, the second input end of the time-to-digital converter is connected to the output end of the frequency divider, the output end of the time-to-digital converter is connected to the input end of the digital filter, the output end of the digital filter is connected to the input end of the double injection digitally controlled oscillator, the output end of the double injection digitally controlled oscillator is connected to the input end of the buffer, and the output end of the buffer is connected to the input end of the frequency divider.

[0008] Further, the double injection digitally controlled oscillator further comprises a first delay unit, a second delay unit, a third delay unit, a fourth delay unit, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor. The first output end of the first delay unit is connected with the second input end of the second delay unit and the first input end of the third delay unit, and the second output end of the first delay unit is connected with the third input end of the second delay unit and the fourth input end of the third delay unit; the first output end of the second delay unit is connected with the second input end of the third delay unit and the first input end of the fourth delay unit, and the second output end of the second delay unit is connected with the third input end of the third delay unit and the fourth input end of the fourth delay unit; the first output end of the third delay unit is connected with the second input end of the fourth delay unit, and the second output end of the third delay unit is connected with the third input end of the fourth delay unit; the first output end of the fourth delay unit is connected with the first input end of the first delay unit, the third input end of the first delay unit and the fourth input end of the second delay unit, and is the in-phase signal output end of the double-injection digitally controlled oscillator; and the second output end of the fourth delay unit is connected with the second input end of the first delay unit, the fourth input end of the first delay unit and the first input end of the second delay unit, and is the anti-phase signal output end of the double-injection digitally controlled oscillator. The drain of the first NMOS transistor is connected with the first output end of the first delay unit, the source thereof is connected with the second output end of the first delay unit, and the gate thereof is connected with the first injection end; the drain of the second NMOS transistor is connected with the first output end of the second delay unit, the source thereof is connected with the second output end of the second delay unit, and the gate thereof is connected with the second injection end; the drain of the third NMOS transistor is connected with the first output end of the third delay unit, the source thereof is connected with the second output end of the third delay unit, and the gate thereof is connected with the first injection end; the drain of the fourth NMOS transistor is connected with the first output end of the fourth delay unit, the source thereof is connected with the second output end of the fourth delay unit, and the gate thereof is connected with the second injection end; and the fifth input ends of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit are connected with the input end of the double-injection digitally controlled oscillator.

[0009] Further, the first delay unit, the second delay unit, the third delay unit and the fourth delay unit each comprise a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a thirteenth NMOS transistor. The source of the first PMOS transistor, the source of the second PMOS transistor, the source of the third PMOS transistor and the source of the fourth PMOS transistor are all connected to a power supply voltage; the drain of the first PMOS transistor is connected to the gate of the third PMOS transistor, and the gate of the first PMOS transistor is the first input end of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; the drain of the fourth PMOS transistor is connected to the gate of the second PMOS transistor, and the gate of the fourth PMOS transistor is the fourth input end of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; the drain of the second PMOS transistor is connected to the drain of the fifth NMOS transistor, and is the first output end of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; the drain of the third PMOS transistor is connected to the drain of the sixth NMOS transistor, and is the second output end of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; The source of the fifth NMOS transistor and the source of the sixth NMOS transistor are both connected to the drain of the thirteenth NMOS transistor, the source of the thirteenth NMOS transistor is grounded, and the gate of the thirteenth NMOS transistor is the fifth input end of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; the gate of the fifth NMOS transistor is the second input end of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; and the gate of the sixth NMOS transistor is the third input end of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit.

[0010] Further, the first phase detector and the second phase detector each include a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor and a twelfth NMOS transistor. The source of the fifth PMOS transistor, the source of the sixth PMOS transistor, the source of the eighth PMOS transistor and the source of the ninth PMOS transistor are all connected with a power supply voltage; the gate of the fifth PMOS transistor, the gate of the seventh PMOS transistor, the gate of the ninth PMOS transistor, the gate of the tenth PMOS transistor, the gate of the eighth NMOS transistor and the gate of the eleventh NMOS transistor are all signal injection ends of the first phase detector and the second phase detector; The drain of the fifth PMOS transistor and the drain of the ninth PMOS transistor are all output ends of the first phase detector and the second phase detector; the drain of the fifth PMOS transistor is connected with the drain of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the drain of the tenth PMOS transistor and the gate of the tenth NMOS transistor; the drain of the ninth PMOS transistor is connected with the source of the seventh PMOS transistor, the gate of the sixth PMOS transistor, the source of the tenth PMOS transistor and the gate of the seventh NMOS transistor; the drain of the seventh NMOS transistor is connected with the drain of the sixth PMOS transistor, and the source of the seventh NMOS transistor is connected with the drain of the eighth NMOS transistor; the source of the eighth NMOS transistor is connected with the drain of the ninth NMOS transistor; the drain of the tenth NMOS transistor is connected with the drain of the eighth PMOS transistor, and the source of the tenth NMOS transistor is connected with the drain of the eleventh NMOS transistor; the source of the eleventh NMOS transistor is connected with the drain of the twelfth NMOS transistor; the gate of the ninth NMOS transistor is a first input end of the first phase detector and the second phase detector; the gate of the twelfth NMOS transistor is a second input end of the first phase detector and the second phase detector; the source of the ninth NMOS transistor and the source of the twelfth NMOS transistor are both grounded.

[0011] Compared with the prior art, the present application has the following beneficial technical effects: Firstly, the present application realizes stronger robustness, reduces power consumption and area by using a digital injection locking architecture, and can meet the wearable health management application field.

[0012] Secondly, the present application adopts a digital background self-calibration technology in the pulse width calibration path and the pulse time calibration path, and realizes low jitter under process, voltage and temperature changes.

[0013] Thirdly, the digital control injection oscillator proposed in the present application adopts a four-stage cascaded pseudo-differential structure, and the oscillation frequency is improved by using a feedforward technology, and the power consumption is significantly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it should be understood that the drawings described below only relate to some embodiments of the present disclosure, rather than limit the present disclosure, wherein: Figure 1 is a system block diagram of a low-power and low-jitter digital injection-locked phase-locked loop proposed by the present application; Figure 2 is a structural diagram of a double-injection digital controlled oscillator in the digital injection-locked phase-locked loop proposed by the present application; Figure 3 is a schematic diagram of a delay unit in the double-injection digital controlled oscillator proposed by the present application; Figure 4 is a schematic diagram of a phase detector in the pulse width calibration path and the pulse time calibration path proposed by the present application. DETAILED DESCRIPTION

[0015] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application.

[0016] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0017] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship when the product of the present application is usually placed, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" and the like are only used for differentiation in description, and cannot be understood as indicating or implying relative importance.

[0018] In the description of the present application, it is necessary to point out that, unless otherwise explicitly specified and limited, the terms "arrange", "mount", "connect", "connect" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0019] It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0020] As Figures 1 to 4 shown, the present application provides a low-power and low-jitter digital injection locking phase-locked loop, which comprises a frequency-locked loop, a time-to-digital converter, a digital filter, a buffer, a frequency divider, a double injection digital controlled oscillator, an injection pulse path, a pulse width calibration path and a pulse time calibration path: The injection pulse path, the input end of which is connected to the reference signal, outputs the injection pulse signal at the output end; the injection pulse path comprises a first controllable delay line, a second controllable delay line and an AND gate; the first input end of the first controllable delay line is connected to the reference signal, the second input end of the first controllable delay line is connected to the first control signal, the output end of the first controllable delay line is connected to the second input end of the AND gate and the first input end of the second controllable delay line; the second input end of the second controllable delay line is connected to the second control signal, the output end of the second controllable delay line is connected to the first input end of the AND gate; the output end of the AND gate is connected to the first injection end and the second injection end of the double injection digital controlled oscillator, and outputs the injection pulse signal; The pulse width calibration path comprises a first phase detector and a successive approximation register; the input end of the first phase detector is connected to the injection pulse signal and the clock signal, the output end of the first phase detector is connected to the input end of the successive approximation register; the output end of the successive approximation register outputs the second control signal to the injection pulse path, for regulating the pulse width of the injection pulse signal; The pulse time calibration path comprises a second phase detector and an accumulator; the input end of the second phase detector is connected to the injection pulse signal and the clock signal, the output end of the second phase detector is connected to the input end of the accumulator; the output end of the accumulator outputs the first control signal to the injection pulse path, for regulating the injection time of the injection pulse signal.

[0021] The double injection digital controlled oscillator comprises a first injection end and a second injection end; the first injection end is connected to the positive end of the injection pulse signal, and the second injection end is connected to the negative end of the injection pulse signal; the output end of the double injection digital controlled oscillator outputs the clock signal; The time and pulse width of the injection pulse signal are regulated through a pulse time calibration path and a pulse width calibration path respectively, low jitter of the digital injection-locked phase-locked loop is realized, and low power consumption of the digital injection-locked phase-locked loop is realized through the synergistic effect of the pulse width calibration path, the pulse time calibration path and the double-injection digitally controlled oscillator.

[0022] In some embodiments of the application, in the injection pulse path, the first controllable delay line and the second controllable delay line respectively determine the injection time and the pulse width of the injection pulse signal; the first controllable delay line and the second controllable delay line in the injection pulse path are analog circuits sensitive to process, voltage and temperature variations; in addition, the time and width of the injection pulse should be optimized at different division ratios; according to the injection locking theory, when the injection pulse signal is aligned with the zero crossing of the output signal and the pulse width is equal to one quarter of the period of the double-injection digitally controlled oscillator, the maximum injection strength can be obtained to realize the lowest jitter. Therefore, it is crucial for the digital injection-locked phase-locked loop to adjust the delays of the first controllable delay line and the second controllable delay line to obtain the optimal injection pulse signal under all working conditions; in addition, the pulse width calibration path and the pulse time calibration path are used to process the reference signal and inject it into the double-injection digitally controlled oscillator to realize cumulative jitter cancellation.

[0023] Specifically, the first input end of the frequency-locked loop is connected with the reference signal, the second input end is connected with the frequency control signal, and the output end of the frequency-locked loop is connected with the input end VC of the double-injection digitally controlled oscillator. The first input end of the time-to-digital converter is connected with the reference signal, the second input end is connected with the output end of the frequency divider, and the output end of the time-to-digital converter is connected with the input end of the digital filter; the output end of the digital filter is connected with the input end of the double-injection digitally controlled oscillator; the output end of the double-injection digitally controlled oscillator is connected with the input end of the buffer; and the output end of the buffer is connected with the input end VC of the frequency divider.

[0024] In some embodiments of the application, the frequency-locked loop based on frequency control is used to perform fast frequency locking and stop working after frequency locking to reduce power consumption; the input end of the time-to-digital converter is connected with the reference signal and the feedback clock signal, and outputs a phase error digital code for measuring the phase difference between the reference signal and the feedback clock signal and digitizing; the digital filter inputs the phase error digital code and outputs a digital control word for filtering noise; the double-injection digitally controlled oscillator inputs the digital control word and outputs a clock signal for generating a clock signal of the required frequency according to the digital control word; the frequency divider inputs the clock signal and outputs the feedback clock signal for dividing the high-frequency output by N to the vicinity of the reference frequency to form a closed loop.

[0025] As Figure 2As shown, the double-injection digitally controlled oscillator further comprises a first delay unit, a second delay unit, a third delay unit, a fourth delay unit, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3 and a fourth NMOS transistor N4; a first output end of the first delay unit is connected to a second input end of the second delay unit and a first input end of the third delay unit, a second output end of the first delay unit is connected to a third input end of the second delay unit and a fourth input end of the third delay unit; a first output end of the second delay unit is connected to a second input end of the third delay unit and a first input end of the fourth delay unit, a second output end of the second delay unit is connected to a third input end of the third delay unit and a fourth input end of the fourth delay unit; a first output end of the third delay unit is connected to a second input end of the fourth delay unit, a second output end of the third delay unit is connected to a third input end of the fourth delay unit; a first output end of the fourth delay unit is connected to a first input end of the first delay unit, a third input end of the first delay unit and a fourth input end of the second delay unit, and is an in-phase signal output end OUT of the double-injection digitally controlled oscillator P; a second output end of the fourth delay unit is connected to a second input end of the first delay unit, a fourth input end of the first delay unit and a first input end of the second delay unit, and is an anti-phase signal output end OUT of the double-injection digitally controlled oscillator N; a drain of the first NMOS transistor N1 is connected to the first output end of the first delay unit, a source thereof is connected to the second output end of the first delay unit, and a gate thereof is connected to a first injection end; a drain of the second NMOS transistor N2 is connected to the first output end of the second delay unit, a source thereof is connected to the second output end of the second delay unit, and a gate thereof is connected to a second injection end; a drain of the third NMOS transistor N3 is connected to the first output end of the third delay unit, a source thereof is connected to the second output end of the third delay unit, and a gate thereof is connected to the first injection end; a drain of the fourth NMOS transistor N4 is connected to the first output end of the fourth delay unit, a source thereof is connected to the second output end of the fourth delay unit, and a gate thereof is connected to the second injection end, and fifth input ends of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit are connected to an input end VC of the double-injection digitally controlled oscillator.

[0026] In some embodiments of the present application, the double-injection digitally controlled oscillator adopts a four-stage cascaded pseudo-differential structure; a double-injection technology is adopted, and the phase noise of the injection digitally controlled oscillator is further suppressed by multi-phase injection at a differential node; the signal conversion is accelerated by adopting a feedforward technology, and compared with a traditional architecture, the double-injection digitally controlled oscillator reduces power consumption while maintaining the same oscillation frequency; two injection paths avoid extra power consumption caused by continuous high-power injection by precisely controlling the width and time of the injection pulse; the whole system can normally work under a 0.6V power supply voltage, and the power consumption is extremely low.

[0027] As shown in Figure 3 The first delay unit, the second delay unit, the third delay unit and the fourth delay unit each include a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth NMOS transistor N5, a sixth NMOS transistor N6 and a thirteenth NMOS transistor N13; the source of the first PMOS transistor P1, the source of the second PMOS transistor P2, the source of the third PMOS transistor P3 and the source of the fourth PMOS transistor P4 are all connected to a power supply voltage; the drain of the first PMOS transistor P1 is connected to the gate of the third PMOS transistor P3, and the gate of the first PMOS transistor P1 is the first input end VSN of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; the drain of the fourth PMOS transistor P4 is connected to the gate of the second PMOS transistor P2, and the gate of the fourth PMOS transistor P4 is the fourth input end VSP of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; the drain of the second PMOS transistor P2 is connected to the drain of the fifth NMOS transistor N5, and is the first output end VOP of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; the drain of the third PMOS transistor P3 is connected to the drain of the sixth NMOS transistor N6, and is the second output end VON of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; the source of the fifth NMOS transistor N5 and the source of the sixth NMOS transistor N6 are both connected to the drain of the thirteenth NMOS transistor N13, the source of the thirteenth NMOS transistor N13 is grounded, and the gate of the thirteenth NMOS transistor N13 is the fifth input end VC of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; the gate of the fifth NMOS transistor N5 is the second input end VPN of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; and the gate of the sixth NMOS transistor is the third input end VPP of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit.

[0028] As shown in Figure 4As shown, the first phase detector and the second phase detector each comprise a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, and a twelfth NMOS transistor N12; the source of the fifth PMOS transistor P5, the source of the sixth PMOS transistor P6, the source of the eighth PMOS transistor P8, and the source of the ninth PMOS transistor P9 are all connected to a power supply voltage; the gate of the fifth PMOS transistor P5, the gate of the seventh PMOS transistor P7, the gate of the ninth PMOS transistor P9, the gate of the tenth PMOS transistor P10, the gate of the eighth NMOS transistor N8, and the gate of the eleventh NMOS transistor N11 are all signal INJ injection ends of the first phase detector and the second phase detector; the drain of the fifth PMOS transistor P5 and the drain of the ninth PMOS transistor P9 are both output ends of the first phase detector and the second phase detector; the drain of the fifth PMOS transistor P5 is connected to the drain of the seventh PMOS transistor P7, the gate of the eighth PMOS transistor P8, the drain of the tenth PMOS transistor P10, and the gate of the tenth NMOS transistor N10; the drain of the ninth PMOS transistor P9 is connected to the source of the seventh PMOS transistor P7, the gate of the sixth PMOS transistor P6, the source of the tenth PMOS transistor P10, and the gate of the seventh NMOS transistor N7; the drain of the seventh NMOS transistor N7 is connected to the drain of the sixth PMOS transistor P6, and the source of the seventh NMOS transistor N7 is connected to the drain of the eighth NMOS transistor N8; the source of the eighth NMOS transistor N8 is connected to the drain of the ninth NMOS transistor N9; the drain of the tenth NMOS transistor N10 is connected to the drain of the eighth PMOS transistor P8, and the source of the tenth NMOS transistor N10 is connected to the drain of the eleventh NMOS transistor N11; the source of the eleventh NMOS transistor N11 is connected to the drain of the twelfth NMOS transistor N12; the gate of the ninth NMOS transistor N9 is a first input end DCON of the first phase detector and the second phase detector; the gate of the twelfth NMOS transistor N12 is a second input end DCOP of the first phase detector and the second phase detector; and the source of the ninth NMOS transistor N9 and the source of the twelfth NMOS transistor N12 are both grounded.

[0029] The application provides a low-power and low-jitter digital injection locking phase-locked loop which adopts 28nm CMOS technology, the digital injection locking phase-locked loop adopts 0.6V power supply, and the power consumption is only 820muW. The bandwidth of the proposed digital injection locking phase-locked loop has been expanded to 2.3MHz, and the phase noise contributed by the digital controlled oscillator is significantly suppressed. At the output frequency of 2.4G, the measured jitter is 542fs, and the reference spur is-65.8dBc, which shows that the calibration circuit effectively aligns the injection pulse with the output signal.

[0030] The above embodiments are preferred examples for realizing the application, and the application is not limited to the above embodiments. Any non-essential addition, replacement made by the person skilled in the art according to the technical features of the technical scheme of the application belongs to the protection scope of the application.

Claims

1. A low power and low jitter digital injection locked phase locked loop, characterized in that: The digital injection locked phase locked loop comprises: an injection pulse path, an input end of which is connected to a reference signal, and an output end of which outputs an injection pulse signal; A pulse width calibration path includes a first phase detector and a successive approximation register; an input end of the first phase detector is connected to an injection pulse signal and a clock signal, and an output end of the first phase detector is connected to an input end of the successive approximation register; an output end of the successive approximation register outputs a second control signal to the injection pulse path for adjusting the pulse width of the injection pulse signal; A pulse time calibration path, comprising a second phase detector and an accumulator; an input of the second phase detector being connected to an injection pulse signal and a clock signal, and an output of the second phase detector being connected to an input of the accumulator; an output of the accumulator outputting a first control signal to the injection pulse path for regulating the injection time of the injection pulse signal; A dual-injection digitally controlled oscillator comprises a first injection terminal and a second injection terminal; the first injection terminal is connected to the positive terminal of the injection pulse signal, and the second injection terminal is connected to the negative terminal of the injection pulse signal; the output terminal of the dual-injection digitally controlled oscillator outputs a clock signal; The time and pulse width of the injected pulse signal are respectively regulated by the pulse time calibration path and the pulse width calibration path to achieve low jitter of the digital injection locked phase-locked loop, and the low power consumption of the digital injection locked phase-locked loop is achieved through the synergy of the pulse width calibration path, the pulse time calibration path and the dual-injection digitally controlled oscillator.

2. The low power consumption and low jitter digital injection locked phase locked loop according to claim 1, characterized in that: The injection pulse path includes a first controllable delay line, a second controllable delay line and an AND gate; The first input end of the first controllable delay line is connected to the reference signal, the second input end thereof is connected to the first control signal, and the output end of the first controllable delay line is connected to the second input end of the AND gate and the first input end of the second controllable delay line; The second input end of the second controllable delay line is connected to the second control signal, and the output end of the second controllable delay line is connected to the first input end of the AND gate; The output end of the AND gate is connected to the first injection end and the second injection end of the dual-injection digitally controlled oscillator, and outputs an injection pulse signal.

3. The low power consumption and low jitter digital injection locked phase locked loop according to claim 1, characterized in that: The digital injection locked phase locked loop also includes a frequency locked loop, a first input end of the frequency locked loop is connected to a reference signal, a second input end thereof is connected to a frequency control signal, and an output end of the frequency locked loop is connected to the input end of the dual injection numerically controlled oscillator.

4. The low power consumption and low jitter digital injection locked phase locked loop according to claim 1, characterized in that: The digital injection locked phase locked loop also includes a time to digital converter, a digital filter, a buffer and a frequency divider; The first input end of the time-to-digital converter is connected to a reference signal, the second input end thereof is connected to the output end of the frequency divider, the output end of the time-to-digital converter is connected to the input end of the digital filter; the output end of the digital filter is connected to the input end of the dual-injection numerically controlled oscillator; the output end of the dual-injection numerically controlled oscillator is connected to the input end of the buffer; and the output end of the buffer is connected to the input end of the frequency divider.

5. The low power consumption and low jitter digital injection locked phase locked loop according to claim 1, characterized in that: The dual-injection digitally controlled oscillator further includes a first delay unit, a second delay unit, a third delay unit, a fourth delay unit, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; The first output of the first delay unit is connected to the second input of the second delay unit and the first input of the third delay unit, and the second output of the first delay unit is connected to the third input of the second delay unit and the fourth input of the third delay unit; the first output of the second delay unit is connected to the second input of the third delay unit and the first input of the fourth delay unit, and the second output of the second delay unit is connected to the third input of the third delay unit and the fourth input of the fourth delay unit; the first output of the third delay unit is connected to the second input of the fourth delay unit, and the second output of the third delay unit is connected to the third input of the fourth delay unit; the first output of the fourth delay unit is connected to the first input of the first delay unit, the third input of the first delay unit and the fourth input of the second delay unit, and serves as the in-phase signal output of the dual injection numerically controlled oscillator; the second output of the fourth delay unit is connected to the second input of the first delay unit, the fourth input of the first delay unit and the first input of the second delay unit, and serves as the inverting signal output of the dual injection numerically controlled oscillator; The drain of the first NMOS transistor is connected to the first output terminal of the first delay unit, the source of the first NMOS transistor is connected to the second output terminal of the first delay unit, and the gate of the first NMOS transistor is connected to the first injection terminal; The drain of the second NMOS transistor is connected to the first output end of the second delay unit, the source thereof is connected to the second output end of the second delay unit, and the gate thereof is connected to the second injection end; the drain of the third NMOS transistor is connected to the first output end of the third delay unit, the source thereof is connected to the second output end of the third delay unit, and the gate thereof is connected to the first injection end; the drain of the fourth NMOS transistor is connected to the first output end of the fourth delay unit, the source thereof is connected to the second output end of the fourth delay unit, and the gate thereof is connected to the second injection end; the fifth input ends of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit are all connected to the input end of the dual-injection numerically controlled oscillator.

6. The low-power and low-jitter digital injection locked phase-locked loop according to claim 5, characterized in that: The first delay unit, the second delay unit, the third delay unit and the fourth delay unit each include a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a thirteenth NMOS transistor; The source of the first PMOS transistor, the source of the second PMOS transistor, the source of the third PMOS transistor, and the source of the fourth PMOS transistor are all connected to a power supply voltage; the drain of the first PMOS transistor is connected to the gate of the third PMOS transistor, and the gate of the first PMOS transistor is the first input terminal of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit; the drain of the fourth PMOS transistor is connected to the gate of the second PMOS transistor, and the gate of the fourth PMOS transistor is the fourth input terminal of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit; the drain of the second PMOS transistor is connected to the drain of the fifth NMOS transistor and is the first output terminal of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit; the drain of the third PMOS transistor is connected to the drain of the sixth NMOS transistor and is the second output terminal of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit; The source of the fifth NMOS transistor and the source of the sixth NMOS transistor are both connected to the drain of the thirteenth NMOS transistor, the source of the thirteenth NMOS transistor is grounded, and the gate of the thirteenth NMOS transistor is the fifth input end of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; the gate of the fifth NMOS transistor is the second input end of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit; and the gate of the sixth NMOS transistor is the third input end of the first delay unit, the second delay unit, the third delay unit and the fourth delay unit.

7. The low power consumption and low jitter digital injection locked phase locked loop according to claim 1, characterized in that: The first phase detector and the second phase detector each include a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor; The source of the fifth PMOS transistor, the source of the sixth PMOS transistor, the source of the eighth PMOS transistor, and the source of the ninth PMOS transistor are all connected to the power supply voltage; the gate of the fifth PMOS transistor, the gate of the seventh PMOS transistor, the gate of the ninth PMOS transistor, the gate of the tenth PMOS transistor, the gate of the eighth NMOS transistor, and the gate of the eleventh NMOS transistor are all signal injection terminals of the first phase detector and the second phase detector; The drain of the fifth PMOS transistor and the drain of the ninth PMOS transistor are both output terminals of the first phase detector and the second phase detector; the drain of the fifth PMOS transistor is connected to the drain of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the drain of the tenth PMOS transistor and the gate of the tenth NMOS transistor; the drain of the ninth PMOS transistor is connected to the source of the seventh PMOS transistor, the gate of the sixth PMOS transistor, the source of the tenth PMOS transistor and the gate of the seventh NMOS transistor; the drain of the seventh NMOS transistor is connected to the drain of the sixth PMOS transistor, and the source of the seventh NMOS transistor is connected to the drain of the seventh PMOS transistor. The drain of the eighth NMOS transistor is connected to the drain of the eighth PMOS transistor; the source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor; the drain of the tenth NMOS transistor is connected to the drain of the eighth PMOS transistor, and the source of the tenth NMOS transistor is connected to the drain of the eleventh NMOS transistor; the source of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor; the gate of the ninth NMOS transistor is the first input terminal of the first phase detector and the second phase detector; the gate of the twelfth NMOS transistor is the second input terminal of the first phase detector and the second phase detector; the source of the ninth NMOS transistor and the source of the twelfth NMOS transistor are both grounded.

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