A semiconductor device in which a substrate potential is suspended

Abstract

The application discloses a semiconductor device with a suspended substrate potential. The semiconductor device comprises, in sequence, a substrate, a buffer layer, a potential shielding layer, a channel layer and a barrier layer, the forbidden band width of the potential shielding layer is greater than that of the buffer layer, the forbidden band width of the potential shielding layer is greater than that of the channel layer, a first P-type nitride layer and a second P-type nitride layer are located on the side of the barrier layer away from the channel layer and are arranged at intervals, a first gate electrode is located on the side of the first P-type nitride layer away from the barrier layer, a second gate electrode is located on the side of the second P-type nitride layer away from the barrier layer, a first source electrode is located on the side of the barrier layer away from the channel layer, and a second source electrode is located on the side of the barrier layer away from the channel layer. The above technical scheme avoids the capture of the two-dimensional electron gas between the buffer layer, the channel layer and the barrier layer, shields the influence of the potential of the substrate on the semiconductor device, further reduces the device area, and saves the cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor device with a substrate potential suspended. Background Technology

[0002] Due to their small chip area and the wide bandgap and high mobility characteristic of third-generation semiconductor devices with floating substrate potential, bidirectional switching devices based on silicon gallium nitride have become a research hotspot in switching devices.

[0003] In unidirectional GaN high electron mobility transistors (HEMTs), the silicon (Si) substrate is connected to the source during use. However, in bidirectional GaN devices, the first and second sources switch between high and low voltages during operation. Therefore, the Si substrate cannot be directly connected to a low potential. An integrated circuit (IC) is needed within the device to manage the substrate potential, connecting the Si substrate to the lower potential of the first or second source. This substrate management IC increases device area and cost, and also increases parasitic parameters, affecting device performance. Summary of the Invention

[0004] This invention provides a semiconductor device with a floating substrate potential. By setting a potential shielding layer, there is no need to set an integrated circuit to control the substrate potential, so as to avoid the buffer layer capturing the two-dimensional electron gas between the channel layer and the barrier layer. This shields the semiconductor device with a floating substrate potential from the influence of the substrate potential, thereby reducing the device area and saving costs.

[0005] According to one aspect of the present invention, a semiconductor device with a substrate potential floating is provided, comprising:

[0006] Substrate; the potential of the substrate is left floating;

[0007] A buffer layer is located on one side of the substrate;

[0008] A potential shielding layer is located on the side of the buffer layer away from the substrate, and the band gap of the potential shielding layer is larger than the band gap of the buffer layer;

[0009] The channel layer is located on the side of the potential shielding layer away from the buffer layer; the bandgap width of the potential shielding layer is greater than the bandgap width of the channel layer;

[0010] A barrier layer is located on the side of the channel layer away from the potential shielding layer; the potential shielding layer is used to prevent the buffer layer from capturing the two-dimensional electron gas between the channel layer and the barrier layer;

[0011] The first P-type nitride layer is located on the side of the barrier layer away from the channel layer;

[0012] a second P-type nitride layer located at a side of the barrier layer away from the channel layer and spaced apart from the first P-type nitride layer;

[0013] a first gate located at a side of the first P-type nitride layer away from the barrier layer;

[0014] a second gate located at a side of the second P-type nitride layer away from the barrier layer;

[0015] a first source located at a side of the barrier layer away from the channel layer;

[0016] a second source located at a side of the barrier layer away from the channel layer.

[0017] Optionally, the content of aluminum component in the potential shielding layer is greater than the content of aluminum component in the buffer layer; and / or, the content of aluminum component in the potential shielding layer is greater than the content of aluminum component in the channel layer.

[0018] Optionally, the content of aluminum component in the potential shielding layer is greater than or equal to 2% and less than or equal to 50%.

[0019] Optionally, the thickness of the potential shielding layer is greater than or equal to 5 nanometers and less than or equal to 500 nanometers.

[0020] Optionally, the buffer layer comprises a group III-V semiconductor layer doped with acceptor energy level.

[0021] Optionally, further comprising an intermediate semiconductor layer, the content of aluminum component in the intermediate semiconductor layer is greater than or equal to the content of aluminum component in the buffer layer, the content of aluminum component in the intermediate semiconductor layer is greater than or equal to the content of aluminum component in the channel layer and less than the content of aluminum component in the potential shielding layer; the intermediate semiconductor layer is located between the buffer layer and the channel layer.

[0022] Optionally, the intermediate semiconductor layer is located between the potential shielding layer and the buffer layer.

[0023] The intermediate semiconductor layer is located between the potential shielding layer and the channel layer.

[0024] Optionally, further comprising an intermediate semiconductor layer, the intermediate semiconductor layer is located in the middle of the potential shielding layer.

[0025] Optionally, the intermediate semiconductor layer and the potential shielding layer are located in the same semiconductor film layer.

[0026] Optionally, in the direction of the potential shielding layer pointing to the intermediate semiconductor layer, the content of aluminum component in the intermediate semiconductor layer shows a decreasing trend.

[0027] Optionally, the buffer layer and the potential shielding layer are directly in contact.

[0028] The semiconductor device with the substrate potential suspended provided by the embodiment of the present application has the potential shielding layer on the side of the buffer layer away from the substrate, the band gap width of the potential shielding layer is greater than the band gap width of the buffer layer, and the band gap width of the potential shielding layer is greater than the band gap width of the channel layer, so that the electrons in the channel cannot jump into the buffer layer and are captured by the defects in the buffer layer. Therefore, the potential shielding layer can be used to avoid the defects in the buffer layer from capturing the two-dimensional electron gas between the channel layer and the barrier layer, so as to ensure the concentration of the two-dimensional electron gas, reduce the leakage current, shield the influence of the potential of the substrate on the enhanced silicon-based bidirectional gallium nitride device, and make the potential of the substrate suspended. Therefore, the substrate control circuit does not need to be set, the device area is greatly reduced, and the cost is saved.

[0029] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0031] Figure 1 is a structural schematic diagram of a semiconductor device with the substrate potential suspended provided by an embodiment of the present application;

[0032] Figure 2 is a structural schematic diagram of another semiconductor device with the substrate potential suspended provided by an embodiment of the present application;

[0033] Figure 3 is a structural schematic diagram of still another semiconductor device with the substrate potential suspended provided by an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should be within the scope of protection of the present application.

[0035] It is to be understood that the terminology "first", "second" and the like used throughout this specification and the annexed drawings is merely intended to distinguish between similar objects and not necessarily to describe a specific sequential or chronological order. It is to be understood that the use of such terms as "first", "second" and the like can be interchanged, unless otherwise expressly specified or limited in context. Furthermore, the terms "comprise", "comprising", "include", "including", and the like are to be construed in a non-exclusive manner when used in this specification and the annexed drawings, unless otherwise expressly specified or limited in context. It is to be understood that the use of such terms as "comprise", "comprising", "include", "including", and the like are to be construed in a non-exclusive manner when used in this specification and the annexed drawings, unless otherwise expressly specified or limited in context.

[0036] As Figure 1 shown, Figure 1 is a structure diagram of a substrate potential suspended semiconductor device provided by an embodiment of the present application. The substrate potential suspended semiconductor device comprises: a substrate 100; a potential suspension of the substrate 100; a buffer layer 200 located on one side of the substrate 100; a potential shielding layer 300 located on a side of the buffer layer 200 away from the substrate 100, the band gap width of the potential shielding layer 300 being greater than the band gap width of the buffer layer 200; a channel layer 400 located on a side of the potential shielding layer 300 away from the buffer layer 200; the band gap width of the potential shielding layer 300 being greater than the band gap width of the channel layer 400; a barrier layer 500 located on a side of the channel layer 400 away from the potential shielding layer 300; the potential shielding layer 300 is used to avoid the buffer layer 200 from capturing the two-dimensional electron gas between the channel layer 400 and the barrier layer 500; a first P-type nitride layer 610 located on a side of the barrier layer 500 away from the channel layer 400; a second P-type nitride layer 620 located on a side of the barrier layer 500 away from the channel layer 400 and spaced apart from the first P-type nitride layer 610; a first gate 630 located on a side of the first P-type nitride layer 610 away from the barrier layer; a second gate 640 located on a side of the second P-type nitride layer 620 away from the barrier layer 500; a first source 710 located on a side of the barrier layer 500 away from the channel layer 400; and a second source 720 located on a side of the barrier layer 500 away from the channel layer 400.

[0037] In the embodiment, the substrate 100 is a silicon substrate. The channel layer 400 includes one or more of GaN, AlGaN and InGaN, preferably GaN. The barrier layer 500 can be AlGaN. The channel layer 400 and the barrier layer 500 have a high concentration of two-dimensional electron gas near the interface. The first P-type nitride layer 610 and the second P-type nitride layer 620 can be P-type doped AlN or GaN, preferably P-type doped GaN, for depleting the two-dimensional electron gas at the corresponding positions of the barrier layer 500 below the first P-type nitride layer 610 and the second P-type nitride layer 620, turning off the gallium nitride device at a low voltage, and forming an enhancement-mode silicon-based bidirectional gallium nitride device. In this case, the first source electrode 710 is a low-voltage source electrode, and the second source electrode 720 is a high-voltage source electrode; or the first source electrode 710 is a high-voltage source electrode, and the second source electrode 720 is a low-voltage source electrode. The first source electrode 710 and the second source electrode 720 are switched between high voltage and low voltage, and the first gate electrode 630 and the second gate electrode 640 are used to drive the switching of the enhancement-mode silicon-based bidirectional gallium nitride device. When the driving voltage of the first gate electrode 630 of the enhancement-mode silicon-based bidirectional gallium nitride device is less than the turn-on voltage of the first gate electrode 630, and the driving voltage of the second gate electrode 640 is less than the turn-on voltage of the second gate electrode 640, the enhancement-mode silicon-based bidirectional gallium nitride device is in an off state. When the driving voltage of the first gate electrode 630 of the enhancement-mode silicon-based bidirectional gallium nitride device is greater than the turn-on voltage of the first gate electrode 630, and the driving voltage of the second gate electrode 640 is greater than the turn-on voltage of the second gate electrode 640, the enhancement-mode silicon-based bidirectional gallium nitride device is in an on state.

[0038] If there is no structure of the potential shielding layer 300, the potential of the substrate 100 will also change during the switching process of the first source electrode 710 and the second source electrode 720, and the substrate 100 is usually provided with a substrate control circuit connected to the substrate 100 to discharge the charge and pull the substrate 100 to a low potential. Due to the setting of the substrate control circuit, the device area is relatively large, and the preparation cost is relatively high.

[0039] The technical scheme provided by the embodiment of the present application is that the potential shielding layer 300 is located on the side of the buffer layer 200 away from the substrate 100, the band gap of the potential shielding layer 300 is greater than the band gap of the buffer layer 200, and the band gap of the potential shielding layer 300 is greater than the band gap of the channel layer 400, so that the electrons in the channel cannot jump into the buffer layer 200 and are captured by the defects in the buffer layer 200. Therefore, the potential shielding layer 300 can be used to avoid the capture of the two-dimensional electron gas between the channel layer 400 and the barrier layer 500 by the defects in the buffer layer 200, ensure the concentration of the two-dimensional electron gas, reduce the leakage current, shield the influence of the potential of the substrate 100 on the enhancement-mode silicon-based bidirectional gallium nitride device, and make the potential of the substrate 100 suspended. Therefore, the substrate control circuit can be omitted, the device area is greatly reduced, and the cost is saved.

[0040] Optionally, based on the technical scheme above, as shown in Figure 1 The content of aluminum component in the potential shielding layer 300 is greater than the content of aluminum component in the buffer layer 200; the content of aluminum component in the potential shielding layer 300 is greater than the content of aluminum component in the channel layer 400. It should be noted that, in the embodiment, the meaning of the potential of the substrate 100 being suspended is that the potential of the substrate 100 is not directly connected to the power supply or the ground through a wire or a conductive film layer.

[0041] Specifically, the content of aluminum component in the potential shielding layer 300 is greater than the content of aluminum component in the buffer layer 200, so that the band gap of the potential shielding layer 300 is greater than the band gap of the buffer layer 200. The content of aluminum component in the potential shielding layer 300 is greater than the content of aluminum component in the channel layer 400, so that the band gap of the potential shielding layer 300 is greater than the band gap of the channel layer 400.

[0042] Optionally, based on the technical scheme above, as shown in Figure 1 The content of aluminum component in the potential shielding layer 300 is greater than or equal to 2% and less than or equal to 50%.

[0043] Specifically, the content of aluminum component in the buffer layer 200 and the channel layer 400 is usually less than 2%. The content of aluminum component in the potential shielding layer 300 is greater than or equal to 2% and less than or equal to 50%, so that the content of aluminum component in the potential shielding layer 300 is greater than the content of aluminum component in the buffer layer 200; the content of aluminum component in the potential shielding layer 300 is greater than the content of aluminum component in the channel layer 400.

[0044] Optionally, based on the technical scheme above, as shown in Figure 1 The thickness of the potential shielding layer 300 is greater than or equal to 5 nanometers and less than or equal to 500 nanometers.

[0045] Specifically, the thickness of the potential shielding layer 300 is too small, so that it is less than 5 nanometers, which is not obvious for avoiding the defects in the buffer layer 200 from capturing the two-dimensional electron gas between the channel layer 400 and the barrier layer 500, and for shielding the potential of the substrate 100. The thickness of the potential shielding layer 300 is too large, so that it is greater than 500 nanometers, which makes the on-resistance of the device too large. Therefore, the thickness of the potential shielding layer 300 is greater than or equal to 5 nanometers and less than or equal to 500 nanometers, which can avoid the defects in the buffer layer 200 from capturing the two-dimensional electron gas between the channel layer 400 and the barrier layer 500, and has the shielding effect on the potential of the substrate 100, and also makes the on-resistance of the device not too large.

[0046] Optionally, based on the technical scheme above, as shown in Figure 1 The buffer layer 200 comprises a Ⅲ-Ⅴ group semiconductor layer doped with an acceptor energy level.

[0047] The buffer layer 200 is, for example, a carbon-doped III-V semiconductor layer. The acceptor-doped atoms have a strong ability to combine with electrons, and without the shielding effect of the potential shielding layer 300, the acceptor-doped atoms are prone to capture the two-dimensional electron gas, thereby increasing the leakage current of the device and affecting the reliability of the electrical parameters of the device. The potential shielding layer 300 is located on the side of the buffer layer 200 away from the substrate 100. The potential shielding layer 300 has a band gap greater than the band gap of the buffer layer 200, and the potential shielding layer 300 has a band gap greater than the band gap of the channel layer 400. The electrons in the channel cannot transition into the buffer layer 200 and are captured by the defects in the buffer layer 200. Therefore, the potential shielding layer 300 can be used to avoid the capture of the two-dimensional electron gas between the channel layer 400 and the barrier layer 500 by the defects in the buffer layer 200, thereby ensuring the concentration of the two-dimensional electron gas and reducing the leakage current, and shielding the influence of the potential of the substrate 100 on the enhanced silicon-based bidirectional gallium nitride device.

[0048] Optionally, on the basis of the technical solution, as shown in Figure 2 and Figure 3 , Figure 2 is another structure diagram of a semiconductor device with a suspended substrate potential provided by an embodiment of the present application, Figure 3 is another structure diagram of a semiconductor device with a suspended substrate potential provided by an embodiment of the present application. The semiconductor device with a suspended substrate potential further includes an intermediate semiconductor layer 800. The content of aluminum components in the intermediate semiconductor layer 800 is greater than or equal to the content of aluminum components in the buffer layer 200, the content of aluminum components in the intermediate semiconductor layer 800 is greater than or equal to the content of aluminum components in the channel layer 400, and the content of aluminum components in the intermediate semiconductor layer 800 is less than the content of aluminum components in the potential shielding layer 300. The intermediate semiconductor layer 800 is located between the buffer layer 200 and the channel layer 400. The intermediate semiconductor layer 800 can be used as a lattice matching layer to reduce the lattice mismatch between the potential shielding layer 300 and the buffer layer 200 and the channel layer 400.

[0049] Optionally, as shown in Figure 2 , the intermediate semiconductor layer 800 is located between the potential shielding layer 300 and the buffer layer 200; and the intermediate semiconductor layer 800 is located between the potential shielding layer 300 and the channel layer 400.

[0050] In the above structure, the intermediate semiconductor layer 800 is arranged on both sides of the potential shielding layer 300. The potential shielding layer 300 and the intermediate semiconductor layer 800 form a structure with small aluminum components on both sides and large aluminum components in the middle.

[0051] Optionally, as shown in Figure 3 , the semiconductor device further includes an intermediate semiconductor layer 800, and the intermediate semiconductor layer 800 is located in the middle of the potential shielding layer 300.

[0052] In the above structure, the intermediate semiconductor layer 800 is located in the middle of the potential shielding layer 300, and the potential shielding layer 300 and the intermediate semiconductor layer 800 form a structure in which the aluminum component is large on both sides and small in the middle. The intermediate semiconductor layer 800 located in the middle of the potential shielding layer 300 can be used to avoid the defects in the buffer layer 200 from capturing the two-dimensional electron gas between the channel layer 400 and the barrier layer 500, thereby ensuring the concentration of the two-dimensional electron gas and reducing the leakage current. At the same time, the effect of shielding the potential of the substrate 100 on the enhanced silicon-based bidirectional gallium nitride device is achieved. At the same time, the intermediate semiconductor layer 800 with a small aluminum component can further reduce the on-resistance of the semiconductor device with the substrate potential suspended.

[0053] Optionally, on the basis of the above technical solution, as shown in Figure 2 and Figure 3 , in the direction of the potential shielding layer 300 pointing to the intermediate semiconductor layer 800, the content of the aluminum component in the intermediate semiconductor layer 800 decreases.

[0054] Specifically, as shown in Figure 2 , in the direction of the potential shielding layer 300 pointing to the intermediate semiconductor layer 800, the content of the aluminum component in the intermediate semiconductor layer 800 decreases in a gradual manner, avoiding a large decrease in the aluminum component, which would cause a large change in the on-resistance of the device and affect the performance of the device.

[0055] As shown in Figure 3 , in the direction of the potential shielding layer 300 pointing to the intermediate semiconductor layer 800, the content of the aluminum component in the intermediate semiconductor layer 800 decreases in a gradual manner, avoiding a large decrease in the aluminum component, which would cause a large change in the on-resistance of the device and affect the performance of the device. Since the intermediate semiconductor layer 800 is located inside the potential shielding layer 300, the lowest aluminum component is in the position of the general thickness of the intermediate semiconductor layer 800. Optionally, on the basis of the above technical solution, as shown in Figure 2 and Figure 3 , the intermediate semiconductor layer 800 and the potential shielding layer 300 are located in the same semiconductor film layer.

[0056] Specifically, Figure 2 and Figure 3 , the intermediate semiconductor layer 800 and the potential shielding layer 300 are the same semiconductor film layer, except that the aluminum component in the intermediate semiconductor layer 800 is smaller than that in the potential shielding layer 300. The semiconductor film layer of the intermediate semiconductor layer 800 and the potential shielding layer 300 can be prepared at the same time, and the aluminum component content is strictly controlled through a doping process. Compared with preparing multiple semiconductor film layers, the preparation process is simplified and the preparation cost is reduced.

[0057] Optionally, on the basis of the above technical solution, as shown inFigure 1 As shown, the buffer layer 200 and the potential shielding layer 300 are directly in contact. Specifically, the buffer layer 200 and the potential shielding layer 300 are directly in contact, avoiding the arrangement of other film layers. On the one hand, the structure of the semiconductor device with the substrate potential suspended is simplified. On the other hand, defects introduced by other film layers are avoided, so that the electrons in the two-dimensional electron gas are captured to improve the performance of the device.

[0058] It should be understood that the various forms of the flow shown above can be used to reorder, add or delete steps. For example, each step described in the present application can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which is not limited herein.

[0059] The above detailed description does not constitute a limitation on the scope of protection of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A semiconductor device with a substrate potential floating, characterized in that, The application relates to a semiconductor device, comprising: a substrate; the potential of the substrate is suspended; a buffer layer is located on one side of the substrate; a potential shielding layer is located on the side of the buffer layer away from the substrate, the forbidden band width of the potential shielding layer is greater than that of the buffer layer; a channel layer is located on the side of the potential shielding layer away from the buffer layer; the forbidden band width of the potential shielding layer is greater than that of the channel layer; a barrier layer is located on the side of the channel layer away from the potential shielding layer; the potential shielding layer is used for avoiding the buffer layer from capturing the two-dimensional electron gas between the channel layer and the barrier layer; a first P-type nitride layer is located on the side of the barrier layer away from the channel layer; a second P-type nitride layer is located on the side of the barrier layer away from the channel layer and is spaced apart from the first P-type nitride layer; a first gate is located on the side of the first P-type nitride layer away from the barrier layer; a second gate is located on the side of the second P-type nitride layer away from the barrier layer; a first source is located on the side of the barrier layer away from the channel layer; and a second source is located on the side of the barrier layer away from the channel layer. The content of the aluminum component in the potential shielding layer is greater than that in the buffer layer; and / or the content of the aluminum component in the potential shielding layer is greater than that in the channel layer. The content of the aluminum component in the potential shielding layer is greater than or equal to 2% and less than or equal to 50%. The thickness of the potential shielding layer is greater than or equal to 5 nm and less than or equal to 500 nm. The buffer layer comprises a group III-V semiconductor layer doped with an acceptor energy level. Further comprising an intermediate semiconductor layer, the content of the aluminum component in the intermediate semiconductor layer is greater than or equal to that in the buffer layer, the content of the aluminum component in the intermediate semiconductor layer is greater than or equal to that in the channel layer and less than that in the potential shielding layer; the intermediate semiconductor layer is located between the buffer layer and the channel layer. The intermediate semiconductor layer is located between the potential shielding layer and the buffer layer. The intermediate semiconductor layer is located between the potential shielding layer and the channel layer. The intermediate semiconductor layer is located in the middle of the potential shielding layer. The intermediate semiconductor layer and the potential shielding layer are located in the same semiconductor film layer. In the direction of the potential shielding layer pointing to the intermediate semiconductor layer, the content of the aluminum component in the intermediate semiconductor layer shows a decreasing trend. The buffer layer and the potential shielding layer are directly in contact.

2. The semiconductor device of claim 1, wherein ​ 3. The semiconductor device of claim 1, wherein ​ 4. The semiconductor device of claim 1, wherein ​ 5. The semiconductor device of claim 1, wherein ​ 6. The semiconductor device of claim 1, wherein ​ 7. The semiconductor device of claim 6, wherein ​ ​ 8. The semiconductor device of claim 6, wherein ​ 9. The semiconductor device according to any one of claims 6 to 8, wherein ​ 10. The semiconductor device according to any one of claims 6 to 8, wherein ​ 11. The semiconductor device of claim 1, wherein ​

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