Power device and method for manufacturing the same, electronic device

Abstract

The application relates to a power device and a preparation method thereof and electronic equipment. The device comprises a substrate, a first surface of the substrate comprising an epitaxial layer; the epitaxial layer comprising source regions, base regions and shielding regions arranged along a first direction towards the substrate via a top surface; a plurality of gates spaced along a second direction parallel to the first surface and penetrating the source regions and the base regions along the first direction and partially embedded in the shielding regions; the gate comprising a gate conductive layer and a gate oxide layer arranged along the first direction; an interlayer dielectric layer located on the top surface of the epitaxial layer and comprising an extension penetrating the gate conductive layer along the first direction and in contact with the gate oxide layer; and a metal layer located on the top surface of the interlayer dielectric layer and comprising a first source electrode extending into the gate via the top surface of the extension; the width and depth of the first source electrode being related to the gate-source capacitance of the power device. The channel density can be ensured while improving the reliability of the gate oxide layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a power device, a preparation method thereof, and an electronic device. BACKGROUND

[0002] A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is a widely used and superior power device. Silicon carbide (SiC) material has strong attraction in high power due to its excellent characteristics and has become one of ideal materials for high-performance power MOSFETs. SiC MOSFET devices mainly have a planar gate structure and a trench gate structure.

[0003] Compared with the planar gate structure, a trench gate silicon carbide (SiC) MOSFET eliminates the JFET area effect due to the trench gate structure, so that the current can flow more vertically and directly from the source to the drift region, and the cell density can be made higher, thereby significantly reducing the on-resistance per unit area. Benefiting from the higher cell density and shorter channel, its input capacitance is smaller, the switching speed is faster, the loss is lower, more device units can be integrated on the same area wafer, and the wafer utilization and chip density are effectively improved.

[0004] However, the trench gate SiC MOSFET has certain process manufacturing difficulty, and due to the special structure that the gate oxide layer is located inside the trench, the gate oxide layer is easily affected by mechanical stress, electric field concentration and other factors, resulting in reduced breakdown voltage and reliability problems. SUMMARY

[0005] Therefore, it is necessary to provide a power device, a preparation method thereof, and an electronic device to at least improve the gate oxide reliability of the power device while improving its dynamic characteristics.

[0006] In a first aspect, the present application provides a power device, comprising: a substrate, a first surface of the substrate comprising an epitaxial layer; the epitaxial layer comprising source regions, base regions, and shielding regions arranged along a first direction toward the substrate via a top surface;

[0007] a plurality of gates, spaced apart along a second direction parallel to the first surface and penetrating the source regions, the base regions, and partially embedded in the shielding regions along the first direction; the gate comprising a gate conductive layer and a gate oxide layer arranged along the first direction;

[0008] an interlayer dielectric layer located on the top surface of the epitaxial layer, comprising an extension portion penetrating the gate conductive layer and contacting the gate oxide layer along the first direction;

[0009] The metal layer is located on the top surface of the interlayer dielectric layer and comprises: a first source electrode extending into the gate via the top surface of the extension; the width and the depth of the first source electrode are related to the gate-source capacitance of the power device; wherein the width is used to represent the size along the second direction; and the depth is used to represent the size along the first direction.

[0010] In the power device in the above embodiment, the shielding region surrounds the bottom of the gate, and the gate oxide layer is separated from the high-voltage region by physical isolation, which can significantly reduce the electric field peak at the bottom of the gate, avoid the risk of gate oxide breakdown caused by excessively high local electric field, and enhance the working reliability. At the same time, the split gate structure formed by the first source electrode and the interlayer dielectric layer extending into the gate can realize precise control of the gate-source capacitance (C gs ) by adjusting the depth and the width of the first source electrode, effectively reducing the power loss of the device in the switching process, and optimizing the dynamic characteristics of the device.

[0011] In some embodiments, the gate comprises:

[0012] The first level has a bottom surface flush with the gate conductive layer;

[0013] The second level has a top surface lower than the bottom surface of the base region and is partially embedded in the shielding region;

[0014] The bottom surface of the extension is located within the top surface of the gate oxide layer of the second level;

[0015] The width of the second level is smaller than the width of the first level.

[0016] In some embodiments, the width of the shielding region is greater than the width of the second level and smaller than the width of the first level;

[0017] The depth of the first source electrode is not greater than the depth of the gate conductive layer.

[0018] In some embodiments, the width and the depth of the first source electrode are related to the gate-source capacitance of the power device, comprising:

[0019] The depth of the first source electrode is positively related to the gate-source capacitance of the power device;

[0020] The width of the first source electrode is negatively related to the gate-source capacitance of the power device.

[0021] In some embodiments, the gate and the interlayer dielectric layer are prepared simultaneously in the same process step.

[0022] In some embodiments, the metal layer further comprises: a second source electrode extending to the base region partially embedded via the top surface of the interlayer dielectric layer along the first direction.

[0023] In a second aspect, the application also provides a preparation method of a power device, for preparing the power device in any of the above embodiments, the preparation method of the power device comprising:

[0024] A substrate is provided, and an epitaxial layer is formed on a first surface of the substrate; the epitaxial layer includes source regions, base regions, and shield regions arranged along a first direction toward the first surface of the substrate;

[0025] After forming a plurality of gates in the epitaxial layer, the gates are spaced apart along a second direction parallel to the first surface and extend through the source regions and the base regions along the first direction and partially embed in the shield regions, a laminated interlayer dielectric layer and a metal layer are formed on a top surface of the epitaxial layer;

[0026] The gates include gate conductive layers arranged along the first direction and gate oxide layers;

[0027] The interlayer dielectric layer includes extensions that extend through the gate conductive layers along the first direction to contact the gate oxide layers;

[0028] The metal layer includes first source electrodes that extend into the gates through top surfaces of the extensions; the width and the depth of the first source electrodes are associated with gate-source capacitance of the power device; the width is used to represent a dimension along the second direction; and the depth is used to represent a dimension along the first direction.

[0029] In the above embodiment, the shield regions are formed at the bottom of the gates to reduce the electric field intensity of the gate oxide layers at the bottom of the trench gates, and the extensions of the interlayer dielectric layer and the first source electrodes are inserted between the gate conductive layers in the gates. By setting the depth and the width of the first source electrodes inserted in the extensions, the size of the gate-source capacitance can be flexibly adjusted. Compared with the conventional method of forming the shield regions by ion implantation at the bottom of the trench, the split-gate structure can improve the dynamic characteristics of the device on the basis of improving the gate oxide reliability of the device.

[0030] In some embodiments, the shield regions are formed by:

[0031] After forming a first-level trench in the epitaxial layer, a sacrificial layer is formed in the first-level trench;

[0032] Part of the sacrificial layer is removed to form a second-level trench that extends through the sacrificial layer along the first direction and to the epitaxial layer; the width of the second-level trench is smaller than the width of the first-level trench;

[0033] An ion implantation process is performed on the epitaxial layer at the bottom of the second-level trench to form the shield regions.

[0034] In some embodiments, the gates, the interlayer dielectric layer, and the metal layer are formed by:

[0035] After the sacrificial layer is removed, an initial gate is formed in the first-level trench;

[0036] Based on the same mask as the second-level trench, a first recess is formed in the initial gate;

[0037] The interlayer dielectric layer is formed in the first recess and on the top surface of the epitaxial layer;

[0038] forming, in the interlayer dielectric layer, second grooves and third grooves arranged alternately along the second direction; the third grooves extend along the first direction to the base region;

[0039] forming a metal layer filling the second grooves and the third grooves and covering the top surface of the interlayer dielectric layer; the metal layer in the second grooves is used to form the first source electrode, and the metal layer in the third grooves is used to form the second source electrode.

[0040] In a third aspect, the present application also provides an electronic device comprising the power device as described in any of the above embodiments or prepared by the preparation method as described in any of the above embodiments.

[0041] In the above embodiments, the electronic device comprising the power device can work at a higher switching frequency, and the power loss in the switching process is significantly reduced, and the operating efficiency is improved. In addition, the improvement of gate oxide reliability can effectively reduce the probability of device damage, prolong the service life, and reduce the maintenance and replacement costs of the equipment.

[0042] The power device and the preparation method thereof and the electronic device provided by the present application have the following unexpected technical effects:

[0043] The power device provided by the present application forms a physical isolation by surrounding the bottom of the gate electrode with the shielding region, effectively separates the gate oxide layer from the high-voltage region, alleviates the gate oxide breakdown problem caused by local electric field concentration, and greatly enhances the reliability of the device under high-voltage working conditions. At the same time, the split gate structure formed by the first source electrode and the extension of the interlayer dielectric layer can realize precise control of the gate-source capacitance (C gs ) by adjusting the depth and width of the first source electrode embedded in the gate electrode, effectively reduces the gate-source capacitance related loss of the device in the switching process, optimizes the switching dynamic characteristics, reduces the switching power consumption, improves the overall energy efficiency, and better adapts to various application scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0045] Figure 1 The power device provided by the related art trench gate structure;

[0046] Figure 2 The power device provided by the trench gate structure in the embodiments of the present application;

[0047] Figure 3 This is a flowchart of a preparation method provided in one embodiment;

[0048] Figure 4 This is a schematic cross-sectional view of the structure obtained after forming a buffer layer and an epitaxial layer in step S202 of the preparation method provided in one embodiment;

[0049] Figure 5 This is a schematic cross-sectional view of the structure obtained after forming the base region and the source region in step S204 of the preparation method provided in one embodiment;

[0050] Figure 6a This is a schematic cross-sectional view of the structure obtained after forming a primary trench in step S206 of the preparation method provided in one embodiment;

[0051] Figure 6b for Figure 6a A schematic diagram of the cross-section of the structure after the sacrificial layer is formed;

[0052] Figure 7 This is a cross-sectional schematic diagram of the structure obtained by forming secondary trenches in step S208 of the preparation method provided in one embodiment;

[0053] Figure 8 This is a schematic cross-sectional view of the structure obtained after forming the shielding region in step S210 of the preparation method provided in one embodiment;

[0054] Figure 9 This is a schematic cross-sectional view of the structure obtained after removing the sacrificial layer in step S402 of the preparation method provided in one embodiment;

[0055] Figure 10 This is a schematic cross-sectional view of the structure obtained after forming the initial gate in step S404 of the preparation method provided in one embodiment;

[0056] Figure 11 This is a schematic cross-sectional view of the structure obtained after forming the first groove in step S406 of the preparation method provided in one embodiment;

[0057] Figure 12 This is a schematic cross-sectional view of the structure obtained after forming the interlayer dielectric layer in step S408 of the preparation method provided in one embodiment;

[0058] Figure 13 This is a cross-sectional schematic diagram of the structure obtained after forming a contact hole in step S410 of the preparation method provided in one embodiment;

[0059] Figure 14 This is a schematic cross-sectional view of the structure obtained after forming a metal layer in step S412 of the preparation method provided in one embodiment;

[0060] Figure 15 To Figure 14 After forming the back metal layer, a cross-sectional schematic view of the resulting structure.

[0061] Reference Signs List:

[0062] 1, initial substrate; 2, buffer layer; 10, substrate; 11, epitaxial layer; 111, source region; 112, base region; 113, shielding region; 20, interlayer dielectric layer; 21, extension; 30, metal layer; 31, first source electrode; 32, second source electrode; 401, sacrificial layer; 402, initial gate electrode; 40, gate electrode; 411, conductive material layer; 41, gate conductive layer; 42, gate oxide layer; 501, primary trench; 502, secondary trench; 503, first recess; 601, second recess; 602, third recess. DETAILED DESCRIPTION

[0063] For the purposes of this application, reference will be made to the accompanying drawings in which the preferred embodiments of the application are illustrated. It should be understood that the application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. It will be apparent that those skilled in the art will be able to make modifications to the embodiments disclosed herein without departing from the scope of the application.

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0065] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first dopant type could be termed a second dopant type, and, similarly, a second dopant type could be termed a first dopant type; a first dopant type and a second dopant type are different dopant types, for example, a first dopant type can be P-type and a second dopant type can be N-type, or a first dopant type can be N-type and a second dopant type can be P-type.

[0066] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that, when the term "comprising" is used in the present description and claims, it does not exclude the presence of other elements or steps than those listed. Likewise, the term "comprising" should not be interpreted as implying that the apparatus or method has to function only in the described way or that it has to function continuously. It should also be understood that the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0067] Embodiments of the application are described herein with reference to the drawings, which show idealized embodiments of the application (and intermediate structures thereof) in cross-section. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and the surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application. It should also be understood that, wherever used, the terms "over", "under", "between", and "on" include wholly or in part by other intervening regions that are present.

[0068] Currently, the industry mainly focuses on two types of trench grid structures: single-groove structures and double-groove structures. Double-groove structures, such as... Figure 1 As shown in Figure (1), this structure has both a source trench and a gate trench, and a p-type shielding region is added to the bottom of the source trench; the single trench structure is as follows Figure 1 As shown in Figure (2), the gate has an asymmetric shielding region, and the gate trench is embedded in the bottom shielding region. Although the above two classic trench gate structures can solve the problem of excessive gate oxide electric field at the bottom of the trench, they both have obvious limitations.

[0069] Specifically, when optimizing the electric field through an asymmetric shielding region, a single-trench structure requires sacrificing approximately half the number of channels, directly leading to an increase in on-resistance. A double-trench structure, on the other hand, necessitates increasing the design cutoff, reducing channel density across the entire chip. Simultaneously, the gate-source capacitance C of the trench gate structure... gs Generally small in size, extremely fast turn-on and turn-off speeds, and prone to oscillations and other characteristics that are detrimental to applications, limiting the optimization of dynamic performance.

[0070] Based on this, this application provides a power device. For ease of understanding, in the embodiments of this application, the epitaxial layer may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, the direction toward the substrate is defined as a first direction perpendicular to the first surface of the substrate and a second direction parallel to the first surface. The first and second directions are perpendicular to each other. The first direction is defined as the Z-axis direction, and the second direction is defined as the Y-axis direction.

[0071] The power device provided in this application will now be described in more detail with reference to the accompanying drawings.

[0072] Please see Figure 2 , Figure 2 A partial cross-sectional view of the power device provided in this application, such as Figure 2 As shown, the power device includes: a substrate 10, an epitaxial layer 11, a gate 40, an interlayer dielectric layer 20, and a metal layer 30.

[0073] The substrate 10 includes an initial substrate 1 and a buffer layer 2, with an epitaxial layer 11 located on the top surface of the buffer layer 2. The epitaxial layer 11 includes a source region 111, a base region 112, and a shielding region 113 arranged sequentially along the OZ direction. In the following embodiments, the source region 111, the substrate 10, and the epitaxial layer 11 are all N-type conductive, while the base region 112 and the shielding region 113 are all P-type conductive. It can be understood that when the substrate 10 is P-type, simply interchange the "P" and "N" in the above structure.

[0074] The power device includes a plurality of gates 40 distributed along the OY direction, and the extension 21 of the interlayer dielectric layer 20 extends along the OZ direction to the bottom of the gate 40, and the gate conductive layer 41 of the gate 40 is distributed on both sides of the extension 21 to form a split gate, thereby reducing the gate leakage capacitance C gd At the same time, the bottom of the gate 40 is surrounded by the shielding area 113, and forms a PN junction with the epitaxial layer 11, thereby attracting part of the electric lines, and to a certain extent, redistributing the electric lines in the epitaxial layer 11, and relieving the problem of electric field concentration at the bottom of the gate 40.

[0075] The gate 40 further includes a first source 31 extending into the gate 40 via the top surface of the extension 21, and a second source 32 extending into the base area 112; the width (dimension along the OY direction) and the depth (dimension along the OZ direction) of the first source 31 are related to the gate-source capacitance C gs of the power device.

[0076] Specifically, the first source 31 extends into the gate 40, and the depth of the first source 31 is positively correlated with the gate-source capacitance C gs of the power device, that is, the deeper the depth, the larger the facing area of the gate and the source terminal, and the larger the gate-source capacitance C gs ; the width of the first source 31 is negatively correlated with the gate-source capacitance C gs of the power device, that is, the smaller the width, the greater the thickness of the extension 21, and the larger the gate-source capacitance C gs . From the perspective of the device, C gs / C gd is greatly increased, and has adjustment space, so that the device can optimize the switching speed, reduce the oscillation, and optimize the switching loss when switching at high speed, and thus the best dynamic performance of the device can be achieved.

[0077] Please continue to refer to Figure 2 In some embodiments, the gate 40 is divided into a two-level structure of a first level and a second level arranged along the OZ direction.

[0078] The first level, the bottom surface of the first level is flush with the gate conductive layer 41;

[0079] The second level, the top surface of the second level is lower than the bottom surface of the base area 112, and is partially embedded in the shielding area 113;

[0080] In the above embodiment, the second level is formed by twice etching, and the width of the second level is smaller than that of the first level. The gate conductive layer 41 is located in the first level, the bottom of the second level is embedded in the shielding area 113, and the extension 21 extends into the second level, and the bottom surface is surrounded by the gate oxide layer 42 of the second level. The specific structure is shown in Figure 2 , which effectively increases the thickness of the gate oxide layer at the bottom of the gate 40, and improves the withstand voltage of the corner region at the bottom of the trench.

[0081] Please refer to Figures 3-14In another aspect, the application provides a method for manufacturing a power device as shown in Figure 2 The method comprises steps S20-S40.

[0082] Step S20: providing a substrate 10, and forming an epitaxial layer 11 on a first surface 10a of the substrate 10; the epitaxial layer 11 comprises source regions 111, base regions 112, and shield regions 113 arranged along an OZ direction via a top surface.

[0083] Step S40: after forming a plurality of gates 40 in the epitaxial layer 11, the gates 40 being spaced apart along an OY direction and penetrating the source regions 111 and the base regions 112 along the OZ direction and partially embedded in the shield regions 113, forming a laminated interlayer dielectric layer 20 and a metal layer 30 on the top surface of the epitaxial layer 11.

[0084] The gates 40 comprise gate conductive layers 41 and gate oxide layers 42 arranged along the OZ direction.

[0085] The interlayer dielectric layer 20 comprises an extension 21 penetrating the gate conductive layers 41 to contact the gate oxide layers 42 along the OZ direction.

[0086] The metal layer 30 comprises a first source electrode 31 extending into the gates 40 via the top surface of the extension 21; the width and depth of the first source electrode 31 are related to the gate-source capacitance C gs .

[0087] It should be understood that, although the steps in the flowchart of Figure 3 are shown in a sequential order, such steps are not necessarily performed in the order shown by the arrows. Unless explicitly stated, the steps are not necessarily performed in the order shown in the flowchart. The steps can be performed in other orders. Moreover, Figure 3 At least some of the steps in may comprise multiple steps or stages, which are not necessarily performed at the same time, but can be performed at different times. The order of the steps or stages is not necessarily sequential, but can be performed in rotation or alternation with other steps or stages of other steps.

[0088] Figures 4 to 15 The following describes an exemplary method for manufacturing a power device according to the application, Figures 3 to 15 to show the step-by-step cross-sectional view of an exemplary method for manufacturing a power device according to the application.

[0089] Referring to Figures 4-8 , step S20 further comprises:

[0090] Step S202: Forming a buffer layer 2, an epitaxial layer 11 in sequence on the top surface of the initial substrate 1 by epitaxial process, the buffer layer 2 and the initial substrate 1 are used to form a substrate 10, the specific structure is as shown in Figure 4 .

[0091] For example, as described above, the doping type of the epitaxial layer 11, the buffer layer 2 and the initial substrate 1 is low concentration N-type doping, medium concentration N-type doping and high concentration N-type doping in sequence.

[0092] Step S204: Injecting a P-type base region 112 and a high concentration N-type source region 111 in sequence on the epitaxial layer 11, the specific structure is as shown in Figure 5

[0093] For example, the depth of the source region 111 ranges from 0.15 μm to 0.25 μm, for example, 0.15 μm, 0.2 μm or 0.25 μm, etc.

[0094] For example, the depth of the base region 112 ranges from 0.9 μm to 1.1 μm, for example, 0.9 μm, 1 μm or 1.1 μm, etc.

[0095] In the embodiment, the depth of the base region 112 is 1 μm, and the depth of the source region 111 is 0.2 μm.

[0096] Step S206: After etching a first level groove 501 in the epitaxial layer 11, a sacrificial layer 401 is formed in the first level groove 501, and is etched back to the top surface of the epitaxial layer 11, the specific structure is as shown in Figure 6a and Figure 6b

[0097] For example, the material of the sacrificial layer 401 includes but is not limited to polysilicon.

[0098] For example, the depth of the first level groove 501 ranges from 1.1 μm to 1.3 μm, for example, 1.1 μm, 1.2 μm or 1.3 μm, etc.; and the width thereof ranges from 2.5 μm to 3.5 μm, for example, 2.5 μm, 3 μm or 3.5 μm, etc.

[0099] In the embodiment, the depth of the first level groove 501 is 1.2 μm.

[0100] Step S208: Etching the sacrificial layer 401 to form a second level groove 502 extending through the sacrificial layer 401 along the OZ direction and extending to the epitaxial layer 11, the specific structure is as shown in Figure 7

[0101] In the above embodiment, the sacrificial layer 401 can be used as a mask layer for etching the second level groove structure and a blocking layer for shielding region injection, thereby improving the process integration.

[0102] ​​​For example, the depth of the secondary trench 502 ranges from 1.4 μm to 1.6 μm, such as 1.4 μm, 1.5 μm or 1.6 μm, etc.; and the width thereof ranges from 0.5 μm to 1.5 μm, such as 0.5 μm, 1 μm or 1.5 μm, etc.

[0103] Step S210: performing an ion implantation process on the epitaxial layer 11 at the bottom of the secondary trench 502 to form a high-concentration P-type doped shielding region 113, and the specific structure is as shown in Figure 8 .

[0104] Please refer to Figures 9-15 In some embodiments, step S40 further includes:

[0105] Step S402: after removing the sacrificial layer 401, performing high-temperature annealing on the epitaxial layer 11 to activate the impurities, and the annealing temperature ranges from 1650 °C to 1700 °C, and the specific structure is as shown in Figure 9 .

[0106] Step S404: using a gate oxide process to form a gate oxide layer 42 in the primary trench 501, and backfilling to form a conductive material layer 411, and the specific obtained initial gate 402 is as shown in Figure 10 . Of course, in some embodiments, a sacrificial oxide layer (not shown) covering the inner surface of the multi-stage trench structure (the primary trench 501 and the secondary trench 502) can be formed before the formal gate oxide growth, which is used to generate a higher quality gate oxide layer.

[0107] For example, the material of the gate conductive layer 41 includes but is not limited to polysilicon.

[0108] For example, the thickness of the gate oxide layer 42 ranges from 45 nm to 55 nm, such as 45 nm, 47 nm, 50 nm, 53 nm or 55 nm. In this embodiment, the thickness of the gate oxide layer 42 is 50 nm.

[0109] Step S406: based on the same mask of the secondary trench 502, a first recess 503 extending along the OZ direction is formed in the gate conductive layer 41. Since the etching has the material selection characteristic, the etching will be automatically cut off on the gate oxide layer 42, and the specific structure is as shown in Figure 11 .

[0110] Step S408: using a deposition process to form an interlayer dielectric layer 20 in the first recess 503 and on the top surface of the epitaxial layer 11, and using a reflow process or a chemical mechanical planarization process to make the top surface flat, and the specific structure is as shown in Figure 12 .

[0111] For example, the material of the interlayer dielectric layer 20 includes, but is not limited to, high-k dielectric constant material formation. For example, aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxide nitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3), etc.

[0112] Step S410: etching the interlayer dielectric layer 20 to form contact holes (second recess 601, third recess 602) arranged alternately along the OY direction; the third recess 602 extends to the base region 112 along the OZ direction, and the specific structure is as shown in Figure 13

[0113] Step S412: after the ohmic contact of the power device structure obtained in step S410 is made, a metal layer 30 is formed to fill the second recess and the third recess, and cover the top surface of the interlayer dielectric layer 20, and the specific structure is as shown in Figure 14

[0114] It should be understood that, Figure 14 The illustration of forming an ohmic contact P-type heavily doped region with the epitaxial layer 11 is omitted, which should not affect the normal understanding of those skilled in the art. In addition, after step S40, a back surface thinning process and back surface metallization are performed on the power device structure prepared by step S412, and the specific structure is as shown in Figure 15

[0115] In some embodiments, the present application also provides an electronic device, and the present application also provides an electronic device comprising the power device as described in any one of the above embodiments; or comprising the power device prepared by the preparation method as described in any one of the above embodiments.

[0116] Since the electronic device of the above-mentioned embodiments and the power device and the preparation method thereof provided by the present application are based on the same inventive concept, the electronic device using the power device has all the advantages of the power device provided by the present application, and therefore, will not be described one by one here.

[0117] In the above-mentioned embodiments, the unexpected technical effect of the present application is:

[0118] Compared with the trench gate transistor in the prior art, the power device provided by the present application has a two-stage structure (first stage and second stage), and cooperates with the shielding region at the bottom as an electric field shielding layer during reverse bias, so as to protect the trench bottom, shield the high electric field, ensure that the channel density is basically not damaged, and significantly enhance the gate oxide reliability of the device, thereby reducing the requirement for the gate oxide process.

[0119] ​​​Meanwhile, by designing the interlayer dielectric layer to split the gate, the facing area of the gate and the drain terminal is reduced, and the gate-drain capacitance C gd The metal layer is inserted between the two gate conductive layers as the first source terminal, and by adjusting the depth of the first source terminal inserted into the gate and the thickness in the extension, the size of the gate-source capacitance C gs Thus, the C gs / C gd is obtained to meet the application requirements.

[0120] In addition, the preparation method provided by the present application has high compatibility with the existing mainstream process platform, excellent process realizability, and outstanding engineering practical value.

[0121] The technical features of the above embodiments can be combined in any manner, and to make the description concise, all possible combinations of the technical features of the above embodiments are not described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0122] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A power device, characterized by, The power device comprises: a substrate, a first surface of the substrate comprising an epitaxial layer; the epitaxial layer comprising a source region, a base region, and a shield region arranged along a first direction towards the substrate via a top surface; a plurality of gates spaced along a second direction parallel to the first surface and penetrating the source region, the base region, and partially embedded in the shield region along the first direction; the gate comprising a gate conductive layer and a gate oxide layer arranged along the first direction; a gate trench of the gate comprising a primary trench and a secondary trench extending into the shield region along the first direction via a bottom surface of the primary trench; an interlayer dielectric layer on the top surface of the epitaxial layer, comprising an extension penetrating the gate conductive layer and contacting the gate oxide layer along the first direction; the extension filling the secondary trench; the extension and the interlayer dielectric layer are simultaneously prepared in the same process step; a metal layer on the top surface of the interlayer dielectric layer, comprising: a first source electrode extending into the gate via the top surface of the extension; the width and the depth of the first source electrode are related to the gate-source capacitance of the power device; wherein the width is used to represent the size along the second direction; the depth is used to represent the size along the first direction; wherein the first recess required for etching the extension has the same mask as the mask for etching the secondary trench.

2. The power device of claim 1, wherein, the top surface of the secondary trench is lower than the bottom surface of the base region, and partially embedded in the shield region; the bottom surface of the extension is within the top surface of the gate oxide layer of the secondary trench; the width of the secondary trench is smaller than the width of the primary trench.

3. The power device of claim 2, wherein, the width of the shield region is greater than the width of the secondary trench and smaller than the width of the primary trench; the depth of the first source electrode is not greater than the depth of the gate conductive layer.

4. The power device of claim 1, wherein, the width and the depth of the first source electrode are related to the gate-source capacitance of the power device, comprising: the depth of the first source electrode is positively correlated with the gate-source capacitance of the power device; the width of the first source electrode is negatively correlated with the gate-source capacitance of the power device.

5. The power device of claim 3, wherein, the gate and the interlayer dielectric layer are simultaneously prepared in the same process step.

6. The power device according to any one of claims 2 to 5, characterized in that, the metal layer further comprises: a second source electrode extending along the first direction to partially embed in the base region via the top surface of the interlayer dielectric layer.

7. A method of manufacturing a power device, characterized by, A method for preparing the power device as claimed in any one of claims 1-6, the method comprising: providing a substrate, a first surface of the substrate comprising an epitaxial layer; the epitaxial layer comprising a source region, a base region, and a shield region arranged along a first direction towards the substrate via a top surface; forming a plurality of gates on the epitaxial layer after forming the gates spaced along a second direction parallel to the first surface and penetrating the source region, the base region, and partially embedded in the shield region along the first direction; the gate comprising a gate conductive layer and a gate oxide layer arranged along the first direction; the interlayer dielectric layer comprising an extension penetrating the gate conductive layer and contacting the gate oxide layer along the first direction; ​ The metal layer comprises: a first source electrode extending into the gate via the top surface of the extension; the width and depth of the first source electrode are related to the gate-source capacitance of the power device; the width is used to represent the size along the second direction; and the depth is used to represent the size along the first direction.

8. The preparation method according to claim 7, characterized in that, The shield region is formed by: forming a sacrificial layer in the first-level trench; removing part of the sacrificial layer to form a second-level trench extending through the sacrificial layer and reaching the epitaxial layer along the first direction; the width of the second-level trench is smaller than the width of the first-level trench; performing ion implantation on the epitaxial layer at the bottom of the second-level trench to form the shield region.

9. The preparation method according to claim 8, characterized in that, The gate, the interlayer dielectric layer and the metal layer are formed by: forming an initial gate in the first-level trench after removing the sacrificial layer; forming a first recess in the initial gate based on the same mask used for the second-level trench; forming the interlayer dielectric layer on the top surface of the epitaxial layer and in the first recess; forming a second recess and a third recess in the interlayer dielectric layer, which are arranged alternately along the second direction; the third recess extends to the base region along the first direction; forming a metal layer filling the second recess and the third recess and covering the top surface of the interlayer dielectric layer; the metal layer in the second recess is used to form a first source electrode, and the metal layer in the third recess is used to form a second source electrode.

10. An electronic device, comprising: The power device comprises: the power device according to any one of claims 1-6; or the power device prepared by the preparation method according to any one of claims 7-9.

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