A method of preparing a silicon epitaxial wafer from a heavily doped silicon single crystal substrate and an epitaxial wafer formed thereby
By employing carbon and oxygen co-doping technology and high-temperature hydrogen pretreatment on heavily doped silicon single crystal substrates, carbon-oxygen co-precipitated layer faults are formed, solving the problem of boron or phosphorus diffusion during high-temperature thermal processes in heavily doped silicon epitaxial wafers. This improves the device's withstand voltage performance and internal gettering capability, and reduces production costs.
CN120797198BActive Publication Date: 2025-12-23ZHONG JING (JIA XING) SEMICON CO LTD
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Patent Information
- Application Number
- CN202511321399.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-16
- Publication Date
- 2025-12-23
- Estimated Expiration
- 2045-09-16
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Figure CN120797198B_ABST
Abstract
The application discloses a method for preparing a silicon epitaxial wafer from a heavily doped silicon single crystal substrate and an epitaxial wafer formed by the method. The method is as follows: a carbon-oxygen co-doped heavily boron or phosphorus straight-drawn single crystal silicon wafer is used as a substrate, the substrate is pre-treated by epitaxial high-temperature hydrogen, then the temperature is increased to an epitaxial temperature to further grow an epitaxial layer, and finally a high-quality silicon epitaxial wafer is prepared. The high-temperature hydrogen pre-treatment step is as follows: the temperature is increased to 1200-1250 DEG C at a rate of 40-60 DEG C / s, kept for 150-300 s, then the temperature is decreased to 600-800 DEG C at a rate of 20-50 DEG C / s, and kept for 30-120 s. The silicon epitaxial wafer prepared by the method can form a high-density carbon-promoted carbon-oxygen co-precipitation induced stacking fault layer with a certain width under a clean area of a substrate surface layer after a device heat processing process, the silicon epitaxial wafer has the characteristics of absorbing self-interstitials and inhibiting boron or phosphorus outward diffusion, and a device with stable voltage resistance and strong impurity gettering capability can be obtained.
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