Voltage and current conversion circuit

Abstract

The invention provides a voltage and current conversion circuit. A transmission gate control signal generation sub-circuit generates two paths of non-overlapped sub-clock signals; the plurality of transmission gate sub-circuits are switched on or switched off according to two paths of non-overlapped sub-clock signals to control the first operational amplifier sub-circuit and the second operational amplifier sub-circuit to work alternately; the first offset elimination sub-circuit is configured to store the offset voltage of the first operational amplifier sub-circuit when the second operational amplifier sub-circuit works, and eliminate the offset voltage when the first operational amplifier sub-circuit works; the second offset elimination sub-circuit is configured to store the offset voltage of the second operational amplifier sub-circuit when the first operational amplifier sub-circuit works, and eliminate the offset voltage when the second operational amplifier sub-circuit works; the output stage sub-circuit is configured to output the converted current and provide feedback voltage for the first operational amplifier sub-circuit and the second operational amplifier sub-circuit. Therefore, the offset voltage is eliminated, and the performance of the voltage-current conversion circuit is further improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a voltage-to-current conversion circuit. BACKGROUND

[0002] In the design of analog integrated circuits, voltage-to-current conversion circuits are key modules for building accurate current sources. Traditional schemes use a single operational amplifier (op-amp) structure to convert a reference voltage into an output current through negative feedback. However, when dealing with millivolt-level low voltage signals, the inherent offset voltage of the op-amp can significantly affect the conversion accuracy. For example, at a 50mV reference voltage, an offset voltage of ±2mV can result in a current error of ±4%, and when the reference voltage drops to 20mV, the error can be as high as ±10%. This accuracy degradation can severely impact the performance of circuits that rely on accurate current sources.

[0003] Therefore, how to improve the op-amp accuracy and thus improve the performance of the voltage-to-current conversion circuit is a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0004] The present application provides a voltage-to-current conversion circuit to solve the defect that the op-amp accuracy is low in the prior art, resulting in poor performance of the voltage-to-current conversion circuit.

[0005] In one aspect, the present application provides a voltage-to-current conversion circuit, comprising a transmission gate control signal generation sub-circuit, a first op-amp sub-circuit, a second op-amp sub-circuit, a first offset cancellation sub-circuit, a second offset cancellation sub-circuit, a plurality of transmission gate sub-circuits, and an output stage sub-circuit.

[0006] The transmission gate control signal generation sub-circuit is configured to receive a clock signal and generate two non-overlapping sub-clock signals.

[0007] The plurality of transmission gate sub-circuits are configured to be turned on or turned off according to the two non-overlapping sub-clock signals to control the first op-amp sub-circuit and the second op-amp sub-circuit to work alternately.

[0008] The first offset cancellation sub-circuit is configured to store the offset voltage of the first op-amp sub-circuit when the second op-amp sub-circuit is working, and to cancel the offset voltage when the first op-amp sub-circuit is working.

[0009] The second offset cancellation sub-circuit is configured to store the offset voltage of the second op-amp sub-circuit when the first op-amp sub-circuit is working, and to cancel the offset voltage when the second op-amp sub-circuit is working.

[0010] The output stage sub-circuit is configured to output the converted current and provide a feedback voltage to the first op-amp sub-circuit and the second op-amp sub-circuit.

[0011] According to the voltage current conversion circuit provided by the application, the plurality of transmission gate sub-circuits comprises a first transmission gate input module, a second transmission gate input module and a first transmission gate output module;

[0012] The input end of the first transmission gate input module is electrically connected with the feedback voltage end of the output stage sub-circuit; the control end of the first transmission gate input module is electrically connected with the transmission gate control signal generation sub-circuit; and the output end of the first transmission gate input module is electrically connected with the first input end of the first operational amplifier sub-circuit.

[0013] The input end of the second transmission gate input module is electrically connected with the reference voltage end; the control end of the second transmission gate input module is electrically connected with the transmission gate control signal generation sub-circuit; and the output end of the second transmission gate input module is electrically connected with the first input end of the first operational amplifier sub-circuit.

[0014] The second input end of the first operational amplifier sub-circuit is electrically connected with the feedback voltage end.

[0015] When the second level signal in the non-overlapping sub-clock signal is input to the control end of the first transmission gate input module, the feedback voltage is input to the two input ends of the first operational amplifier sub-circuit respectively, so that the first offset elimination sub-circuit stores the offset voltage of the first operational amplifier sub-circuit.

[0016] When the first level signal in the non-overlapping sub-clock signal is input to the control end of the second transmission gate input module, the reference voltage of the reference voltage end is input to the first input end of the first operational amplifier sub-circuit, and the feedback voltage is input to the second input end of the first operational amplifier sub-circuit, and the reference voltage and the feedback voltage are compared to adjust the output signal of the first operational amplifier sub-circuit.

[0017] According to the voltage current conversion circuit provided by the application, the first operational amplifier sub-circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor.

[0018] The first offset elimination sub-circuit comprises a first capacitor, and the plurality of transmission gate sub-circuits comprises a fifth transmission gate input module.

[0019] The first pole of the first transistor is electrically connected with the output end of a first current source and the first pole of the second transistor.

[0020] The control pole of the first transistor is electrically connected with the output end of the first transmission gate input module and the output end of the second transmission gate input module.

[0021] The second electrode of the first transistor is electrically connected with the second electrode of the third transistor, the input end of the fifth transmission gate input module and the input end of the first transmission gate output module;

[0022] The control electrode of the second transistor is electrically connected with the feedback voltage end;

[0023] The second electrode of the second transistor is electrically connected with the second electrode of the fourth transistor and the control electrode of the fourth transistor;

[0024] The first electrode of the third transistor is electrically connected with the ground end and the second end of the first capacitor;

[0025] The control electrode of the third transistor is electrically connected with the output end of the fifth transmission gate input module and the first end of the first capacitor;

[0026] The first electrode of the fourth transistor is electrically connected with the ground end.

[0027] According to the voltage current conversion circuit, the input end of the third transmission gate input module is electrically connected with the feedback voltage end of the output stage sub-circuit; the control end of the third transmission gate input module is electrically connected with the transmission gate control signal generation sub-circuit; and the output end of the third transmission gate input module is electrically connected with the first input end of the second operational amplifier sub-circuit;

[0028] The input end of the fourth transmission gate input module is electrically connected with the reference voltage end; the control end of the fourth transmission gate input module is electrically connected with the transmission gate control signal generation sub-circuit; and the output end of the fourth transmission gate input module is electrically connected with the first input end of the second operational amplifier sub-circuit;

[0029] The second input end of the second operational amplifier sub-circuit is electrically connected with the feedback voltage end;

[0030] When the second level signal in the non-overlapping sub-clock signal is input to the control end of the third transmission gate input module, the feedback voltage is input to the two input ends of the second operational amplifier sub-circuit, so that the second offset cancellation sub-circuit stores the offset voltage of the second operational amplifier sub-circuit;

[0031] When the first level signal in the non-overlapping sub-clock signal is input to the control end of the fourth transmission gate input module, the reference voltage of the reference voltage end is input to the first input end of the second operational amplifier sub-circuit, and the feedback voltage is input to the second input end of the second operational amplifier sub-circuit; the reference voltage and the feedback voltage are compared, and the output signal of the second operational amplifier sub-circuit is adjusted.

[0032] The second operational amplifier sub-circuit comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor;

[0033] The second offset cancellation sub-circuit comprises a second capacitor, and the plurality of transmission gate sub-circuits comprise a sixth transmission gate input module;

[0034] The first pole of the fifth transistor is electrically connected with the output end of the second current source and the first pole of the sixth transistor;

[0035] The control pole of the fifth transistor is electrically connected with the output end of the third transmission gate input module and the output end of the fourth transmission gate input module;

[0036] The second pole of the fifth transistor is electrically connected with the second pole of the seventh transistor, the input end of the sixth transmission gate input module and the input end of the second transmission gate output module;

[0037] The control pole of the sixth transistor is electrically connected with the feedback voltage end;

[0038] The second pole of the sixth transistor is electrically connected with the second pole of the eighth transistor and the control pole of the eighth transistor;

[0039] The first pole of the seventh transistor is electrically connected with the ground end and the second end of the second capacitor;

[0040] The control pole of the seventh transistor is electrically connected with the output end of the sixth transmission gate input module and the first end of the first capacitor;

[0041] The first pole of the eighth transistor is electrically connected with the ground end.

[0042] The output stage sub-circuit comprises a ninth transistor, a tenth transistor, an eleventh transistor and a resistor;

[0043] The control pole of the ninth transistor is electrically connected with the output end of the first operational amplifier sub-circuit and the output end of the second operational amplifier sub-circuit;

[0044] The first pole of the ninth transistor is electrically connected with the first end of the resistor, and the feedback voltage is outputted;

[0045] The second end of the resistor is electrically connected with the ground end;

[0046] The second pole of the ninth transistor is electrically connected with the second pole of the tenth transistor, the control pole of the tenth transistor and the control pole of the eleventh transistor;

[0047] The first electrode of the tenth transistor and the first electrode of the eleventh transistor are electrically connected with a voltage terminal.

[0048] The output stage sub-circuit further comprises a filtering module.

[0049] The control electrode of the ninth transistor is electrically connected with the output terminals of the first operational amplifier sub-circuit and the second operational amplifier sub-circuit through the filtering module.

[0050] The filtering module comprises a third capacitor, a fourth capacitor and a twelfth transistor.

[0051] The control electrode of the ninth transistor is electrically connected with a third current source, the first terminal of the third capacitor and the second electrode of the twelfth transistor.

[0052] The first electrode of the twelfth transistor is electrically connected with a grounding terminal.

[0053] The control electrode of the twelfth transistor is electrically connected with the second terminal of the third capacitor and the first terminal of the fourth capacitor.

[0054] The second terminal of the fourth capacitor is electrically connected with the grounding terminal.

[0055] The transmission gate control signal generation sub-circuit comprises a first logic gate, a second logic gate, a first inversion module, a second inversion module and a third inversion module.

[0056] The first input terminal of the first logic gate is electrically connected with a clock signal terminal.

[0057] The second input terminal of the first logic gate is electrically connected with the output terminal of the second logic gate.

[0058] The output terminal of the first logic gate is electrically connected with the input terminal of the first inversion module.

[0059] The output terminal of the first inversion module is electrically connected with the control terminals of the first part of the plurality of transmission gate sub-circuits.

[0060] The first input terminal of the second logic gate is electrically connected with the output terminal of the first logic gate.

[0061] The second input terminal of the second logic gate is electrically connected with the output terminal of the second inversion module.

[0062] The output terminal of the second logic gate is further electrically connected with the input terminal of the third inversion module.

[0063] The input terminal of the second inversion module is electrically connected with the clock signal terminal.

[0064] The output end of the third inversion module is electrically connected to the control end of the second part of the plurality of transmission gate sub-circuits.

[0065] According to the voltage current conversion circuit provided by the application, the first logic gate and the second logic gate are both NAND gates.

[0066] The voltage current conversion circuit provided by the application separates the working period of the operational amplifier and the calibration period in the time dimension through the cooperation of the double operational amplifiers and the dynamic offset storage mechanism, so that each operational amplifier can obtain the accurate offset compensation stored in the previous period in the effective working period, thereby breaking through the limitation of the offset voltage of the device itself on the system accuracy. In this way, the effective elimination of the offset voltage of the operational amplifier under the condition of low voltage input makes the voltage to current conversion accuracy no longer limited by the inherent characteristics of the operational amplifier device, and the voltage current conversion circuit is particularly suitable for integrated circuit application scenarios that require high-precision micro-current generation, and the accuracy and reliability of the voltage current conversion circuit are improved. BRIEF DESCRIPTION OF DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the application or prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0068] Figure 1 is a structural schematic diagram of the existing voltage current conversion circuit;

[0069] Figure 2 is a structural schematic diagram of the voltage current conversion circuit of the application;

[0070] Figure 3 is a structural schematic diagram of the transmission gate control signal generation sub-circuit. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical scheme and advantages of the application more clear, the technical scheme in the application will be described clearly and completely in combination with the drawings in the application. Obviously, the described embodiments are some embodiments of the application, not all embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the application.

[0072] In the present application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. In the case of using MOS tubes with opposite polarities or in the case of changing the current direction in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes exchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be exchanged.

[0073] Figure 1 is a structural schematic diagram of an existing voltage current conversion circuit, as Figure 1 shown, the voltage current conversion circuit can include an operational amplifier U0, a regulating tube MN0 (which can be an NMOS tube), a resistor R, and two PMOS tubes; the operational amplifier U0 has a reference voltage Vref input at the positive terminal, and through negative feedback adjustment, the positive terminal and the negative terminal voltage are equal, and the converted current is Vref / R0; if Vref is in the millivolt level, when Vref=50mV, the offset voltage of the ordinary operational amplifier is about ±2mV, and then the converted current will have an error of ±4%; if Vref is smaller than 50mV, the converted current accuracy will become worse (for example, when Vref is 20mV, the error will increase to ±10%), the current source accuracy is not high, and the circuit performance will be poor.

[0074] Therefore, in order to solve the above problems, it is found through research that the traditional single operational amplifier structure has inherent defects in the elimination of offset voltage, and the embodiment provides a dynamic offset voltage cancellation through time division multiplexing double operational amplifier structure. The core idea is to use a clock signal to control two sets of operational amplifiers to work alternately, when one set of operational amplifier is in working state, the other set of operational amplifier stores the offset voltage, and the stored offset information is kept by the capacitor and compensated in the subsequent working period, thereby breaking through the limitation of single operational amplifier offset voltage on system accuracy.

[0075] Specifically, Figure 2 is a structural schematic diagram of a voltage current conversion circuit of the present application, as Figure 2As shown, the voltage-current conversion circuit of the embodiment can include a transmission gate control signal generation sub-circuit, a first operational amplifier sub-circuit 21, a second operational amplifier sub-circuit 22, a first offset cancellation sub-circuit 23, a second offset cancellation sub-circuit 24, a plurality of transmission gate sub-circuits, and an output stage sub-circuit 25. The transmission gate control signal generation sub-circuit receives a clock signal to generate two non-overlapping sub-clock signals, where the first level signal of the non-overlapping sub-clock signals can be denoted as S0C1, and the second level signal can be denoted as S0C2. The two operational amplifier sub-circuits are controlled to work alternately by the transmission gate sub-circuits. The first offset cancellation sub-circuit 23 stores the offset voltage of the first operational amplifier sub-circuit 21 when the second operational amplifier sub-circuit 22 is working, and cancels the offset voltage when the first operational amplifier sub-circuit 21 is working. The second offset cancellation sub-circuit 24 performs a symmetric operation. The output stage sub-circuit 25 outputs a conversion current and provides a feedback voltage Vf to the input terminals of the first operational amplifier sub-circuit 21 and the second operational amplifier sub-circuit 22.

[0076] In a specific implementation process, the transmission gate control signal generation sub-circuit refers to a logic circuit that generates control signals with a non-overlapping timing relationship, which can be implemented by combining NAND gates and inverters to ensure that the two control signals are not in an active state at the same time, avoiding conflicts in the working state of the operational amplifier.

[0077] The first operational amplifier sub-circuit 21 and the second operational amplifier sub-circuit 22 refer to differential amplifiers with the same circuit structure, which can be implemented by PMOS and NMOS, respectively, to be responsible for voltage comparison functions under different clock phases.

[0078] The first offset cancellation sub-circuit 23 and the second offset cancellation sub-circuit 24 refer to voltage holding circuits containing storage capacitors, which can be implemented by capacitors to capture the operational amplifier offset voltage in the non-working phase and inject compensation voltage in the working phase.

[0079] The plurality of transmission gate sub-circuits refer to analog switches composed of NMOS and PMOS in parallel, which are turned on or off according to the control signal to realize the dynamic switching of the input terminals of the operational amplifier.

[0080] The output stage sub-circuit 25 refers to a current output module containing an adjustment tube (the ninth transistor T9) and a resistor R, which can be implemented by a common source amplification structure in cooperation with a current mirror to convert a voltage signal into a stable current output.

[0081] Specifically, the transmission gate control signal generating sub-circuit converts the external clock signal into two-phase complementary control signals to drive two groups of transmission gate sub-circuits respectively. When the first level signal SOC1 is valid, the first operational amplifier sub-circuit 21 is connected to compare the feedback voltage Vf with the reference voltage, and the second operational amplifier sub-circuit 22 stores the current offset information through the offset cancellation sub-circuit. After the control signal is switched, the second operational amplifier sub-circuit 22 enters the working state to perform voltage comparison, and at this time, the offset cancellation sub-circuit of the first operational amplifier sub-circuit 21 injects the stored offset voltage into the input channel for compensation. The two operational amplifier sub-circuits alternately perform signal processing and offset calibration through clock control, and the output stage sub-circuit 25 integrates the output signals of the two operational amplifiers to generate a stable current proportional to the input voltage through the feedback resistor R.

[0082] In the embodiment, the dual operational amplifier is used to separate the operational amplifier working period and the calibration period in the time dimension through the dynamic offset storage mechanism, so that each operational amplifier can obtain the accurate offset compensation stored in the previous period in the effective working period, thereby breaking the limitation of the device itself offset voltage on the system precision.

[0083] Through the above technical solution, the operational amplifier offset voltage is effectively eliminated under the condition of low voltage input, so that the voltage-to-current conversion precision is no longer limited by the inherent characteristics of the operational amplifier device, and the application is particularly suitable for integrated circuit application scenarios requiring high-precision micro-current generation.

[0084] Continuing to refer to Figure 2In the voltage-current conversion circuit of the embodiment, the plurality of transmission gate sub-circuits include a first transmission gate input module TG1, a second transmission gate input module TG2, and a first transmission gate output module TG7; the input end of the first transmission gate input module TG1 is electrically connected with the feedback voltage end of the output stage sub-circuit 25, the control end is electrically connected with the transmission gate control signal generation sub-circuit, and the output end is electrically connected with the first input end of the first operational amplifier sub-circuit 21; the input end of the second transmission gate input module TG2 is electrically connected with the reference voltage end, the control end is electrically connected with the transmission gate control signal generation sub-circuit, and the output end is electrically connected with the first input end of the first operational amplifier sub-circuit 21; the second input end of the first operational amplifier sub-circuit 21 is electrically connected with the feedback voltage end; when the second level signal SOC2 in the non-overlapping sub-clock signals is input to the control end of the first transmission gate input module TG1, the feedback voltage Vf is input to the two input ends of the first operational amplifier sub-circuit 21, so that the first offset cancellation sub-circuit 23 stores the offset voltage of the first operational amplifier sub-circuit 21; when the first level signal SOC1 in the non-overlapping sub-clock signals is input to the control end of the second transmission gate input module TG2, the reference voltage Vref of the reference voltage end is input to the first input end of the first operational amplifier sub-circuit 21, the feedback voltage Vf is input to the second input end of the first operational amplifier sub-circuit 21, and the reference voltage Vref of the reference voltage end is compared with the feedback voltage Vf to adjust the output signal of the first operational amplifier sub-circuit 21.

[0085] The first transmission gate input module TG1 refers to an input path for signal on-off control realized by a transmission gate structure, which can be realized by a complementary transmission gate composed of parallel-connected NMOS and PMOS transistors, and the on-off state thereof is determined by the sub-clock signal received by the control end. The second transmission gate input module TG2 refers to another independently controlled input path, which has a similar structure to the first transmission gate input module TG1, but the input end is connected to the reference voltage Vref instead of the feedback voltage Vf. The first input end of the first operational amplifier sub-circuit 21 refers to one of the positive or negative input ends of the operational amplifier, and the polarity is determined according to the circuit design requirements. The first level signal SOC1 and the second level signal SOC2 in the non-overlapping sub-clock signals refer to two kinds of logic level signals whose phases do not overlap, such as time sequence control signals of high level signals and low level signals alternately switched, which are used to avoid the competition risk phenomenon in the signal transmission process.

[0086] Specifically, two non-overlapping sub-clock signals generated by the transmission gate control signal generation sub-circuit are applied to the control terminals of the first transmission gate input module TG1 and the second transmission gate input module TG2 respectively. When the second level signal SOC2 is valid, the first transmission gate input module TG1 is turned on, and the feedback voltage Vf is connected to the two input terminals of the first operational amplifier sub-circuit 21 at the same time. At this time, the operational amplifier is in the offset voltage sampling stage, and the voltage difference at the input terminal is stored in the capacitor in the first offset elimination sub-circuit 23. When the first level signal SOC1 is valid, the second transmission gate input module TG2 is turned on, and the reference voltage Vref is connected to the first input terminal of the first operational amplifier sub-circuit 21, while the feedback voltage Vf is still connected through the second input terminal of the first operational amplifier sub-circuit 21. At this time, the operational amplifier enters the normal working stage, generates the output signal by comparing the reference voltage Vref and the feedback voltage Vf, and simultaneously performs real-time compensation using the offset voltage stored in the previous stage. This time-sharing switching mode makes the offset voltage of the operational amplifier be dynamically eliminated in each working period.

[0087] Compared with the traditional voltage conversion circuit, the traditional voltage current conversion circuit adopts a single operational amplifier structure and does not set a time-sharing switching transmission gate module, resulting in that the offset voltage is directly superimposed in the input signal. In the embodiment, the time-sharing multiplexing of the operational amplifier input terminal is realized through the modular transmission gate structure, the offset voltage sampling and signal processing stage are separated in the time dimension, so that the cumulative influence of the offset voltage on the conversion precision is avoided.

[0088] Through the above technical solutions, the present application can accurately control the signal switching timing of the operational amplifier input terminal, effectively eliminate the influence of the inherent offset voltage of the operational amplifier on the feedback loop in the low voltage conversion scene. The structure realizes dynamic error compensation without increasing additional calibration circuit through the cooperative work of hardware modules, and significantly improves the linearity and stability of voltage current conversion.

[0089] Continuing to refer to Figure 2In the voltage current conversion circuit of the embodiment, the first operational amplifier sub-circuit 21 comprises a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4; the first offset cancellation sub-circuit 23 comprises a first capacitor C1; and the plurality of transmission gate sub-circuits comprise a fifth transmission gate input module TG5. The first pole of the first transistor T1 is electrically connected with the output end of a first current source I1 and the first pole of the second transistor T2; the control pole of the first transistor T1 is electrically connected with the output end of a first transmission gate input module TG1 and the output end of a second transmission gate input module TG2; the second pole of the first transistor T1 is electrically connected with the second pole of the third transistor T3, the input end of the fifth transmission gate input module TG5 and the input end of a first transmission gate output module TG7; the control pole of the second transistor T2 is electrically connected with a feedback voltage end; the second pole of the second transistor T2 is electrically connected with the second pole of the fourth transistor T4 and the control pole of the fourth transistor T4; the first pole of the third transistor T3 is electrically connected with a ground end GND and the second end of the first capacitor C1; the control pole of the third transistor T3 is electrically connected with the output end of the fifth transmission gate input module TG5 and the first end of the first capacitor C1; and the first pole of the fourth transistor T4 is electrically connected with the ground end GND.

[0090] The first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 refer to MOS transistors constituting a differential input pair and a current mirror structure, which can be implemented by a combination of PMOS and NMOS, for amplifying an input voltage difference and generating an output current. The first transistor T1 and the second transistor T2 can be PMOS transistors, and the third transistor T3 and the fourth transistor T4 can be NMOS transistors. The first capacitor C1 refers to a capacitor element for storing an offset voltage, which can be implemented by a metal-insulator-metal structure, and is connected at both ends with the control pole of the third transistor T3 and the ground end GND, for storing the offset voltage of the operational amplifier sub-circuit at a specific clock stage. The fifth transmission gate input module TG5 refers to a switching circuit composed of transmission gates, which can be implemented by complementary MOS transmission gates, and is connected at the input end with the second pole of the first transistor T1 and at the output end with the control pole of the third transistor T3, for controlling the connection state of the capacitor and the operational amplifier sub-circuit according to a clock signal.

[0091] Specifically, the first operational amplifier sub-circuit 21 is formed by the first transistor T1 and the second transistor T2 as a differential input pair, and the third transistor T3 and the fourth transistor T4 as a current mirror load. When the fifth transmission gate input module TG5 is turned on, the first capacitor C1 is connected to the control electrode of the third transistor T3, and at this time, the offset voltage of the operational amplifier sub-circuit is stored in the first capacitor C1; when the fifth transmission gate input module TG5 is turned off, the first capacitor C1 keeps the stored voltage value, so that the potential of the control electrode of the third transistor T3 is fixed, thereby offsetting the offset voltage during the operation of the operational amplifier sub-circuit. By controlling the conduction and non-conduction of the fifth transmission gate input module TG5 through the clock signal, the periodic storage and compensation of the offset voltage are realized, so that the operational amplifier sub-circuit can eliminate the influence of its own offset on the output voltage in the alternating operation stage.

[0092] Compared with the traditional operational amplifier sub-circuit, the traditional operational amplifier sub-circuit directly adjusts the output voltage through the feedback loop, and the offset voltage directly affects the comparison result of the feedback voltage Vf and the reference voltage. In the embodiment, the first capacitor C1 and the fifth transmission gate input module TG5 are additionally arranged, the offset voltage is stored in the capacitor during the non-operation stage of the operational amplifier sub-circuit, and the stored voltage is used to offset the actual offset during the operation stage, so that the dynamic compensation of the offset voltage is realized at the circuit structure level.

[0093] Through the above technical solution, the influence of the offset voltage of the operational amplifier sub-circuit on the voltage-current conversion precision can be effectively eliminated, and especially when processing millivolt-level low-voltage signals, the current output error caused by the input offset of the operational amplifier can be significantly reduced, and the overall precision of the conversion circuit is improved.

[0094] Continuing to refer to Figure 2In the voltage current conversion circuit of the embodiment, the plurality of transmission gate sub-circuits comprises a third transmission gate input module TG3, a fourth transmission gate input module TG4 and a second transmission gate output module TG8; the input end of the third transmission gate input module TG3 is electrically connected with the feedback voltage end of the output stage sub-circuit 25, the control end is electrically connected with the transmission gate control signal generation sub-circuit, and the output end is electrically connected with the first input end of the second operational amplifier sub-circuit 22; the input end of the fourth transmission gate input module TG4 is electrically connected with the reference voltage end, the control end is electrically connected with the transmission gate control signal generation sub-circuit, and the output end is electrically connected with the first input end of the second operational amplifier sub-circuit 22; the second input end of the second operational amplifier sub-circuit 22 is electrically connected with the feedback voltage end; when the first level signal SOC1 in the non-overlapping sub-clock signal is input to the control end of the third transmission gate input module TG3, the feedback voltage Vf is input to the two input ends of the second operational amplifier sub-circuit 22, so that the second offset cancellation sub-circuit 24 stores the offset voltage of the second operational amplifier sub-circuit 22; when the second level signal SOC2 in the non-overlapping sub-clock signal is input to the control end of the fourth transmission gate input module TG4, the reference voltage of the reference voltage end is input to the first input end of the second operational amplifier sub-circuit, the feedback voltage Vf is input to the second input end of the second operational amplifier sub-circuit, and the reference voltage Vref of the reference voltage end is compared with the feedback voltage Vf to adjust the output signal of the second operational amplifier sub-circuit 22.

[0095] The fourth transmission gate input module TG4 refers to a functional module for transmitting the reference voltage signal to the input end of the second operational amplifier sub-circuit 22, which can be realized by a CMOS transmission gate structure, and its conduction state is controlled by the clock signal output by the transmission gate control signal generation sub-circuit. The third transmission gate input module TG3 refers to a functional module for transmitting the feedback voltage Vf signal to the input end of the second operational amplifier sub-circuit 22, which can be realized by a transmission gate circuit composed of parallel-connected NMOS and PMOS transistors, and its conduction state is also controlled by the clock signal. The second transmission gate output module TG8 refers to a functional module for transmitting the output signal of the second operational amplifier sub-circuit 22 to the output stage sub-circuit 25, which can be realized by combining a transmission gate with a filter circuit. The non-overlapping sub-clock signal refers to two clock signals with complementary phases and no overlap, which is generated by frequency division and shaping of the original clock signal through a logic gate circuit, and is used to ensure that the switching action of the transmission gate module will not cause signal conflict.

[0096] Specifically, when the first level signal SOC1 is input to the control end of the third transmission gate input module TG3, the module is turned on and simultaneously loads the feedback voltage Vf to the two input ends of the second operational amplifier sub-circuit 22, at this time, the second operational amplifier sub-circuit 22 is in the offset voltage storage stage, and the working state of the internal transistor is recorded and maintained by the capacitor in the second offset elimination sub-circuit 24. When the second level signal SOC2 is input to the control end of the fourth transmission gate input module TG4, the module is turned on and loads the reference voltage to the first input end of the second operational amplifier sub-circuit 22, and simultaneously loads the feedback voltage Vf to the second input end of the second operational amplifier sub-circuit 22, at this time, the second operational amplifier sub-circuit 22 enters the normal working stage, and the output signal thereof is adjusted according to the difference between the reference voltage Vref and the feedback voltage Vf, and is transmitted to the output stage sub-circuit 25 through the second transmission gate output module TG8. In this process, the second offset elimination sub-circuit 24 offsets the inherent offset voltage of the second operational amplifier sub-circuit 22 by using the stored voltage, so that the comparison result of the reference voltage Vref and the feedback voltage Vf is not affected by the internal parameter deviation of the operational amplifier.

[0097] Compared with the traditional voltage current conversion circuit, the single operational amplifier structure in the traditional voltage current conversion circuit directly superimposes the offset voltage on the reference voltage when the low voltage is input, resulting in a significant error of the output current. However, by setting the third transmission gate input module TG3 and the fourth transmission gate input module TG4 and cooperating with the non-overlapping clock signal control, the second operational amplifier sub-circuit 22 is periodically switched between the offset storage and normal working states, so that the influence of the operational amplifier offset voltage is limited within a single clock period, and the error accumulation is avoided.

[0098] Through the above technical scheme, the dynamic elimination of the offset voltage of the second operational amplifier sub-circuit 22 is realized, so that in the low voltage input scene, the comparison process of the reference voltage and the feedback voltage Vf is not disturbed by the internal parameter deviation of the operational amplifier, thereby improving the voltage current conversion precision. The scheme automatically compensates the offset voltage when the operational amplifier working state is switched through the synergistic effect of timing control and capacitor storage, and ensures the stability of the output current.

[0099] Continuing to refer to Figure 2In the voltage-current conversion circuit of the embodiment, the second operational amplifier sub-circuit 22 comprises a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8; the second offset cancellation sub-circuit 24 comprises a second capacitor C2; and the transmission gate sub-circuit comprises a sixth transmission gate input module TG6. The first pole of the fifth transistor T5 is connected with the output end of the second current source I2 and the first pole of the sixth transistor T6, the control pole is connected with the output end of the third transmission gate input module TG3 and the fourth transmission gate input module TG4, and the second pole is connected with the second pole of the seventh transistor T7, the input end of the sixth transmission gate input module TG6 and the input end of the second transmission gate output module TG8. The control pole of the sixth transistor T6 is connected with the feedback voltage end, and the second pole is connected with the second pole and the control pole of the eighth transistor T8. The first pole of the seventh transistor T7 is connected with the ground end GND and the second end of the second capacitor C2, the control pole is connected with the output end of the sixth transmission gate input module TG6 and the first end of the second capacitor C2. The first pole of the eighth transistor T8 is connected with the ground end GND.

[0100] The second operational amplifier sub-circuit 22 is a differential input structure composed of the fifth transistor T5 to the eighth transistor T8, which can be realized by a combination of PMOS and NMOS transistors, and is used for comparing the reference voltage Vref with the feedback voltage Vf and outputting an adjustment signal at a specific clock phase. The fifth transistor T5 and the sixth transistor T6 can be PMOS transistors, and the seventh transistor T7 and the eighth transistor T8 can be NMOS transistors. The second capacitor C2 in the second offset cancellation sub-circuit 24 is used for storing the offset voltage of the second operational amplifier sub-circuit 22, and can be realized by a metal-insulator-metal capacitor, the two ends of which are respectively connected with the control pole of the seventh transistor T7 and the ground end GND, so as to keep the voltage stable during clock switching. The sixth transmission gate input module TG6 is a signal path composed of a transmission gate, which can be realized by a CMOS transmission gate, and is used for controlling the connection state between the gate and the drain of the seventh transistor T7 according to the sub-clock signal, so as to establish an offset voltage storage path during the non-working period of the second operational amplifier sub-circuit 22.

[0101] Specifically, when the second level signal SOC2 acts on the fourth transmission gate input module TG4 control end, the reference voltage Vref is input to the first input end of the second operational amplifier sub-circuit 22, and the feedback voltage Vf is connected to the second input end. At this time, the sixth transmission gate input module TG6 is in the off state, so that the gate and drain of the seventh transistor T7 are isolated, and the second capacitor C2 stores the offset voltage of the second operational amplifier sub-circuit 22 through the conduction path. When switching to the first level signal SOC1, the sixth transmission gate input module TG6 is turned on, and the stored offset voltage is applied to the gate of the seventh transistor T7 to offset the error voltage caused by the internal device mismatch of the operational amplifier. By alternately switching the clock signal, the second capacitor C2 continuously retains the offset voltage information in the non-working stage of the second operational amplifier sub-circuit 22, ensuring that the adjustment signal output in the working stage is not affected by the inherent offset.

[0102] Compared with the traditional voltage current conversion circuit, the traditional voltage current conversion circuit adopts a single operational amplifier structure and lacks a dynamic offset compensation mechanism, resulting in a significant error during low voltage conversion. The embodiment realizes the periodic storage and real-time compensation of the operational amplifier offset voltage by setting the second operational amplifier sub-circuit 22 and the special offset elimination sub-circuit, combined with the clock-controlled transmission gate module. This dynamic compensation mechanism breaks through the limitation of relying on device matching accuracy in traditional circuits, significantly reduces the influence of offset voltage on conversion accuracy under the same process conditions.

[0103] Through the above technical scheme, the inherent offset voltage of the second operational amplifier sub-circuit 22 during low voltage operation can be effectively eliminated, and the accurate comparison of the reference voltage and the feedback voltage Vf is ensured. The structure realizes the voltage current conversion process by the periodic storage and compensation mechanism, and is not affected by the internal device mismatch of the operational amplifier, and is particularly suitable for the accurate conversion of millivolt level reference voltage, significantly improving the current output accuracy and system stability.

[0104] Continuing to refer to Figure 2 In the embodiment, the output stage sub-circuit 25 includes the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11 and the resistor R; the control electrode of the ninth transistor T9 is electrically connected with the output end of the first operational amplifier sub-circuit 21 and the output end of the second operational amplifier sub-circuit 22; the first electrode of the ninth transistor T9 is electrically connected with the first end of the resistor R, and outputs the feedback voltage Vf; the second end of the resistor R is electrically connected with the ground end GND; the second electrode of the ninth transistor T9 is electrically connected with the second electrode of the tenth transistor T10, the control electrode of the tenth transistor T10 and the control electrode of the eleventh transistor T11; the first electrode of the tenth transistor T10 and the first electrode of the eleventh transistor T11 are electrically connected with the voltage end.

[0105] The ninth transistor T9 refers to a field effect transistor as an output stage core adjusting element, which can be implemented by an NMOS transistor or a PMOS transistor, the gate of which receives alternating control signals from the two operational amplifiers, the source of which is connected to the ground through a resistor R to form a feedback voltage Vf node, and the drain of which is connected with the current mirror structure. The resistor R refers to an element for converting the output current into a feedback voltage Vf, which can be implemented by a polysilicon resistor R or a diffusion resistor R, and the resistance value thereof is in the range of 1 kΩ to 100 kΩ, which converts the current flowing through the ninth transistor T9 into a voltage signal through Ohm's law. The tenth transistor T10 and the eleventh transistor T11 refer to the pair of elements constituting the current mirror structure, which can be implemented by PMOS transistors of the same size, the gates of which are interconnected and connected with the drain of the ninth transistor T9, and the sources of which are commonly connected to the power supply voltage terminal, which ensures the stability of the output current through the current mirror principle.

[0106] Specifically, the ninth transistor T9 adjusts its conduction state under the control of the alternately working first operational amplifier sub-circuit 21 and the second operational amplifier sub-circuit 22, when the operational amplifier output signal changes, the gate voltage of the ninth transistor T9 changes accordingly, resulting in the feedback voltage Vf at the connection point of the source of the ninth transistor T9 and the resistor R being adjusted accordingly. The resistor R converts the current flowing through the ninth transistor T9 into a voltage signal, and the feedback voltage Vf is transmitted to the input terminals of the two operational amplifier sub-circuits to form a closed-loop control. The current mirror structure composed of the tenth transistor T10 and the eleventh transistor T11 mirrors the current at the drain of the ninth transistor T9 to the output terminal, and through the matching device size, the proportional relationship between the output current and the reference current is ensured to be stable, wherein the output current is Iref. When the external load changes and causes the output current to fluctuate, the feedback voltage Vf drives the ninth transistor T9 to adjust the conduction state through the adjustment of the operational amplifier sub-circuit, so that the output current returns to the set value.

[0107] Continuing to refer to Figure 2 In the embodiment, the output stage sub-circuit 25 further includes a filtering module 251, and the control electrode of the ninth transistor T9 is electrically connected with the output terminals of the first operational amplifier sub-circuit 21 and the second operational amplifier sub-circuit 22 through the filtering module 251. The filtering module 251 includes a third capacitor C3, a fourth capacitor C4 and a twelfth transistor T12, the control electrode of the ninth transistor T9 is electrically connected with a third current source I3, a first terminal of the third capacitor C3 and a second electrode of the twelfth transistor T12, the first electrode of the twelfth transistor T12 is electrically connected with the ground terminal GND, the control electrode of the twelfth transistor T12 is electrically connected with a second terminal of the third capacitor C3 and a first terminal of the fourth capacitor C4, and the second terminal of the fourth capacitor C4 is electrically connected with the ground terminal GND.

[0108] Specifically, the filter module 251 refers to a signal processing unit arranged between the output stage sub-circuit 25 and the operational amplifier output end, which can be implemented by an RC network combined with a transistor structure, for filtering high-frequency noise and stabilizing the output signal. The third capacitor C3 refers to an energy storage element for filtering high-frequency noise, which can be implemented by a metal-insulator-metal structure capacitor, and its capacitance value can range from 0.1 pF to 10 pF. The fourth capacitor C4 refers to an energy storage element for filtering low-frequency fluctuations, which can be implemented by a polysilicon-oxide-polysilicon structure capacitor, and its capacitance value can range from 1 nF to 100 nF. The twelfth transistor T12 refers to an N-type field effect transistor constituting a common-source amplification structure, which can be an enhancement type device with a threshold voltage of 0.5 V, and its channel width to length ratio can be 50:1 to 200:1. The third capacitor C3 and the fourth capacitor C4 form a multi-stage filter network, and the twelfth transistor T12 realizes signal amplification and secondary filtering through gate capacitance coupling.

[0109] Specifically, the third current source I3 provides a bias current for the filter module 251, and the third capacitor C3 is directly connected in parallel between the control electrode of the ninth transistor T9 and the ground to absorb high-frequency interference signals. The drain of the twelfth transistor T12 and the third capacitor C3 together form a first-stage filter node, and its gate is grounded through the fourth capacitor C4 to form a low-frequency filter loop. When high-frequency noise exists in the feedback voltage Vf signal, the third capacitor C3 bypasses it to the ground through a low-impedance path; when low-frequency fluctuations exist in the signal, the fourth capacitor C4 and the gate capacitance of the twelfth transistor T12 form a filter network with a large time constant, which smoothes the voltage change through charge storage effect. The twelfth transistor T12, as an active device, not only amplifies the signal but also enhances the filtering effect by using its transconductance characteristic, finally making the control electrode of the ninth transistor T9 obtain a stable gate voltage signal. With the addition of the amplification filter circuit, if there is no twelfth transistor T12, the ninth transistor T9 cannot be driven; if there is no third capacitor C3 and fourth capacitor C4, the output of the two operational amplifiers after clock switching will have glitches, therefore, filtering processing is needed.

[0110] Compared with the traditional scheme, the traditional scheme only uses a single-capacitor filter structure, which cannot simultaneously suppress high-frequency noise and low-frequency fluctuations. In this embodiment, by combining capacitor hierarchical configuration with transistor active filtering, a two-stage filtering mechanism is constructed in the feedback path. The third capacitor C3 quickly attenuates the high-frequency glitches generated by switching, and the fourth capacitor C4 and the RC network composed of transistors effectively eliminate the low-frequency ripple generated in the operational amplifier offset compensation process. This composite filter structure significantly improves the stability of the voltage reference.

[0111] By the technical solution, the high-frequency noise and low-frequency interference in the feedback voltage Vf signal are effectively reduced, and the input end of the operational amplifier is prevented from being modulated by the parasitic signal. The multi-stage structure of the filtering module 251 keeps the gate voltage of the output stage transistor stable, thereby ensuring the accuracy of the feedback loop in the voltage-current conversion process and finally improving the linearity and repeatability of the current output under low voltage conditions. It should be noted that the output current Iref can be changed by adjusting the width-length ratio of the eleventh transistor T11, adjusting the resistance R, and adjusting the reference voltage Vref.

[0112] Compared with the traditional voltage-current conversion circuit, the traditional voltage-current conversion circuit adopts a structure in which a single adjusting tube is connected in series with a resistance R, and is susceptible to the influence of the adjusting tube conduction resistance R change at low voltage input. In this embodiment, the working current of the adjusting tube is separated from the output current by introducing a current mirror structure, for example, the eleventh transistor T11 directly outputs the load current, and the ninth transistor T9 only works as a feedback adjusting element in a small current state, thereby reducing the influence of the adjusting tube conduction resistance R on the output accuracy. In addition, the mechanism that the two operational amplifier sub-circuits alternately control the ninth transistor T9 can avoid the accumulation of the operational amplifier offset voltage in the feedback loop compared with a single operational amplifier structure.

[0113] By the technical solution, the accurate generation of the feedback voltage Vf and the synchronous control of the stable output current are realized. The feedback node formed by the ninth transistor T9 and the resistance R can quickly respond to the change of the operational amplifier output signal, ensuring the dynamic matching of the feedback voltage Vf and the reference voltage; the current mirror structure suppresses the influence of process fluctuations on the output current through device matching characteristics, for example, when the power voltage fluctuates, the gate-source voltages of the tenth transistor T10 and the eleventh transistor T11 change synchronously, maintaining the output current constant. This structure is particularly suitable for application scenarios where the input voltage is less than 100 millivolts, and can effectively improve the system performance in the fields of biosensor signal conditioning, high-precision digital-to-analog converters, etc.

[0114] In a specific implementation process, Figure 2 The working principle of the voltage-current conversion circuit is as follows:

[0115] When the clock signal OSC is high, the OSC1 signal is high, the OSC2 signal is low, TG2, TG3, TG7, and TG6 are turned on, TG1, TG4, TG5, and TG8 are turned off, the operational amplifier A is connected to the reference voltage Vref, the operational amplifier B is connected to the feedback voltage Vf, the gate and the drain of the first transistor T1 of the first operational amplifier sub-circuit 21 are disconnected, and the gate and the drain of the seventh transistor T7 of the first operational amplifier sub-circuit 21 are short-circuited. At this time, the output of the first operational amplifier sub-circuit 21 is connected to the output stage sub-circuit 25.

[0116] When the OSC signal is low, the OSC1 signal is low, the OSC2 is high, the TG1, TG4, TG5, TG8 are on, the TG2, TG3, TG7, TG6 are off, the first operational amplifier sub-circuit 21 connects the feedback voltage Vf, the second operational amplifier sub-circuit 22 connects the reference voltage Vref, the first transistor T1 of the first operational amplifier sub-circuit 21 is shorted, the seventh transistor T7 of the second operational amplifier sub-circuit 22 is disconnected, and the output stage sub-circuit 25 of the second operational amplifier sub-circuit 22 is connected.

[0117] In this connection mode, when the OSC signal is low, the TG1, TG4, TG5, TG8 are on, the two input terminals of the first operational amplifier sub-circuit 21 are connected to the feedback voltage Vf, and the input offset of the first operational amplifier sub-circuit 21 is stored through the first capacitor C1, that is, the gate voltage of the first transistor T1 is Vc1. After the OSC signal becomes high, the two input terminals of the first operational amplifier sub-circuit 21 are connected to the reference voltage Vref and the feedback voltage Vf, but the gate voltage Vc1 of the first transistor T1 remains unchanged as the voltage stored when the OSC signal is low. The first operational amplifier sub-circuit 21 adjusts the reference voltage Vref and the feedback voltage Vf to be completely equal. It is equivalent to that the first operational amplifier sub-circuit 21 stores the offset when the OSC signal is low, and the offset voltage is offset when the first operational amplifier sub-circuit 21 is connected to the output stage sub-circuit 25 to work normally, so that the reference voltage Vref and the feedback voltage Vf are completely equal.

[0118] Similarly, when the OSC signal is high, the TG2, TG3, TG7, TG6 are on, the two input terminals of the second operational amplifier sub-circuit 22 are connected to the feedback voltage Vf, and the input offset of the second operational amplifier sub-circuit 22 is stored through the second capacitor C2, that is, the gate voltage of the seventh transistor T7 is Vc2. After the OSC signal becomes low, the two input terminals of the second operational amplifier sub-circuit 22 are connected to the reference voltage Vref and the feedback voltage Vf, but the gate voltage Vc2 of the seventh transistor T7 remains unchanged as the voltage stored when the OSC signal is high. The second operational amplifier sub-circuit 22 adjusts the reference voltage Vref and the feedback voltage Vf to be completely equal. It is equivalent to that the second operational amplifier sub-circuit 22 stores the offset when the OSC signal is high, and the offset voltage is offset when the second operational amplifier sub-circuit 22 is connected to the output stage sub-circuit 25 to work normally, so that the reference voltage Vref and the feedback voltage Vf are completely equal.

[0119] That is, by changing the high and low levels of the clock signal, the operational amplifier A and the operational amplifier B are switched to work, and the offset voltage is stored in segments and offset in the next time period, thereby reducing the offset voltage of the entire circuit and greatly improving the voltage current conversion precision when the low voltage current is converted.

[0120] Figure 3 is a structural schematic diagram of a transmission gate control signal generation sub-circuit. As shown in Figure 3 a transmission gate control signal generation sub-circuit includes a first logic gate U1, a second logic gate U2, a first inversion module U3, a second inversion module U4, and a third inversion module U5; the first input end of the first logic gate U1 is electrically connected with the clock signal end; the second input end of the first logic gate U1 is electrically connected with the output end of the second logic gate U2; the output end of the first logic gate U1 is electrically connected with the input end of the first inversion module U3; the output end of the first inversion module U3 is electrically connected with the control end of the first part of a plurality of transmission gate sub-circuits, to calculate the first level signal SOC1 for the part of the transmission gate sub-circuits; the first input end of the second logic gate U2 is electrically connected with the output end of the first logic gate U1; the second input end of the second logic gate U2 is electrically connected with the output end of the second inversion module U4; the output end of the second logic gate U2 is also electrically connected with the input end of the third inversion module U5; the input end of the second inversion module U4 is electrically connected with the clock signal end; the output end of the third inversion module U5 is electrically connected with the control end of the second part of a plurality of transmission gate sub-circuits.

[0121] Among them, the first logic gate U1 and the second logic gate U2 refer to the basic elements for generating logic control signals, which can be realized by NAND gates, and the interlocking structure is formed by cross connection to generate stable control timing. The first inversion module U3, the second inversion module U4, and the third inversion module U5 refer to the circuit units for signal polarity conversion, which can be realized by inverter chains, and their function is to drive the transmission gate control end after inverting the signal output by the logic gate. The function of the interlocking structure is to ensure that the two control signals cannot be in the effective state at the same time at any time, thereby avoiding the misoperation of the transmission gate sub-circuit.

[0122] Specifically, the clock signal is processed by the interlocking structure composed of the first logic gate U1 and the second logic gate U2 to form an intermediate signal with a fixed phase relationship. The first logic gate U1 receives the original clock signal and the feedback signal output by the second logic gate U2 to generate a first intermediate signal through NAND logic operation. The signal is inverted by the first inversion module U3 to form a first sub-clock signal, which is used to control the first part of the transmission gate sub-circuit. The second logic gate U2 receives the first intermediate signal and the clock feedback signal processed by the second inversion module U4, and generates a second intermediate signal through twice NAND operation. The signal is inverted by the third inversion module U5 to form a second sub-clock signal, which is used to control the second part of the transmission gate sub-circuit. The second inversion module U4 inverts the original clock signal to ensure that the two sub-clock signals are strictly non-overlapping in timing.

[0123] In some specific embodiments, the first logic gate U1 and the second logic gate U2 can be implemented as NAND gate circuits in a CMOS process, and the transistor sizes can be optimized according to the clock frequency requirements. The inverting module can be composed of an odd number of inverters connected in series, for example, a three-stage inverter series structure is used to enhance the driving capability. The rising edge and the falling edge of the clock signal are processed by the logic gate and the inverting module, and finally two non-overlapping control signals with fixed delay difference are output.

[0124] Compared with the prior art, the traditional clock phase splitting circuit is usually implemented by a simple inverter chain or a delay line, and there is a risk of signal overlap. The embodiment realizes precise timing control while ensuring signal integrity by the cooperative design of the logic gate interlocking structure and the multi-stage inverting module, and effectively eliminates the race hazard phenomenon in the transmission gate switching process.

[0125] Through the above technical solutions, the application realizes the generation of high-reliability non-overlapping clock signals, ensures that the two operational amplifier sub-circuits do not produce signal conflicts when working alternately. The structure fundamentally avoids the problem of overlapping control signals that may occur in traditional circuits through the interlocking mechanism of hardware logic, provides a stable timing basis for the accurate storage and elimination of the misadjustment voltage, and thus improves the operation accuracy and reliability of the entire voltage-current conversion circuit.

[0126] The device embodiments described above are only schematic, and the units shown as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e., they can be located in one place or distributed on multiple network units. Some or all of the modules can be selected to achieve the purpose of the embodiment scheme according to actual needs. Those skilled in the art can understand and implement it without creative labor.

[0127] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A voltage-current conversion circuit, characterized in that: It includes a transmission gate control signal generating subcircuit, a first operational amplifier subcircuit, a second operational amplifier subcircuit, a first offset cancellation subcircuit, a second offset cancellation subcircuit, a plurality of transmission gate subcircuits and an output stage subcircuit; The transmission gate control signal generating sub-circuit is configured to receive a clock signal and generate two non-overlapping sub-clock signals; The plurality of transmission gate sub-circuits are configured to be turned on or off according to the two non-overlapping sub-clock signals to control the first operational amplifier sub-circuit and the second operational amplifier sub-circuit to operate alternately; The first offset cancellation sub-circuit is configured to store the offset voltage of the first operational amplifier sub-circuit when the second operational amplifier sub-circuit is operating, and to cancel the offset voltage when the first operational amplifier sub-circuit is operating; The second offset cancellation sub-circuit is configured to store the offset voltage of the second operational amplifier sub-circuit when the first operational amplifier sub-circuit is operating, and to cancel the offset voltage when the second operational amplifier sub-circuit is operating; The output stage sub-circuit is configured to output the converted current and provide a feedback voltage to the first operational amplifier sub-circuit and the second operational amplifier sub-circuit.

2. The voltage-to-current conversion circuit according to claim 1, wherein: The plurality of transmission gate sub-circuits include a first transmission gate input module, a second transmission gate input module, and a first transmission gate output module; The input terminal of the first transmission gate input module is electrically connected to the feedback voltage terminal of the output stage sub-circuit; the control terminal of the first transmission gate input module is electrically connected to the transmission gate control signal generating sub-circuit; The output terminal of the first transmission gate input module is electrically connected to the first input terminal of the first operational amplifier sub-circuit; The input terminal of the second transmission gate input module is electrically connected to the reference voltage terminal; the control terminal of the second transmission gate input module is electrically connected to the transmission gate control signal generating sub-circuit; The output terminal of the second transmission gate input module is electrically connected to the first input terminal of the first operational amplifier sub-circuit; The second input terminal of the first operational amplifier sub-circuit is electrically connected to the feedback voltage terminal; When the second level signal in the non-overlapping sub-clock signal is input to the control terminal of the first transmission gate input module, the feedback voltage is respectively input to the two input terminals of the first operational amplifier sub-circuit, so that the first offset cancellation sub-circuit stores the offset voltage of the first operational amplifier sub-circuit; When the first level signal in the non-overlapping sub-clock signal is input to the control end of the second transmission gate input module, the reference voltage of the reference voltage end is input to the first input end of the first operational amplifier sub-circuit, and the feedback voltage is input to the second input end of the first operational amplifier sub-circuit. The reference voltage is compared with the feedback voltage to adjust the output signal of the first operational amplifier sub-circuit.

3. The voltage-to-current conversion circuit according to claim 2, wherein: The first operational amplifier sub-circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; The first offset cancellation subcircuit includes a first capacitor, and the plurality of transmission gate subcircuits include a fifth transmission gate input module; The first electrode of the first transistor is electrically connected to the output end of the first current source and the first electrode of the second transistor; The control electrode of the first transistor is electrically connected to the output end of the first transmission gate input module and the output end of the second transmission gate input module; The second electrode of the first transistor is electrically connected to the second electrode of the third transistor, the input end of the fifth transmission gate input module, and the input end of the first transmission gate output module; The control electrode of the second transistor is electrically connected to the feedback voltage terminal; The second electrode of the second transistor is electrically connected to the second electrode of the fourth transistor and the control electrode of the fourth transistor; The first electrode of the third transistor is electrically connected to the ground terminal and the second terminal of the first capacitor; The control electrode of the third transistor is electrically connected to the output end of the fifth transmission gate input module and the first end of the first capacitor; The first electrode of the fourth transistor is electrically connected to the ground terminal.

4. The voltage-to-current conversion circuit according to claim 1, wherein: The plurality of transmission gate sub-circuits include a third transmission gate input module, a fourth transmission gate input module, and a second transmission gate output module; The input terminal of the third transmission gate input module is electrically connected to the feedback voltage terminal of the output stage sub-circuit; the control terminal of the third transmission gate input module is electrically connected to the transmission gate control signal generating sub-circuit; The output terminal of the third transmission gate input module is electrically connected to the first input terminal of the second operational amplifier sub-circuit; The input terminal of the fourth transmission gate input module is electrically connected to the reference voltage terminal; the control terminal of the fourth transmission gate input module is electrically connected to the transmission gate control signal generating sub-circuit; The output terminal of the fourth transmission gate input module is electrically connected to the first input terminal of the second operational amplifier sub-circuit; The second input terminal of the second operational amplifier sub-circuit is electrically connected to the feedback voltage terminal; When the first level signal in the non-overlapping sub-clock signal is input to the control terminal of the third transmission gate input module, the feedback voltage is respectively input to the two input terminals of the second operational amplifier sub-circuit, so that the second offset cancellation sub-circuit stores the offset voltage of the second operational amplifier sub-circuit; When the second level signal in the non-overlapping sub-clock signal is input to the control end of the fourth transmission gate input module, the reference voltage of the reference voltage end is input to the first input end of the second operational amplifier sub-circuit, and the feedback voltage is input to the second input end of the second operational amplifier sub-circuit. The reference voltage is compared with the feedback voltage to adjust the output signal of the second operational amplifier sub-circuit.

5. The voltage-to-current conversion circuit according to claim 4, wherein: The second operational amplifier sub-circuit includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The second offset cancellation subcircuit includes a second capacitor, and the plurality of transmission gate subcircuits include a sixth transmission gate input module; The first electrode of the fifth transistor is electrically connected to the output end of the second current source and the first electrode of the sixth transistor; The control electrode of the fifth transistor is electrically connected to the output end of the third transmission gate input module and the output end of the fourth transmission gate input module; The second electrode of the fifth transistor is electrically connected to the second electrode of the seventh transistor, the input end of the sixth transmission gate input module, and the input end of the second transmission gate output module; The control electrode of the sixth transistor is electrically connected to the feedback voltage terminal; The second electrode of the sixth transistor is electrically connected to the second electrode of the eighth transistor and the control electrode of the eighth transistor; The first electrode of the seventh transistor is electrically connected to the ground terminal and the second terminal of the second capacitor; The control electrode of the seventh transistor is electrically connected to the output end of the sixth transmission gate input module and the first end of the first capacitor; The first electrode of the eighth transistor is electrically connected to the ground terminal.

6. The voltage-to-current conversion circuit according to claim 1, wherein: The output stage sub-circuit includes a ninth transistor, a tenth transistor, an eleventh transistor and a resistor; The control electrode of the ninth transistor is electrically connected to the output terminal of the first operational amplifier sub-circuit and the output terminal of the second operational amplifier sub-circuit; The first electrode of the ninth transistor is electrically connected to the first end of the resistor and outputs the feedback voltage; The second end of the resistor is electrically connected to the ground end; The second electrode of the ninth transistor is electrically connected to the second electrode of the tenth transistor, the control electrode of the tenth transistor, and the control electrode of the eleventh transistor; The first electrode of the tenth transistor and the first electrode of the eleventh transistor are electrically connected to the voltage terminal.

7. The voltage-to-current conversion circuit according to claim 6, wherein: The output stage subcircuit further includes a filtering module; The control electrode of the ninth transistor is electrically connected to the output end of the first operational amplifier sub-circuit and the output end of the second operational amplifier sub-circuit through the filtering module.

8. The voltage-to-current conversion circuit according to claim 7, wherein: The filtering module includes a third capacitor, a fourth capacitor and a twelfth transistor; The control electrode of the ninth transistor is electrically connected to the third current source, the first end of the third capacitor and the second electrode of the twelfth transistor; The first electrode of the twelfth transistor is electrically connected to the ground terminal; The control electrode of the twelfth transistor is electrically connected to the second end of the third capacitor and the first end of the fourth capacitor; The second end of the fourth capacitor is electrically connected to the ground end.

9. The voltage-to-current conversion circuit according to any one of claims 1 to 8, characterized in that: The transmission gate control signal generating sub-circuit includes a first logic gate, a second logic gate, a first inversion module, a second inversion module and a third inversion module; The first input terminal of the first logic gate is electrically connected to the clock signal terminal; The second input terminal of the first logic gate is electrically connected to the output terminal of the second logic gate; The output end of the first logic gate is electrically connected to the input end of the first inversion module; The output end of the first inverter module is electrically connected to the control end of the first part of the plurality of transmission gate sub-circuits; The first input terminal of the second logic gate is electrically connected to the output terminal of the first logic gate; The second input end of the second logic gate is electrically connected to the output end of the second inversion module; The output end of the second logic gate is also electrically connected to the input end of the third inversion module; The input end of the second inversion module is electrically connected to the clock signal end; The output end of the third inversion module is electrically connected to the control end of the second part of the plurality of transmission gate sub-circuits.

10. The voltage-to-current conversion circuit according to claim 9, wherein: The first logic gate and the second logic gate are both NAND gates.

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