Intelligent control method and device for processor, chip and electronic equipment

Abstract

The invention belongs to the technical field of electronic information, and discloses an intelligent control method and device for a processor, a chip and electronic device.The method comprises the steps that at any stage before to-be-processed executable codes are submitted to an execution unit of the processor, an analysis unit corresponding to the stage obtains and analyzes the executable codes; identifying, by an analysis unit, whether the executable code contains a predefined instruction, instruction sequence, or program indicating a resource-intensive feature, the resource-intensive feature referring to a feature that at runtime may cause at least one of power consumption, bandwidth utilization, or computing resource utilization of the processor to exceed its corresponding security threshold; if yes, responding to the recognized instruction, instruction sequence or program, and generating a corresponding output result; according to the method, instructions, instruction sequences or programs possibly causing resource overload are actively recognized, so that countermeasures are taken in advance before problems occur, and safer, more efficient and more stable processor control is realized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of electronic information technology, and particularly relates to an intelligent control method and device for a processor, a chip and an electronic device. BACKGROUND

[0002] With the continuous progress of semiconductor technology, the computing power of processors (including CPUs, GPUs, NPUs and various XPUs) is increasingly powerful, and the integration is increasingly high, and the power density also significantly increases. When the processor, system on chip (SOC) and embedded system are running complex applications, abnormal behaviors such as over-temperature, over-voltage, over-current or overload may occur.

[0003] In the prior art, these special signals are generally sensed by temperature / voltage / current sensors, and after sensing the corresponding signals, it is inferred that over-temperature / over-voltage / over-current problems have occurred, and then relevant temperature control / voltage control / power control measures are taken to achieve the purpose of safe, efficient and stable operation of the CPU / SOC / embedded system. This control scheme realized by sensors belongs to a post-sensing and post-remedy scheme, which may cause the system to have performance jitter or enter an unsafe state before taking measures. SUMMARY

[0004] The purpose of the present application is to break through the passive control mode of relying on sensors for post-sensing and feedback in traditional technology, and instead, by analyzing and predicting the executable code at various possible stages before the code is finally executed by the processor, the instructions, instruction sequences or programs that may cause resource overload (such as over-temperature, over-voltage, over-current, overload) are actively identified, and different outputs are generated based on the prediction results to take measures in advance before the problem occurs, so as to realize safer, more efficient and stable processor control.

[0005] In a first aspect, an embodiment of the present application provides an intelligent control method for a processor, the method comprising: Before the executable code to be processed is submitted to the execution unit of the processor, the analysis unit corresponding to any stage acquires and analyzes the executable code; the stage is a program compilation stage, a binary code analysis stage after compilation, a program static code scanning stage or an instruction decoding stage during program runtime; The analysis unit identifies whether the executable code contains predefined instructions, instruction sequences or programs indicating resource-intensive features, the resource-intensive features indicating features that can cause at least one of the power consumption, bandwidth utilization or computing resource utilization of the processor to exceed the corresponding safety threshold during runtime; If yes, a corresponding output result is generated in response to the identified instructions, instruction sequences or programs; When the stage is a program compiling stage, a post-compilation binary code analyzing stage or a program static code scanning stage, the output result is a prompt information, which is used to guide a developer to insert a preventive instruction in a code, the preventive instruction including a function call instruction for calling a system power management interface, a thermal management interface or a frequency management interface. When the stage is an instruction decoding stage of a program running time, the output result is a control signal, which is used to directly trigger a hardware function module to adjust a running parameter of the processor.

[0006] Optionally, when the stage is a program compiling stage, the analysis unit is a special code analyzing module in a compiler. When the stage is a post-compilation binary code analyzing stage, the analysis unit is a binary code scanning tool. When the stage is a program static code scanning stage, the analysis unit is a static code analyzing tool. When the stage is an instruction decoding stage of a program running time, the analysis unit is an instruction recognition circuit integrated in a processor hardware, or the analysis unit is a recognition module realized by a special thread, a special CPU core or a special subsystem running on the processor.

[0007] Optionally, the analysis unit identifies whether the executable code contains a predefined instruction, instruction sequence or program indicating a resource-intensive feature in the following at least one manner: identifying whether the executable code contains a predefined specific type instruction; the specific type instruction includes at least one of a load store instruction, a data movement instruction, a floating point operation instruction, a Neon instruction or a cache flush instruction; statistically analyzing a frequency or density of the specific type instruction in the executable code and judging whether the frequency or density exceeds a corresponding statistical threshold value; identifying whether a program of the executable code matches a predefined resource-intensive program; the predefined resource-intensive program includes a loop nesting depth exceeding a threshold value or a function call relationship containing a known high power consumption function.

[0008] Optionally, the predefined instruction, instruction sequence or program indicating the resource-intensive feature is determined in the following at least one manner: defining a specific type instruction related to high resource consumption based on a theoretical analysis of a processor instruction set architecture; summarizing an instruction sequence or program related to high resource consumption based on an experience summary of power consumption, bandwidth or performance data of a historical code running time; By executing instructions, instruction sequences or programs under preset environmental conditions and measuring their runtime power consumption, bandwidth or performance data, instructions, instruction sequences or programs that reach the resource consumption threshold are calibrated according to the measurement results.

[0009] Optionally, when the stage is an instruction decoding stage during program execution, generating a control signal includes: The instruction recognition circuit generates a hardware interrupt signal or issues a control instruction via a system bus after recognizing the instruction, instruction sequence or program; The hardware interrupt signal or control instruction is used to directly trigger at least one of the following functional modules to perform an operation: Temperature control module, used to start or enhance cooling measures; a power management module for performing voltage regulation; The clock module is used to perform preparations for clock frequency switching.

[0010] Optionally, issuing a control instruction through a system bus includes: Writing specific control values ​​to the registers of the power management module triggers voltage adjustments.

[0011] In a second aspect, an embodiment of the present invention provides an intelligent control device for a processor, the device comprising: An acquisition and analysis module is configured to acquire and analyze the executable code at any stage before the executable code to be processed is submitted to the execution unit of the processor; the stage corresponding to the stage is: the program compilation stage, the post-compilation binary code analysis stage, the program static code scanning stage, or the instruction decoding stage during program runtime; an identification module, configured to, by the analysis unit, identify whether the executable code includes a predefined instruction, instruction sequence, or program indicating a resource-intensive feature, wherein the resource-intensive feature refers to a feature that may cause at least one of processor power consumption, bandwidth utilization, or computing resource utilization to exceed a corresponding safety threshold when the executable code is executed; an output generation module, configured to generate corresponding output results in response to the identified instructions, instruction sequences or programs; Wherein, when the stage is the program compilation stage, the post-compilation binary code analysis stage or the program static code scanning stage, the output result is prompt information, and the prompt information is used to guide the developer to insert preventive instructions in the code, and the preventive instructions include function call instructions for calling the system power management interface, thermal management interface or frequency management interface; When the stage is the instruction decoding stage during program execution, the output result is a control signal, and the control signal is used to directly trigger a hardware function module to adjust the operating parameters of the processor.

[0012] In a third aspect, an embodiment of the present application further provides a chip integrated with the intelligent control device for a processor in the second aspect.

[0013] In a fourth aspect, an embodiment of the present application further provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the method in the first aspect when executing the program.

[0014] Optionally, the electronic device is any one of a smartphone, a tablet computer, a notebook computer, a server, a base station, a drone, a robot, or a smart car.

[0015] In a fifth aspect, an embodiment of the present application further provides a computer readable storage medium, when instructions in the computer readable storage medium are executed by a processor of an electronic device, the electronic device can execute the method in the first aspect.

[0016] In a sixth aspect, an embodiment of the present application further provides a computer program product including a computer program, and the computer program implements the method in the first aspect when executed by a processor.

[0017] Embodiments of the present application provide an intelligent control method for a processor, and the core idea is to break through the passive control mode of post-sensing and feedback relying on sensors in traditional technology, and instead, to analyze and predict the code at each possible stage before it is finally executed by the processor, to actively identify instructions, instruction sequences, or programs that may trigger resource overload (such as over-temperature, over-voltage, over-current, and overloading), and to generate different outputs based on the prediction results to take measures in advance before the problem occurs, so as to achieve safer, more efficient, and more stable processor control. Moreover, embodiments of the present application predict the running behavior by directly analyzing the characteristics of the code itself, and the judgment basis completely relies on the code instructions and structure, and is not affected by factors such as sensor physical layout, PCB wiring, and environmental temperature interference. Therefore, the prediction and control accuracy is much higher than that of the traditional scheme relying on external sensor sampling, and more accurate power consumption and performance management is achieved.

[0018] Embodiments of the present application also cover multiple stages from "program compilation" to "instruction decoding", forming a complete solution throughout the whole life cycle of product development and operation. It is suitable for offline analysis and optimization in the development stage, and also suitable for real-time hardware control in the product operation stage, and can be widely applied to products such as chips, terminals, base stations, and cars carrying processors, and has strong universality and scalability.

[0019] In addition, the application predicts by analyzing the existing instruction stream in the running stage, without or greatly reducing the need to arrange a large number of high-precision temperature and voltage sensors around the key circuits of the chip, which not only reduces the silicon area and hardware cost, but also simplifies the complexity of PCB layout and wiring, and avoids the additional overhead caused by sensor calibration. The application innovatively generates two kinds of output results according to different stages. In the development stage, prompt information is provided to guide the developer to optimize fundamentally from the software level, improving the code quality; in the running stage, hardware control signals are generated to realize automatic and rapid response. This dual-path mechanism provides unprecedented flexibility for system optimization.

[0020] In summary, the application successfully solves the inherent problems of the traditional feedback control scheme, such as hysteresis, poor precision, and high cost, by forward-looking prediction based on code characteristics, providing a new solution for processor power consumption and thermal management that is safer, more efficient, more accurate, and more cost-effective, significantly improving the competitiveness of products. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A flowchart of an intelligent control method for a processor provided by an embodiment of the application; Figure 2 A structural schematic diagram of an intelligent control device for a processor provided by an embodiment of the application; Figure 3 A structural schematic diagram of an electronic device provided by an embodiment of the application. DETAILED DESCRIPTION

[0022] The application will be described in detail below through embodiments.

[0023] With the continuous advancement of semiconductor technology, the computing power of processors (including CPUs, GPUs, NPUs, and various XPUs) is increasingly powerful, and the integration is increasingly high, and the power density is also significantly increased. When running complex applications, processors, system on chips (SOCs), and embedded systems may exhibit abnormal behaviors such as over-temperature, over-voltage, over-current, or overload.

[0024] In the prior art, temperature / voltage / current sensors are generally used to sense these special signals, and after sensing the corresponding signals, it is inferred that over-temperature, over-voltage, or over-current problems have occurred, and then relevant temperature control, voltage control, or power control measures are taken to achieve the purpose of safe, efficient, and stable operation of the CPU / SOC / embedded system. This control scheme realized by sensors belongs to a post-sensing and post-remedy scheme, which may cause the system to have performance jitter or enter an unsafe state before taking measures.

[0025] In addition to the hysteresis, the prior art implementation has the following technical problems: 1. High cost. Various sensors need to be added at specific locations, such as temperature sensors, voltage sensors, etc. inside the CPU, increasing hardware costs; and calibration of these sensors at some links is required to effectively ensure the sensing accuracy of the sensors.

[0026] 2. Spatial limitation. The sensor needs to be close to the object to be sensed to ensure accuracy, but due to product structure, sensor size and other factors, the position of the sensor is not easy to be placed at the optimal position, and finally it is often a balance between sampling accuracy and component layout, product structure, etc.

[0027] 3. Large accuracy difference: the closer to the collection object, the more accurate the collection accuracy, and vice versa; and the sensor is also easily disturbed by some other factors, resulting in sampling errors and affecting accuracy.

[0028] To solve the above technical problems existing in the prior art, the embodiments of the present application provide an intelligent control method for a processor. The core idea is to break through the passive control mode of relying on sensors for post-sensing and feedback in traditional technology, and instead analyze and predict the code at each possible stage before it is finally executed by the processor, actively identify instructions, instruction sequences or programs that may cause resource overload (such as over-temperature, over-voltage, over-current, and overload), and generate different outputs based on the prediction results to take measures in advance before the problem occurs, thereby realizing safer, more efficient and stable processor control.

[0029] As shown in Figure 1 The method can include the following steps: S110, before the executable code to be processed is submitted to the execution unit of the processor, an analysis unit corresponding to any stage acquires and analyzes the executable code.

[0030] The stage is a program compilation stage, a binary code analysis stage after compilation, a program static code scanning stage, or an instruction decoding stage during program runtime.

[0031] The present application innovatively expands the analysis opportunity to multiple stages of the code life cycle, covering the whole process from development to runtime. In practical applications, the following four stages can be covered.

[0032] 1. Program compilation phase. This phase analyzes high-level language source code (such as C and C++). The corresponding analysis unit is the compiler's dedicated code analysis module. This module, integrated into the compilation toolchain, scans and analyzes the intermediate code representation or the target code to be generated after the compiler completes syntactic and semantic analysis. The advantage of this phase is that it can identify potential problems early, providing developers with an opportunity to modify their code.

[0033] 2. Post-compilation binary code analysis. This phase analyzes the binary object file or executable file output by the compiler. The corresponding analysis unit is a binary code scanner (a special offline analysis tool). This tool reads the binary file and converts it into an instruction sequence using a disassembly engine, or directly parses its binary structure for analysis.

[0034] 3. Static code scanning. This stage analyzes either source code or binary code. The corresponding analysis unit is a static code analysis tool. These tools don't run the program; they analyze the code's syntax, structure, control flow, and data flow to discover underlying patterns. Their advantage lies in their comprehensive analysis, capable of identifying even complex instructions, instruction sequences, or programs.

[0035] 4. The instruction decoding stage during program execution. This stage analyzes the instruction stream entering the processor's pipeline execution unit. The corresponding analysis unit is the instruction recognition circuit integrated into the processor hardware. This circuit is a dedicated hardware logic module located between the processor's instruction fetch unit and decode unit. It scans and performs pattern matching on each instruction or instruction window passing through it in real time with low latency. The advantage of this stage is that it can achieve extreme real-time performance and proactive control.

[0036] During the instruction decoding stage of program execution, specific types of instructions / instruction sequences / programs can be identified not only through special logic circuits (i.e., the instruction recognition circuit described above), but also by adding a thread, or specifically assigning a CPU, or designing a special subsystem to judge and identify specific types of instructions / instruction sequences / programs, to achieve accurate predictions and take relevant measures in advance when high resource consumption scenarios are predicted.

[0037] For example, during actual execution, another CPU will judge and identify the special instruction sequence. When it is identified that a high-power instruction / instruction sequence / program is about to be executed, countermeasures can be taken in advance, such as turning on the fan / increasing the fan speed, turning on the liquid cooling system / increasing the cooling speed, or reducing the voltage and frequency of other low-priority subsystems.

[0038] For example, a component is added inside the CPU, which identifies special instructions / instruction sequences when the CPU fetches instructions, and sends out relevant notifications so that the system can take measures in advance.

[0039] S120, by the analysis unit, identifying whether the executable code contains predefined instructions, instruction sequences, or programs indicating resource-intensive features.

[0040] Among them, the resource-intensive feature refers to a feature that can cause at least one of the processor's power consumption, bandwidth utilization, or computing resource utilization to exceed its corresponding safety threshold at runtime.

[0041] Specifically, this is the core step of the present application to achieve accurate prediction. Among them, the resource-intensive feature is a generalization, which refers to the inherent properties or tendencies exhibited by the code that can cause at least one of the processor core's power consumption, bandwidth utilization, or computing resource utilization to exceed its corresponding safety threshold at runtime.

[0042] As an implementation manner of an embodiment of the present application, the determination manner of the predefined instructions, instruction sequences, or programs indicating resource-intensive features can include multiple ways, which can refer to some standard cognition in the industry (such as the maxpower program and memory copy program of ARM CPU) and theory to judge, can also be judged by experience (such as 8-core chip, software code with 8 cores all on and working at the highest frequency), and can also be judged by experimental measurement and experimental results. The determination manner of the predefined instructions, instruction sequences, or programs indicating resource-intensive features will be described in detail below.

[0043] The first way is to define specific types of instructions related to high resource consumption based on theoretical analysis of the processor instruction set architecture.

[0044] Specifically, according to the ARM CPU instruction technology theory (instructions with frequent data operations and data interactions will cause more power consumption), the following instructions are identified as high-power instructions: (a1), load store instructions (such as ldr, str); (a2), data transfer instructions (such as mov); (a3), floating-point operation instructions (such as floating-point multiplication, floating-point division, floating-point multiplication and addition); (a4), Neon instructions; (a5), Flush cache instructions.

[0045] The second way is to summarize instruction sequence patterns or program structure patterns related to high resource consumption based on empirical summary of power consumption, bandwidth or performance data of historical code runtime.

[0046] Specifically, according to the use experience of the CPU, the programs in the following scenarios are identified to have greater power consumption, which are high-power programs, and are respectively: (b1) Programs corresponding to large data processing, such as large data compression / decompression, large data encoding / decoding, and large data encryption / decryption.

[0047] (b2) Programs corresponding to large data transmission (such as a large number of memory copy).

[0048] (b3) Programs corresponding to high-speed data processing.

[0049] (b4) Programs corresponding to frequent memory access.

[0050] (b5) Maxpower program.

[0051] (b6) Programs for 8-core chips with 8 cores all turned on and working at the highest frequency.

[0052] The third way is to execute instructions, instruction sequences or programs under preset environmental conditions and measure their runtime power consumption, bandwidth or performance data, and label instructions, instruction sequences or programs reaching resource consumption thresholds according to the measurement results.

[0053] Specifically, in addition to theory and experience, power consumption of special instructions / instruction sequences / programs can also be measured through experiments to identify high-power instructions / instruction sequences / programs.

[0054] For example, under the same environmental conditions, such as the same temperature, CPU voltage, CPU frequency, and CPU configuration, let the CPU execute a certain instruction / instruction sequence / program continuously for a period of time and measure the power consumption in this scenario. By comparing the power consumption of different instructions / instruction sequences / programs, it can be identified which instructions / instruction sequences / programs belong to high-power instructions / programs, and the degree of power consumption of different instructions / instruction sequences / programs can be identified.

[0055] Furthermore, as an implementation manner of the embodiment of the present application, the analysis unit identifies whether the executable code contains predefined instructions, instruction sequences or programs indicating resource-intensive features, including at least one of the following ways: The first way is to identify whether the executable code contains predefined specific type instructions.

[0056] The specific type of instruction includes at least one of a load store instruction, a data movement instruction, a floating point operation instruction, a Neon instruction, or a cache flush instruction.

[0057] Since the above specific type of instruction will cause more power consumption, the above specific type of instruction can be referred to as a high power consumption instruction. Of course, in actual application, the high power consumption instruction can include the above listed instructions, and can also include other high power consumption instructions, which are not limited by the embodiments of the present application. In addition, the specific type of instruction can also include instructions in terms of high performance and high bandwidth, which are not enumerated here.

[0058] The second way is to count the frequency or density of the specific type of instruction in the executable code, and determine whether it exceeds the corresponding statistical threshold.

[0059] Specifically, the frequency or density of the specific type of instruction is counted: the analysis unit counts the number of occurrences or the proportion of the above specific type of instruction in a predetermined instruction window (such as 128 instructions). If the statistical value exceeds the preset statistical threshold (such as the proportion exceeds 40%), it is determined as a high-risk instruction. For example, it is identified that the density of memory access instructions in a loop body is extremely high, and it is predicted that it will lead to excessive memory bandwidth utilization.

[0060] The third way is to identify whether the program of the executable code matches the predefined resource-intensive program.

[0061] The predefined resource-intensive program includes a loop nesting depth exceeding a threshold or a function call relationship containing a known high power consumption function.

[0062] Specifically, it can be identified whether the executable code includes a program corresponding to large data processing, a program corresponding to high-speed data processing, a program corresponding to frequent memory access, a Maxpower program, or an 8-core chip, an 8-core full-on program, and a program working at the highest frequency.

[0063] In addition, it can also be analyzed whether the loop nesting depth exceeds the threshold or whether the function call relationship contains a known high power consumption function. The loop nesting depth refers to the number of levels formed by the loop structure containing another loop structure in the program code. Each additional level of nesting usually exponentially increases the computational complexity, thereby sharply increasing the demand for processor computing resources and power consumption.

[0064] The above exceeding the preset threshold means that the number of nesting layers reaches a safety limit value preset by theoretical analysis, empirical summary or experimental measurement, and exceeding the limit value is considered to be extremely likely to cause the processor to enter a high load state.

[0065] The analysis unit (such as a static code analysis tool or a compiler module) parses the control flow graph of the code and traces the nested relationship of the loops. It starts counting from the outermost loop and increments inwards layer by layer to finally determine the maximum nesting depth value and compare the value with the preset threshold.

[0066] For example, taking the innermost core calculation unit of a three-dimensional matrix multiplication as an example, the code usually presents a triple nested loop structure. If it is measured by experiment that when the loop nesting depth reaches 3 or more in the processor, the processor power consumption has a probability of more than 95% to exceed the temperature wall, the threshold can be preset to 3. When the analysis unit identifies the above code segment, it will determine that the nesting depth is 3, which is equal to or exceeds the threshold, and thus mark it as having a high resource-intensive feature.

[0067] In this way, the embodiment of the application can identify potential computing "hot spots" in the code structure in advance in the compilation or static scanning phase, without actually running the program, and can predict the high-performance computing demand and high-power consumption risk it may bring.

[0068] The above known high-power consumption function refers to a function library, system API or custom function that is pre-marked as high resource consumption through theory, experience or experimental measurement.

[0069] "Contains in the function call relationship" means that the function currently being analyzed or its call chain directly or indirectly calls the above known high-power consumption function.

[0070] Specifically, the analysis unit will construct or access a predefined high-power consumption function list. When analyzing, it will parse the call graph of the code and check whether the current function calls the function in the list or whether it exists in a call path that eventually calls the high-power consumption function.

[0071] The following examples are given from the aspects of direct call and indirect call.

[0072] First, direct call. The current function func_a() directly calls the AES_encrypt() function in the encryption library, which has been included in the high-power consumption list. The analysis unit can directly identify this risk.

[0073] Second, indirect call: the current function func_b() calls func_c(), and func_c() internally calls the highly optimized FFT (Fast Fourier Transform) function in the mathematical library, which is also listed as a high-power consumption function. Through analysis of the call relationship, the analysis unit can infer that func_b() also has a high-power consumption tendency.

[0074] The method uses a knowledge base formed by historical performance data to quickly and accurately identify code that uses a recognized high-performance computing library, encryption and decryption library, or graphics rendering interface, and can effectively predict resource-intensive features even if the code structure itself is not complex.

[0075] Through the judgment of the two modes, the application realizes accurate and efficient predictive identification of resource-intensive programs from two dimensions of code structure complexity and known high-performance library calls. This provides a solid and reliable basis for subsequent generation of prompt information or triggering of real-time hardware control signals.

[0076] S130, in response to the identified instruction, instruction sequence or program, generating a corresponding output result.

[0077] When the stage is a program compilation stage, a post-compilation binary code analysis stage, or a program static code scanning stage, the output result is a prompt information, and the prompt information is used to guide the developer to insert a preventive instruction in the code, and the preventive instruction includes a function call instruction for calling a system power management interface, a thermal management interface or a frequency management interface. When the stage is an instruction decoding stage of a program running, the output result is a control signal, and the control signal is used to directly trigger a hardware function module to adjust the running parameters of the processor.

[0078] For example, in the program compilation stage and the post-compilation binary code analysis stage, it is predicted that the maxpower program will be executed for a long time and that the over-temperature behavior will occur in a certain special code segment, reminding the developer to increase the temperature control protection measures (turn on the fan / increase the fan speed, turn on the liquid cooling system / increase the cooling speed, or reduce the voltage and frequency of other low-priority subsystems) corresponding to the code before and after the corresponding code position.

[0079] Or, in a certain code, it is identified that high-power instructions (such as mov / ldr / str instructions) / instruction sequences will be executed for a long time, reminding the developer to increase the temperature control protection measures corresponding to the code before and after the corresponding code position.

[0080] Or, in a certain code, it is identified that the density of high-power instructions (such as mov / ldr / str instructions) / instruction sequences is very high, reminding the developer to increase the temperature control protection measures corresponding to the code before and after the corresponding code position.

[0081] In the program static code scanning stage, after scanning the dangerous situation (such as high power consumption), an alarm information is given to notify the programmer that there is a high-power instruction in a certain place, reminding the programmer to add high-power prevention measures corresponding to the code position.

[0082] In the instruction decoding stage of the program running, the special logic circuit identifies the special instruction / instruction sequence / program, and after identifying the relevant situation, the special signal such as interruption / bus instruction is transmitted to the corresponding logic circuit, and the corresponding logic circuit takes measures.

[0083] The embodiment of the present application provides an intelligent control method for a processor, and the core idea is that: breaking through the passive control mode of the traditional technology which depends on the sensor for post-sensing and feedback, and instead, the code is analyzed and predicted in each possible stage before the code is finally executed by the processor, the instructions, instruction sequences or programs which may cause resource overload (such as over-temperature, over-voltage, over-current and overload) are actively identified, and different outputs are generated based on the prediction results, so that the countermeasures are taken in advance before the problem occurs, so that the processor control is more safe, efficient and stable. Moreover, the embodiment of the present application predicts the running behavior by directly analyzing the characteristics of the code itself, and the judgment basis completely depends on the code instructions and structure, and is not affected by factors such as sensor physical layout, PCB wiring, environmental temperature interference and the like. Therefore, the prediction and control precision is much higher than that of the traditional scheme which depends on external sensor sampling, and more accurate power consumption and performance management is realized.

[0084] The embodiment of the present application also covers multiple stages from "program compilation" to "instruction decoding", and forms a complete solution which runs through the whole life cycle of product development and operation. It is suitable for offline analysis and optimization in the development stage, and is also suitable for real-time hardware control in the operation stage of the product, and can be widely applied to products such as chips, terminals, base stations and automobiles which carry processors, and has strong universality and scalability.

[0085] In addition, the present application predicts by analyzing the existing instruction flow in the operation stage, and the need for arranging a large number of high-precision temperature and voltage sensors around the key circuit of the chip is not needed or is greatly reduced, which not only reduces the silicon area and hardware cost, but also simplifies the complexity of PCB layout and wiring, and avoids the additional cost caused by sensor calibration. Moreover, the present application innovatively generates two kinds of output results according to different stages. In the development stage, prompt information is provided to guide the developers to make fundamental optimization from the software level, and the code quality is improved; in the operation stage, hardware control signals are generated to realize automatic and rapid response. This double-path mechanism provides unprecedented flexibility for system optimization.

[0086] In summary, the present application successfully solves the inherent problems such as hysteresis, poor precision and high cost of the traditional feedback control scheme through the forward-looking prediction based on the code characteristics, and provides a new solution which is safer, more efficient, more accurate and more cost-effective for the power consumption and thermal management of the processor, and significantly improves the competitiveness of the product.

[0087] As an implementation manner of the embodiment of the present application, when the stage is the instruction decoding stage of the program running, the control signal is generated, including: The instruction recognition circuit generates a hardware interrupt signal or sends a control instruction through the system bus after recognizing the instruction, the instruction sequence or the program; The hardware interrupt signal or the control instruction is used to directly trigger the operation of at least one of the following function modules: The temperature control module is used to execute the opening or enhancement of the cooling measure.

[0088] The power management module is used to execute the voltage adjustment.

[0089] The clock module is used to execute the preparation work of the clock frequency switching.

[0090] For example, after recognizing that the high-power-consumption instruction is about to be executed, the temperature control module / co-processor is informed, and the corresponding temperature control measure is started in advance. The temperature control measure includes but is not limited to the following measures: 1. Turn on the fan / increase the fan speed.

[0091] 2. Turn on the liquid cooling system / increase the refrigeration speed.

[0092] 3. Reduce the voltage and frequency of other low-priority subsystems.

[0093] 4. For example, after recognizing that the high-power-consumption instruction is about to be executed, the voltage boosting module is informed, and the voltage boosting is performed in advance to avoid the circuit voltage being too low due to IRDrop and various abnormalities. 5. For example, after recognizing that the high-power-consumption instruction is about to be executed, the clock module is informed, and the various preparation works of switching the high-frequency clock are performed in advance to reduce the waiting time of the clock switching and avoid various abnormalities caused by the insufficient clock switching time or the unstable clock after the switching.

[0094] As an implementation manner of the embodiment of the present application, the control instruction sent through the system bus can include the following steps: A specific control value is written into the register of the power management module to trigger the voltage adjustment.

[0095] Specifically, after recognizing the dangerous instruction sequence, the circuit internal logic of the instruction recognition circuit generates the control value and the target register address. The instruction recognition circuit, as the bus master, sends the write command packet composed of the control value and the target register address to the system bus. The system bus routes the command packet to the power management module. The power management module decodes the address and writes the control value into the voltage control register. The write operation of the voltage control register triggers the voltage regulator to change the output.

[0096] The beneficial effects of this implementation manner include the following aspects: 1. Extremely low latency. This process is completely completed at the hardware level without the intervention of the operating system kernel or driver, achieving a response speed of microseconds or even nanoseconds.

[0097] 2. High reliability. Based on the control mode of the hardware register, the timing is stable and is not disturbed by factors such as software task scheduling and interruption delay.

[0098] 3. Precise control. By writing different control values to the register, very fine voltage regulation (such as step-up / step-down) can be achieved, thereby achieving the optimal balance between power consumption and performance.

[0099] In summary, writing control values to the registers of the power management module through the system bus is a core hardware mechanism for the present application to achieve efficient, precise, and fast forward-looking voltage control. It effectively converts the prediction at the instruction level into adjustment actions at the power level, and is the key to overcoming the high delay of traditional software solutions and achieving the technical effects of the present application.

[0100] It should be noted that specific types of instructions / instruction sequences / programs include but are not limited to the above-described high-power features, and can also be high-performance / high-bandwidth features. The above scheme focuses on the identification / judgment and application (power consumption control, temperature control, etc.) of high-power instructions / instruction sequences / programs for processors. Similar schemes can also be used for the identification / judgment and application (bus usage control, memory usage control, performance control, system control, etc.) of high-performance / high-bandwidth instructions / instruction sequences / programs for processors.

[0101] In addition, the processor described in the embodiments of the present application can also use similar schemes for CPU, GPU / NPU / DPU / DSP, etc. to achieve early identification of specific types of instructions / instruction sequences / programs, and to take corresponding control measures accordingly, so that GPU / NPU / DPU / DSP, etc. and systems and products using these processors can work better (with lower power consumption, higher performance, better stability, etc.).

[0102] It should be noted that the measures for specific types of instructions / instruction sequences / programs can include but are not limited to the above-described temperature control, voltage boost, frequency boost, and alarm prompt.

[0103] The embodiments of the present application also provide an intelligent control device 20 for a processor, as shown in Figure 2 The device includes: The acquisition and analysis module 210 is configured to acquire and analyze the executable code by the analysis unit at any stage before the executable code to be processed is submitted to the execution unit of the processor, wherein the stage is a program compiling stage, a post-compiling binary code analysis stage, a program static code scanning stage or an instruction decoding stage during program runtime. The identification module 220 is configured to identify, by the analysis unit, whether the executable code contains predefined instructions, instruction sequences or programs indicating resource-intensive features, wherein the resource-intensive features refer to features that can cause at least one of power consumption, bandwidth utilization or computing resource utilization of the processor to exceed a corresponding safety threshold during runtime. The output generation module 230 is configured to generate a corresponding output result in response to the identified instructions, instruction sequences or programs. When the stage is the program compiling stage, the post-compiling binary code analysis stage or the program static code scanning stage, the output result is prompt information, wherein the prompt information is used to guide the developer to insert a preventive instruction in the code, and the preventive instruction includes a function call instruction for calling a system power management interface, a thermal management interface or a frequency management interface. When the stage is the instruction decoding stage during program runtime, the output result is a control signal, wherein the control signal is used to directly trigger a hardware function module to adjust the running parameter of the processor.

[0104] The embodiment of the present application further provides a chip, wherein the chip is integrated with the intelligent control device for the processor in the second aspect.

[0105] The embodiment of the present application further provides an electronic device 300, as shown in the figure, comprising a memory 301, a processor 302 and a computer program stored in the memory and capable of running on the processor, wherein the processor implements the method in the first aspect when executing the program. Figure 3

[0106] Optionally, the electronic device is any one of a smart phone, a tablet computer, a notebook computer, a server, a base station, a drone, a robot or a smart car.

[0107] The embodiment of the present application further provides a computer readable storage medium, wherein when instructions in the computer readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method in the first aspect.

[0108] The embodiment of the present application further provides a computer program product, comprising a computer program, wherein the computer program is executed by a processor to implement the method in the first aspect.

[0109] ​Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary and are not to be construed as limiting the present application, and that changes, modifications, substitutions and variations can be made by those skilled in the art without departing from the spirit and scope of the present application.

Claims

1. An intelligent control method for a processor, characterized in that: The method comprises: At any stage before the executable code to be processed is submitted to the execution unit of the processor, the executable code is acquired and analyzed by the analysis unit corresponding to the stage; the stage is: program compilation stage, post-compilation binary code analysis stage, program static code scanning stage or instruction decoding stage during program runtime; The analyzing unit identifies whether the executable code includes a predefined instruction, instruction sequence, or program indicating a resource-intensive feature, wherein the resource-intensive feature refers to a feature that may cause at least one of processor power consumption, bandwidth utilization, or computing resource utilization to exceed a corresponding safety threshold when the executable code is executed; If so, generating a corresponding output result in response to the identified instruction, instruction sequence, or program; Wherein, when the stage is the program compilation stage, the post-compilation binary code analysis stage or the program static code scanning stage, the output result is prompt information, and the prompt information is used to guide the developer to insert preventive instructions in the code, and the preventive instructions include function call instructions for calling the system power management interface, thermal management interface or frequency management interface; When the stage is the instruction decoding stage during program execution, the output result is a control signal, and the control signal is used to directly trigger a hardware function module to adjust the operating parameters of the processor.

2. The method according to claim 1, wherein When the stage is the program compilation stage, the analysis unit is a dedicated code analysis module in the compiler; When the stage is the post-compilation binary code analysis stage, the analysis unit is a binary code scanning tool; When the stage is the program static code scanning stage, the analysis unit is a static code analysis tool; When the stage is the instruction decoding stage during program execution, the analysis unit is an instruction recognition circuit integrated in the processor hardware; or, the analysis unit is an identification module implemented by a dedicated thread, dedicated CPU core or dedicated subsystem running on the processor.

3. The method according to claim 1, wherein The analyzing unit identifying whether the executable code includes a predefined instruction, instruction sequence, or program indicating a resource-intensive feature includes at least one of the following methods: Identifying whether the executable code includes a predefined specific type of instruction; the specific type of instruction includes at least one of a load / store instruction, a data move instruction, a floating-point operation instruction, a Neon instruction, or a cache flush instruction; Counting the occurrence frequency or density of a specific type of instructions in the executable code, and determining whether it exceeds a corresponding statistical threshold; Identify whether the executable code program matches a predefined resource-intensive program; the predefined resource-intensive program includes a loop nesting depth exceeding a threshold or a function call relationship containing a known high-power consumption function.

4. The method according to any one of claims 1 to 3, characterized in that The predefined instruction, instruction sequence, or program indicating a resource-intensive characteristic is determined by at least one of the following methods: Based on theoretical analysis of the processor instruction set architecture, specific types of instructions associated with high resource consumption are defined; Based on empirical analysis of historical code runtime power consumption, bandwidth, or performance data, identify instruction sequences or programs associated with high resource consumption. By executing instructions, instruction sequences or programs under preset environmental conditions and measuring their runtime power consumption, bandwidth or performance data, instructions, instruction sequences or programs that reach the resource consumption threshold are calibrated according to the measurement results.

5. The method according to claim 2, characterized in that When the stage is the instruction decoding stage during program execution, generating a control signal includes: The instruction recognition circuit generates a hardware interrupt signal or issues a control instruction via a system bus after recognizing the instruction, instruction sequence or program; The hardware interrupt signal or control instruction is used to directly trigger at least one of the following functional modules to perform an operation: Temperature control module, used to start or enhance cooling measures; a power management module for performing voltage regulation; The clock module is used to perform preparations for clock frequency switching.

6. The method according to claim 5, characterized in that The issuing of a control instruction via the system bus includes: Writing specific control values ​​to the registers of the power management module triggers voltage adjustments.

7. An intelligent control device for a processor, characterized in that: The device comprises: An acquisition and analysis module is configured to acquire and analyze the executable code at any stage before the executable code to be processed is submitted to the execution unit of the processor; the stage corresponding to the stage is: the program compilation stage, the post-compilation binary code analysis stage, the program static code scanning stage, or the instruction decoding stage during program runtime; an identification module, configured to, by the analysis unit, identify whether the executable code includes a predefined instruction, instruction sequence, or program indicating a resource-intensive feature, wherein the resource-intensive feature refers to a feature that may cause at least one of processor power consumption, bandwidth utilization, or computing resource utilization to exceed a corresponding safety threshold when the executable code is executed; an output generation module, configured to generate corresponding output results in response to the identified instructions, instruction sequences or programs; Wherein, when the stage is the program compilation stage, the post-compilation binary code analysis stage or the program static code scanning stage, the output result is prompt information, and the prompt information is used to guide the developer to insert preventive instructions in the code, and the preventive instructions include function call instructions for calling the system power management interface, thermal management interface or frequency management interface; When the stage is the instruction decoding stage during program execution, the output result is a control signal, and the control signal is used to directly trigger a hardware function module to adjust the operating parameters of the processor.

8. A chip, characterized in that: The chip is integrated with the intelligent control device for the processor as claimed in claim 7.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the method according to any one of claims 1 to 6 is implemented.

10. The electronic device according to claim 9, characterized in that The electronic device is any one of a smart phone, a tablet computer, a laptop computer, a server, a base station, a drone, a robot or a smart car.

Images