A method, device, chip, and electronic device for intelligent control of processors.

Abstract

This invention belongs to the field of electronic information technology and discloses an intelligent control method, device, chip, and electronic device for processors. The method includes: at any stage before the executable code to be processed is submitted to the execution unit of the processor, an analysis unit corresponding to the stage acquires and analyzes the executable code; the analysis unit identifies whether the executable code contains predefined instructions, instruction sequences, or programs that indicate resource-intensive characteristics, where resource-intensive characteristics refer to features that, during operation, may cause at least one of the processor's power consumption, bandwidth utilization, or computing resource utilization to exceed its corresponding safety threshold; if so, in response to the identified instructions, instruction sequences, or programs, corresponding output results are generated; instructions, instruction sequences, or programs that may cause resource overload are proactively identified to take countermeasures in advance before problems occur, thereby achieving safer, more efficient, and stable processor control.

Description

Technical Field

[0001] This invention belongs to the field of electronic information technology, and specifically relates to an intelligent control method, device, chip, and electronic device for processors. Background Technology

[0002] With the continuous advancement of semiconductor technology, the computing power of processors (including CPUs, GPUs, NPUs, and various XPUs) is becoming increasingly powerful, their integration is becoming higher and higher, and their power consumption density is also increasing significantly. When processors, systems-on-chips (SoCs), and embedded systems are running complex applications in actual use, abnormal behaviors such as over-temperature, over-voltage, over-current, or overload may occur.

[0003] In existing technologies, these specific signals are typically detected using sensors such as temperature, voltage, and current sensors. Upon detecting these signals, it is inferred that over-temperature, over-voltage, or over-current problems have occurred, and then relevant temperature control, voltage control, and power control measures are taken to ensure the safe, efficient, and stable operation of the CPU / SOC / embedded system. This sensor-based control scheme is a reactive, after-the-fact detection and remediation approach, which may result in performance fluctuations or the system entering an unsafe state before appropriate action is taken. Summary of the Invention

[0004] The purpose of this invention is to break through the passive control mode of traditional technology that relies on sensors for post-event perception and feedback. Instead, it analyzes and predicts various possible stages before the code is finally executed by the processor, actively identifies instructions, instruction sequences or programs that may cause resource overload (such as overtemperature, overvoltage, overcurrent, overload), and generates different outputs based on the prediction results. This allows for proactive measures to be taken before problems occur, thereby achieving safer, more efficient and stable processor control.

[0005] In a first aspect, embodiments of the present invention provide an intelligent control method for a processor, the method comprising:

[0006] At any stage before the executable code to be processed is submitted to the processor's execution unit, the executable code is acquired and analyzed by the analysis unit corresponding to the stage; the stage is: program compilation stage, compiled binary code analysis stage, program static code scanning stage, or program runtime instruction decoding stage;

[0007] The analysis unit identifies whether the executable code contains predefined instructions, instruction sequences, or programs that indicate resource-intensive characteristics. The resource-intensive characteristics refer to features that, during runtime, can cause at least one of the processor's power consumption, bandwidth utilization, or computing resource utilization to exceed its corresponding safety threshold.

[0008] If so, in response to the identified instruction, instruction sequence, or program, generate the corresponding output result;

[0009] When the stage is the program compilation stage, the post-compilation binary code analysis stage, or the program static code scanning stage, the output result is a prompt message. The prompt message is used to guide developers to insert preventive instructions in the code. The preventive instructions include function call instructions for calling the system power management interface, thermal management interface, or frequency management interface.

[0010] When the stage is the instruction decoding stage during program execution, the output result is a control signal, which is used to directly trigger the hardware functional module to adjust the processor's operating parameters.

[0011] Optionally, when the stage is the program compilation stage, the analysis unit is a dedicated code analysis module in the compiler;

[0012] When the stage is the post-compiled binary code analysis stage, the analysis unit is a binary code scanning tool;

[0013] When the stage is the static code scanning stage, the analysis unit is a static code analysis tool;

[0014] When the stage is the instruction decoding stage during program execution, the analysis unit is an instruction recognition circuit integrated into the processor hardware; or, the analysis unit is an identification module implemented by a dedicated thread, dedicated CPU core, or dedicated subsystem running on the processor.

[0015] Optionally, the step of the analysis unit identifying whether the executable code contains predefined instructions, instruction sequences, or programs that indicate resource-intensive characteristics includes at least one of the following methods:

[0016] Identify whether the executable code contains predefined specific type instructions; the specific type instructions include at least one of load storage instructions, data transfer instructions, floating-point operation instructions, Neon instructions, or cache flush instructions.

[0017] The frequency or density of specific types of instructions in the executable code is statistically analyzed, and it is determined whether they exceed the corresponding statistical threshold.

[0018] The program that identifies the executable code matches a predefined resource-intensive program; the predefined resource-intensive program includes loops with a nesting depth exceeding a threshold or function call relationships containing known high-power functions.

[0019] Optionally, the predefined instructions, instruction sequences, or programs indicating resource-intensive characteristics are determined by at least one of the following methods:

[0020] Based on theoretical analysis of processor instruction set architecture, specific types of instructions related to high resource consumption are defined;

[0021] Based on experience summarizing power consumption, bandwidth, or performance data from historical code execution, instruction sequences or programs associated with high resource consumption are identified.

[0022] By executing instructions, instruction sequences, or programs under preset environmental conditions and measuring their runtime power consumption, bandwidth, or performance data, instructions, instruction sequences, or programs that reach resource consumption thresholds can be calibrated based on the measurement results.

[0023] Optionally, when the stage is the instruction decoding stage during program execution, control signals are generated, including:

[0024] After recognizing the instruction, instruction sequence, or program, the instruction recognition circuit generates a hardware interrupt signal or issues a control command through the system bus.

[0025] The hardware interrupt signal or control command is used to directly trigger at least one of the following functional modules to perform operations:

[0026] The temperature control module is used to activate or enhance cooling measures;

[0027] The power management module is used to perform voltage regulation;

[0028] The clock module is used to prepare for clock frequency switching.

[0029] Optionally, issuing control commands via the system bus includes:

[0030] Write specific control values ​​to the registers of the power management module to trigger voltage regulation.

[0031] Secondly, embodiments of the present invention provide an intelligent control device for a processor, the device comprising:

[0032] An acquisition and analysis module is used to acquire and analyze the executable code at any stage before the executable code to be processed is submitted to the processor's execution unit, by an analysis unit corresponding to the stage; the stage is: program compilation stage, compiled binary code analysis stage, program static code scanning stage, or program runtime instruction decoding stage;

[0033] The identification module is used by the analysis unit to identify whether the executable code contains predefined instructions, instruction sequences or programs that indicate resource-intensive characteristics, wherein the resource-intensive characteristics refer to features that, during runtime, may cause at least one of the processor's power consumption, bandwidth utilization or computing resource utilization to exceed its corresponding safety threshold.

[0034] The output generation module is used to generate corresponding output results in response to the identified instructions, instruction sequences, or programs.

[0035] When the stage is the program compilation stage, the post-compilation binary code analysis stage, or the program static code scanning stage, the output result is a prompt message. The prompt message is used to guide developers to insert preventive instructions in the code. The preventive instructions include function call instructions for calling the system power management interface, thermal management interface, or frequency management interface.

[0036] When the stage is the instruction decoding stage during program execution, the output result is a control signal, which is used to directly trigger the hardware functional module to adjust the processor's operating parameters.

[0037] Thirdly, embodiments of the present invention also provide a chip that integrates the intelligent control device for the processor described in the second aspect.

[0038] Fourthly, embodiments of the present invention also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described in the first aspect.

[0039] Optionally, the electronic device may be any one of a smartphone, tablet computer, laptop computer, server, base station, drone, robot, or smart car.

[0040] Fifthly, embodiments of the present invention also provide a computer-readable storage medium that, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method described in the first aspect.

[0041] In a sixth aspect, embodiments of the present invention also provide a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0042] This invention provides an intelligent control method for processors. Its core idea is to break away from the passive control mode of traditional technologies that rely on sensors for post-event perception and feedback. Instead, it analyzes and predicts various possible stages before the code is finally executed by the processor, proactively identifying instructions, instruction sequences, or programs that may cause resource overload (such as overtemperature, overvoltage, overcurrent, and overload). Based on the prediction results, it generates different outputs to take preventative measures before problems occur, thereby achieving safer, more efficient, and stable processor control. Furthermore, this invention predicts the execution behavior by directly analyzing the characteristics of the code itself. Its judgment is entirely based on the code instructions and structure, unaffected by factors such as sensor physical layout, PCB traces, or ambient temperature interference. Therefore, its prediction and control accuracy is far higher than traditional schemes that rely on external sensor sampling, achieving more precise power consumption and performance management.

[0043] This invention also covers multiple stages from "program compilation" to "instruction decoding," forming a complete solution that spans the entire product development and operation lifecycle. It is applicable to both offline analysis and optimization during the development phase and real-time hardware control during product operation. It can be widely used in various processor-equipped products such as chips, terminals, base stations, and automobiles, exhibiting strong versatility and scalability.

[0044] Furthermore, this invention makes predictions by analyzing the existing instruction flow during the runtime phase, eliminating or significantly reducing the need for numerous high-precision temperature and voltage sensors around critical chip circuits. This not only reduces silicon area and hardware costs but also simplifies PCB layout and routing complexity, avoiding the additional overhead of sensor calibration. Moreover, this invention innovatively generates two output results based on different stages. During the development phase, it provides prompts to guide developers in fundamental software optimization, improving code quality; during the runtime phase, it generates hardware control signals, enabling fully automatic and rapid response. This dual-path mechanism provides unprecedented flexibility for system optimization.

[0045] In summary, this invention, through forward-looking prediction based on code features, successfully solves the inherent problems of hysteresis, poor accuracy, and high cost of traditional feedback control schemes, providing a safer, more efficient, more accurate, and more cost-effective new solution for processor power consumption and thermal management, significantly enhancing product competitiveness. Attached Figure Description

[0046] Figure 1 A flowchart illustrating an intelligent control method for a processor provided in an embodiment of the present invention;

[0047] Figure 2A schematic diagram of the structure of an intelligent control device for a processor provided in an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0049] The present invention will be described in detail below through embodiments.

[0050] With the continuous advancement of semiconductor technology, the computing power of processors (including CPUs, GPUs, NPUs, and various XPUs) is becoming increasingly powerful, their integration is becoming higher and higher, and their power consumption density is also increasing significantly. When processors, systems-on-chips (SoCs), and embedded systems are running complex applications in actual use, abnormal behaviors such as over-temperature, over-voltage, over-current, or overload may occur.

[0051] In existing technologies, these specific signals are typically detected using sensors such as temperature, voltage, and current sensors. Upon detecting these signals, it is inferred that over-temperature, over-voltage, or over-current problems have occurred, and then relevant temperature control, voltage control, and power control measures are taken to ensure the safe, efficient, and stable operation of the CPU / SOC / embedded system. This sensor-based control scheme is a reactive, after-the-fact detection and remediation approach, which may result in performance fluctuations or the system entering an unsafe state before appropriate action is taken.

[0052] Besides being outdated, this existing implementation method also has the following technical problems:

[0053] 1. High cost. Various sensors need to be added in specific locations, such as temperature sensors and voltage sensors inside the CPU, which increases hardware costs; moreover, these sensors need to be calibrated at some stages to effectively ensure the sensing accuracy of the sensors.

[0054] 2. Spatial limitations. Sensors need to be close to the object being sensed to ensure accuracy. However, due to factors such as product structure and sensor size, the sensor is not easily placed in the optimal position. Ultimately, a balance is often struck between sampling accuracy and component layout and product structure.

[0055] 3. Significant differences in accuracy: The closer to the object being sampled, the more accurate the sampling, and vice versa; in addition, the sensor is also easily affected by other factors, which can lead to sampling errors and affect accuracy.

[0056] To address the aforementioned technical problems in existing technologies, this invention provides an intelligent control method for processors. Its core idea is to break away from the passive control mode of traditional technologies that relies on sensors for post-event perception and feedback. Instead, it analyzes and predicts various possible stages before the code is finally executed by the processor, proactively identifying instructions, instruction sequences, or programs that may cause resource overload (such as overtemperature, overvoltage, overcurrent, or overload). Based on the prediction results, it generates different outputs to take preventative measures before problems occur, thereby achieving safer, more efficient, and stable processor control.

[0057] like Figure 1 As shown, the method may include the following steps:

[0058] S110, at any stage before the executable code to be processed is submitted to the processor's execution unit, the executable code is acquired and analyzed by the analysis unit corresponding to that stage.

[0059] This stage includes: program compilation stage, post-compilation binary code analysis stage, program static code scanning stage, or instruction decoding stage during program runtime.

[0060] This invention innovatively extends the analysis timing to multiple stages of the code lifecycle, covering the entire process from development to runtime. In practical applications, it can be divided into the following four stages.

[0061] 1. Program Compilation Stage. The object of analysis in this stage is the source code of a high-level language (such as C or C++). The corresponding analysis unit is a dedicated code analysis module within the compiler. This module is integrated into the compilation toolchain and scans and analyzes the intermediate code representation or the target code to be generated after the compiler has completed syntax and semantic analysis. The advantage of this stage is that it can detect potential problems earliest, providing developers with the opportunity to modify the code.

[0062] 2. Post-compilation binary code analysis stage. The object of analysis in this stage is the binary object file or executable file output by the compiler. The corresponding analysis unit is a binary code scanning tool (a special type of offline analysis tool). This tool reads the binary file, converts it into an instruction sequence through a disassembler engine, or directly parses its binary structure for analysis.

[0063] 3. Static Code Scanning Phase. The object of analysis in this phase can be source code or binary code. The corresponding analysis unit is a static code analysis tool. These tools do not run the program; they only analyze the syntax, structure, control flow, and data flow of the code to discover potential patterns. Their advantage lies in their comprehensive analysis, capable of discovering complex instructions, instruction sequences, or programs.

[0064] 4. Instruction Decoding Stage During Program Execution. This stage analyzes the instruction stream that is about to enter the processor's pipeline execution unit. The corresponding analysis unit is the instruction recognition circuit integrated into the processor hardware. This circuit is a dedicated hardware logic module, located between the processor's instruction fetch unit and decoding unit. It can scan and match patterns for each instruction or instruction window in real time with low latency. The advantage of this stage is its ability to achieve ultimate real-time performance and proactive control.

[0065] During the instruction decoding phase of program execution, the identification of specific types of instructions / instruction sequences / programs can be achieved not only through special logic circuits (i.e., the instruction identification circuit mentioned above), but also by adding a thread, assigning a dedicated CPU, or designing a dedicated subsystem to judge and identify specific types of instructions / instruction sequences / programs, thereby achieving accurate prediction and taking relevant measures in advance after predicting high resource consumption scenarios.

[0066] For example, during actual execution, another CPU can determine and identify special instruction sequences. When it is identified that a high-power instruction / instruction sequence / program is about to be executed, countermeasures can be taken in advance, such as turning on the fan / increasing the fan speed, turning on the liquid cooling system / increasing the cooling speed, or reducing the voltage and frequency of other low-priority subsystems.

[0067] For example, a component can be added inside the CPU to identify instructions when the CPU fetches them. When a special instruction / instruction sequence is identified, a relevant notification is issued so that the system can take countermeasures in advance.

[0068] S120, the analysis unit, identifies whether the executable code contains predefined instructions, instruction sequences, or programs that indicate resource-intensive characteristics.

[0069] Among them, resource-intensive features refer to features that, during operation, can cause at least one of the processor's power consumption, bandwidth utilization, or computing resource utilization to exceed its corresponding safety threshold.

[0070] Specifically, this is the core step in achieving accurate prediction in this invention. The resource-intensive characteristic is a general term referring to the inherent attributes or tendencies exhibited by the code that, during runtime, could cause at least one of the following—processor core power consumption, bandwidth utilization, or computing resource utilization—to exceed its corresponding safety threshold.

[0071] As one implementation of this invention, the determination method for predefined instructions, instruction sequences, or programs indicating resource-intensive characteristics can include various methods. These can be based on existing industry standards (e.g., the maxpower program and memory copy program for ARM CPUs) and theories, or on experience (e.g., software code that enables all eight cores to operate at their highest frequencies on an 8-core chip), or on experimental measurements and results. The determination method for predefined instructions, instruction sequences, or programs indicating resource-intensive characteristics will be described in detail below.

[0072] The first approach is to define specific types of instructions related to high resource consumption based on theoretical analysis of the processor instruction set architecture.

[0073] Specifically, according to ARM CPU instruction theory (instructions with frequent data operations and data interactions tend to consume more power), the following instructions are identified as high-power instructions:

[0074] (a1) Load storage instructions (such as ldr, str);

[0075] (a2) Data transfer commands (such as mov);

[0076] (a3) Floating-point arithmetic instructions (such as floating-point multiplication, floating-point division, floating-point multiplication and addition);

[0077] (a4) Neon instruction;

[0078] (a5) The command to flush cache.

[0079] The second approach is to summarize the instruction sequence patterns or program structure patterns related to high resource consumption based on experience with historical code execution data on power consumption, bandwidth, or performance.

[0080] Specifically, based on CPU usage experience, the following programs have been identified as high-power programs due to their significant power consumption:

[0081] (b1) Programs for processing large amounts of data. For example, compression / decompression of large amounts of data; encoding / decoding of large amounts of data; and encryption / decryption of large amounts of data.

[0082] (b2) Large data volume transmission (such as a large number of memory copies).

[0083] (b3) Programs for high-speed data processing.

[0084] (b4) Programs that frequently access memory.

[0085] (b5) Maxpower program.

[0086] (b6) An 8-core chip, with all 8 cores running at their highest frequency.

[0087] The third method is to execute instructions, instruction sequences, or programs under preset environmental conditions and measure their runtime power consumption, bandwidth, or performance data, and then calibrate the instructions, instruction sequences, or programs that reach the resource consumption threshold based on the measurement results.

[0088] Specifically, in addition to theory and experience, experiments can also be conducted to measure the power consumption of specific instructions / instruction sequences / programs in order to identify high-power instructions / instruction sequences / programs.

[0089] For example, under the same environmental conditions, such as the same temperature, CPU voltage, CPU frequency, and CPU configuration, the CPU is made to execute a certain instruction / instruction sequence / program continuously for a period of time, and the power consumption under this scenario is measured. By comparing the power consumption under different instructions / instruction sequences / programs, it is possible to identify which instructions / instruction sequences / programs are high-power instructions / programs, and to identify the degree of power consumption of different instructions / instruction sequences / programs.

[0090] Furthermore, as one implementation of this invention, the analysis unit identifies whether the executable code contains predefined instructions, instruction sequences, or programs that indicate resource-intensive characteristics, including at least one of the following methods:

[0091] The first method is to identify whether the executable code contains predefined instructions of a specific type.

[0092] Among them, specific types of instructions include at least one of the following: load storage instructions, data transfer instructions, floating-point operation instructions, Neon instructions, or cache flush instructions (also known as Flush cache instructions).

[0093] Since the aforementioned specific types of instructions all result in significant power consumption, they can be referred to as high-power instructions. Of course, in practical applications, high-power instructions can include not only those listed above but also other high-power instructions; this embodiment of the invention does not specifically limit this. Furthermore, specific types of instructions can also include instructions with high performance, high bandwidth, etc., which will not be exhaustively listed here.

[0094] The second method involves statistically analyzing the frequency or density of specific types of instructions in the executable code and determining whether they exceed the corresponding statistical threshold.

[0095] Specifically, the analysis unit counts the frequency or density of specific instruction types: within a predetermined instruction window (e.g., 128 instructions), it counts the number of times or the percentage of such specific instruction types appear. If this statistical value exceeds a preset threshold (e.g., the percentage exceeds 40%), it is determined to be a high-risk instruction. For example, if an extremely high density of memory access instructions within a loop is identified, it is predicted that this will lead to excessive memory bandwidth utilization.

[0096] The third method is to identify whether the executable code matches a predefined resource-intensive program.

[0097] Among them, predefined resource-intensive programs include loops with nested depths exceeding a threshold or function call relationships containing known high-power functions.

[0098] Specifically, it can identify whether the executable code includes programs for processing large amounts of data, programs for high-speed data processing, programs for frequent memory access, Maxpower programs, or programs with all 8 cores running at their highest frequency.

[0099] Furthermore, it can analyze whether the nesting depth of loops exceeds a threshold or whether the function call relationship contains known high-power functions. Loop nesting depth refers to the number of levels in program code where one loop structure contains another. Each additional level of nesting typically increases computational complexity exponentially, thus drastically increasing the demand on processor computing resources and power consumption.

[0100] The above-mentioned exceeding the preset threshold means that the nesting level has reached a safety limit that has been set in advance through theoretical analysis, experience summary or experimental measurement. Exceeding this limit is considered to be highly likely to cause the processor to enter a high-load state.

[0101] Analysis units (such as static code analysis tools or compiler modules) parse the control flow graph of the code, tracing the nesting of loops. It starts counting from the outermost loop, incrementing inwards layer by layer, eventually determining the maximum nesting depth and comparing it to a preset threshold.

[0102] For example, consider the innermost core computing unit of a three-dimensional matrix multiplication problem. Its code typically exhibits a triple-nested loop structure. If experiments show that in this processor, when the nesting depth reaches three levels or more, there is a greater than 95% probability that the processor's power consumption will exceed the temperature limit, then the threshold can be preset to 3. When the analysis unit identifies the above code snippet, it will determine that its nesting depth is 3, which is equal to or exceeds the threshold, thus marking it as having high resource-intensive characteristics.

[0103] In this way, embodiments of the present invention can identify potential computing "hot spots" in advance from the code structure during the compilation or static scanning stage, and predict the high-performance computing requirements and high power consumption risks that they may bring without actually running the program.

[0104] The aforementioned known high-power functions refer to a function library, system API, or user-defined function that has been pre-marked as high-resource-consuming based on theoretical, empirical, or experimental measurements.

[0105] "Included in function call relationships" means that the function being analyzed or its call chain directly or indirectly calls the aforementioned known high-power functions.

[0106] Specifically, the analysis unit constructs or accesses a predefined list of high-power functions. During analysis, it parses the code's call graph, checking whether the current function calls a function in the list, or whether it exists on a call path that ultimately leads to a high-power function.

[0107] The following examples illustrate both direct and indirect invocation.

[0108] First, there's the direct call. The current function `func_a()` directly calls the `AES_encrypt()` function from the encryption library, which is listed in the high-power inventory. The analysis unit can directly identify this risk.

[0109] Second, indirect calls: the current function func_b() calls func_c(), which in turn calls a highly optimized FFT (Fast Fourier Transform) function from the math library. This FFT function is also listed as a high-power function. By analyzing the call relationships, the analysis unit can infer that func_b() also has a high-power tendency.

[0110] This method utilizes a knowledge base formed from historical performance data to quickly and accurately identify code that uses recognized high-performance computing libraries, encryption / decryption libraries, or graphics rendering interfaces. Even if the code structure itself is not complex, its resource-intensive characteristics can be effectively predicted.

[0111] By employing the two aforementioned assessment methods, this invention achieves accurate and efficient predictive identification of resource-intensive programs based on both code structure complexity and known high-performance library calls. This provides a solid and reliable basis for subsequent decision-making, whether generating prompts or triggering real-time hardware control signals.

[0112] S130 generates corresponding output results in response to the identified instructions, instruction sequences, or programs.

[0113] When the stage is the program compilation stage, the post-compilation binary code analysis stage, or the program static code scanning stage, the output result is a prompt message. The prompt message is used to guide developers to insert preventive instructions in the code. The preventive instructions include function call instructions for calling the system power management interface, thermal management interface, or frequency management interface.

[0114] When the stage is the instruction decoding stage during program execution, the output is a control signal, which is used to directly trigger the hardware functional module to adjust the processor's operating parameters.

[0115] For example, during the program compilation stage and the post-compilation binary code analysis stage, if a specific code segment is predicted to be running the maxpower program for an extended period of time or to exhibit overheating behavior, the developer is alerted and the corresponding code is added before and after the code location to implement temperature control protection measures (such as turning on the fan / increasing the fan speed, turning on the liquid cooling system / increasing the cooling speed, or reducing the voltage and frequency of other low-priority subsystems).

[0116] Alternatively, if a code snippet is detected that a high-power instruction (such as mov / ldr / str instruction) or instruction sequence is about to be executed for an extended period, the developer is alerted to add corresponding temperature control protection code before and after the relevant code location.

[0117] Alternatively, if a high density of high-power instructions (such as mov / ldr / str instructions) or instruction sequences is detected in a certain code segment, the developer is reminded to add corresponding temperature control protection code before and after the corresponding code location.

[0118] During the static code scanning phase, if a dangerous situation (such as high power consumption) is detected, an alarm message is given to notify the programmer that there is a high power consumption instruction in a certain place, and to remind the programmer to add the corresponding high power consumption prevention code at the corresponding code location.

[0119] During the instruction decoding phase of program execution, special logic circuits identify instructions / instruction sequences / programs with special indicators. After identifying the relevant situation, they transmit the information to the corresponding logic circuits through special signals such as interrupts / bus instructions, and the corresponding logic circuits take appropriate measures.

[0120] This invention provides an intelligent control method for processors. Its core idea is to break away from the passive control mode of traditional technologies that rely on sensors for post-event perception and feedback. Instead, it analyzes and predicts various possible stages before the code is finally executed by the processor, proactively identifying instructions, instruction sequences, or programs that may cause resource overload (such as overtemperature, overvoltage, overcurrent, and overload). Based on the prediction results, it generates different outputs to take preventative measures before problems occur, thereby achieving safer, more efficient, and stable processor control. Furthermore, this invention predicts the execution behavior by directly analyzing the characteristics of the code itself. Its judgment is entirely based on the code instructions and structure, unaffected by factors such as sensor physical layout, PCB traces, or ambient temperature interference. Therefore, its prediction and control accuracy is far higher than traditional schemes that rely on external sensor sampling, achieving more precise power consumption and performance management.

[0121] This invention also covers multiple stages from "program compilation" to "instruction decoding," forming a complete solution that spans the entire product development and operation lifecycle. It is applicable to both offline analysis and optimization during the development phase and real-time hardware control during product operation. It can be widely used in various processor-equipped products such as chips, terminals, base stations, and automobiles, exhibiting strong versatility and scalability.

[0122] Furthermore, this invention makes predictions by analyzing the existing instruction flow during the runtime phase, eliminating or significantly reducing the need for numerous high-precision temperature and voltage sensors around critical chip circuits. This not only reduces silicon area and hardware costs but also simplifies PCB layout and routing complexity, avoiding the additional overhead of sensor calibration. Moreover, this invention innovatively generates two output results based on different stages. During the development phase, it provides prompts to guide developers in fundamental software optimization, improving code quality; during the runtime phase, it generates hardware control signals, enabling fully automatic and rapid response. This dual-path mechanism provides unprecedented flexibility for system optimization.

[0123] In summary, this invention, through forward-looking prediction based on code features, successfully solves the inherent problems of hysteresis, poor accuracy, and high cost of traditional feedback control schemes, providing a safer, more efficient, more accurate, and more cost-effective new solution for processor power consumption and thermal management, significantly enhancing product competitiveness.

[0124] As one implementation of this invention, when the stage is the instruction decoding stage during program execution, a control signal is generated, including:

[0125] After recognizing an instruction, instruction sequence, or program, the instruction recognition circuit generates a hardware interrupt signal or issues a control command through the system bus.

[0126] Hardware interrupt signals or control instructions are used to directly trigger at least one of the following functional modules to perform operations:

[0127] The temperature control module is used to activate or enhance cooling measures.

[0128] The power management module is used to perform voltage regulation.

[0129] The clock module is used to prepare for clock frequency switching.

[0130] For example, upon detecting that a high-power instruction is about to be executed, the temperature control module / coprocessor is notified to activate the corresponding temperature control measures in advance. These temperature control measures include, but are not limited to, the following:

[0131] 1. Turn on the fan / increase the fan speed.

[0132] 2. Turn on the liquid cooling system / increase the cooling speed.

[0133] 3. Reduce the voltage and frequency of other low-priority subsystems.

[0134] 4. For example, if a high-power instruction is about to be executed, the boost module is notified to boost the voltage in advance to avoid the circuit voltage being too low and abnormalities occurring due to IRDrop;

[0135] 5. For example, if a high-power instruction is about to be executed, notify the clock module and make all necessary preparations for switching to a high-frequency clock in advance to reduce the waiting time for clock switching and avoid various abnormalities caused by insufficient clock switching time or unstable clock after switching.

[0136] As one implementation of this invention, issuing control commands via the system bus may include the following steps:

[0137] Write specific control values ​​to the registers of the power management module to trigger voltage regulation.

[0138] Specifically, after the instruction recognition circuit identifies a dangerous instruction sequence, its internal logic generates a control value and a target register address. As the bus master, the instruction recognition circuit sends a write command packet consisting of the control value and the target register address to the system bus. The system bus router then delivers the command packet to the power management module. The power management module decodes the address and writes the control value into its voltage control register. The voltage control register write operation triggers the voltage regulator to change its output.

[0139] The beneficial effects of this implementation method include the following aspects:

[0140] 1. Extremely low latency. This process is completed entirely at the hardware level, without the intervention of the operating system kernel or drivers, achieving microsecond or even nanosecond-level response speeds.

[0141] 2. High reliability. The hardware register-based control method ensures stable timing and is unaffected by software task scheduling, interrupt delays, or other factors.

[0142] 3. Precise control. By writing different control values ​​into the register, very fine voltage regulation (such as stepped boost / buck) can be achieved, thereby realizing the optimal balance between power consumption and performance.

[0143] In summary, writing control values ​​to the registers of the power management module via the system bus is a core hardware mechanism for achieving efficient, accurate, and fast forward-looking voltage control in this invention. It effectively and rapidly transforms the prediction at the instruction level into adjustment actions at the power level, which is the key to overcoming the excessive latency of traditional software solutions and achieving the technical effects of this invention.

[0144] It should be noted that specific types of instructions / instruction sequences / programs include, but are not limited to, the high power consumption characteristics described above, and can also include characteristics such as high performance / high bandwidth;

[0145] The above solutions focus on the identification, judgment, and application of high-power instructions / instruction sequences / programs for processors (power consumption control, temperature control, etc.).

[0146] A similar approach can be adopted for the identification, judgment, and application of high-performance / high-bandwidth instructions / instruction sequences / programs of the processor (bus usage control, memory usage control, performance control, system control, etc.).

[0147] Furthermore, the processors described in the embodiments of the present invention, in addition to CPUs, can also adopt similar schemes for GPUs / NPUs / DPUs / DSPs to achieve early identification of specific types of instructions / instruction sequences / programs and to take corresponding control schemes accordingly, thereby enabling GPUs / NPUs / DPUs / DSPs and the systems and products that use these processors to work better (lower power consumption, higher performance, better stability, etc.).

[0148] It should be noted that the countermeasures for specific types of instructions / instruction sequences / programs may include, but are not limited to, the measures described above, such as temperature control, voltage increase, frequency increase, and alarm prompts.

[0149] This invention also provides an intelligent control device 20 for a processor, such as... Figure 2 As shown, the device includes:

[0150] The acquisition and analysis module 210 is used to acquire and analyze the executable code at any stage before the executable code to be processed is submitted to the execution unit of the processor by the analysis unit corresponding to the stage; the stage is: program compilation stage, compiled binary code analysis stage, program static code scanning stage, or instruction decoding stage during program runtime;

[0151] The identification module 220 is used by the analysis unit to identify whether the executable code contains predefined instructions, instruction sequences or programs that indicate resource-intensive characteristics, wherein the resource-intensive characteristics refer to features that, during runtime, may cause at least one of the processor's power consumption, bandwidth utilization or computing resource utilization to exceed its corresponding safety threshold.

[0152] The output generation module 230 is used to generate corresponding output results in response to the identified instructions, instruction sequences or programs;

[0153] When the stage is the program compilation stage, the post-compilation binary code analysis stage, or the program static code scanning stage, the output result is a prompt message. The prompt message is used to guide developers to insert preventive instructions in the code. The preventive instructions include function call instructions for calling the system power management interface, thermal management interface, or frequency management interface.

[0154] When the stage is the instruction decoding stage during program execution, the output result is a control signal, which is used to directly trigger the hardware functional module to adjust the processor's operating parameters.

[0155] This invention also provides a chip that integrates the intelligent control device for the processor described in the second aspect.

[0156] This invention also provides an electronic device 300, such as... Figure 3 As shown, it includes a memory 301, a processor 302, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described in the first aspect.

[0157] Optionally, the electronic device may be any one of a smartphone, tablet computer, laptop computer, server, base station, drone, robot, or smart car.

[0158] This invention also provides a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method described in the first aspect.

[0159] This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0160] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A method for intelligent control of a processor, characterized in that, The method includes: At any stage before the executable code to be processed is submitted to the processor's execution unit, the executable code is acquired and analyzed by the analysis unit corresponding to the stage; the stage is: program compilation stage, compiled binary code analysis stage, program static code scanning stage, or program runtime instruction decoding stage; The analysis unit identifies whether the executable code contains predefined instructions, instruction sequences, or programs that indicate resource-intensive characteristics. The resource-intensive characteristics refer to features that, during runtime, can cause at least one of the processor's power consumption, bandwidth utilization, or computing resource utilization to exceed its corresponding safety threshold. If so, in response to the identified instruction, instruction sequence, or program, generate the corresponding output result; When the stage is the program compilation stage, the post-compilation binary code analysis stage, or the program static code scanning stage, the output result is a prompt message. The prompt message is used to guide developers to insert preventive instructions in the code. The preventive instructions include function call instructions for calling the system power management interface, thermal management interface, or frequency management interface. When the stage is the instruction decoding stage during program execution, the output result is a control signal, which is used to directly trigger the hardware functional module to adjust the processor's operating parameters.

2. The method as described in claim 1, characterized in that, When the stage is the program compilation stage, the analysis unit is a dedicated code analysis module in the compiler; When the stage is the post-compiled binary code analysis stage, the analysis unit is a binary code scanning tool; When the stage is the static code scanning stage, the analysis unit is a static code analysis tool; When the stage is the instruction decoding stage during program execution, the analysis unit is an instruction recognition circuit integrated into the processor hardware; or, the analysis unit is an identification module implemented by a dedicated thread, dedicated CPU core, or dedicated subsystem running on the processor.

3. The method as described in claim 1, characterized in that, The analysis unit identifies whether the executable code contains predefined instructions, instruction sequences, or programs that indicate resource-intensive characteristics, including at least one of the following methods: Identify whether the executable code contains predefined specific type instructions; the specific type instructions include at least one of load storage instructions, data transfer instructions, floating-point operation instructions, Neon instructions, or cache flush instructions. The frequency or density of specific types of instructions in the executable code is statistically analyzed, and it is determined whether they exceed the corresponding statistical threshold. The program that identifies the executable code matches a predefined resource-intensive program; the predefined resource-intensive program includes loops with a nesting depth exceeding a threshold or function call relationships containing known high-power functions.

4. The method according to any one of claims 1 to 3, characterized in that, The predefined instructions, instruction sequences, or programs that indicate resource-intensive characteristics are determined by at least one of the following methods: Based on theoretical analysis of processor instruction set architecture, specific types of instructions related to high resource consumption are defined; Based on experience summarizing power consumption, bandwidth, or performance data from historical code execution, instruction sequences or programs associated with high resource consumption are identified. By executing instructions, instruction sequences, or programs under preset environmental conditions and measuring their runtime power consumption, bandwidth, or performance data, instructions, instruction sequences, or programs that reach resource consumption thresholds can be calibrated based on the measurement results.

5. The method according to claim 2, characterized in that, When the aforementioned stage is the instruction decoding stage during program execution, control signals are generated, including: After recognizing the instruction, instruction sequence, or program, the instruction recognition circuit generates a hardware interrupt signal or issues a control command through the system bus. The hardware interrupt signal or control command is used to directly trigger at least one of the following functional modules to perform operations: The temperature control module is used to activate or enhance cooling measures; The power management module is used to perform voltage regulation; The clock module is used to prepare for clock frequency switching.

6. The method according to claim 5, characterized in that, The control commands issued via the system bus include: Write specific control values ​​to the registers of the power management module to trigger voltage regulation.

7. An intelligent control device for a processor, characterized in that, The device includes: An acquisition and analysis module is used to acquire and analyze the executable code at any stage before the executable code to be processed is submitted to the processor's execution unit, by an analysis unit corresponding to the stage; the stage is: program compilation stage, compiled binary code analysis stage, program static code scanning stage, or program runtime instruction decoding stage; The identification module is used by the analysis unit to identify whether the executable code contains predefined instructions, instruction sequences or programs that indicate resource-intensive characteristics, wherein the resource-intensive characteristics refer to features that, during runtime, may cause at least one of the processor's power consumption, bandwidth utilization or computing resource utilization to exceed its corresponding safety threshold. The output generation module is used to generate corresponding output results in response to the identified instructions, instruction sequences, or programs. When the stage is the program compilation stage, the post-compilation binary code analysis stage, or the program static code scanning stage, the output result is a prompt message. The prompt message is used to guide developers to insert preventive instructions in the code. The preventive instructions include function call instructions for calling the system power management interface, thermal management interface, or frequency management interface. When the stage is the instruction decoding stage during program execution, the output result is a control signal, which is used to directly trigger the hardware functional module to adjust the processor's operating parameters.

8. A chip, characterized in that, The chip integrates the intelligent control device for the processor as described in claim 7.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method as described in any one of claims 1 to 6.

10. The electronic device according to claim 9, characterized in that, The electronic device is any one of a smartphone, tablet computer, laptop computer, server, base station, drone, robot, or smart car.

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