Front-end processing module, processor, system and RISC-V custom instruction operation module

Abstract

The invention discloses a front-end processing module, a processor, a system and an RISC-V custom instruction operation module. An RISC-V instruction generation unit of the front-end processing module outputs an X86 instruction as a corresponding RISC-V instruction according to a pre-stored instruction processing result; the instruction processing result comprises that a first or third or fifth instruction is taken as input, and a second or fourth or sixth instruction is taken as output; if an equivalent RISC-V standard instruction replacing the X86 instruction exists, the X86 instruction and the equivalent RISC-V standard instruction are the first instruction and the second instruction respectively; otherwise, if a non-equivalent RISC-V standard instruction replacing the X86 instruction exists and the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirement or not, determining that the X86 instruction and the non-equivalent RISC-V standard instruction are a third instruction and a fourth instruction respectively if the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirement; and if not, determining that the X86 instruction and the corresponding RISC-V custom instruction are the fifth instruction and the sixth instruction respectively. According to the method, the X86 instruction set can be quickly and efficiently operated by the RISC-V architecture.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer technology, and in particular to a front-end processing module, a processor, a system and a RISC-V custom instruction operation module. BACKGROUND

[0002] Instruction Set Architecture (ISA), also known as instruction set or instruction set architecture, is the part of computer architecture related to programming. It defines the set of instructions that a CPU can execute and the data types, which is a complete definition of the interface between software and hardware. ISA not only includes basic data types, instruction sets, registers, addressing modes, but also involves storage architecture, interrupts, exception handling and external I / O, etc.

[0003] ISA has an important impact on computer performance, because it determines the way and efficiency of computer executing instructions. Specifically, ISA defines the set of all instructions that a computer can execute, each instruction specifies what operation the computer performs, the address space where the operand is stored, and the operand type. Therefore, ISA is the bridge connecting software and hardware in computer architecture, which enables software developers to write programs compatible with specific hardware architecture.

[0004] Common instruction set architecture types include X86, ARM and RISC-V, etc. Among them, X86 is a widely used instruction set architecture, originally introduced by Intel Corporation and has become the dominant architecture in the personal computer (PC) field. It has a complex instruction set and variable-length instruction encoding, suitable for high-performance computing and general-purpose computing. RISC-V is an open instruction set architecture with the characteristics of simplicity, scalability and customization. It is an instruction set architecture that has emerged in recent years and is widely used in various fields, including embedded systems, Internet of Things, high-performance computing, etc.

[0005] Currently, the Windows operating system ecosystem is still the most complete architecture in laptop, desktop and workstation application environments. However, due to the WinTel (Windows-Intel) architecture, the chances of Windows directly supporting RISC-V are minimal in the present and foreseeable future, which greatly limits the market development of RISC-V. Existing technical solutions are to run virtual machines on other systems or use software translation to run Windows or Windows application software, but the performance will be greatly reduced.

[0006] The disclosure of the foregoing Background is only used to assist in understanding the inventive concept and technical solutions of the present application, and does not necessarily constitute the prior art of the present application, nor necessarily give technical teaching; in the absence of explicit evidence that the above-mentioned content has been disclosed before the filing date of the present application, the above-mentioned background should not be used to evaluate the novelty and inventiveness of the present application. SUMMARY

[0007] The purpose of the present application is to provide a front-end processing module, a processor, a system and a RISC-V custom instruction operation module, which can quickly and efficiently implement the RISC-V architecture running the X86 instruction set.

[0008] To achieve the above purpose, the technical scheme adopted by the present application is as follows:

[0009] A front-end processing module suitable for the RISC-V architecture running the X86 instruction set, comprising an input end, an X86 instruction decoder and a RISC-V instruction generation unit;

[0010] The input end reads the X86 instruction and transmits it to the X86 instruction decoder;

[0011] The X86 instruction decoder decodes the X86 instruction and outputs it to the RISC-V instruction generation unit;

[0012] The RISC-V instruction generation unit has pre-stored the instruction processing result of the X86 instruction corresponding to the RISC-V instruction, and the instruction processing result is obtained by the following way:

[0013] For any one X86 instruction in the target X86 instruction set;

[0014] Determine whether there is an equivalent RISC-V standard instruction to replace the X86 instruction, the function of the equivalent RISC-V standard instruction is consistent with the function of the X86 instruction and the execution efficiency difference between the two is within a preset range, if there is, determine the X86 instruction as the first instruction, and determine the equivalent RISC-V standard instruction as the second instruction;

[0015] If not, determine whether there is a non-equivalent RISC-V standard instruction to replace the X86 instruction, if there is, determine whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirement, if it meets, determine the X86 instruction as the third instruction, and determine the non-equivalent RISC-V standard instruction as the fourth instruction;

[0016] If it does not meet, determine the RISC-V custom instruction to replace the X86 instruction, and determine the X86 instruction as the fifth instruction, and determine the RISC-V custom instruction as the sixth instruction;

[0017] Based on the above steps, the instruction processing result is obtained, including: taking the first instruction as input, then taking the second instruction as output; taking the third instruction as input, then taking the fourth instruction as output; taking the fifth instruction as input, then taking the sixth instruction as output;

[0018] The RISC-V instruction generation unit translates the decoded X86 instruction into a corresponding RISC-V instruction according to the instruction processing result.

[0019] The necessary condition for replacing the X86 instruction with the RISC-V instruction is that the function of the RISC-V instruction is consistent with the function of the X86 instruction. Based on the function, the present application further judges whether there is a RISC-V standard instruction (existing) that can replace the X86 instruction, and further divides the RISC-V standard instruction into equivalent RISC-V standard instruction and non-equivalent RISC-V standard instruction based on the execution efficiency difference of the RISC-V standard instruction replacing the corresponding X86 instruction, that is, the RISC-V standard instruction includes the equivalent RISC-V standard instruction and the non-equivalent RISC-V standard instruction. If the execution efficiency of a RISC-V standard instruction is consistent or close to the execution efficiency of the X86 instruction (the execution efficiency difference of the two is within a preset range) or the execution efficiency of the RISC-V standard instruction is better, it is judged that the RISC-V standard instruction is the equivalent RISC-V standard and the X86 instruction is directly replaced by the equivalent RISC-V standard. If the execution efficiency of a RISC-V standard instruction is quite different from the execution efficiency of the X86 instruction (the execution efficiency difference of the two is not within a preset range), it is necessary to further judge whether the execution efficiency of the RISC-V standard instruction can meet the application requirement. If it can, the RISC-V standard instruction is used to replace the X86 instruction, otherwise the RISC-V custom instruction is used to replace the X86 instruction.

[0020] Further, any of the technical solutions or a combination of the technical solutions described above further includes obtaining the instruction processing result by the following steps:

[0021] For any one X86 instruction in the target X86 instruction set;

[0022] If there is no equivalent RISC-V standard instruction to replace the X86 instruction, and there is also no non-equivalent RISC-V standard instruction to replace the X86 instruction;

[0023] The RISC-V custom instruction is determined to replace the X86 instruction, the X86 instruction is determined to be the fifth instruction, and the RISC-V custom instruction is determined to be the sixth instruction.

[0024] Further, any of the technical solutions or combinations of the technical solutions described above, traversing any one X86 instruction in the target X86 instruction set and obtaining the instruction processing result, the instruction processing result including a first instruction set, a second instruction set, a third instruction set, a fourth instruction set, a fifth instruction set and a sixth instruction set;

[0025] Among them, the first instruction set includes one or more first instructions, the second instruction set includes one or more second instructions, and the second instruction corresponds to the first instruction one by one;

[0026] The third instruction set includes one or more third instructions, the fourth instruction set includes one or more fourth instructions, and the fourth instruction corresponds to the third instruction one by one;

[0027] The fifth instruction set includes one or more fifth instructions, the sixth instruction set includes one or more sixth instructions, and the sixth instruction corresponds to the fifth instruction one by one.

[0028] Further, any of the technical solutions or combinations of the technical solutions described above, further comprising a code stream running optimization module, the code stream running optimization module is configured to monitor the RISC-V instruction code stream output by the RISC-V instruction generation unit, the RISC-V instruction code stream includes one or more of the second instruction, the fourth instruction and the sixth instruction; the code stream running optimization module is also configured to adjust the output order and / or execution order of each RISC-V instruction in the RISC-V instruction code stream;

[0029] And / or,

[0030] Further comprising a RISC-V decoder, the RISC-V decoder is configured to decode the RISC-V instruction output by the RISC-V instruction generation unit.

[0031] Further, any of the technical solutions or combinations of the technical solutions described above, further comprising a RISC-V self-defined instruction operation module, the RISC-V self-defined instruction operation module runs the sixth instruction with an efficiency greater than that of the RISC-V standard instruction operation module running the sixth instruction;

[0032] The RISC-V self-defined instruction operation module is configured to run the sixth instruction output by the RISC-V instruction generation unit.

[0033] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the RISC-V custom instruction operation module includes a data cache unit, a register unit and an operation unit, wherein the number of the register unit and the operation unit are both multiple and the two are electrically connected in a one-to-one correspondence to form an operator, and the multiple operators are connected in series to form an operator group;

[0034] The output end of the data cache unit is electrically connected to the input end of the operator group, and the output end of the operator group is electrically connected to the input end of the data cache unit.

[0035] Furthermore, according to any one of the technical solutions or a combination of multiple technical solutions described above, the output end of each of the arithmetic units is electrically connected to the input end of the data cache unit.

[0036] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, the RISC-V custom instruction operation module is also configured to run the second instruction and / or the fourth instruction.

[0037] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, whether the execution efficiency of the non-equivalent RISC-V standard instructions meets the preset requirements is determined by the following method:

[0038] Determine the execution duration of the X86 instruction and determine it as a first duration;

[0039] Determine the execution duration of the non-equivalent RISC-V standard instruction and determine it as the second duration;

[0040] Whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements is determined based on the second time length and the first time length.

[0041] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, judging whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements according to the second duration and the first duration includes:

[0042] Calculate the difference between the second duration and the first duration to obtain a duration difference, where the duration difference = the second duration - the first duration;

[0043] If the duration difference is less than a preset duration difference threshold, the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements; otherwise, it does not meet the requirements.

[0044] Further, according to any one of the above technical solutions or a combination of the above technical solutions, the execution efficiency of the non-equivalent RISC-V standard instruction is determined to meet the preset requirement according to the second time length and the first time length.

[0045] A time length difference is calculated according to the second time length and the first time length, and the time length difference = the second time length - the first time length.

[0046] An execution efficiency ratio of the non-equivalent RISC-V standard instruction relative to the execution efficiency of the X86 instruction is calculated to obtain an execution efficiency ratio, and the execution efficiency ratio = (the time length difference / the first time length) x 100%.

[0047] If the execution efficiency ratio is less than a preset ratio threshold, the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirement; otherwise, the execution efficiency of the non-equivalent RISC-V standard instruction does not meet the preset requirement.

[0048] Further, according to any one of the above technical solutions or a combination of the above technical solutions, the execution efficiency of the non-equivalent RISC-V standard instruction is determined to meet the preset requirement by the following method:

[0049] The execution time length of the X86 instruction is determined and is determined as a first time length.

[0050] If the first time length is less than a preset time length threshold, the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirement.

[0051] According to another aspect of the present application, a processor for running an X86 instruction set by a RISC-V architecture is provided, and the processor comprises the front-end processing module for running the X86 instruction set by the RISC-V architecture according to any one of the above technical solutions or a combination of the above technical solutions.

[0052] According to another aspect of the present application, a computer system is provided, and the computer system is configured to be based on the front-end processing module for running the X86 instruction set by the RISC-V architecture according to any one of the above technical solutions or a combination of the above technical solutions.

[0053] According to another aspect of the present application, a RISC-V self-defined instruction operation module for running a RISC-V instruction is provided, and the RISC-V self-defined instruction operation module comprises a data buffer unit, a register unit, and an operation unit, wherein the number of the register unit and the operation unit is multiple, and the register unit and the operation unit are electrically connected one by one to form an operation unit, and multiple operation units are connected in series to form an operation unit group.

[0054] The output end of the data cache unit is electrically connected with the input end of the operation group, and the output end of the operation group is electrically connected with the input end of the data cache unit.

[0055] a. The present application stores the instruction processing result in the hardware device, and translates the X86 instruction to RISC-V in real time through hardware, so that the designer can maintain the original RISC-V design as much as possible, and the RISC-V processor does not need to rely on software translation, does not need to rely on simulation software or hardware, does not use the virtual machine of the operating system, can directly support the running of the X86 instruction set, and can directly run the Windows operating system, does not need to realize the translation or compile software optimization, thereby avoiding the result that the instruction code becomes more due to the instruction translation, and the method provided by the present application can effectively improve the efficiency and compatibility of the RISC-V architecture running the X86 instruction set;

[0056] b. The present application can reduce the complexity of the RISC-V architecture supporting Intel AVX and SIMD type instructions, and further improve the efficiency and performance of the RISC-V architecture running the X86 instruction set by using the RISC-V self-defined instruction and the RISC-V self-defined instruction operation module;

[0057] c. The present application can let the subsequent instruction operation module process as much as possible in parallel by using the code stream running optimization module to monitor one or more of the second instruction, the fourth instruction and the sixth instruction, and adjusting and distributing the output order and / or execution order of each RISC-V instruction in the RISC-V instruction code stream constituted by one or more of the second instruction, the fourth instruction and the sixth instruction, thereby reducing the waiting time of the code stream and improving the instruction running efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the present application, and those skilled in the art can obtain other drawings according to these drawings without creating any creative labor.

[0059] Figure 1 The selection flowchart for translating X86 instruction to RISC-V instruction provided by an exemplary embodiment of the present application;

[0060] Figure 2A flowchart of a method for implementing the RISC-V architecture to run the X86 instruction set through hardware is provided as an exemplary embodiment of the present invention;

[0061] Figure 3 A flowchart of selecting a method for translating AVX512 instructions into RISC-V instructions is provided for an exemplary embodiment of the present invention;

[0062] Figure 4 A schematic diagram of a typical five-stage processing flow of a processor provided for an exemplary embodiment of the present invention;

[0063] Figure 5 A schematic diagram of the architecture of a RISC-V processor provided as an exemplary embodiment of the present invention;

[0064] Figure 6 A schematic diagram of the architecture of a front-end processing module provided for an exemplary embodiment of the present invention;

[0065] Figure 7 This is a schematic diagram of the architecture of a RISC-V instruction operation module in the prior art;

[0066] Figure 8 A schematic diagram of the architecture of a RISC-V custom instruction operation module provided as an exemplary embodiment of the present invention;

[0067] Figure 9 A schematic diagram of the dependency relationship between instructions in a machine code stream of a RISC-V instruction is provided as an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0068] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0069] It should be noted that the terms "first", "second", and the like in the description and claims of the application and the above drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, device, product or equipment including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or equipment.

[0070] Instruction set architecture (ISA) is an indispensable part of computer architecture, which defines the instruction format, instruction type and data type of computer, and has an important influence on computer performance. With the growing demand for chip autonomy and the expanding demand in the fields of Internet of Things and edge computing, the instruction set architecture is showing the following development trends:

[0071] Open source and customizability: The rise of open source instruction set architectures such as RISC-V allows designers to tailor and customize according to specific application requirements, better adapting to different application scenarios;

[0072] High performance and low power consumption: With the continuous advancement of technology, future instruction set architectures will focus more on the balance between high performance and low power consumption to meet the growing computing demands;

[0073] Multi-architecture fusion: In order to adapt to the application requirements of different fields, future computer systems may adopt a fusion scheme of multiple instruction set architectures to achieve higher performance and flexibility.

[0074] Based on this, the present application proposes a method, processor and system for implementing RISC-V architecture to run X86 instruction set through hardware, which can quickly and efficiently implement RISC-V architecture to run X86 instruction set, in order to meet the development trends of open source and customizability, high performance and low power consumption, and multi-architecture fusion.

[0075] In one embodiment of the application, a method for implementing RISC-V architecture to run X86 instruction set through hardware is provided, referring to Figure 1 and Figure 2 , the method comprises the following steps:

[0076] for any one X86 instruction in the target X86 instruction set;

[0077] determining whether there is an equivalent RISC-V standard instruction that replaces the X86 instruction, the function of the equivalent RISC-V standard instruction is consistent with the function of the X86 instruction, and the execution efficiency difference between the two is within a preset range, if there is, determining the X86 instruction as a first instruction, and determining the equivalent RISC-V standard instruction as a second instruction;

[0078] if not, determining whether there is a non-equivalent RISC-V standard instruction that replaces the X86 instruction, if there is, determining whether the execution efficiency of the non-equivalent RISC-V standard instruction meets a preset requirement, if it meets, determining the X86 instruction as a third instruction, and determining the non-equivalent RISC-V standard instruction as a fourth instruction;

[0079] if not, determining a RISC-V custom instruction that replaces the X86 instruction, and determining the X86 instruction as a fifth instruction, and determining the RISC-V custom instruction as a sixth instruction;

[0080] based on the above steps, obtaining an instruction processing result and storing it in a hardware device, the instruction processing result includes:

[0081] with the first instruction as input, the second instruction is output;

[0082] with the third instruction as input, the fourth instruction is output;

[0083] with the fifth instruction as input, the sixth instruction is output.

[0084] based on the above method of implementing the RISC-V architecture to run the X86 instruction set through hardware, the instruction processing result is configured as a processing module stored in the hardware device, which can enable designers to quickly design new solutions in an integrated manner (based on the processing module, the solution of running the corresponding X86 instruction set based on the RISC-V architecture can be quickly implemented), under the premise of maintaining the original RISC-V design as much as possible, the RISC-V processor does not need to rely on software translation, does not need to rely on simulation software or hardware, does not use the virtual machine (virtual machine) of the operating system, can directly support the X86 instruction set, and can directly run the Windows operating system, so that the RISC-V architecture processor can efficiently run Windows and the application software thereon.

[0085] The above method provided by the present application can dynamically convert the machine code stream of the X86 instruction into a single machine code or a sequence of machine codes of the corresponding RISC-V instruction (hereinafter referred to as equivalent translation) in time under the condition of maintaining the original RISC-V architecture, and then send the machine code into the operation unit in the RISC-V processor for operation. During the operation process, the X86 instruction does not need to be translated in advance by means of software, nor does it need to be processed by means of any virtual machine instruction or virtual machine mode to realize the operation of the X86 instruction set in the RISC-V architecture. Therefore, the method provided by the present application can effectively improve the performance and compatibility of the operation of the X86 instruction set in the RISC-V architecture.

[0086] In the present embodiment, as shown in Figure 1 and Figure 2 , any one X86 instruction in the target X86 instruction set is traversed to obtain the instruction processing result, and the instruction processing result includes a first instruction set, a second instruction set, a third instruction set, a fourth instruction set, a fifth instruction set and a sixth instruction set.

[0087] The first instruction set includes one or more first instructions, the second instruction set includes one or more second instructions, and the second instruction corresponds to the first instruction one by one; the third instruction set includes one or more third instructions, the fourth instruction set includes one or more fourth instructions, and the fourth instruction corresponds to the third instruction one by one; the fifth instruction set includes one or more fifth instructions, and the sixth instruction set includes one or more sixth instructions, and the sixth instruction corresponds to the fifth instruction one by one. After determining the first instruction set, the second instruction set, the third instruction set, the fourth instruction set, the fifth instruction set and the sixth instruction set, any one X86 instruction in the target X86 instruction set can be directly equivalent translated into the corresponding RISC-V instruction by means of table lookup.

[0088] Preferably, the first instruction is configured with a first label, the second instruction is configured with a second label, the second label has a corresponding relationship with the first label; the third instruction is configured with a third label, the fourth instruction is configured with a fourth label, the fourth label has a corresponding relationship with the third label; the fifth instruction is configured with a fifth label, and the sixth instruction is configured with a sixth label, the sixth label has a corresponding relationship with the fifth label. By setting the label, the efficiency of equivalent translation of the X86 instruction into the corresponding RISC-V instruction can be further improved. For example, the first instruction configured with the first label only needs to find the corresponding RISC-V instruction in the plurality of second instructions configured with the second label, and does not need to find the corresponding RISC-V instruction in the second instruction set, the fourth instruction set and the sixth instruction set.

[0089] In one embodiment of the present application, a method for running X86 instruction set through RISC-V architecture by hardware is provided, as shown in Figure 1 and Figure 2 The method further comprises the following steps:

[0090] for any one X86 instruction in the target X86 instruction set;

[0091] if there is no equivalent RISC-V standard instruction to replace the X86 instruction, and there is also no non-equivalent RISC-V standard instruction to replace the X86 instruction;

[0092] determine a RISC-V custom instruction to replace the X86 instruction, and determine the X86 instruction as the fifth instruction, and determine the RISC-V custom instruction as the sixth instruction.

[0093] The method for running X86 instruction set through RISC-V architecture by hardware provided by the present application utilizes the feature that in RISC-V instruction set architecture, in addition to including RISC-V standard instruction set, custom instructions / instruction set can also be defined. In the process of designing and selecting to translate X86 instructions into RISC-V instructions, if there is inefficiency caused by instruction translation, or there is no existing RISC-V standard instruction to replace X86 instructions, then a RISC-V custom instruction is defined to replace the X86 instruction.

[0094] It should be noted that in any of the above embodiments, there are multiple implementation methods for determining the RISC-V custom instruction to replace the X86 instruction. Specifically, the RISC-V custom instruction can be implemented by hardware or by software. The present application does not limit the specific method for determining the RISC-V custom instruction to replace the X86 instruction. As long as the function of the newly determined / defined RISC-V custom instruction is consistent with the function of the X86 instruction, and the performance (usually execution efficiency) of the RISC-V custom instruction meets the expectation.

[0095] Among them, the hardware implementation of the RISC-V custom instruction to replace the X86 instruction includes modifying the hardware description file, for example, adding the implementation of the RISC-V custom instruction consistent with the function of the X86 instruction in the hardware description file (usually.v file) of the RISC-V core. Generally, the instruction decoding part and the execution part need to be modified to support new instruction formats and operation codes, so that the custom instruction can be correctly parsed and executed; and Quartus and other tools are used for hardware synthesis and implementation to generate.pof files and the like for configuring FPGA and other hardware devices, so as to fix the hardware logic of the custom instruction in the hardware.

[0096] The RISC-V instruction replacing the X86 instruction is implemented by a software manner through a binary compiler and the like, including defining a new custom instruction and operation logic to define the RISC-V custom instruction; generating an operation code macro definition, defining a new operation code macro in a header file, so as to be used in assembly code, such as #define DOT_OPCODE 0x6B; modifying the GNU tool chain to support the new custom instruction, usually including modifying the assembler, linker and compiler; finally testing the RISC-V custom instruction, writing a test program to verify whether the function of the new RISC-V custom instruction is consistent with the target X86 instruction, and verifying the performance of the RISC-V custom instruction, to ensure that the correctness and performance of the RISC-V custom instruction meet the expectations.

[0097] Referring to Figure 3 As for the AVX-512 instruction set in the Intel X86 processor, the instruction width is expanded to 512 bits, and 32 double-precision or 64 single-precision floating point (FP) operations can be performed in each clock cycle, which is specially designed for application scenarios such as large-scale operation requirements of image / audio / video processing, data analysis, scientific calculation, data encryption and compression, and deep learning. Figure 3The dashed line in the figure indicates the flow line that is not selected after the judgment. At present, there is no equivalent RISC-V standard instruction with the same function as the AVX-512 instruction and close execution efficiency, so it is judged that there is no equivalent RISC-V standard instruction that can replace the AVX-512 instruction. The AVX-512 instruction can be translated by the "V" standard vector extension of RISC-V, so it is judged that there is a non-equivalent RISC-V standard instruction to replace the AVX-512 instruction. However, using a non-equivalent RISC-V standard instruction to translate the AVX-512 instruction cannot meet the requirements in terms of running efficiency. Because if a non-equivalent RISC-V standard instruction is used to translate the AVX-512 instruction, loop processing will be required, and the memory address will not be aligned, which will slow down the running speed, so a large number of RISC-V instructions will be required to complete an X86 instruction, which will also cause the RISC-V architecture to run the AVX-512 instruction set inefficiently. Therefore, in the present application, the RISC-V custom instruction is used to replace the AVX-512 instruction, and more preferably, it is further judged whether the running efficiency of the RISC-V custom instruction replacing the AVX-512 instruction can meet the requirements, and if not, a custom instruction operation unit is added to improve the operation efficiency of the translated RISC-V instruction. In addition, if there is no support for V-standard extension instructions, the RISC-V architecture cannot run the AVX-512 instruction set in the form of instruction translation, so using the RISC-V custom instruction to replace the AVX-512 instruction is the preferred solution.

[0098] In the above various embodiments, there are multiple ways to judge whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements.

[0099] The first way is to determine the execution time of the X86 instruction as a first time length, and determine the execution time of the non-equivalent RISC-V standard instruction as a second time length; according to the second time length and the first time length, judge whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements. Specifically, the difference between the second time length and the first time length is calculated to obtain a time difference, the time difference = the second time length - the first time length; if the time difference is less than a preset time difference threshold, then the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements; otherwise, it does not meet the requirements.

[0100] The second way is to determine the execution time of the X86 instruction and determine it as a first time length, and determine the execution time of the non-equivalent RISC-V standard instruction and determine it as a second time length; according to the second time length and the first time length, it is judged whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirement. The difference between the second time length and the first time length is calculated to obtain a time length difference, the time length difference = the second time length - the first time length. The ratio of the execution efficiency of the non-equivalent RISC-V standard instruction to the execution efficiency of the X86 instruction is calculated to obtain an execution efficiency ratio, the execution efficiency ratio = (the time length difference / the first time length) x 100%. If the execution efficiency ratio is less than a preset ratio threshold, whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirement; otherwise, it does not meet.

[0101] The third way is to determine the execution time of the X86 instruction and determine it as a first time length; if the first time length is less than a preset time length threshold, the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirement.

[0102] It should be noted that the above three judgment methods are exemplary, and the present application does not limit the way of judging whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirement to only the above three judgment methods.

[0103] In order to further improve the efficiency and performance of running the X86 instruction set through the hardware implementing the RISC-V architecture, in an embodiment of the present application, as shown in Figure 8 The method further comprises pre-designing a RISC-V custom instruction operation module, the efficiency of the RISC-V custom instruction operation module running the sixth instruction is greater than that of the RISC-V standard instruction operation module running the sixth instruction; and configuring the RISC-V custom instruction operation module to run the sixth instruction.

[0104] The RISC-V custom instruction operation module includes a data buffer unit, a register unit, and an operation unit, wherein the number of the register unit and the operation unit is multiple and they are one-to-one corresponding and electrically connected to form an operation unit, and multiple operation units are connected in series to form an operation unit group. The output end of the data buffer unit is electrically connected with the input end of the operation unit group, and the output end of the operation unit group is electrically connected with the input end of the data buffer unit. More preferably, the output end of each operation unit is also electrically connected with the input end of the data buffer unit. The present application utilizes the RISC-V custom instruction set and the corresponding RISC-V custom instruction operation module to support the X86 special instruction set or the SIMD instruction required by Windows, thereby improving the efficiency and compatibility of RISC-V running the X86 instruction set. It should be noted that the specific architecture of the RISC-V custom instruction operation module is not limited to the one shown in the embodiment Figure 8 The RISC-V custom instruction operation module can also have other settings as long as it can run the RISC-V custom instruction and improve the running efficiency of the RISC-V custom instruction.

[0105] Taking the 512-bit matrix operation required by the AVX-512 instruction set as an example, the existing RISC-V instruction operation module as shown in Figure 7 has only one set of 64-bit operation unit 603 (operation unit or multiplier), and when matrix data needs to be operated, it needs to pass through the operation unit 603 and the register one 601 and the register two 602 multiple times, and store the result of each operation to the data buffer 604 for next time operation through the register and the operation unit, so the operation efficiency is low. However, if the RISC-V custom instruction operation module as shown in Figure 8 is used, it includes one-to-one corresponding four register units and four operation units, each register unit includes two operation units or multipliers, as shown in Figure 8As shown, the four register units include a first register unit, a second register unit, a third register unit and a fourth register unit, the first register unit includes a first register 701 and a second register 702, the second register unit includes a third register 703 and a fourth register 704, the third register unit includes a fifth register 705 and a sixth register 706, the fourth register unit includes a seventh register 707 and an eighth register 708, and the four operation units include a first operation unit 709 to a fourth operation unit 712. For example, four matrix operations are required, and the RISC-V instruction operation module provided in the application is used, the operation result of the first operation unit 709 is directly output to the second register unit and a second matrix operation is performed by using the second operation unit 710, the operation result of the second operation unit 710 is directly output to the third register unit and a third matrix operation is performed by using the third operation unit 711, the operation result of the third operation unit 711 is directly output to the fourth register unit and a fourth matrix operation is performed by using the fourth operation unit 712, and finally the operation result is transmitted to the data cache unit 713. It is not necessary to transmit the operation result of each operation unit to the data cache unit and then send it to the operation unit again to perform the next operation as shown in the RISC-V instruction operation module. Figure 7 Therefore, the RISC-V instruction operation module provided in the application can effectively improve the operation efficiency and performance of the RISC-V instruction.

[0106] In addition, the output end of each operation unit is also electrically connected with the input end of the data cache unit, and the output end of the data cache unit is electrically connected with the input end of each operation unit. Figure 8 As shown, the RISC-V self-defined instruction operation module configured with four operation units can directly output the operation result of the third operation unit 711 to the data cache unit 713 when processing three matrix operations, and does not need to pass through the fourth operation unit 712 and the corresponding register group, thereby further improving the operation efficiency of the RISC-V instruction.

[0107] The method provided in the application can use the self-defined RISC-V instruction and the RISC-V self-defined instruction operation module to reduce the overhead caused by replacing the X86 CISC instruction with the RISC-V instruction sequence, and can also reduce the complexity of making the RISC-V architecture support the Intel AVX and the SIMD (Single Instruction Multiple Data) type instruction. For example, the instruction set specific to the INTEL X86 processor, such as the AVX instruction set or the SIMD instruction set. It should be noted that the RISC-V self-defined instruction operation module can also be configured to run the second instruction and the fourth instruction.

[0108] In an embodiment of the present application, the method of running X86 instruction set through hardware implementing RISC-V architecture further comprises configuring a code stream running optimization module, the code stream running optimization module is configured to monitor RISC-V instruction code stream, the RISC-V instruction code stream comprises one or more of the second instruction, the fourth instruction and the sixth instruction. Preferably, the second instruction, the fourth instruction and the sixth instruction are all input into the code stream running optimization module, and the code stream running optimization module is configured to adjust and allocate the output order and / or execution order of each RISC-V instruction in the RISC-V instruction code stream.

[0109] The typical five-stage processing flow of a processor is shown as Figure 4 One of the purposes of the present application is to obtain a front-end processing module capable of being quickly imported into a processor or a front-end processing module capable of being called by a processor based on the above design method to minimize the changes of the original design.

[0110] In an embodiment of the present application, based on the instruction processing result in the above embodiment, a front-end processing module for running X86 instruction set through hardware implementing RISC-V architecture is provided, as shown in Figure 5 The front-end processing module has the function of an instruction reading unit, the binary code stream of X86 instruction is input into the input end of the front-end processing module, and the front-end processing module directly and equivalently translates X86 instruction into the binary code stream of RISC-V and sends it into a back-end decoder.

[0111] Specifically, the architecture of the front-end processing module 210 is shown in Figure 6 The input end 211 is configured with an input end temporary storage unit, so that the front-end processing module 210 can read and cache X86 instruction in advance through the input end, thereby reducing the waiting time and delay caused by cache miss.

[0112] The X86 instruction read and cached through the input end 211 is further output to the X86 instruction decoder 212, the X86 instruction decoder 212 decodes the X86 instruction and outputs it to the RISC-V instruction generation unit 213, and the RISC-V instruction generation unit 213 directly and equivalently translates the decoded X86 instruction into the corresponding RISC-V instruction based on the method of running X86 instruction set through hardware implementing RISC-V architecture provided in the above embodiment.

[0113] In designing the equivalent translation function of the RISC-V instruction generation unit 213, one or a sequence of instructions in the RISC-V standard instruction can be selected to complete, or be translated with RISC-V custom instructions. In order to maximize the use of the operation unit derived from the custom instruction, and can be classified into different custom instruction sets according to the characteristics and the custom operation unit used by the custom instruction. The selection logic of the equivalent translation is as shown in Figure 1 and Figure 2 The translation selection of the above X86 AVX-512 instruction will have a flow selection as Figure 3 The result of the selection is used to determine what kind of corresponding RISC-V instruction machine code stream combination the RISC-V instruction generation unit 213 should generate.

[0114] A more efficient way is to prestore the instruction processing results of the X86 instruction corresponding to the RISC-V instruction in the RISC-V instruction generation unit 213, which includes the first instruction set, the second instruction set, the third instruction set, the fourth instruction set, the fifth instruction set and the sixth instruction set.

[0115] Among them, the first instruction set includes one or more first instructions, the second instruction set includes one or more second instructions, and the second instruction corresponds to the first instruction one by one; the third instruction set includes one or more third instructions, the fourth instruction set includes one or more fourth instructions, and the fourth instruction corresponds to the third instruction one by one; the fifth instruction set includes one or more fifth instructions, and the sixth instruction set includes one or more sixth instructions, and the sixth instruction corresponds to the fifth instruction one by one. After determining the first instruction set, the second instruction set, the third instruction set, the fourth instruction set, the fifth instruction set and the sixth instruction set, any X86 instruction in the target X86 instruction set can be directly equivalent to the corresponding RISC-V instruction by table lookup.

[0116] Preferably, the first instruction is configured with a first label, the second instruction is configured with a second label, the second label has a corresponding relationship with the first label; the third instruction is configured with a third label, the fourth instruction is configured with a fourth label, the fourth label has a corresponding relationship with the third label; the fifth instruction is configured with a fifth label, the sixth instruction is configured with a sixth label, the sixth label has a corresponding relationship with the fifth label. By setting the label, the efficiency of equivalent translation of the X86 instruction into the corresponding RISC-V instruction can be further improved. For example, the first instruction configured with the first label only needs to find the corresponding RISC-V instruction in the plurality of second instructions configured with the second label, and does not need to find the corresponding RISC-V instruction in the second instruction set, the fourth instruction set and the sixth instruction set. It should be noted that the instruction processing result can be obtained by the method for running the X86 instruction set through the RISC-V architecture through hardware provided in any of the above embodiments, or can be obtained by other means.

[0117] The output end 214 is configured with a corresponding output end buffer area, and the machine code of the RISC-V instruction obtained by X86 instruction translation is temporarily stored in the output end temporary storage area of the front-end processing module in the form of an output queue.

[0118] In order to maintain the original design integrity of the original RISC-V processor to the greatest extent and reduce the resource investment of design integration, the result of the front-end processing module 210 provided in the embodiment is sent to the RISC-V decoder 220 in the form of RISC-V instruction machine code, instead of microcode, so that the RISC-V processor can minimize the integration of the translation function and play the effect of modularization.

[0119] By configuring the front-end processing module 210 provided in the embodiment in the RISC-V processor, the function of directly reading the binary code stream of X86 and directly equivalent translating into the binary code stream of RISC-V and sending into the back-end RISC-V decoder of the RISC-V processor can be realized.

[0120] In addition, the above-mentioned method and front-end processing module of the present application are provided with an arithmetic unit (ALU) supporting the operation function required by the custom instruction, so that the custom instruction can be simplified and the efficiency can be improved by cooperating with the additional arithmetic unit module.

[0121] Currently, each design company needs to invest a lot of resources to research the method of running X86 instructions based on RISC-V architecture, and by using the method and front-end processing module provided by the application and the open source characteristics of RISC-V, the design sharing or authorization is carried out in a standardized manner, so that each design company can integrate the design in the form of modules through authorization, thereby reducing the investment of repeated research and development resources and accelerating the speed of product launch. The method provided by the application promotes the establishment of X86 translation to RISC-V instruction standardization and reduces the investment of repeated resources.

[0122] Therefore, in one embodiment of the application, a processor for running X86 instruction set based on RISC-V architecture by hardware is also provided. The architecture of the processor is as shown in Figure 5 The processor includes a front-end processing module 210, a RISC-V decoder 220, a code stream running optimization module 230, a RISC-V standard instruction operation module 240, a RISC-V self-defined instruction operation module 250, and a storage management module 260.

[0123] The front-end processing module 210 is configured to directly and equivalently translate X86 instructions into corresponding RISC-V instructions and output them to the RISC-V decoder 220. The RISC-V instructions include equivalent RISC-V standard instructions, non-equivalent RISC-V standard instructions, and RISC-V self-defined instructions that replace the X86 instructions.

[0124] The RISC-V decoder 220 decodes the input RISC-V instructions and outputs the decoded RISC-V instructions to the code stream running optimization module 230. To improve the execution efficiency of the translated RISC-V instruction code stream, the code stream running optimization module 230 is arranged at the output end of the RISC-V decoder 220. The code stream running optimization module 230 is electrically connected to the front-end processing module 210, and is configured to read the RISC-V instructions temporarily stored at the output end of the front-end processing module 210. By monitoring / inspecting the code stream temporarily stored at the output end of the front-end processing module in advance, the resource-related degree of the execution process and the dependency between operations are calculated, and the execution order and output order of the instructions are optimized.

[0125] More preferably, the micro processing unit 231 (Micro Controler Module, MCU), cache and register 232 built-in the processor are used to run the corresponding instructions in the code stream in advance, increase parallel processing, reduce the congestion of subsequent operation units, improve the utilization of operation resources, and thus improve the execution efficiency. The micro processing unit 231 and the cache and register 232 can be integrated in the code stream running optimization module 230, or can be arranged outside the code stream running optimization module 230 and electrically connected with the code stream running optimization module 230, so as to realize the function of the code stream running optimization module adjusting and distributing the output order and / or execution order of each RISC-V instruction in the RISC-V instruction code stream.

[0126] After the output order and / or execution order of each RISC-V instruction in the RISC-V instruction code stream is adjusted and distributed by the code stream running optimization module 230, the RISC-V standard instructions are sequentially transmitted to the RISC-V standard instruction operation module 240, and the RISC-V self-defined instructions are sequentially transmitted to the RISC-V self-defined instruction operation module 250. The RISC-V standard instruction operation module 240 and the RISC-V self-defined instruction operation module 250 respectively process and run the RISC-V instructions received thereby, and transmit the running results to the storage management module 260 for storage. The storage management module 260 includes registers and memories.

[0127] The storage management module 260 is electrically connected with the micro processing unit 231, and uses the micro processing unit 231 to process part or all of the instructions in the instruction stream code in advance, or optimizes the processing of the corresponding instructions and stores them in the cache and register 232. After the instruction operation is completed, the storage management module 260 receives the corresponding instruction operation results, and the micro processing unit 231 is notified by the end register and memory, i.e. the storage management module 260, to release the resources occupied by the cache and register 232.

[0128] In the present application, the instruction translation is performed in real time by hardware, and does not need to use software to implement translation or compiler for optimization, so that the result of increasing the number of instruction codes caused by instruction translation can be avoided. In addition, since the output of the front-end processing module provided by the present application is the machine code of RISC-V, not the microcode, and the code stream pre-stored in the output queue at the output end of the front-end processing module is checked by the code stream running optimization module, the subsequent RISC-V operation module can be processed as much as possible in parallel, so that the waiting time of the code stream can be reduced, and the efficiency can be improved. The following is described through a specific embodiment.

[0129] In one embodiment of the present application, a machine code stream translated into RISC-V instructions is expressed in RISC-V assembly language as shown in Table 1. For simplicity of illustration, only the adder in the arithmetic unit and the memory management function are used, and the operation of the adder requires one clock cycle, and the cache read using memory management requires two clock cycles. If run sequentially, it takes eight clock cycles to complete as shown in Table 2.

[0130] But based on the register, the dependency of the instruction, the dependency between the instructions such as operation and storage can be established as shown in Table 3. Figure 9 The code stream running optimization module 230 is configured to perform running optimization based on the dependency between the instructions such as operation and storage, and advance the running of instruction 4, and instructions 5 and 6 can also be advanced and processed in parallel, adjust the timing of the instructions sent to the calculation unit, and obtain a new instruction running result as shown in Table 3. Considering that instruction 5 requires two clock cycles to complete, the new running can be completed in six clock cycles, which is more efficient than the original eight clock cycles to complete, effectively improving the instruction running efficiency.

[0131] Table 1

[0132] Program Assembly Arithmetic unit Clock number 1 ADDI R1, R2, 4 Adder 1 2 LD R3, 16(R2) Memory management 2 3 ADDI R4, R2, 8 Adder 1 4 ADDI R5, R1, 4 Adder 1 5 LD R4, 32(R3) Memory management 2 6 ADDI R1, R2, 16 Adder 1

[0133] Table 2

[0134]

[0135] Table 3

[0136]

[0137] In one embodiment of the present application, a front-end processing module for running X86 instruction set based on RISC-V architecture by hardware is provided. In this embodiment, the front-end processing module further includes a RISC-V decoder 220 and a code stream running optimization module 230 based on the above-mentioned front-end processing module embodiment, that is, in this embodiment, the RISC-V decoder 220 and the code stream running optimization module 230 in the above-mentioned front-end processing module embodiment are integrated in the front-end processing module. Further, the RISC-V custom instruction operation module 250 can also be integrated in the front-end processing module.

[0138] In one embodiment of the present application, a processor is provided, which is configured to call an instruction processing result pre-stored in a hardware device, and replace an X86 instruction with a RISC-V instruction according to the instruction processing result, and the instruction processing result is obtained based on the method for running X86 instruction set based on RISC-V architecture by hardware in any one of the above-mentioned embodiments or a combination of multiple embodiments.

[0139] In one embodiment of the present application, a computer system is provided, which is configured to implement RISC-V architecture to run X86 instruction set based on the method of implementing RISC-V architecture to run X86 instruction set by hardware as any one of the above embodiments or combination of multiple embodiments.

[0140] It should be noted that the processor, computer system and front-end processing module embodiments provided by the present application have the same inventive concept as the method embodiments of implementing RISC-V architecture to run X86 instruction set by hardware, and all the contents of the method embodiments of implementing RISC-V architecture to run X86 instruction set by hardware are incorporated into the processor, computer system and front-end processing module embodiments by introduction.

[0141] It should be noted that in this document, relational terms such as first and second and the like can only be used to distinguish one entity or action from another entity or action, without necessarily requiring or implying that there is any such actual relationship or order between these entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof are intended to cover a non-exclusive inclusion, so that a process, method, article, or apparatus that comprises a list of elements does not include only those elements, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0142] The above description is merely one specific implementation of the present application, and it should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A front-end processing module suitable for running the X86 instruction set on the RISC-V architecture, characterized in that: It includes input terminal, X86 instruction decoder and RISC-V instruction generation unit; The input terminal reads the X86 instruction and transmits it to the X86 instruction decoder; The X86 instruction decoder decodes the X86 instruction and outputs it to the RISC-V instruction generation unit; The RISC-V instruction generation unit pre-stores the instruction processing result of the X86 instruction corresponding to the RISC-V instruction, and the instruction processing result is obtained in the following manner: For any X86 instruction in the target X86 instruction set; Determining whether there is an equivalent RISC-V standard instruction that can replace the X86 instruction, where the function of the equivalent RISC-V standard instruction is consistent with the function of the X86 instruction and the difference in execution efficiency between the two is within a preset range; if so, determining that the X86 instruction is the first instruction, and determining that the equivalent RISC-V standard instruction is the second instruction; If not, determining whether there is a non-equivalent RISC-V standard instruction that replaces the X86 instruction; if so, determining whether the execution efficiency of the non-equivalent RISC-V standard instruction meets a preset requirement; if so, determining that the X86 instruction is the third instruction, and determining that the non-equivalent RISC-V standard instruction is the fourth instruction; If not satisfied, determining a RISC-V custom instruction to replace the X86 instruction, determining the X86 instruction as the fifth instruction, and determining the RISC-V custom instruction as the sixth instruction; Obtaining the instruction processing result based on the above steps includes: taking the first instruction as input, and then taking the second instruction as output; taking the third instruction as input, and then taking the fourth instruction as output; taking the fifth instruction as input, and then taking the sixth instruction as output; The RISC-V instruction generation unit translates the decoded X86 instruction into a corresponding RISC-V instruction according to the instruction processing result.

2. The front-end processing module suitable for running the X86 instruction set in the RISC-V architecture according to claim 1, characterized in that: The method further includes obtaining the instruction processing result by the following steps: For any X86 instruction in the target X86 instruction set; If there is no equivalent RISC-V standard instruction to replace the X86 instruction, and there is no non-equivalent RISC-V standard instruction to replace the X86 instruction; Then determine the RISC-V custom instruction that replaces the X86 instruction, determine the X86 instruction as the fifth instruction, and determine the RISC-V custom instruction as the sixth instruction.

3. The front-end processing module suitable for running the X86 instruction set in the RISC-V architecture according to claim 1 or 2, characterized in that: Traversing any X86 instruction in the target X86 instruction set and obtaining the instruction processing result, wherein the instruction processing result includes a first instruction set, a second instruction set, a third instruction set, a fourth instruction set, a fifth instruction set, and a sixth instruction set; The first instruction set includes one or more first instructions, the second instruction set includes one or more second instructions, and the second instructions correspond to the first instructions in a one-to-one manner; The third instruction set includes one or more third instructions, the fourth instruction set includes one or more fourth instructions, and the fourth instructions correspond one-to-one to the third instructions; The fifth instruction set includes one or more fifth instructions, the sixth instruction set includes one or more sixth instructions, and the sixth instructions correspond one-to-one to the fifth instructions.

4. The front-end processing module suitable for running the X86 instruction set in the RISC-V architecture according to claim 1, characterized in that: The system further includes a code stream operation optimization module, wherein the code stream operation optimization module is configured to monitor the RISC-V instruction code stream output by the RISC-V instruction generation unit, wherein the RISC-V instruction code stream includes one or more of the second instruction, the fourth instruction, and the sixth instruction; the code stream operation optimization module is further configured to adjust the output order and / or execution order of each RISC-V instruction in the RISC-V instruction code stream; and / or, It also includes a RISC-V decoder, which is configured to decode the RISC-V instructions output by the RISC-V instruction generation unit.

5. The front-end processing module suitable for running the X86 instruction set in the RISC-V architecture according to claim 1, characterized in that: Also included is a RISC-V custom instruction operation module, wherein the efficiency of the RISC-V custom instruction operation module in running the sixth instruction is greater than the efficiency of the RISC-V standard instruction operation module in running the sixth instruction; The RISC-V custom instruction operation module is configured to run the sixth instruction output by the RISC-V instruction generation unit.

6. The front-end processing module suitable for running the X86 instruction set in the RISC-V architecture according to claim 5, characterized in that: The RISC-V custom instruction operation module includes a data cache unit, a register unit and an operation unit, wherein the number of the register unit and the operation unit are both multiple and the two are electrically connected in a one-to-one correspondence to form an operator, and the multiple operators are connected in series to form an operator group; The output end of the data cache unit is electrically connected to the input end of the operator group, and the output end of the operator group is electrically connected to the input end of the data cache unit.

7. The front-end processing module suitable for running the X86 instruction set in the RISC-V architecture according to claim 6, characterized in that: The output end of each of the arithmetic units is electrically connected to the input end of the data cache unit.

8. The front-end processing module suitable for running the X86 instruction set in the RISC-V architecture according to claim 5, characterized in that: The RISC-V custom instruction operation module is also configured to run the second instruction and / or the fourth instruction.

9. The front-end processing module suitable for running the X86 instruction set in the RISC-V architecture according to claim 1, characterized in that: Whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements is determined by the following method: Determine the execution duration of the X86 instruction and determine it as a first duration; Determine the execution duration of the non-equivalent RISC-V standard instruction and determine it as the second duration; Whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements is determined based on the second time length and the first time length.

10. The front-end processing module suitable for running the X86 instruction set in the RISC-V architecture according to claim 9, characterized in that: Determining whether the execution efficiency of the non-equivalent RISC-V standard instruction meets a preset requirement according to the second duration and the first duration includes: Calculate the difference between the second duration and the first duration to obtain a duration difference, where the duration difference = the second duration - the first duration; If the duration difference is less than a preset duration difference threshold, the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements; otherwise, it does not meet the requirements.

11. The front-end processing module suitable for running the X86 instruction set in the RISC-V architecture according to claim 9, characterized in that: Determining whether the execution efficiency of the non-equivalent RISC-V standard instruction meets a preset requirement according to the second duration and the first duration includes: Calculate the difference between the second duration and the first duration to obtain a duration difference, where the duration difference = the second duration - the first duration; Calculating a ratio of the execution efficiency of the non-equivalent RISC-V standard instruction to the execution efficiency of the X86 instruction to obtain an execution efficiency ratio, where the execution efficiency ratio = (the duration difference / the first duration) × 100%; If the execution efficiency ratio is less than the preset ratio threshold, the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements; otherwise, it does not meet the requirements.

12. The front-end processing module suitable for running the X86 instruction set in the RISC-V architecture according to claim 1, characterized in that: Whether the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements is determined by the following method: Determine the execution duration of the X86 instruction and determine it as a first duration; If the first duration is less than a preset duration threshold, the execution efficiency of the non-equivalent RISC-V standard instruction meets the preset requirements.

13. A processor that implements the RISC-V architecture and runs the X86 instruction set through hardware, characterized in that: The processor includes a front-end processing module according to any one of claims 1 to 12 suitable for running the X86 instruction set in the RISC-V architecture.

14. A computer system, characterized in that: The computer system is configured as a front-end processing module for running an X86 instruction set based on a RISC-V architecture as described in any one of claims 1 to 12.

15. A RISC-V custom instruction operation module, characterized in that: Used to run RISC-V instructions, the RISC-V custom instruction operation module includes a data cache unit, a register unit and an operation unit, wherein the number of the register unit and the operation unit are both multiple and the two are electrically connected in a one-to-one correspondence to form an operator, and the multiple operators are connected in series to form an operator group; The output end of the data cache unit is electrically connected to the input end of the operator group, and the output end of the operator group is electrically connected to the input end of the data cache unit.

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