High-bandwidth DDR command scheduling system based on multi-FIFO cascade

Abstract

The invention particularly relates to a high-bandwidth DDR (Double Data Rate) command scheduling system based on multi-FIFO (First In First Out) cascade. The high-bandwidth DDR command scheduling system comprises a read channel and a write channel, wherein the read channel consists of an RD Buffer FIFO and a plurality of Page FIFOs; the write channel consists of a WR Buffer FIFO and a plurality of Page FIFOs; the RD Buffer FIFO is a read cache FIFO, and the data content of the RD Buffer FIFO is a read address, a token and a timer in a RawIF reading command sent by a host; the WRBuffer FIFO is a write cache FIFO, and the data content of the WRBuffer FIFO is a write address, write data Wrdata, a data mask and a timer in a write RawIF command sent by a host; according to the method, the defects that the transmission bandwidth and the transmission efficiency of the DDR are low, and part of low-priority commands cannot be executed for a long time and are starved can be overcome.

Description

TECHNICAL FIELD

[0001] The present application relates to command scheduling, in particular to a high-bandwidth DDR command scheduling system based on multi-FIFO cascading. BACKGROUND

[0002] With the continuous acceleration of the process of digitization, the requirements of various electronic devices for data processing capacity are growing exponentially. From supercomputers to mobile intelligent terminals, from industrial automation devices to cloud computing servers, DDR (Double Data Rate) memory as a key component for temporary data storage and high-speed transmission, its performance is directly related to the running efficiency of the whole system.

[0003] In the prior art, the address mapping of the DDR command scheduling system usually directly maps the AXI command to the SDRAM particle address, which often causes the SDRAM read and write commands split from the same AXI Burst to frequently switch the row address in the same bank. After the fixed priority or simple polling scheduling strategy, the Act and Precharge commands which require a large time overhead frequently appear, which greatly reduces the transmission bandwidth of the DDR. In order to avoid conflicts between read and write commands, the existing controller usually uses a scheduling method of alternately executing read and write commands, which reduces the continuity of the execution of commands in the same direction and seriously affects the transmission efficiency. In addition, the controller using the fixed priority scheduling strategy may cause some low-priority commands to be starved for a long time. SUMMARY

[0004] (I) Technical problems solved

[0005] In view of the above shortcomings of the prior art, the present application provides a high-bandwidth DDR command scheduling system based on multi-FIFO cascading, which can effectively overcome the defects of low transmission bandwidth and transmission efficiency of the DDR and long-term starvation of some low-priority commands in the prior art.

[0006] (II) Technical solutions

[0007] To achieve the above purpose, the present application is realized by the following technical solutions:

[0008] The high-bandwidth DDR command scheduling system based on multi-FIFO cascading comprises a read channel composed of an RD Buffer FIFO and a plurality of Page FIFOs, a write channel composed of a WR Buffer FIFO and a plurality of Page FIFOs, a CMD FIFO, a TOKEN FIFO FOR CMD, a TOKEN FIFO FOR RD DATA, and a WDATA FIFO.

[0009] RD Buffer FIFO, for buffering read address, token and timer in read RawIF command sent by host;

[0010] WR Buffer FIFO, for buffering write address, write data, data mask and timer in write RawIF command sent by host;

[0011] Page FIFO, for buffering address, token, write data, data mask and timer in command after mapping with page information;

[0012] CMD FIFO, for buffering address of scheduling completion command;

[0013] TOKEN FIFO FOR CMD, for buffering token sent to DFI with read address;

[0014] TOKEN FIFO FOR RDDATA, for buffering token sent to AXI with read data;

[0015] WDATA FIFO, for buffering write data and data mask corresponding to write address.

[0016] Preferably, when Page FIFO is empty, after storing a command, the page information and timer of the stored command become the page information and timer of the stored Page FIFO, and with the continuous storage of subsequent commands, the timer of Page FIFO is set to the timer of the command with shorter time.

[0017] Preferably, the working process of read channel includes:

[0018] When host sends read RawIF command, if RD Buffer FIFO is not full, then buffer read address, token and timer in read RawIF command;

[0019] The command readout in the RD Buffer FIFO is address mapped, i.e. the read address is converted into the SDRAM particle address SDRAMAddr, the low bits of the read address are converted into the col bits of the SDRAM particle address SDRAMAddr, and the remaining bits are converted into the bankgroup, bank, row, cs bits of the SDRAM particle address SDRAMAddr from low to high. In this way, the continuous AXI address will not appear in the case of switching the row address in the same bank, the number of Act and Precharge commands to be sent is reduced, the bankgroup is switched preferentially, and the interval between two commands when switching the bank is shorter.

[0020] The read address, token Token and timer Timer in the mapped command are transmitted into the subsequent Page FIFO.

[0021] The token Token is used to reorder the read data Rddata returned out of order when the read data Rddata corresponding to the read address is read out from the SDRAM particle.

[0022] The timer Timer is used to record the countdown of the time elapsed since the command enters the scheduling. The countdown will continue in the RD Buffer FIFO and the Page FIFO.

[0023] Preferably, the read command read out from the RD Buffer FIFO enters the Page FIFO in the following manner:

[0024] All address bits except the col bit, i.e. the page information of the read command, are compared with the page information of the Page FIFO in turn:

[0025] 1) If there is a Page FIFO with the same page information as the read command, and the Page FIFO is not full, not empty, and not starting to discharge the command, the read address, token Token and timer Timer in the read command are stored into the first successfully compared Page FIFO;

[0026] 2) If there is a Page FIFO with the same page information as the read command, but the Page FIFO with the same page information is full or is discharging the command, or there is no Page FIFO with the same page information as the read command, but there is an empty Page FIFO, the read address, token Token and timer Timer in the read command are stored into the empty Page FIFO with the smallest index value.

[0027] 3) If there is a Page FIFO with the same page information as the read command, but all Page FIFOs with the same page information are full or are discharging commands, and all Page FIFOs with different page information are not empty, or there is no Page FIFO with the same page information as the read command, and all Page FIFOs are not empty, then the transmission is suspended until the above-mentioned 1) or 2) is met, and the read address, token Token and timer Timer in the read command are stored in the corresponding Page FIFO.

[0028] Preferably, the working process of the write channel includes:

[0029] When the host sends a write RawIF command, if the WRBufferFIFO is not full, the write address, write data Wrdata, data mask DataMask and timer Timer in the write RawIF command are cached;

[0030] The command in the WRBufferFIFO is read out for address mapping, i.e. the write address is converted into SDRAM chip address SDRAMAddr;

[0031] The write address, write data Wrdata, data mask DataMask and timer Timer in the mapped command are transmitted into the subsequent Page FIFO;

[0032] Wherein, the write data Wrdata and data mask DataMask are the write data and DM information corresponding to the command respectively;

[0033] The timer Timer is used to record the countdown of the time experienced by the command after entering the dispatch, and the countdown will continue in the WRBufferFIFO and Page FIFO.

[0034] Preferably, the way of entering the Page FIFO for the write command read out from the WRBufferFIFO includes:

[0035] All address bits except the col bit, i.e. the page information of the write command, are compared with the page information of the Page FIFO in turn:

[0036] 1) If there is a Page FIFO with the same page information as the write command, and the Page FIFO is not full, not empty, and has not started discharging commands, then the write address, write data Wrdata, data mask DataMask and timer Timer in the write command are stored in the first successfully compared Page FIFO;

[0037] 2) If there is a Page FIFO with the same page information as the write command, but all Page FIFOs with the same page information are full or are discharging commands, or there is no Page FIFO with the same page information as the write command, but there is an empty Page FIFO, then the write address, write data Wrdata, data mask Data Mask and timer Timer in the write command are stored in the empty Page FIFO with the smallest index value;

[0038] 3) If there is a Page FIFO with the same page information as the write command, but all Page FIFOs with the same page information are full or are discharging commands, and all Page FIFOs with different page information are not empty, or there is no Page FIFO with the same page information as the write command, and all Page FIFOs are not empty, then transmission is suspended until the above-mentioned 1) or 2) is satisfied, and the write address, write data Wrdata, data mask Data Mask and timer Timer in the write command are stored in the corresponding Page FIFO.

[0039] Preferably, one Page FIFO with the highest priority is selected in the read channel and the write channel respectively, and then a Page FIFO with higher priority is selected from the two Page FIFOs. If the CMD FIFO is not full and the selected command is a write command, then the selected Page FIFO directly starts discharging the command. If the selected command is a read command, then the selected Page FIFO starts discharging the command only when the TOKEN FIFO FORRDDATA is also not full. The next selection of Page FIFO is performed after the selected Page FIFO is emptied.

[0040] Since the same Page FIFO caches commands with the same page information, the commands with page hit can be continuously transmitted. The maximum number of continuously transmitted commands with page hit can be adjusted by controlling the depth of the Page FIFO, so as to avoid the situation that the commands without page hit are starved due to the continuous transmission of the commands with page hit.

[0041] Preferably, the strategy of selecting one Page FIFO with the highest priority in the read channel or the write channel includes:

[0042] The first priority is Starved FIFO, that is, the Page FIFO whose timer Timer has been counted down to 0;

[0043] The second priority is the Address collision FIFO, i.e. the Page FIFO in which there is a command whose address is identical to that of the command about to enter the dispatch system;

[0044] The third priority is the Page FIFO with a smaller timer Timer when there is no Starved FIFO of the first priority and no Address collision FIFO of the second priority;

[0045] When there are multiple Page FIFOs with the highest priority selected from the read channel or the write channel, the Page FIFO with a smaller index value is selected preferentially;

[0046] The strategy for selecting the Page FIFO with a higher priority between the read channel and the write channel comprises:

[0047] The first priority is the Starved FIFO, and if the Page FIFOs with the highest priority selected from the read channel and the write channel are both Starved FIFOs, the Starved FIFO in the same direction as the last executed command is selected preferentially;

[0048] The second priority is the Address collision FIFO, and if the Page FIFOs with the highest priority selected from the read channel and the write channel are both Address collision FIFOs, the Address collision FIFO in the same direction as the last executed command is selected preferentially;

[0049] The third priority is the Page FIFO with a smaller timer Timer, and if the timers Timer of the Page FIFOs with the highest priority selected from the read channel and the write channel are identical, the Page FIFO in the same direction as the last executed command is selected preferentially.

[0050] Preferably, after the selected Page FIFO starts to issue the command, the address of the command is sent to the CMD FIFO, and if the issued command is a read command, the token Token in the read command is written into the TOKEN FIFO FOR CMD and the TOKEN FIFO FOR RDDATA; if the issued command is a write command, the write data Wrdata and the data mask DataMask in the write command are written into the WDATA FIFO.

[0051] Preferably, when the CMD FIFO is not empty, a req signal is generated to send a command request to the subsequent module, if the subsequent module generates a response, a command is read from the CMD FIFO, if the read command is a read command, a token Token is read from the TOKEN FIFO FOR CMD and sent to the subsequent module together with the read command; if the read command is a write command, a set of write data Wrdata and data mask DataMask are read from the WDATA FIFO and sent to the subsequent module together with the write command;

[0052] When the read command is executed and the read data transmitted by the DFI is received, the token Token transmitted from the DFI is compared with the current token Token in the TOKEN FIFO FOR RDDATA, if the two tokens Token are the same, the read data is sent to the AXI together with the current token Token in the TOKEN FIFO FOR RDDATA for reordering and then sent to the host.

[0053] (Three) beneficial effects

[0054] Compared with the prior art, the high-bandwidth DDR command scheduling system based on the multi-FIFO cascade provided by the application can split an AXI command sent by the host into multiple SDRAM commands through address mapping, and at the same time, the multiple SDRAM commands are collected on the same Page FIFO as much as possible, and the commands in the same Page FIFO are preferentially scheduled, so that the page hit command is continuously sent. Through the above two levels of control, the protocol overhead time can be greatly reduced. In the command scheduling between the read channel and the write channel, when the priority of the read command and the write command is the same, the command in the same direction as the last executed command is preferentially scheduled to reduce the protocol overhead time of read-write switching. By adding the timer Timer, the situation that the low-priority command is "starved" can be effectively avoided. The system greatly improves the transmission bandwidth and transmission efficiency of the DDR through reasonable control of the command scheduling, and reduces the difficulty of system implementation through the use of the multi-FIFO cascade mode. BRIEF DESCRIPTION OF DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0056] Figure 1 The system schematic diagram of the present application;

[0057] Figure 2 Flowchart for selecting a Page FIFO with the highest priority in the read channel or the write channel in the present application;

[0058] Figure 3 Flowchart for selecting a Page FIFO with the higher priority between the read channel and the write channel in the present application, and the last executed command is a write command;

[0059] Figure 4 Flowchart for selecting a Page FIFO with the higher priority between the read channel and the write channel in the present application, and the last executed command is a read command. DETAILED DESCRIPTION

[0060] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0061] A high-bandwidth DDR command scheduling system based on multi-FIFO cascade, as shown in FIG. 1, includes a read channel composed of one RDBufferFIFO and multiple (2-8) Page FIFOs, a write channel composed of one WRBufferFIFO and multiple (2-8) Page FIFOs, and a CMD FIFO, a TOKEN FIFO FOR CMD, a TOKEN FIFO FOR RDDATA and a WDATA FIFO; Figure 1 RD BufferFIFO, a read cache FIFO, data content is the read address, token Token and timer Timer in the read RawIF command sent by the host;

[0062] WRBufferFIFO, a write cache FIFO, data content is the write address, write data Wrdata, data mask DataMask and timer Timer in the write RawIF command sent by the host;

[0063]

[0064] ​Page FIFO, a FIFO for buffering address, token Token, write data Wrdata, data mask Data Mask and timer Timer in a page information buffered post-command (wherein read address, token Token and timer Timer in a read Page FIFO buffered post-command, write address, write data Wrdata, data mask Data Mask and timer Timer in a write Page FIFO buffered post-command), when the Page FIFO is empty, after storing a command, the page information and timer Timer of the stored command become the page information and timer Timer of the stored Page FIFO, as subsequent commands are continuously stored, the timer Timer of the Page FIFO is set to the timer Timer of the command with shorter time;

[0065] CMD FIFO, a FIFO for buffering address of a dispatch complete command;

[0066] TOKEN FIFO FOR CMD, a FIFO for buffering token Token sent to DFI along with a read address;

[0067] TOKEN FIFO FOR RDDATA, a FIFO for buffering token Token sent to AXI along with read data;

[0068] WDATA FIFO, a FIFO for buffering write data Wrdata and data mask Data Mask corresponding to a write address.

[0069] The working process of the read channel includes:

[0070] When the host sends a read RawIF command, if the RD Buffer FIFO is not full, the read address, token Token and timer Timer in the read RawIF command are buffered;

[0071] The command in the RD Buffer FIFO is read out for address mapping, i.e. the read address is converted into SDRAM particle address SDRAMAddr, the low bits of the read address are converted into the col bits of the SDRAM particle address SDRAMAddr, and the remaining bits are converted into the bankgroup (if any), bank, row and cs bits of the SDRAM particle address SDRAMAddr from low to high, so that continuous AXI addresses will not appear in the switching of row addresses within the same bank, reducing the number of Act and Precharge commands to be sent, and the bank group is switched preferentially, so that the interval between two commands when switching the bank is shorter;

[0072] The read address, token Token and timer Timer in the mapped command are transmitted into the subsequent Page FIFO;

[0073] The token Token is used to reorder the read data Rddata returned out of order when the read data Rddata corresponding to the read address is read from the SDRAM chip.

[0074] The timer Timer is used to record the countdown of the time elapsed since the command entered the scheduling.

[0075] Specifically, the read command read from the RD Buffer FIFO enters the Page FIFO in the following manner:

[0076] All address bits except the col bit, i.e. the page information of the read command, are compared with the page information of the Page FIFO in turn:

[0077] 1) If there is a Page FIFO with the same page information as the read command, and the Page FIFO is not full, not empty, and not starting to discharge the command, the read address, token Token and timer Timer in the read command are stored into the first successfully compared Page FIFO.

[0078] 2) If there is a Page FIFO with the same page information as the read command, but the Page FIFO with the same page information is full or is discharging the command, or there is no Page FIFO with the same page information as the read command, but there is an empty Page FIFO, the read address, token Token and timer Timer in the read command are stored into the empty Page FIFO with the smallest index value.

[0079] 3) If there is a Page FIFO with the same page information as the read command, but the Page FIFO with the same page information is full or is discharging the command, and the remaining Page FIFOs with different page information are all not empty, or there is no Page FIFO with the same page information as the read command, and all the Page FIFOs are not empty, the transmission is suspended until the above-mentioned 1) or 2) is satisfied, and the read address, token Token and timer Timer in the read command are stored into the corresponding Page FIFO.

[0080] The working process of the write channel includes:

[0081] When the host sends a write RawIF command, if the WRBufferFIFO is not full, the write address, write data Wrdata, data mask DataMask and timer Timer in the write RawIF command are buffered;

[0082] The command in the WRBufferFIFO is read out for address mapping, i.e. the write address is converted into an SDRAM chip address SDRAMAddr;

[0083] The write address, write data Wrdata, data mask DataMask and timer Timer in the mapped command are transmitted into a subsequent Page FIFO;

[0084] The write data Wrdata and data mask DataMask are write data and DM information corresponding to the command, respectively;

[0085] The timer Timer is used to record the countdown of the time experienced by the command after entering the dispatch, and the countdown will continue in the WRBufferFIFO and Page FIFO.

[0086] Specifically, the write command read out from the WRBufferFIFO enters the Page FIFO in the following manner:

[0087] All address bits except the col bit, i.e. the page information of the write command, are compared with the page information of the Page FIFO in turn:

[0088] 1) If there is a Page FIFO with the same page information as the write command, and the Page FIFO is not full, not empty, and not starting to discharge the command, the write address, write data Wrdata, data mask DataMask and timer Timer in the write command are stored into the first Page FIFO in which the comparison is successful;

[0089] 2) If there is a Page FIFO with the same page information as the write command, but the Page FIFO with the same page information is full or is discharging the command, or there is no Page FIFO with the same page information as the write command, but there is an empty Page FIFO, the write address, write data Wrdata, data mask DataMask and timer Timer in the write command are stored into the empty Page FIFO with the smallest index value;

[0090] 3) If there is a Page FIFO with the same page information as the write command, but all Page FIFOs with the same page information are full or are draining commands, and all Page FIFOs with different page information are not empty, or there is no Page FIFO with the same page information as the write command, and all Page FIFOs are not empty, then the transmission is suspended until one of the above 1) or 2) occurs, and the write address, write data Wrdata, data mask DataMask and timer Timer in the write command are stored in the corresponding Page FIFO.

[0091] In the read channel and the write channel, one Page FIFO with the highest priority is selected respectively, and then a Page FIFO with a higher priority is selected from the two Page FIFOs. If the CMD FIFO is not full, and the selected Page FIFO is a write command, the selected Page FIFO directly starts to drain the command. If the selected Page FIFO is a read command, the selected Page FIFO starts to drain the command only when the TOKEN FIFO FOR RDDATA is also not full. The next selection of the Page FIFO is performed after the selected Page FIFO is emptied.

[0092] Since the same Page FIFO caches commands with the same page information, the commands with page hit can be continuously transmitted. The maximum number of continuously transmitted commands with page hit can be adjusted by controlling the depth of the Page FIFO, so as to avoid the situation that the commands without page hit are starved due to the continuous transmission of the commands with page hit.

[0093] Specifically, the strategy of selecting one Page FIFO with the highest priority in the read channel or the write channel includes the following steps, as shown in FIG. 1: Figure 2

[0094] The first priority is a Starved FIFO, that is, a Page FIFO whose timer Timer has been counted down to 0;

[0095] The second priority is an Address collision FIFO, that is, a Page FIFO with a command address that is the same as that of a command from the opposite channel that is about to enter the scheduling system;

[0096] The third priority is a Page FIFO with a smaller timer Timer when there is no Starved FIFO of the first priority and no Address collision FIFO of the second priority;

[0097] ​When the Page FIFOs with the highest priority selected from the read channel and the write channel are multiple, the Page FIFO with the smaller index value is selected preferentially.

[0098] Specifically, the strategy of selecting the Page FIFO with higher priority between the read channel and the write channel, as shown in Figure 3 and Figure 4 , includes:

[0099] The first priority is StarvedFIFO, if the Page FIFOs with the highest priority selected from the read channel and the write channel are all StarvedFIFOs, the StarvedFIFO with the same direction as the last executed command (i.e. if the last executed command is a read command, the read command is selected preferentially, and if the last executed command is a write command, the write command is selected preferentially) is selected preferentially.

[0100] The second priority is Address collisionFIFO, if the Page FIFOs with the highest priority selected from the read channel and the write channel are all Address collisionFIFOs, the Address collisionFIFO with the same direction as the last executed command is selected preferentially.

[0101] The third priority is the Page FIFO with smaller Timer, if the Page FIFOs with the highest priority selected from the read channel and the write channel have the same Timer, the Page FIFO with the same direction as the last executed command is selected preferentially.

[0102] After the selected Page FIFO starts to send out the command, the address of the command is sent to the CMD FIFO, if the sent out command is a read command, the token Token in the read command is written into the TOKEN FIFO FOR CMD and the TOKEN FIFO FOR RDDATA; if the sent out command is a write command, the write data Wrdata and the data mask DataMask in the write command are written into the WDATA FIFO.

[0103] When the CMD FIFO is not empty, a req signal is generated to send a command request to the subsequent module, if the subsequent module generates a response, a command is read from the CMD FIFO, if the read command is a read command, a token Token is read from the TOKEN FIFO FOR CMD and sent to the subsequent module together with the read command; if the read command is a write command, a group of write data Wrdata and data mask DataMask are read from the WDATA FIFO and sent to the subsequent module together with the write command.

[0104] When the read command is executed and the read data transmitted by the DFI is received, the token Token transmitted from the DFI is compared with the current token Token in the TOKEN FIFO FOR RDDATA, if the two tokens Token are the same, the read data and the current token Token in the TOKEN FIFO FOR RDDATA are sent to the AXI for reordering and then sent to the host.

[0105] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit the present application; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced equivalently; and these modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A high-bandwidth DDR command scheduling system based on multiple FIFO cascades, characterized by: It includes a read channel consisting of an RDBufferFIFO and multiple Page FIFOs, a write channel consisting of a WR Buffer FIFO and multiple Page FIFOs, as well as CMD FIFO, TOKEN FIFO FOR CMD, TOKEN FIFO FOR RDDATA, and WDATAFIFO; RD BufferFIFO is a read buffer FIFO. The data content is the read address, token, and timer in the read RawIF command sent by the host. WRBufferFIFO is a write buffer FIFO. The data content is the write address, write data Wrdata, data mask DataMask and timer Timer in the write RawIF command sent by the host. Page FIFO is a FIFO that caches the address, token, write data Wrdata, data mask DataMask and timer Timer in the command after mapping according to the page information; CMD FIFO, a FIFO used to cache the address of the scheduling completion command; TOKEN FIFO FOR CMD, used to cache the token sent to DFI along with the read address; TOKEN FIFO FOR RDDATA, used to cache the token Token sent to AXI along with the read data; WDATAFIFO is a FIFO used to cache the write data Wrdata and data mask DataMask corresponding to the write address.

2. The high-bandwidth DDR command scheduling system based on multiple FIFO cascades according to claim 1, characterized in that: When the Page FIFO is empty, after a command is stored, the page information and timer of the stored command become the page information and timer stored in the Page FIFO respectively. As subsequent commands are continuously stored, the timer of the Page FIFO is set to the timer of the command with a shorter time.

3. The high-bandwidth DDR command scheduling system based on multiple FIFO cascades according to claim 2, characterized in that: The working process of the read channel includes: When the host sends a Read RawIF command, if the RD BufferFIFO is not full, the read address, token, and timer in the Read RawIF command are cached; The command in the RD Buffer FIFO is read out and address mapped, that is, the read address is converted into the SDRAM particle address SDRAMAddr, the low bit of the read address is converted into the col bit of the SDRAM particle address SDRAMAddr, and the remaining bits are converted from low to high to the bankgroup, bank, row, and cs bits of the SDRAM particle address SDRAMAddr. In this way, continuous AXI addresses will not switch row addresses within the same bank, reducing the number of Act and Precharge commands that need to be sent. Bankgroup switching is prioritized, making the interval between two commands shorter when switching banks; The read address, token and timer in the mapped command are passed to the subsequent Page FIFO; The token Token is used to reorder the read data Rddata returned out of order when the read data Rddata corresponding to the read address is read from the SDRAM particle; The timer is used to record the countdown of the time after the command enters the schedule, and the countdown will continue in the RD BufferFIFO and PageFIFO.

4. The high-bandwidth DDR command scheduling system based on multiple FIFO cascades according to claim 3, characterized in that: The read commands from the RD Buffer FIFO enter the Page FIFO in the following ways: Select all address bits except the col bit, that is, the page information of the read command, and compare them with the page information of the Page FIFO in sequence: 1) If there is a Page FIFO with the same page information as the read command, and the Page FIFO is neither full nor empty, and the command has not started to be discharged, the read address, token Token and timer Timer in the read command are stored in the first relatively successful Page FIFO; 2) If there is a Page FIFO with the same page information as the read command, but all Page FIFOs with the same page information are full or are ejecting commands, or if there is no Page FIFO with the same page information as the read command, but there is an empty Page FIFO, then the read address, token Token, and timer Timer in the read command are stored in the empty Page FIFO with the smallest index value; 3) If there is a Page FIFO with the same page information as the read command, but the Page FIFOs with the same page information are full or are ejecting commands, and the remaining Page FIFOs with different page information are all not empty, or if there is no Page FIFO with the same page information as the read command and all Page FIFOs are not empty, then the transmission is suspended until the above two conditions 1) and 2) are met, and the read address, token Token, and timer Timer in the read command are stored in the corresponding Page FIFO.

5. The high-bandwidth DDR command scheduling system based on multi-FIFO cascade according to claim 3, characterized in that: The working process of the write channel includes: When the host sends a write RawIF command, if the WRBufferFIFO is not full, the write address, write data Wrdata, data mask DataMask and timer Timer in the write RawIF command are cached; Read the command in WRBufferFIFO and perform address mapping, that is, convert the write address into SDRAM particle address SDRAMAddr; The write address, write data Wrdata, data mask Data Mask and timer Timer in the mapped command are passed to the subsequent Page FIFO; Among them, the write data Wrdata and the data mask DataMask are the write data and DM information corresponding to the command respectively; The timer is used to record the countdown of the time after the command enters the schedule, and the countdown will continue in the WR BufferFIFO and PageFIFO.

6. The high-bandwidth DDR command scheduling system based on multiple FIFO cascades according to claim 5, characterized in that: The write commands read from the WR Buffer FIFO enter the Page FIFO in the following ways: Select all address bits except the col bit, that is, the page information of the write command, and compare them with the page information of the Page FIFO in sequence: 1) If there is a Page FIFO with the same page information as the write command, and the Page FIFO is neither full nor empty, and the command has not started to be discharged, the write address, write data Wrdata, data mask Data Mask and timer Timer in the write command are stored in the first relatively successful Page FIFO; 2) If there is a Page FIFO with the same page information as the write command, but all Page FIFOs with the same page information are full or are ejecting commands, or there is no Page FIFO with the same page information as the write command, but there is an empty Page FIFO, then the write address, write data Wrdata, data mask Data Mask and timer Timer in the write command are stored in the empty Page FIFO with the smallest index value; 3) If there is a Page FIFO with the same page information as the write command, but the Page FIFOs with the same page information are full or are emitting commands, and the remaining Page FIFOs with different page information are all not empty, or if there is no Page FIFO with the same page information as the write command, and all Page FIFOs are not empty, the transmission is suspended until both conditions 1) and 2) above are met. Then, the write address, write data Wrdata, data mask DataMask, and timer Timer in the write command are stored in the corresponding Page FIFO.

7. The high-bandwidth DDR command scheduling system based on multiple FIFO cascades according to claim 5, characterized in that: A Page FIFO with the highest priority is selected from each of the read and write channels. The Page FIFO with the higher priority is then selected from these two Page FIFOs. If the CMD FIFO is not full and a write command is selected, the selected Page FIFO starts to discharge commands directly. If a read command is selected, the selected Page FIFO starts to discharge commands only when the TOKEN FIFO FOR RDDATA is also not full. The next Page FIFO selection is performed only after the selected Page FIFO is emptied. Because the same Page FIFO caches commands with the same page information, page hit commands can be sent continuously. By controlling the Page FIFO depth, the maximum number of page hit commands that can be sent continuously is adjusted to avoid the situation where non-page hit commands are starved due to continuous sending of page hit commands.

8. The high-bandwidth DDR command scheduling system based on multiple FIFO cascades according to claim 7, characterized in that: The strategy for selecting the highest priority Page FIFO in the read channel or write channel includes: The first priority is the Starved FIFO, that is, the Page FIFO whose timer has counted down to 0; The second priority is Address collision FIFO, that is, the Page FIFO where there is a command with the same address as the command of the opposite channel that is about to enter the scheduling system; The third priority is the Page FIFO with a smaller timer when the Starved FIFO of the first priority and the AddresscollisionFIFO of the second priority do not exist; When there are multiple Page FIFOs with the highest priority selected from the read channel or write channel, the Page FIFO with the smaller index value is selected first; The strategy for selecting a Page FIFO with a higher priority between the read channel and the write channel includes: The first priority is StarvedFIFO. If the Page FIFOs with the highest priority selected from the read channel and the write channel are both StarvedFIFOs, the StarvedFIFO with the same direction as the last executed command will be selected first. The second priority is Address collision FIFO. If the Page FIFOs with the highest priority selected from the read channel and the write channel are both Address collision FIFOs, the Address collision FIFO with the same direction as the last executed command will be selected first. The third priority is the Page FIFO with a smaller timer. If the timers of the highest priority Page FIFOs selected from the read channel and the write channel are the same, the Page FIFO with the same direction as the last executed command is selected first.

9. The high-bandwidth DDR command scheduling system based on multi-FIFO cascade according to claim 7, characterized in that: After the selected Page FIFO starts to discharge commands, the address of the command is sent to the CMD FIFO. If the discharged command is a read command, the token Token in the read command is written to the TOKEN FIFO FOR CMD and TOKEN FIFO FOR RDDATA. If the discharged command is a write command, the write data Wrdata and data mask DataMask in the write command are written to the WDATAFIFO.

10. The high-bandwidth DDR command scheduling system based on multi-FIFO cascade according to claim 9, characterized in that: When the CMD FIFO is not empty, a req signal is generated to send a command request to the subsequent module. If the subsequent module generates a response, a command is read from the CMD FIFO. If the command read is a read command, a token Token is read from the TOKEN FIFO FOR CMD and sent to the subsequent module together with the read command; if the command read is a write command, a set of write data Wrdata and data mask Data Mask is read from the WDATAFIFO and sent to the subsequent module together with the write command; When the read data transmitted by DFI is received after the read command is executed, the token Token transmitted back from DFI is compared with the current token Token in TOKENFIFO FOR RDDATA. If the two tokens Token are the same, the read data is sent together with the current token Token in TOKEN FIFO FOR RDDATA to AXI for reordering and then sent to the host.

Images