High-performance digital signal processor application verification system and method

Abstract

The invention belongs to the field of integrated circuit application and development, and discloses a high-performance digital signal processor application verification system and method. Comprising a multi-power-domain heavy-load power supply module, a high-speed memory controller verification module, a high-speed serial communication verification module, an application verification module with a reserved expansion interface and an application verification module based on a user application background, application verification of all design functions of the high-performance digital signal processor and application verification based on a user application background are realized, basic conditions of engineering applications are verified, application examples and development modes of the engineering applications are designed, design examples are provided for engineering applications with more functions for users, and the engineering applications with more functions are verified. And a foundation is laid for large-scale application and popularization of the high-performance digital signal processor.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of integrated circuit application and development, and relates to a high-performance digital signal processor application verification system and method. BACKGROUND

[0002] The LCDSP1602 is a high-performance DSP (Digital Signal Processor) device, which is a heterogeneous multi-core high-performance processor for image processing and intelligent computing, integrates two main control processors compatible with PowerISA V2.05 (Power Instruction Set Architecture version 2.05), 16 DSP processors compatible with RISC-V 32IF (RISC-V with 32-bit Instruction Format), two configurable FFT (Fast Fourier Transform) pipelines, and a special computing engine supporting convolutional neural network acceleration; integrates RapidIO (a high-performance, low-latency serial communication protocol), PCIe (Peripheral Component Interconnect Express) and Ethernet (Ethernet, a computer network technology) high-speed peripheral bus controllers for inter-chip high-bandwidth data interaction; integrates DDR (Double Data Rate) and QDR (Quad Data Rate) high-speed memory controllers to meet the storage requirements of on-chip task scheduling and large data computation; the whole chip adopts a multi-level interconnection architecture to realize unified programming, and an independent register access bus is arranged for command scheduling and inter-core communication. The existing application verification method block for general DSP devices cannot meet the application verification requirements of the LCDSP1602, and a conventional DSP device application verification implementation diagram is as shown in Figure 1

[0003] ​The conventional DSP device is designed with single core or multi-core, but the power consumption is generally low, and a large load power supply is not required. Since the function is simple, there is no too much power supply domain power supply requirement, and the power supply network cannot meet the demand of the high-performance processor for multi-power large load power supply. Secondly, the conventional DSP device integrates a low-speed memory controller interface. In the application verification, the low-speed memory device with timing matching is connected, which can meet the demand of program storage, loading and running. The application verification method cannot meet the application verification requirement of the high-performance DSP multi-speed memory controller interface. Furthermore, the conventional DSP device integrates a low-speed communication interface or control bus. In the application verification, the communication interface, network or controlled device is directly connected, which cannot meet the application verification requirement of the high-performance DSP integrated high-speed communication module. Then, the conventional DSP device generally integrates a relatively simple function, and generally has no expandable interface. The communication or interconnection with the remaining devices is realized only through the communication interface, which cannot meet the application verification of the expandable reserved interface integrated by the high-performance DSP. Finally, the conventional DSP device has strong universality, mainly verifies the integrated function, and will not add the application verification based on the application background of specific users, which cannot meet the application verification requirement of the high-performance DSP device based on the user background. SUMMARY

[0004] The application aims at overcoming the defects of the prior art, and providing a high-performance digital signal processor application verification system and method.

[0005] In order to achieve the above-mentioned purpose, the application adopts the following technical scheme:

[0006] In the first aspect of the application, a high-performance digital signal processor application verification system is provided, which comprises a multi-power domain large load power module, a high-speed memory controller verification module, a high-speed serial communication verification module, an application verification module of a reserved expansion interface and an application verification module based on a user application background. The multi-power domain large load power module is used for the power-on verification of each component of the high-performance digital signal processor based on a plurality of power domains which are required to be powered on according to the power-on sequence. The high-speed memory controller verification module is used for the verification of the memory controller of the high-performance digital signal processor based on the DDR storage space and the QDR storage space. The high-speed serial communication verification module is used for the verification of the PCIe module and the RapidIO module of the high-performance digital signal processor based on the high-speed differential reference clock source. The application verification module of the reserved expansion interface is used for the function expansion verification of the high-performance digital signal processor. The application verification module based on the user application background is used for the user background-based application verification of the high-performance digital signal processor based on the high-speed sampling result of the external analog signal.

[0007] Optionally, the multi-power-domain large-load power module adopts +4~+14V power supply, and provides a core load power supply of up to 36A and power supply isolation, and uses the PG pin of the core power module as a normal power supply identifier and an enable signal of the next level power supply.

[0008] Optionally, the multi-power-domain large-load power module is externally provided with a +4~+14V stabilized power supply, and adopts four-stage power management, the first stage being a 36A load capacity core power supply, the second stage using the PG signal of the first stage as an enable signal to generate a VDDIO_1V8 power supply, a VDDR4_1V2 power supply, a VDDPLL_1V8 power supply and a VDD_1V5 power supply with a load capacity of 4A, the third stage using the PG signal of the second stage as an enable signal to generate a VDD_1V2 power supply, a VCC_3V3 power supply, a VCC_2V5 power supply and a SerDes_AVCC_1V0 power supply with a load capacity of 4A, and the fourth stage using the PG signal of the third stage as an enable signal to generate a F_VCCINT_1V0 power supply with a load capacity of 8A, a F_VCCO_3V3 power supply with a load capacity of 4A and a F_VCC_1V8 power supply with a load capacity of 4A.

[0009] Optionally, the high-speed memory controller verification module includes three pieces of DDR3 SDRAM, three pieces of DDR4 SDRAM and a QDRII+SRAM unit; the three pieces of DDR3 SDRAM are connected with a DDR0 controller of the high-performance digital signal processor, the three pieces of DDR4 SDRAM are connected with a DDR1 controller of the high-performance digital signal processor, and the QDRII+SRAM unit is connected with a QDR controller of the high-performance digital signal processor.

[0010] Optionally, the DDR3 SDRAM and the DDR4 SDRAM are designed according to a fly-by layout; the highest working frequency of the QDRII+SRAM unit is 550MHz, and the signal integrity design principles of 8-bit data lines, control line grouping equal length and all address lines, clock lines plus control lines equal length are obeyed.

[0011] Optionally, the high-speed serial communication verification module provides a 100MHz differential clock in RC working mode and EP working mode and a 250MHz differential clock in Gen2 / Gen3 working mode for a PCIe module through a high-speed differential reference clock module, and crosses tests the RC working mode and the EP working mode through a PCIE-064-02-F-D-TH connector and a conversion cable, and is compatible with the Gen2 / Gen3 working mode.

[0012] Optionally, the high-speed serial communication verification module generates a plurality of pairs of 125MHz and 156.25MHz differential clocks by adopting the mode selection of CDCM6208 according to the working frequency of the RapidIO module, and sets the interconnection of the K7 FPGA in the 1X / 4X mode of the board, the interconnection between the FPGA or the remaining devices through the HDMI interface and the interconnection between the boards through the SMA interface, to perform the verification of the 1X communication rate of 2.5G / 5G and the verification of the 4X communication rate of 2.5G / 5G.

[0013] Optionally, the application verification module of the reserved expansion interface connects the SRAM and the PROM through the EMIF interface, sets the PROM to be shared by the high-performance digital signal processor and the K7 FPGA in the reserved expansion interface, and realizes the control of the K7 FPGA in the reserved expansion interface by the high-performance digital signal processor through the EMIF interface, to perform the function extension verification of the high-performance digital signal processor.

[0014] Optionally, the application verification module based on the user application background sets the 2-way ADC control logic by the K7 FPGA in the reserved expansion interface through the EMIF interface, and transmits the data collected by the 2-way ADC to the high-performance digital signal processor, to perform the application verification of the high-performance digital signal processor based on the user background.

[0015] In the second aspect, the application provides a high-performance digital signal processor application verification method based on the high-performance digital signal processor application verification system, which comprises the following steps: performing the power-on verification of each component of the high-performance digital signal processor by the multi-power domain large load power module based on a plurality of power domains required to be powered on according to the power-on sequence; performing the verification of the memory controller of the high-performance digital signal processor by the high-speed memory controller verification module based on the DDR storage space and the QDR storage space; performing the verification of the PCIe module and the RapidIO module of the high-performance digital signal processor by the high-speed serial communication verification module based on the high-speed differential reference clock source; performing the function extension verification of the high-performance digital signal processor by the application verification module of the reserved expansion interface; and performing the application verification of the high-performance digital signal processor based on the user background based on the high-speed sampling result of the external analog signal by the application verification module based on the user application background.

[0016] Compared with the prior art, the application has the following beneficial effects:

[0017] The application discloses a high-performance digital signal processor application verification system, which comprises a multi-power domain large-load power module, a high-speed memory controller verification module, a high-speed serial communication verification module, a reserved expansion interface application verification module and a user application background-based application verification module. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 An implementation block diagram of the application verification of the existing DSP device is shown.

[0019] Figure 2 A structure block diagram of the application verification system of the DSP device of the embodiment of the application is shown.

[0020] Figure 3 A first-stage structure block diagram of the multi-power domain large-load power module of the embodiment of the application is shown.

[0021] Figure 4 A second-stage structure block diagram of the multi-power domain large-load power module of the embodiment of the application is shown.

[0022] Figure 5 A third-stage structure block diagram of the multi-power domain large-load power module of the embodiment of the application is shown.

[0023] Figure 6 A fourth-stage structure block diagram of the multi-power domain large-load power module of the embodiment of the application is shown.

[0024] Figure 7 A structure block diagram of the high-speed memory controller verification module of the embodiment of the application is shown.

[0025] Figure 8 A structure block diagram of the high-speed differential reference clock module of the embodiment of the application is shown.

[0026] Figure 9 The PCIe module application verification block diagram of an embodiment of the present application is shown in Fig. 1.

[0027] Figure 10 The RapidIO module application verification block diagram of an embodiment of the present application is shown in Fig. 2.

[0028] Figure 11 The application verification block diagram of the reserved expansion interface and user application background of an embodiment of the present application is shown in Fig. 3. DETAILED DESCRIPTION

[0029] In order to make the persons skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the persons skilled in the art without creative labor should belong to the protection scope of the present application.

[0030] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to the clearly listed steps or units, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0031] The present application will be described in further detail below with reference to the drawings:

[0032] Referring to Figure 2 In an embodiment of the present application, a high-performance digital signal processor application verification system is provided, which is suitable for a high-performance DSP device LCDSP1602 and can realize application verification of all design functions of the high-performance DSP device LCDSP1602 and also verify the basic situation of engineering application.

[0033] Specifically, the high-performance digital signal processor application verification system comprises a multi-power domain large load power module, a high-speed memory controller verification module, a high-speed serial communication verification module, an application verification module of a reserved expansion interface, and an application verification module based on a user application background.

[0034] The multi-power domain large load power module is used for power-on verification of each component of the high-performance digital signal processor based on a plurality of power domains required to be powered on according to a power-on sequence; the high-speed memory controller verification module is used for verification of a memory controller of the high-performance digital signal processor based on a DDR storage space and a QDR storage space; the high-speed serial communication verification module is used for verification of a PCIe module and a RapidIO module of the high-performance digital signal processor based on a high-speed differential reference clock source; the application verification module of the reserved expansion interface is used for function expansion verification of the high-performance digital signal processor; and the application verification module based on a user application background is used for user background-based application verification of the high-performance digital signal processor based on high-speed sampling results of external analog signals.

[0035] The application verification system of the high-performance digital signal processor verifies the basic situation of engineering application by designing the multi-power domain large load power module, the high-speed memory controller verification module, the high-speed serial communication verification module, the application verification module of the reserved expansion interface and the application verification module based on the user application background, and designs application examples and development modes, thereby providing design examples for engineering application of more functions of the user and laying a foundation for large-scale application and promotion of the high-performance digital signal processor.

[0036] In a possible implementation, taking a high-performance DSP device LCDSP1602 as an example, the high-performance DSP device LCDSP1602 is a heterogeneous multi-core high-performance processor facing image processing and intelligent computing, integrates two main control processors compatible with PowerISA V2.05, 16 DSP processors compatible with RISC-V 32IF, two configurable FFT pipelines and a special computing engine supporting convolutional neural network acceleration, integrates high-speed peripheral bus controllers such as RapidIO, PCIe and Ethernet on a chip for high-bandwidth data interaction between chips, integrates high-speed memory controllers such as DDR and QDR to meet the storage demand of on-chip task scheduling and large data volume calculation, and uses a multi-level interconnection architecture to realize unified programming, and sets an independent register access bus for command scheduling and inter-core communication.

[0037] According to the function and performance requirements of the high-performance DSP device LCDSP1602, the application verification system for the high-performance digital signal processor can be used to verify and develop all functions of the high-performance DSP device LCDSP1602, lay a foundation for the function verification and rapid application of the high-performance DSP device LCDSP1602, and provide a development platform and application examples for users. Through the application verification and development of the high-performance DSP device LCDSP1602 based on the application background, the technical indexes and parameters proposed by the pre-research new product are comprehensively covered, the application verification is designed according to the application background of the existing users, the application verification and development examples of the extended and reserved resources are provided, and a solid foundation is laid for the smooth application of the high-performance DSP device LCDSP1602.

[0038] In a possible implementation, the multi-power-domain large-load power module is powered by +4~+14V, and provides a core load power supply of up to 36A and power supply isolation, and uses the PG pin of the core power module as an identification of normal power supply.

[0039] Optionally, the multi-power-domain large-load power module is provided with a stabilized power supply of +4~+14V from outside, and adopts four-stage power management, the first stage being a core power supply with a load capacity of 36A; the second stage using the PG signal of the first stage as an enable signal to generate a VDDIO_1V8 power supply, a VDDR4_1V2 power supply, a VDDPLL_1V8 power supply and a VDD_1V5 power supply with a load capacity of 4A; the third stage using the PG signal of the second stage as an enable signal to generate a VDD_1V2 power supply, a VCC_3V3 power supply, a VCC_2V5 power supply and a SerDes_AVCC_1V0 power supply with a load capacity of 4A; and the fourth stage using the PG signal of the third stage as an enable signal to generate a F_VCCINT_1V0 power supply with a load capacity of 8A, a F_VCCO_3V3 power supply with a load capacity of 4A and a F_VCC_1V8 power supply with a load capacity of 4A.

[0040] Explanatorily, a conventional DSP device is designed with a single core or multiple cores, but the power consumption is generally low, and a large-load power supply is not needed, and since the function is simple, there is no much requirement for power supply domain, and the power supply network cannot meet the demand of the high-performance processor for multi-power large-load power supply.

[0041] For the high-performance DSP device LCDSP1602, a multi-power-domain large-load power module is designed, 37 power supply designs of different power domains are completed, and the processor core power normal signal with a maximum load of 36A is used as a trigger starting signal to complete the design of the power-on sequence requirement of different power domains.

[0042] Referring to Figures 3 to 6A steady voltage power supply is connected to the power input end, and four power management modules are used to complete the power supply for high-performance processors, FPGAs and peripheral circuits, and to complete the application design of four power supply modes.

[0043] Specifically, the first stage: +4~+14V power supply, by selecting high precision, high stability, high load power management device for the core of LCDSP1602 to provide the highest 36A large load power supply, to meet the peak power consumption requirements of high performance DSP device LCDSP1602 high performance processing performance. The PG pin of the core power supply module is used as the identification of normal power supply, and is used as the start signal of the subsequent power supply module, which meets the control of the high performance DSP device LCDSP1602 and its peripheral circuit on the power-on sequence of different power supply domains. The second stage: +4~+14V regulated power supply is provided by the external, and the PG signal of the previous stage is used as an enable signal, respectively generating VDDIO_1V8, VDDR4_1V2, VDDPLL_1V8 and VDD_1V5 power supply which can provide 4A load capacity, for 1.8V IO pin of LCDSP1602, 1.2V DDR4 SDRAM controller and memory, 1.8V high performance DSP device LCDSP1602 PLL module, and 1.5V LCDSP1602 DDR3 SDRAM and QDRII+SRAM memory controller interface and memory power supply, and the power supply of DDR3 SDRAM and QDRII+SRAM module is isolated to avoid interference between each other. The third stage: +4~+14V regulated power supply is provided by the external, and the PG signal of the previous stage is used as an enable signal, respectively generating VDD_1V2, VCC_3V3, VCC_2V5 and SerDes_AVCC_1V0 power supply which can provide 4A load capacity, VDD_1V2 provides isolated 1.2V power supply for SerDes of LCDSP1602 and SerDes of K7 FPGA; VCC_3V3 provides 3.3V power supply for 3.3V IO pin of LCDSP1602 and 3.3V power supply domain of the rest of the peripheral devices; VCC_2V5 provides power supply for IO pin of K7 FPGA and VPP of DDR4 SDRAM; and SerDes_AVCC_1V0 provides +1.0V analog voltage power supply for SerDes module of LCDSP1602. The fourth stage: +4~+14V regulated power supply is provided by the external, and the PG signal of the previous stage is used as an enable signal, respectively generating F_VCCINT_1V0 with 8A load capacity, F_VCCO_3V3 with 4A load capacity and F_VCC_1V8 with 4A load capacity. F_VCCINT_1V0 provides analog power supply for F_MGTAVCC_1V0 of K7 FPGA; F_VCCO_3V3 provides 3.3V power supply for 3.3V bank of K7 FPGA; F_VCC_1V8 provides 1.8V power supply for two isolated MGTVCCAUX_1V8 and VCCAUX_1V8 of K7 FPGA.

[0044] In a possible implementation, the high-speed memory controller verification module includes 3 pieces of DDR3 SDRAM, 3 pieces of DDR4 SDRAM, and 1 piece of QDRII+SRAM unit; the 3 pieces of DDR3 SDRAM are connected with a DDR0 controller of the high-performance digital signal processor, the 3 pieces of DDR4 SDRAM are connected with a DDR1 controller of the high-performance digital signal processor, and the 1 piece of QDRII+SRAM unit is connected with a QDR controller of the high-performance digital signal processor.

[0045] Optionally, the DDR3 SDRAM and the DDR4 SDRAM are implemented according to a fly-by layout design; the highest working frequency of the QDRII+SRAM unit is 550 MHz, and the QDRII+SRAM unit complies with the principle that an 8-bit data line, a control line, and a clock line are equal in length and the principle of signal integrity design that all address lines and control lines are equal in length.

[0046] Explanatorily, a conventional DSP device integrates a low-speed memory controller interface, and in application verification, a low-speed memory device matched in timing is connected to meet the requirements of program storage, loading, and running, and the application verification method cannot meet the application verification requirements of multiple high-speed memory controller interfaces of a high-performance DSP.

[0047] Explanatorily, a high-speed memory controller verification module connects DDR3 SDRAM and DDR4 SDRAM memories by using integrated 2 DDR SDRAM controller interfaces, and is strictly implemented according to a fly-by layout design to complete application verification design of a high-speed memory interface DDR SDRAM memory controller interface. A QDRII+SRAM unit is connected by using an integrated QDR SRAM memory controller interface to complete functional verification and performance verification design of a high-speed memory interface QDR memory controller interface. Referring to Figure 7 , 3 pieces of DDR3 SDRAM and 3 pieces of DDR4 SDRAM high-speed DDR memory controller interface application verification units are respectively designed by using 2 DDR controller interfaces integrated in a high-performance DSP; a QDRII+SRAM unit is designed based on a QDRII memory controller interface integrated in the high-performance DSP to complete application verification of a high-speed memory controller interface integrated in the high-performance DSP.

[0048] Specifically, the high-performance DSP integrates a high-speed memory controller module, utilizes two integrated DDR SDRAM controller interfaces, connects DDR3 SDRAM at a DDR0 interface and DDR4 SDRAM memory at a DDR1 interface respectively, realizes the application verification design of the high-speed memory interface DDR SDRAM memory controller interface according to the fly-by layout design, utilizes the integrated QDR SRAM memory controller interface, connects the QDRII+SRAM with a maximum working frequency of 550MHz, and in the design realization, the 8-bit data line, the control line and the clock line are equal in length, the signal integrity design principle of all address lines plus control lines being equal in length is followed, the functional verification and performance verification design of the high-speed memory interface QDR memory controller interface are completed, and the requirements of the high-performance DSP on large storage space and high-speed storage space in the application are met.

[0049] In a possible implementation, the high-speed serial communication verification module provides 100MHz differential clock in RC and EP working modes and 250MHz differential clock in Gen2 / Gen3 working modes for the PCIe module through a high-speed differential reference clock module, and cross tests RC and EP working modes and compatible tests Gen2 / Gen3 working modes through a PCIE-064-02-F-D-TH connector and a conversion cable.

[0050] Optionally, the high-speed serial communication verification module generates several 125MHz and 156.25MHz differential clocks through the mode selection of CDCM6208 according to the working frequency of the RapidIO module, and sets the interconnection of K7 FPGA in the 1X / 4X mode in the board and the reserved expansion interface, the interconnection between the FPGA or other devices through the HDMI interface and the interconnection between the boards through the SMA interface, and performs the verification of 1X communication rate of 2.5G / 5G and the verification of 4X communication rate of 2.5G / 5G.

[0051] Explanatorily, the conventional DSP device integrates a low-speed communication interface or a control bus, and directly connects the communication interface, the network or the controlled device in the application verification, which cannot meet the application verification requirements of the high-speed communication module integrated by the high-performance DSP.

[0052] Explanatory, high-speed serial communication verification module to meet its high-speed communication on the high-precision high-speed differential reference clock requirements, the introduction of high-speed differential reference clock module, respectively for PCIe 100MHz, 250MHz high-precision differential reference clock source and RapidIO 125MHz and 156.25MHz variable high-precision differential reference clock source. For integrated PCIe module, respectively, complete Gen2, Gen3 mode verification, and single board to complete RC and EP function verification. For integrated RapidIO module, respectively, complete 1X communication rate of 2.5G / 5G verification and 4X communication rate of 2.5G / 5G application verification and performance testing, and to achieve 4X mode of board and the reserved expansion interface module K7 FPGA interconnection, inter-board and FPGA or other devices through the HDMI interface interconnection and through the SMA interface inter-board interconnection, complete different application and test case function verification and performance testing.

[0053] Referring to Figure 8 , for high-performance DSP integrated high-speed serial communication module on the demand of high-speed differential reference clock, the design of high-speed differential reference clock module, for PCIe module and RapidIO application verification to provide high-speed differential clock reference. Referring to Figure 9 , to verify and test the function and performance of high-performance DSP integrated PCIe module, designed to meet the PCIe Gen2, Gen3 working rate under RC mode and EP mode of work verification. Referring to Figure 10 , according to the design of high-performance DSP RapidIO module, 1X / 4X RapidIO module of board, inter-board, standard test module application verification and performance testing.

[0054] Specifically, for high-performance DSP integrated high-speed serial communication module, in order to meet the high-speed communication of high-precision high-speed differential reference clock requirements, design high-speed differential reference clock module, through the high-performance differential reference crystal oscillator for PCIe module to provide RC mode and EP mode under 100MHz differential clock, and in Gen2 / Gen3 mode under 250MHz high-precision differential reference clock source; According to the working frequency of RapidIO module, through the mode selection of CDCM6208 to generate multiple 125MHz and 156.25MHz variable high-precision differential reference clock source. For high-performance DSP integrated PCIe module, through PCIE-064-02-F-D-TH connector and adapter cable, realize the direct connection of RC mode EP and EP clock cross application, respectively complete Gen2, Gen3 mode verification, and single board completed RC mode and EP mode verification. For high-performance DSP integrated RapidIO module, the design of 1X / 4X mode of board and K7 FPGA in the reserved expansion interface module, interconnection between boards and FPGA or other devices through HDMI interface and SMA interface interconnection between boards, complete the function verification and performance test of different application and test situation.

[0055] In one possible implementation, the application verification module of the reserved expansion interface is connected with SRAM and PROM through EMIF interface, and the PROM is shared by the high-performance digital signal processor and K7 FPGA in the reserved expansion interface. The K7 FPGA in the reserved expansion interface is controlled by the high-performance digital signal processor through the EMIF interface, and the function expansion verification of the high-performance digital signal processor is performed.

[0056] Explanatorily, the conventional DSP device is generally integrated with relatively simple functions, and generally does not have an expandable interface. Only through the communication interface, the communication or interconnection with other devices can be realized, and the application verification of the expandable reserved interface of the high-performance DSP cannot be met.

[0057] Explanatorily, referring to Figure 11 , the application verification module of the reserved expansion interface is connected with SRAM and PROM through EMIF interface, and the PROM is shared by the high-performance digital signal processor and K7 FPGA in the reserved expansion interface. The K7 FPGA in the reserved expansion interface is controlled by the high-performance digital signal processor through the EMIF interface, and the function expansion verification of the high-performance digital signal processor is performed.

[0058] In a possible implementation, the application verification module based on the user application background controls the K7 FPGA setting 2-way ADC control logic in the reserved expansion interface through the EMIF interface, and transmits the data collected by the 2-way ADC to the high-performance digital signal processor for high-performance digital signal processor based on the user background application verification.

[0059] Explanatorily, the versatility of the conventional DSP device is relatively strong, and mainly verifies the integrated functions, and does not add the application verification based on the specific user application background, and does not meet the requirement of the high-performance DSP device based on the user background application verification.

[0060] Explanatorily, referring again to Figure 11 The application verification function based on the user engineering application background controls the K7 FPGA, designs 2-way high-speed ADC control logic, and transmits the data after the completion of the ADC to the LCDSP1602 for signal processing, realizes the high-speed sampling and processing of the external analog signal, and meets the application verification and development of the user application situation.

[0061] The application verification system of the high-performance digital signal processor, for the high-performance digital signal processor, designs a multi-power domain large load power supply module, and completes the control of the power-on sequence requirement on different power domains, so as to replace the simple power management module of the conventional DSP device, and meet the application verification requirement of the high-performance DSP device on the design function; the high-speed memory controller verification module of DDR3 / 4 and QDRII+ is designed, and the requirement of the high-performance DSP on the large storage space and the high-speed storage space in the application is completed; based on the high-speed serial communication interface PCIe and RapidIO function modules integrated in the high-performance DSP, the function of the expandable interface is developed, the high-speed serial communication verification module is designed, the functions of PCIe Gen2 / Gen3 and RapidIO different speed rate function verification are realized, and the verification and performance test of different application situations are realized; and the application verification module based on the user application background is designed, and the verification and development of the user application function are realized.

[0062] In another embodiment of the present application, a high-performance digital signal processor application verification method is provided, which is implemented based on the high-performance digital signal processor application verification system described above. Specifically, the high-performance digital signal processor application verification method comprises the following steps: performing power-on verification of each component of the high-performance digital signal processor by the multi-power domain large load power module based on a plurality of power domains required to be powered on in sequence; performing verification of the memory controller of the high-performance digital signal processor based on the DDR storage space and the QDR storage space by the high-speed memory controller verification module; performing verification of the PCIe module and the RapidIO module of the high-performance digital signal processor based on the high-speed differential reference clock source by the high-speed serial communication verification module; performing functional extension verification of the high-performance digital signal processor by the application verification module of the reserved extension interface; and performing user background-based application verification of the high-performance digital signal processor based on the high-speed sampling result of the external analog signal by the application verification module based on the user application background.

[0063] The high-performance digital signal processor application verification method can be applied in the development of high-performance digital signal processors. After the high-performance DSP is packaged, the application verification of the designed function and the user background-based application verification can be completed by using the high-performance digital signal processor application verification method, and the high-performance, high-speed memory interface, high-speed communication interface, and multi-functional extension module integrated in other fields can be provided as a reference, thereby laying a foundation for the application verification of the designed function and the user application verification and development.

[0064] The power supply design for the high-performance DSP application verification can be directly applied to system integration and can meet different application scenarios. The application verification of the high-speed memory controller interface of the high-performance DSP can accumulate experience for the application verification and development of the integrated DDR / QDR modules and the like. The application verification design of the high-speed serial communication module of the high-performance DSP provides a design reference for the application and development of the popular PCIe and RapidIO high-speed serial communication interfaces. The application verification of the reserved extensible interface of the high-performance DSP fully demonstrates the verification idea of the extensible interface, and the user application background-based application verification provides a designable idea for the combination of user application and design verification. The above designs can be applied in the application verification and development of the multi-functional, high-performance, and high-speed interface modules involved in the high-performance DSP with the same technical requirements.

[0065] The above content only illustrates the technical idea of the present application and cannot limit the protection scope of the present application. Any modification made according to the technical idea of the present application on the basis of the technical solution falls within the protection scope of the claims of the present application.

Claims

1. A high-performance digital signal processor application verification system, characterized in that: It includes a multi-power domain large-load power supply module, a high-speed memory controller verification module, a high-speed serial communication verification module, an application verification module with reserved expansion interface, and an application verification module based on user application background; The multi-power domain high-load power supply module is used to verify the power-on of various components of a high-performance digital signal processor based on several power domains that are required to be powered on in a power-on sequence; The high-speed memory controller verification module is used to verify the memory controller of the high-performance digital signal processor based on DDR storage space and QDR storage space; the high-speed serial communication verification module is used to verify the PCIe module and RapidIO module of the high-performance digital signal processor based on the high-speed differential reference clock source; the application verification module with reserved expansion interface is used to verify the functional expansion of the high-performance digital signal processor; the application verification module based on user application background is used to verify the application of the high-performance digital signal processor based on the user background based on the high-speed sampling results of the external analog signal.

2. The high-performance digital signal processor application verification system according to claim 1, characterized in that: The multi-power domain large load power supply module adopts +4~+14V power supply, provides core load power supply of up to 36A and power supply isolation, and uses the PG pin of the core power supply module as an indicator of normal power supply and an enable signal for the next level.

3. The high-performance digital signal processor application verification system according to claim 2, characterized in that: The multi-power domain large-load power supply module is provided with an external +4~+14V regulated power supply and adopts a four-level power management. The first level is for core power supply with a load capacity of 36A; the second level uses the PG signal of the first level as an enable signal to generate a VDDIO_1V8 power supply, a VDDR4_1V2 power supply, a VDDPLL_1V8 power supply and a VDD_1V5 power supply that can provide a load capacity of 4A; the third level uses the PG signal of the second level as an enable signal to generate a VDD_1V2 power supply, a VCC_3V3 power supply, a VCC_2V5 power supply and a SerDes_AVCC_1V0 power supply that can provide a load capacity of 4A; the fourth level uses the PG signal of the third level as an enable signal to generate an F_VCCINT_1V0 power supply that can provide an 8A load capacity, an F_VCCO_3V3 power supply with a load capacity of 4A and an F_VCC_1V8 power supply with a load capacity of 4A.

4. The high-performance digital signal processor application verification system according to claim 1, characterized in that: The high-speed memory controller verification module includes 3 DDR3 SDRAMs, 3 DDR4 SDRAMs and 1 QDRII+SRAM unit; the 3 DDR3 SDRAMs are connected to the DDR0 controller of the high-performance digital signal processor, the 3 DDR4 SDRAMs are connected to the DDR1 controller of the high-performance digital signal processor, and the QDRII+SRAM unit is connected to the QDR controller of the high-performance digital signal processor.

5. The high-performance digital signal processor application verification system according to claim 4, characterized in that: The DDR3 SDRAM and DDR4 SDRAM are implemented according to a fly-by layout design. The maximum operating frequency of the QDRII+ SRAM unit is 550 MHz, and the signal integrity design principle of 8-bit data lines and control lines being grouped with equal lengths and all address lines plus control lines and clock lines being of equal lengths is complied with.

6. The high-performance digital signal processor application verification system according to claim 1, characterized in that: The high-speed serial communication verification module provides the PCIe module with a 100MHz differential clock in RC and EP working modes, as well as a 250MHz differential clock in Gen2 / Gen3 working modes, through a high-speed differential reference clock module. Through the PCIE-064-02-FD-TH connector and adapter cable, it cross-tests the RC and EP working modes, and compatibility tests the Gen2 / Gen3 working modes.

7. The high-performance digital signal processor application verification system according to claim 6, characterized in that: The high-speed serial communication verification module uses the mode selection of CDCM6208 to generate several 125MHz and 156.25MHz differential clocks according to the operating frequency of the RapidIO module, and sets the 1X / 4X mode for the interconnection between the board and the K7 FPGA in the reserved expansion interface, the interconnection between the boards and the FPGA or other devices through the HDMI interface, and the inter-board interconnection through the SMA interface to perform verification of 1X communication rates of 2.5G / 5G and 4X communication rates of 2.5G / 5G.

8. The high-performance digital signal processor application verification system according to claim 1, characterized in that: The application verification module of the reserved extension interface is connected to the SRAM and PROM through the EMIF interface, and the PROM is set to be shared by the high-performance digital signal processor and the K7 FPGA in the reserved extension interface, and the high-performance digital signal processor controls the K7 FPGA in the reserved extension interface through the EMIF interface to perform functional expansion verification of the high-performance digital signal processor.

9. The high-performance digital signal processor application verification system according to claim 1, characterized in that: The application verification module based on user application background controls the K7 FPGA in the reserved extension interface through the EMIF interface to set the 2-way ADC control logic, and transmits the data collected by the 2-way ADC to the high-performance digital signal processor to perform application verification based on the user background of the high-performance digital signal processor.

10. A high-performance digital signal processor application verification method based on the high-performance digital signal processor application verification system according to any one of claims 1 to 9, characterized in that: include: The multi-power domain heavy load power supply module is used to verify the power-on of various components of a high-performance digital signal processor based on several power domains that are required to be powered on in a power-on sequence. Verify the memory controller of high-performance digital signal processors based on DDR memory space and QDR memory space through the high-speed memory controller verification module; Verify the PCIe and RapidIO modules of high-performance digital signal processors using a high-speed serial communication verification module based on a high-speed differential reference clock source. Verify the functional expansion of high-performance digital signal processors through application verification modules with reserved expansion interfaces; The application verification module based on the user application background is used to perform application verification of the high-performance digital signal processor based on the user application background based on the high-speed sampling results of the external analog signal.

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