Method for optimizing communication parameters of a core particle, core particle and chip

Abstract

The application provides a core particle communication parameter optimization method, a core particle and a chip. The optimization method comprises the following steps: performing data sending tests through all sending ends of the core particle according to preset different phases; calculating a phase optimal value according to test information of all data sending tests, and optimizing a clock signal of the core particle according to the phase optimal value; performing data receiving tests through each receiving end of the core particle according to preset different decision levels based on the optimized clock signal; calculating a corresponding decision level optimal value according to a test result of the data receiving test of each receiving end, and optimizing a decision level of the corresponding receiving end according to the decision level optimal value. The core particle communication parameter optimization method, the core particle and the chip provided by the application can solve the technical problem that the parameters of the communication link between core particles are difficult to optimize.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a method for optimizing communication parameters of a die, a die and a chip. BACKGROUND

[0002] With the progress of chip design and packaging technology, die interconnection technology has become the focus of the industry because it can effectively reduce the cost, size of single chip design and improve manufacturing yield. As an emerging standard, UCIe supports PCIe 6.0, CXL 2.0 / 3.0 and custom protocols through protocol layers, and the adaptation layer and physical layer of the die implement efficient Die-to-Die data transmission to adapt to 2.5D / 3D advanced packaging. This technology replaces the limitations of traditional interconnection such as PCIe, provides transmission rate and bandwidth of the communication link between dies, and significantly improves the data transmission efficiency between dies.

[0003] In the UCIe physical layer, the increase in clock frequency leads to a decrease in timing margin and voltage margin, inter-module skew and difficulty in equalization adjustment, and the calibration of the communication parameters of the communication link becomes more difficult. The hardware-embedded calibration process may produce inaccurate parameters, and the protocol specification is difficult to flexibly adjust the algorithm, which reduces the performance and stability of the communication link between dies, and there is an urgent need for a flexible and reliable parameter optimization method to improve calibration accuracy. SUMMARY

[0004] The present application provides a method for optimizing communication parameters of a die, a die and a chip to solve the technical problem that the parameters of the communication link between dies are difficult to optimize.

[0005] The present application provides a method for optimizing communication parameters of a die, which is applied to a die, and the optimization method comprises:

[0006] According to the preset different phases, data transmission tests are performed through all the sending ends of the die; wherein the preset different phases are obtained by gradually adjusting the initial phase value of the die according to the preset phase step amount;

[0007] The optimal phase value is calculated according to the test information of all data transmission tests, and the clock signal of the die is optimized according to the optimal phase value;

[0008] Based on the optimized clock signal, data reception tests are performed through each receiving end of the die according to the preset different decision levels; wherein the preset different decision levels are obtained by gradually adjusting the preset minimum level and the preset maximum level of the die according to the preset level step amount;

[0009] According to the test result of the data receiving test of each receiving end, a corresponding decision level optimal value is calculated, and a decision level of the corresponding receiving end is optimized according to the decision level optimal value.

[0010] In an embodiment of the present application, the step of performing data sending tests through all the sending ends of the core grain according to the preset different phases comprises:

[0011] Starting from the initial phase value, the initial phase value of the core grain is adjusted step by step according to a preset negative phase offset direction and a preset phase code step size until one clock cycle is adjusted; data sending tests are performed through all the sending ends of the core grain according to the phase obtained after each adjustment.

[0012] Starting from the initial phase value, the initial phase value is adjusted step by step according to a preset positive phase offset direction and the phase code step size until one clock cycle is adjusted; data sending tests are performed through all the sending ends of the core grain according to the phase obtained after each adjustment.

[0013] In an embodiment of the present application, after the step of starting from the initial phase value, adjusting the initial phase value of the core grain step by step according to a preset negative phase offset direction and a preset phase code step size until one clock cycle is adjusted, the step further comprises:

[0014] The adjusted phase is adjusted step by step according to the phase code step size in a positive phase offset direction until the initial phase value is adjusted.

[0015] In an embodiment of the present application, after the step of starting from the initial phase value, adjusting the initial phase value step by step according to a preset positive phase offset direction and the phase code step size until one clock cycle is adjusted, the step further comprises:

[0016] The adjusted phase is adjusted step by step according to the phase code step size in a negative phase offset direction until the initial phase value is adjusted.

[0017] In an embodiment of the present application, the step of calculating a phase optimal value according to the test information of all the data sending tests and optimizing the clock signal of the core grain according to the phase optimal value comprises:

[0018] The test information is reserved for the phase passing the test.

[0019] The reserved phase is sorted to obtain a corresponding continuous sequence.

[0020] The phase optimal value is calculated according to the continuous sequence.

[0021] According to the phase optimal value, the clock signal of the core particle is optimized.

[0022] In an embodiment of the present application, the step of calculating the phase optimal value according to the continuous sequence comprises:

[0023] The difference between two adjacent phases in the continuous sequence is calculated, and the difference is compared with the phase code step amount;

[0024] The number of the difference greater than the phase code step amount is counted as the number of abnormal point positions;

[0025] According to the comparison result of the number of abnormal point positions and the preset threshold, the phase optimal value of the continuous sequence is found.

[0026] In an embodiment of the present application, the step of finding the phase optimal value of the continuous sequence according to the comparison result of the number of abnormal point positions and the preset threshold comprises:

[0027] It is judged whether the number of abnormal point positions is less than the preset threshold:

[0028] When the number of abnormal point positions is less than the preset threshold, the center value of the continuous sequence is found as the phase optimal value;

[0029] Otherwise, the continuous sequence is split into a plurality of sub-continuous sequences according to the abnormal point positions, and the sub-continuous sequence with the largest number of phases is selected as the target sub-continuous sequence; the center value of the target sub-continuous sequence is found as the phase optimal value.

[0030] In an embodiment of the present application, the step of performing data receiving test through each receiving end of the core particle according to the preset different decision levels based on the optimized clock signal comprises:

[0031] The decision levels of all receiving ends of the core particle are set to start from the preset minimum level, and the minimum level of all receiving ends of the core particle is adjusted step by step according to the preset level step amount until the preset maximum level is reached;

[0032] According to the decision level obtained by each adjustment and the optimized clock signal, data receiving test is performed through each receiving end of the core particle respectively, and the test result of data receiving test of each receiving end is obtained.

[0033] In an embodiment of the present application, the step of calculating the corresponding decision level optimal value according to the test result of data receiving test of each receiving end, and optimizing the decision level of the corresponding receiving end according to the decision level optimal value comprises:

[0034] For each receiving end:

[0035] retaining the test result as a decision level of passing the test;

[0036] calculating an average value of the maximum value and the minimum value of the decision level corresponding to the retention as an optimal value of the decision level of the receiving end;

[0037] optimizing the decision level of the receiving end according to the optimal value of the decision level.

[0038] The application further discloses a core particle, and the core particle uses the optimization method of the communication parameter of the core particle.

[0039] The application further discloses a chip, and the chip comprises the core particle.

[0040] The application has the following beneficial effects: the dynamic calibration of the UCIe physical layer communication parameter is realized through a software / firmware algorithm, the problems of timing margin compression, voltage margin reduction and multi-channel skew under a high-frequency clock are effectively solved, the problems caused by clock jitter can be eliminated based on the optimal value of the phase calculated through phase scanning, and the vertical noise tolerance can be maximized through the full-range level scanning starting from the preset minimum level and the calculation of the optimal value of the independent decision level of each receiving end, so that the problem of eye diagram asymmetry caused by process deviation is solved. BRIEF DESCRIPTION OF DRAWINGS

[0041] The drawings incorporated into the specification and constituting a part of the specification show embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the drawings.

[0042] In the drawings:

[0043] Figure 1 A flowchart of an optimization method of a communication parameter of a core particle provided for an embodiment of the present application;

[0044] Figure 2 A schematic diagram of a continuous sequence of phase tests provided in an embodiment of the present application;

[0045] Figure 3 Another schematic diagram of a continuous sequence of phase tests provided in an embodiment of the present application;

[0046] Figure 4 A schematic diagram of a decision level test provided in an embodiment of the present application.

[0047] The reference signs are as follows:

[0048] 11, minimum index number; 12, maximum index number; 13, start index number; 14, end index number; 15, center index number; 21, preset level minimum value; 22, preset level maximum value; 23, level minimum value; 24, level maximum value; 25, decision level optimal value. DETAILED DESCRIPTION

[0049] Other advantages and benefits of the present application will become apparent to those skilled in the art upon consideration of the disclosure or can be learned by practice of the application. The application can be realized and achieved by means of the structures and combinations of features described in the description above and in the claims. The application can also be realized and achieved by means of other different specific embodiments, which are also protected by the scope of the claims.

[0050] It is to be understood that the drawings shown below are only schematic and that the actual implementation of the application can vary as a consequence of the implementation possibilities of those skilled in the art, and as a consequence of manufacturing processes, while the drawings only show the components related to the application and not an entire assembly, which would be drawn in a manner that is not in accordance with the actual proportions of the components, their shapes and sizes. The actual implementation of the components can vary in shape, number and proportions, and the layout of the components can be more complex.

[0051] In the following description, numerous specific details are discussed in order to provide a thorough explanation of the embodiments of the application. It will be apparent, however, to one of ordinary skill in the art that the embodiments of the application can be practiced without these specific details. In other instances, well-known structures and devices are not described in detail in order to avoid obscuring the embodiments of the application.

[0052] Referring to Figure 1 The application discloses a method for optimizing communication parameters of a core particle. The method can be applied to the core particle to optimize the communication parameters of a communication link between core particles. Before optimizing the communication link between core particles, basic parameters need to be configured, including setting a target transmission rate (including optional values such as 4G, 8G or 16G) and a target link width (i.e. the total number of channels). At the same time, the UCIe state machine is suspended in the MBTRAIN.DATATRAINCENTER2 state defined in its specification, which represents the equalization training phase for the center channel (this state machine is the inherent hardware logic of the UCIe protocol, and the present scheme only calls its suspension function).

[0053] In some embodiments, the core particles can be divided into local core particles and remote core particles. The multiple sending ends of the local core particles are connected one-to-one with the multiple receiving ends of the remote core particles, forming multiple independent data sending channels. The multiple receiving ends of the local core particles are connected one-to-one with the multiple sending ends of the remote core particles, forming multiple independent data receiving channels. In the subsequent optimization process, the local core particles are taken as an example for description, and the local core particles are denoted as core particles.

[0054] In some embodiments, the optimization method can comprise the following steps: step S10, performing data sending tests through all the sending ends of the core particles according to preset different phases; wherein the preset different phases are obtained by gradually adjusting the initial phase value of the core particles according to a preset phase code step amount.

[0055] In some embodiments, step S10 can comprise the following steps: step S11, starting from the initial phase value, adjusting the initial phase value of the core particles according to a preset negative phase offset direction and according to a preset phase code step amount, until one clock period is adjusted; and performing data sending tests through all the sending ends of the core particles according to the phase obtained after each adjustment.

[0056] In some embodiments, the preset phase code step amount is (1 / MAX_PI)UI when the initial phase value is adjusted in the preset negative phase offset direction (i.e. the phase angle decreasing direction). Wherein MAX_PI represents the maximum number of phase interpolators; the number of adjustments can be MAX_PI; and UI represents the time for transmitting a single data. By adjusting MAX_PI times, one clock period is cumulatively adjusted in the negative phase offset direction. After each adjustment, PRBS (Pseudo Random Binary Sequence) test code streams are synchronously sent from all the sending ends of the core particles to the remote core particles. The remote core particles monitor each data receiving channel in real time: if any data receiving channel has abnormal data points (such as error codes, timing dislocations, etc.), it is determined that the test at the current phase is failed; if the data of all data receiving channels are normal, it is determined that the test is passed.

[0057] In some embodiments, by shifting one complete clock period to the left in a step-by-step manner, the phase fault tolerance range of the left half of the clock period is systematically scanned; by using PRBS code streams to simulate high-load random data and forcing all sending channels to work in parallel, the weakest channel bottleneck in the link can be exposed; by the remote abnormal point feedback mechanism, the failure threshold of the phase offset is accurately identified, providing data support for subsequent optimization.

[0058] In some embodiments, step S10 can further comprise the following step: step S12, adjusting the adjusted phase according to a preset positive phase offset direction and according to a phase code step amount, until the initial phase value is reached.

[0059] In some embodiments, the current phase value is gradually increased by the phase code step size in the preset positive phase shift direction (phase angle increasing direction) until it returns to the initial phase value. This process does not trigger any data transmission test. Through the above process, the instantaneous voltage / current overshoot caused by the phase value jumping from the negative limit back to the initial value can be avoided, preventing signal ringing or power supply noise in high-frequency circuits; at the same time, a unified phase reference point can be established for subsequent positive shift tests, ensuring the consistency of test conditions in each stage.

[0060] In some embodiments, step S10 can further include the following step: step S13, starting from the initial phase value, gradually adjusting the initial phase value according to the phase code step size in the positive phase shift direction until one clock cycle is adjusted; and performing data transmission tests through all the transmitting ends of the core grain according to the phase obtained after each adjustment.

[0061] In some embodiments, the initial phase value is gradually adjusted by the same phase code step size in the preset positive phase shift direction (phase angle increasing direction), and the cumulative adjustment achieves a right shift of one clock cycle. After each adjustment, the transmitting ends of the core grain are started to synchronously transmit PRBS test code streams to the remote core grain. The remote core grain monitors each data receiving channel in real time: if any data receiving channel has abnormal data points (such as error codes, timing misplacement, etc.), it is determined that the test at the current phase is failed; if the data of all data receiving channels are normal, it is determined that the test is passed.

[0062] In some embodiments, by extending the scan to the right half of the clock cycle and merging it with the negative scan formed by the above process, the phase window of two consecutive clock cycles is completely covered. By shifting left and right by one clock cycle, potential timing conflicts (such as overlapping regions of data eye diagrams) across clock cycles can be captured, avoiding the blind area of traditional single-cycle calibration.

[0063] In some embodiments, step S10 can further include the following step: step S14, gradually adjusting the adjusted phase according to the phase code step size in the negative phase shift direction until it is adjusted to the initial phase value.

[0064] In some embodiments, the current phase value is gradually decreased by the same phase code step size in the preset negative phase shift direction (phase angle decreasing direction) until it returns to the initial phase value. No data transmission test is performed in this stage. Through the above process, the transient response problem of the driving circuit caused by the phase jumping from the positive limit back to zero can be avoided, maintaining signal integrity.

[0065] In some embodiments, by the combination strategy of left shift by one clock cycle and right shift by one clock cycle, the traditional single cycle calibration limit can be broken through, and the robustness to clock jitter and timing deviation can be significantly improved. Although the phase recovery operation does not participate in the performance test, the hardware transient risk is eliminated by the step reset, which is particularly important in high frequency (such as 16Gbps) scenarios. Each phase adjustment forces all data transmission channels to work synchronously, and combined with independent abnormality detection of the remote multi-receiving channel, the link bottleneck can be efficiently optimized.

[0066] In some embodiments, the optimization method can include the following steps: step S20, calculating the optimal phase value according to the test information of all data transmission tests, and optimizing the clock signal of the core grain according to the optimal phase value.

[0067] In some embodiments, step S20 can include: step S21, retaining the phase for which the test information is passed.

[0068] In some embodiments, by retaining only the phase for which the test information is passed (i.e., the remote core grain feedbacks that all data transmission channels have no abnormal points), and ignoring all phases for which the test is not passed, a phase set to be analyzed can be formed. By excluding phases with channel failure, it is ensured that subsequent analysis is based only on stable and available working phases; at the same time, invalid data interference can be avoided, and the phase interval within the actual fault tolerance capability of the link can be focused.

[0069] In some embodiments, step S20 can further include: step S22, sorting the retained phases to obtain a corresponding continuous sequence.

[0070] In some embodiments, the retained phases are sorted according to the number of adjustments to generate an ordered phase sequence. For the phases corresponding to the negative phase offset direction, the retained phases can be sorted in descending order of the number of adjustments. For the phases corresponding to the positive phase offset direction, the retained phases can be sorted in ascending order of the number of adjustments. At this time, the two sequences can be integrated to obtain a continuous sequence. The left side of the continuous sequence represents the phase when the number of adjustments in the negative phase offset direction is the largest, and the right side of the continuous sequence represents the phase when the number of adjustments in the positive phase offset direction is the largest.

[0071] In some embodiments, step S20 can further include: step S23, calculating the optimal phase value according to the continuous sequence.

[0072] In some embodiments, step S23 can include: step S231, calculating the difference between two adjacent phases in the continuous sequence, and comparing the difference with the phase code step size.

[0073] In some embodiments, by traversing the continuous sequence, the difference between every two adjacent phases in the continuous sequence (e.g., the latter minus the former) is calculated. Each difference is compared with the phase code step size. When the adjacent phase difference is greater than the phase code step size, it indicates that there is a test-failed corresponding phase at this position. When the adjacent phase difference is equal to the phase code step size, it indicates that there is no test-failed corresponding phase at this position.

[0074] In some embodiments, step S23 can further include step S232, counting the number of differences greater than the phase code step size as the number of abnormal point positions.

[0075] In some embodiments, the number of adjacent phase code step sizes greater than the phase code step size is accumulated, and the number is defined as the number of abnormal point positions. For example, if there are 3 differences greater than the phase code step size in a continuous sequence, the number of abnormal point positions is equal to 3. The number of abnormal point positions can directly reflect the fragmentation degree of the phase available interval, and the higher the value, the worse the link timing fault tolerance.

[0076] In some embodiments, step S23 can further include step S233, finding the phase optimal value of the continuous sequence according to the comparison result of the number of abnormal point positions and the preset threshold.

[0077] In some embodiments, step S233 can include: judging the number of abnormal point positions and the preset threshold; when the number of abnormal point positions is less than the preset threshold, finding the center value of the continuous sequence as the phase optimal value; otherwise, splitting the continuous sequence into multiple sub-continuous sequences according to the abnormal point positions, and screening out the sub-continuous sequence with the largest number of phase positions as the target sub-continuous sequence; finding the center value of the target sub-continuous sequence as the phase optimal value.

[0078] In some embodiments, the number of abnormal point positions and the preset threshold (e.g., 3) can be compared and processed respectively. If the number of abnormal point positions is less than or equal to the preset threshold, the center phase value of the continuous sequence is directly obtained as the phase optimal value. If the number of abnormal point positions is greater than the preset threshold, the continuous sequence is split into multiple sub-continuous sequences according to the abnormal point positions. Then, the sub-continuous sequence with the largest number of phase positions is screened out as the target sub-sequence, and the center phase value thereof is obtained as the phase optimal value.

[0079] Please refer to Figure 2 and Figure 3 In some embodiments, the number of abnormal point positions is less than or equal to the preset threshold. The start index number 13 of the phase passed the test and the end index number 14 of the phase passed the test can be distributed on both sides of the minimum index number 11 or the maximum index number 12, or on the same side of the minimum index number 11 or the maximum index number 12. Figure 2 The displayed continuous sequence can be a bar,Figure 3 The displayed continuous sequence can be circular, from Figure 2 and Figure 3 As can be seen from the data, with the starting division number 13 as the starting point and the ending division number 14 as the ending point, the center division number 15 corresponding to the optimal phase value is located at the center of the two.

[0080] In some embodiments, step S20 may further include: step S24, optimizing the chip's clock signal according to the optimal phase value. Specifically, by writing the optimal phase value into the clock generator register to overwrite the initial phase value, dynamic calibration of the chip's transmitter clock phase can be achieved. Dynamically adjusting the clock phase based on measured data can compensate for timing offsets caused by process / voltage / temperature (PVT) deviations.

[0081] In some embodiments, the optimization method may include the following steps: Step S30: Based on the optimized clock signal, data reception tests are performed through each receiver of the chip according to preset different decision levels. The preset different decision levels are obtained by gradually adjusting the preset minimum level of the chip according to preset level step amounts.

[0082] In some embodiments, step S30 may include the following steps: Step S31: Set the decision level of all receivers of the chip to start from the preset minimum level value, and gradually adjust the minimum level value of all receivers of the chip according to the preset level step amount until the preset maximum level value is reached.

[0083] In some embodiments, the decision level of all data receivers in the chip is uniformly set to a preset minimum level, such as 0, as the starting reference point for the decision level scan. This operation is achieved by configuring the reference voltage register of the internal comparator of the receiver. This configuration ensures that all receivers start the test from the same low-level baseline, eliminating differences in the initial hardware state.

[0084] In some embodiments, the preset level step can be expressed as 1 / preset maximum level, where the preset maximum level refers to the maximum decision level that the receiver can withstand. In this case, the decision levels of all receivers can be adjusted synchronously, with the cumulative number of adjustments reaching the maximum value. Each adjustment increases the level step. This step-by-step increment mechanism avoids transient current overload caused by level jumps, protecting the receiver comparator circuit. Simultaneously, all receivers maintain the exact same decision level value, ensuring consistent test conditions. By repeatedly adjusting and fully scanning the operating range from 0 to the maximum value, the optimal decision point is captured without omission.

[0085] In some embodiments, step S30 can further include the following step: step S32, performing data receiving test through each receiving end of the die respectively according to the decision level obtained after each adjustment and the optimized clock signal, to obtain the test result of the data receiving test of each receiving end.

[0086] In some embodiments, according to the decision level obtained after each adjustment and the optimized clock signal, the far-end die can be controlled to continuously send the PRBS test code stream to all receiving ends of the die, and the data recovery state of each receiving end can be monitored independently. If ≥1 abnormal point (such as error code, data loss) occurs in a receiving end, the current decision level test result of the receiving end is marked as test failure. If all data of a receiving end is normally recovered, the current decision level test result of the receiving end is marked as test success. Finally, the test result under each decision level can be recorded for each receiving end respectively. By constructing a pass / fail state table under complete decision level scanning for each receiving end, the subsequent optimal level calculation can be supported.

[0087] In some embodiments, the optimization method can include the following step: step S40, calculating the optimal value of the decision level corresponding to each receiving end according to the test result of the data receiving test of the receiving end, and optimizing the decision level of the corresponding receiving end according to the optimal value of the decision level.

[0088] In some embodiments, step S40 can include the following step: step S41, for each receiving end: retaining the decision level with test success test result. Specifically, for each receiving end, all decision levels marked as test success test result can be extracted from the test result to generate the valid decision level set of the receiving end. If the data receiving of the receiving end is normal under a decision level (i.e. the PRBS code stream sent by the far-end die is completely and correctly recovered), the decision level is retained; otherwise, if there is an abnormal point, the decision level is excluded.

[0089] In some embodiments, step S40 can further include the following step: step S42, calculating the average value of the maximum value and the minimum value of the retained decision level as the optimal value of the decision level of the receiving end.

[0090] In some embodiments, the maximum value and the minimum value of the corresponding reserved decision level can be calculated for each receiving end, and the average value of the maximum value and the minimum value is the optimal decision level of the receiving end. The traditional fixed threshold method is prone to failure when the eye diagram is asymmetric. The optimal decision level calculated above is based on the measured pass interval, and automatically aligns the decision point to the position of the maximum vertical direction fault tolerance margin (i.e. the geometric center of the maximum value and the minimum value). For multiple receiving end cores, the eye diagram heights of the channels are inconsistent due to process deviation (e.g. the eye opening height of channel A is 0.4V, and the eye opening height of channel B is 0.3V). Independent calculation enables each receiving end to obtain an individual optimal level.

[0091] Referring to Figure 4 In some embodiments, the minimum value of the test pass level 23 can be distributed between the preset minimum level 21 and the preset maximum level 22, and the maximum value of the test pass level 24 can be distributed between the preset minimum level 21 and the preset maximum level 22. By calculating the average value of the minimum value of the test pass level 23 and the maximum value of the test pass level 24, the optimal decision level 25 can be obtained.

[0092] In some embodiments, step S40 can further include the following step: step S43, optimizing the decision level of the receiving end according to the optimal decision level. Specifically, by independently writing the calculated optimal decision level of each receiving end into the decision level register of the corresponding receiving end, the preset initial level can be overwritten, and the optimization of the full-link receiving end can be completed.

[0093] In some embodiments, after completing the first clock phase optimization and the receiving end decision level optimization, the UCIe link state machine can be restarted, and the optimization process can be re-executed. If the state machine still does not enter the Active state (i.e. the link stability standard required by the protocol is not met), the above process is continuously executed in a loop; the number of loops is not limited, and the state machine finally enters the Active state.

[0094] As can be seen, in the above scheme, the dynamic calibration of the UCIe physical layer communication parameters is realized by a software / firmware algorithm, effectively solving the problems of timing margin compression, voltage margin reduction and multi-channel skew under high-frequency clock. Based on the optimal phase value calculated by phase scanning and calculation, the problems caused by clock jitter can be eliminated. By full-range level scanning starting from the preset minimum level and independent decision level optimization calculation of each receiving end, the vertical direction noise tolerance can be maximized, and the problem of eye diagram asymmetry caused by process deviation can be solved.

[0095] The application further discloses a chip, which can include a plurality of interconnected core particles. The core particles can be the core particles in the above-mentioned embodiments. The chip can be divided into a local chip and a remote chip. When the local chip and the remote chip are interconnected, part of the core particles in the local chip can be interconnected with part of the core particles in the remote chip. The optimization method can optimize the communication parameters of the communication link of the interconnected local chip and remote chip.

[0096] The application further discloses a chip, which can include a plurality of interconnected core particles. The core particles can be the core particles in the above-mentioned embodiments. The chip can be divided into a local chip and a remote chip. When the local chip and the remote chip are interconnected, part of the core particles in the local chip can be interconnected with part of the core particles in the remote chip. The optimization method can optimize the communication parameters of the communication link of the interconnected local chip and remote chip.

[0097] The above-mentioned embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the application should be covered by the claims of the application.

Claims

1. A method of optimizing a communication parameter of a core particle, characterized by, Applied to the core particle, the optimization method comprises: According to the preset different phase, the data sending test is carried out through all the sending ends of the core particle; wherein, the preset different phase is obtained by gradually adjusting the initial phase value of the core particle according to the preset phase code step amount; Reserve test information as the phase of test passing; Sort the reserved phase to obtain the corresponding continuous sequence; Calculate the difference value of adjacent two phases in the continuous sequence, and compare the difference value with the phase code step amount; The number of difference values greater than the phase code step amount is counted as the number of abnormal points; Determine the number of abnormal points and the preset threshold value: when the number of abnormal points is less than the preset threshold value, find the center value of the continuous sequence as the optimal phase value; otherwise, according to the abnormal point, the continuous sequence is divided into a plurality of sub continuous sequences, and the sub continuous sequence with the largest number of phases is selected as the target sub continuous sequence; find the center value of the target sub continuous sequence as the optimal phase value; According to the optimal phase value, the clock signal of the core particle is optimized; The decision level of all receiving ends of the core particle is set to start from the preset minimum level, and the minimum level of all receiving ends of the core particle is adjusted step by step according to the preset level step amount, until the preset maximum level is reached; According to the decision level obtained by each adjustment and the optimized clock signal, data receiving test is carried out through each receiving end of the core particle respectively, and the test result of data receiving test of each receiving end is obtained; According to the test result of data receiving test of each receiving end, the corresponding optimal decision level is calculated, and the decision level of the corresponding receiving end is optimized according to the optimal decision level.

2. The method of optimizing communication parameters of a core grain according to claim 1, characterized in that, The step of carrying out data sending test through all the sending ends of the core particle according to the preset different phase comprises: From the initial phase value, the initial phase value of the core particle is adjusted step by step according to the preset phase code step amount in the preset negative phase offset direction, until one clock cycle is adjusted; according to the phase obtained by each adjustment, data sending test is carried out through all the sending ends of the core particle respectively; From the initial phase value, the initial phase value is adjusted step by step according to the phase code step amount in the preset positive phase offset direction, until one clock cycle is adjusted; according to the phase obtained by each adjustment, data sending test is carried out through all the sending ends of the core particle respectively.

3. The method of optimizing communication parameters of a core particle according to claim 2, wherein, After the step of adjusting the initial phase value of the core particle step by step according to the preset phase code step amount in the preset negative phase offset direction from the initial phase value, until one clock cycle is adjusted, it further comprises: According to the preset positive phase offset direction, the adjusted phase is adjusted step by step according to the phase code step amount until the initial phase value is adjusted.

4. The method of optimizing communication parameters of a core grain according to claim 2, wherein, After the step of adjusting the initial phase value step by step according to the phase code step amount in the preset positive phase offset direction from the initial phase value, until one clock cycle is adjusted, it further comprises: According to the negative phase offset direction, the adjusted phase is adjusted step by step according to the phase code step amount until the initial phase value is adjusted.

5. The method of optimizing communication parameters of a core grain according to claim 1, wherein, The step of calculating the optimal value of the decision level corresponding to each receiving end according to the test result of the data receiving test of the receiving end and optimizing the decision level of the corresponding receiving end according to the optimal value of the decision level comprises: For each receiving end: Reserve the decision level with a test result of test pass; Calculate the average value of the maximum value and the minimum value of the reserved decision level as the optimal value of the decision level of the receiving end; Optimize the decision level of the receiving end according to the optimal value of the decision level.

6. A core particle characterized by, The optimization method of the communication parameter of the core particle as claimed in any one of claims 1 to 5.

7. A chip, characterized by The chip comprises the core particle as claimed in claim 6. The chip comprises the core particle as claimed in claim 6.

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