System for data communication, semiconductor chip, and data communication method

Abstract

A system includes a plurality of semiconductor chips stacked on one another and including first and second semiconductor chips. The first semiconductor chip includes a clock signal generation circuit, a transmission circuit, and a reception circuit. The clock signal generation circuit generates a clock signal and a delayed version of the clock signal. The transmission circuit transmits a first data signal in response to a clock signal. The receiving circuit receives a second data signal in response to a delayed version of the clock signal. For example, the receiving circuit receives a delayed version of the clock signal while the transmitting circuit receives the clock signal. The embodiment of the invention provides a system for data communication, a semiconductor chip and a data communication method.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a system for data communication, a semiconductor chip and a method of data communication. BACKGROUND

[0002] Systems such as three-dimensional integrated circuit (3D-IC) systems, chip-on-wafer-on-substrate (CoWoS) systems, or other packaging technology systems involve stacking semiconductor chips together. Such arrangements can improve performance while reducing the surface area occupied by the semiconductor chips on a packaging substrate. Proper clock signal synchronization within these semiconductor chips is often very important for optimal performance of such systems. SUMMARY

[0003] One embodiment of the present application provides a system for data communication, comprising a plurality of semiconductor chips stacked with each other, the plurality of semiconductor chips stacked with each other comprising a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip comprises a clock signal generation circuit, a transmission circuit and a reception circuit, the clock signal generation circuit configured to generate a first clock signal and a delayed version of the first clock signal, the transmission circuit configured to transmit a first data signal in response to the first clock signal, the reception circuit configured to receive a second data signal in response to the delayed version of the first clock signal, wherein the reception circuit is configured to receive the delayed version of the first clock signal substantially simultaneously with the transmission circuit being configured to receive the first clock signal.

[0004] Another embodiment of the present application provides a semiconductor chip, comprising: a clock signal source configured to generate a first clock signal; a data signal transmitter configured to transmit a first data signal in response to the first clock signal; a clock signal transmitter configured to transmit the first clock signal; and a data signal receiver configured to receive a second data signal in response to a delayed version of the first clock signal or a second clock signal.

[0005] Yet another embodiment of the present application provides a method of data communication, comprising: generating, by a first semiconductor chip, a first clock signal; transmitting, in response to the first clock signal, a first data signal to a second semiconductor chip as a second data signal; transmitting the first clock signal to the second semiconductor chip as a second clock signal; receiving, by the second semiconductor chip, the second clock signal; transmitting, in response to the second clock signal, a third data signal to the first semiconductor chip as a fourth data signal; and receiving, by the first semiconductor chip, the fourth data signal in response to a delayed version of the first clock signal. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the present disclosure can be best understood with reference to the following detailed description when read in conjunction with the accompanying drawings.

[0007] Figure 1 is a block diagram of an exemplary system according to embodiments of the present disclosure;

[0008] Figure 2 is a circuit / block diagram of another exemplary system according to embodiments of the present disclosure;

[0009] Figure 3 is a circuit / block diagram of another exemplary system according to embodiments of the present disclosure;

[0010] Figure 4 is a circuit / block diagram of another exemplary system according to embodiments of the present disclosure;

[0011] Figure 5 is a circuit / block diagram of another exemplary system according to embodiments of the present disclosure;

[0012] Figure 6 is a circuit / block diagram of another exemplary system according to embodiments of the present disclosure;

[0013] Figure 7 is a circuit / block diagram of another exemplary system according to embodiments of the present disclosure; and

[0014] Figure 8 is a flow diagram illustrating an exemplary method of data communication between semiconductor chips according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and the second component are in direct contact, and can also include embodiments where additional components are formed between the first component and the second component such that the first component and the second component can not be in direct contact. Further, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0016] In example embodiments, a system includes first and second semiconductor chips joined together. In response to a clock signal, the first semiconductor chip sends data signals to the second semiconductor chip and receives data signals from the second semiconductor chip, and vice versa. The clock signals at the first and second semiconductor chips can be out of sync. This out of sync can cause data communication errors between the first and second semiconductor chips. The systems and methods described in certain examples herein alleviate the synchronization issue by employing a delay circuit that introduces a predetermined propagation delay into a signal (e.g., a clock signal) in the system. As will be described in detail below, in examples, the delay circuit can help ensure that the clock signals arrive at the first and second semiconductor chips at substantially the same time. This synchronization facilitates stable data communication between the first and second semiconductor chips.

[0017] Figure 1 is a block diagram of an example system 100 in accordance with embodiments of the present disclosure. In certain embodiments, the example system 100 (e.g., a three-dimensional integrated circuit (3D-IC) system, a chip-on-wafer-on-substrate (CoWoS) system, or other packaging technology system) complies with a specification for die-to-die interconnects (and serial buses) between chipsets, such as the Universal Chipset Interconnect Express (UCIE) standard. As shown, the system 100 includes a first semiconductor chip 110 and a second semiconductor chip 120 joined to the first semiconductor chip 110 by a plurality of interconnects (e.g., interconnects 230). The interconnects establish electrical connections between the semiconductor chips or between the semiconductor chips and a packaging substrate, interposer, or PCB. Such interconnects include micro-bumps, solder balls, copper pillars, ball grid arrays (BGAs), combinations of metal and dielectric interconnects, other interconnects produced by hybrid bonding, tape automated bonding (TAB), wire bonding, or flip chip bonding, other suitable interconnects, or combinations thereof. Figure 1 Figure 2

[0018] In some embodiments, the semiconductor chip 110 has a top or bottom surface that is joined to a top or bottom surface of the semiconductor chip 120. In other embodiments, an interposer interconnects the semiconductor chips 110, 120. In these other embodiments, the interposer includes an interposer substrate, a frontside redistribution layer (RDL), and one or more interposer vias (IVs). Examples of materials for the interposer substrate include silicon, organic materials, glass, ceramic, polymer-based materials, other suitable interposer substrate materials, and combinations thereof. The frontside RDL is formed on a top surface of the interposer and includes horizontal and vertical metal lines. Each IV extends from the frontside RDL to a bottom surface of the interposer.

[0019] ​​In alternative embodiments, the interposer further includes a backside RDL formed on the interposer backside. In such alternative embodiments, the TIV is connected between the frontside and backside RDLs. Material examples for the frontside and backside RDLs and the TIV include copper, nickel, gold, silver, cobalt, tungsten, aluminum, other conductive materials, and combinations thereof.

[0020] Each semiconductor chip 110, 120 includes a chip substrate, chip circuitry, and a conductive layer. Material examples for the chip substrate include silicon, germanium, III-V semiconductor materials, other suitable semiconductor materials, and combinations thereof. The chip circuitry is fabricated on the chip substrate and performs one or more circuit functions. The conductive layer (e.g., back end of line or BEOL) interconnects circuit elements of the chip circuitry. In one example, the circuit elements include active circuit components (e.g., transistors, diodes, and integrated circuits) and passive circuit components (e.g., resistors, inductors, and capacitors).

[0021] In this example embodiment, semiconductor chip 110 includes a clock signal generation circuit 130, a transmit circuit 140, and a receive circuit 150. Clock signal (Cl) generation circuit 130 generates a clock signal (Cl) and transmits the clock signal (Cl) as a clock signal (C2) to semiconductor chip 120. Transmit circuit 140 transmits a data signal (Dl) as a data signal (D2) to semiconductor chip 120 in response to the clock signal (Cl). In some embodiments, receive circuit 150 receives a data signal (D4) in response to the clock signal (Cl). In other embodiments, receive circuit 150 receives the data signal (D4) in response to a delayed version of the clock signal (Cl). In these other embodiments, the delayed version of the clock signal (Cl) arrives at receive circuit 150 substantially simultaneously with the clock signal (C2) arriving at semiconductor chip 120. This synchronization facilitates stable data communication between semiconductor chips 110, 120.

[0022] Similarly, semiconductor chip 120 includes a receive circuit 160 and a transmit circuit 170. In some embodiments, receive circuit 160 receives a data signal (D2) in response to the clock signal (C2). In these embodiments, transmit circuit 170 transmits a data signal (D3) as a data signal (D4) to semiconductor chip 110 in response to the clock signal (C2). In other embodiments, receive circuit 160 receives the data signal (D2) in response to the clock signal (C2) and another clock signal (e.g., clock signal (C3)). In other embodiments, transmit circuit 170 transmits the data signal (D3) as the data signal (D4) to semiconductor chip 110 in response to the clock signal (C3). In certain embodiments, transmit circuit 170 transmits the clock signal (C3) to semiconductor chip 110. Figure 2

[0023] ​Figure 2 is a circuit / block diagram of another exemplary system 200 according to embodiments of the present disclosure. As shown, the exemplary system 200 (e.g., system 100) includes a first semiconductor chip 210 and a second semiconductor chip 220 bonded to the first semiconductor chip 210 by a plurality of interconnects 230. In this exemplary embodiment, the semiconductor chip 210 includes first and second data signal processors 210a, 210b, a clock signal source 210c, first and second clock trees 210d, 210e, a data signal transmitter 210f, a clock signal transmitter 210g, a clock signal receiver 210h, and a data signal receiver 210i. The data signal processor 210a (e.g., a central processing unit or CPU, a graphics processing unit or GPU, a mathematical co-processor (e.g., a floating point unit or FPU), a memory device, other device that processes data signals, or a combination thereof) generates a data signal (Dl). Figure 2

[0024] The clock signal source 210c generates a clock signal (Cl), which in this exemplary embodiment includes a phase-locked loop (PLL) that adjusts and stabilizes the frequency of the clock signal (Cl) based on the frequency of a reference clock signal. The clock tree 210d is connected between the clock signal (Cl) source 210b and the data signal (Dl) transmitter 210f, distributes the clock signal (Cl) to chip circuitry of the semiconductor chip 210 (e.g., the data signal Dl transmitter 210f), and ensures that the clock signal (Cl) arrives at the data signal transmitter at the same time or with minimal skew (i.e., timing difference). The data signal (Dl) transmitter 210f transmits the data signal (Dl) as a data signal (D2) to the semiconductor chip 220. For example, the data signal (Dl) transmitter 210d includes a flip-flop (FF) circuit 210f’ and a buffer circuit. Responsive to the clock signal (Cl), the flip-flop circuit 210f’ (e.g., a D-type flip-flop circuit, a JK flip-flop circuit, other suitable flip-flop circuit, or a combination thereof) holds or stores bits of the data signal (Dl). Each stored bit is available at the output of the flip-flop circuit 210f’ at the rising edge (or falling edge) of the clock signal (Cl). The buffer circuit of the data signal (Dl) transmitter 210f maintains the integrity of the data signal (Dl) by amplifying the data signal (Dl), providing isolation, reducing noise, and minimizing delay.

[0025] ​The clock signal (C1) transmitter 210g transmits the clock signal (C1) as a clock signal (C2) to the semiconductor chip 220. For example, the clock signal (C1) transmitter 210g includes an inverter and a buffer circuit. The inverter generates an inverted version of the clock signal (C1). The buffer circuit of the clock signal (C1) transmitter 210g maintains the integrity of the clock signal (C1) by amplifying the clock signal (C1), providing isolation, reducing noise, and minimizing delay.

[0026] The clock signal receiver 210h receives the clock signal (C4) from the semiconductor chip 220. For example, the clock signal (C4) receiver 210h includes a buffer circuit that maintains the integrity of the clock signal (C4) by amplifying the clock signal (C4), providing isolation, reducing noise, and minimizing delay. The clock tree 210e is connected between the clock signal (C4) receiver 210h and the data signal receiver 210i, distributes the clock signal (C4) to chip circuits (e.g., the data signal receiver 210i) of the semiconductor chip 210, and ensures that the clock signal (C4) arrives at the data signal receiver simultaneously or with minimal skew (i.e., timing difference).

[0027] The data signal receiver 210i receives the data signal (D4) from the semiconductor chip 220. For example, the data signal (D4) receiver 210i includes a buffer circuit, a flip-flop circuit 210i’, and a register circuit 210i”. The buffer circuit of the data signal (D4) receiver 210i maintains the integrity of the data signal (D4) by amplifying the data signal (D4), providing isolation, reducing noise, and minimizing delay. In response to the clock signal (C4), the flip-flop circuit 210i’ (e.g., a D-type flip-flop circuit, a JK flip-flop circuit, other suitable flip-flop circuit, or a combination thereof) holds or stores bits of the data signal (D4). Each stored bit is available at an output of the flip-flop circuit 210i’ at a rising edge (or a falling edge) of the clock signal (C4).

[0028] Register circuit 210i” outputs bits of data signal (D4) in the order received in response to clock signals (C1, C4). For example, in some embodiments, register circuit 210i” is a first-in-first-out (FIFO) register circuit and outputs bits of data signal (D4) in the same order as received. In these embodiments, clock signal (C4) controls writing of data signal (D4) to register circuit 210i”, while clock signal (C4) controls reading of data signal (D4) from register circuit 210i” by data signal (D4) processor 210b. In this example embodiment, clock signals (C1, C4) operate in different clock domains. For example, they (C1, C4) have different frequencies, phases, or are independent of each other. In other embodiments, various configurations of register circuit 210i” are contemplated. Data signal (D4) processor 210b (e.g., a CPU, GPU, mathematical co-processor (e.g., FPU), memory device, other device that generates data signals, or combination thereof) processes data signal (D4).

[0029] Similarly, semiconductor chip 220 includes clock signal (C2) receiver 220a, first and second clock trees 220b, 220c, clock signal source 220d, data signal (D2) receiver 220e, first and second data signal processors 220f, 220g, data signal transmitter 220h, and clock signal (C4) transmitter 220i. Clock signal (C2) receiver 220a receives clock signal (C2) from semiconductor chip 210. For example, clock signal (C2) receiver 220a includes a buffer circuit that preserves the integrity of clock signal (C2) by amplifying clock signal (C2), providing isolation, reducing noise, and minimizing delay. Clock tree 220b is connected between clock signal (C2) receiver 220a and data signal (D2) receiver 220e, distributes clock signal (C2) to chip circuits of semiconductor chip 220 (e.g., data signal D2 receiver 220e), and ensures that clock signal (C2) arrives at data signal receivers at the same time or with minimal skew (i.e., timing difference).

[0030] The clock signal source 220d generates a clock signal (C3) and, in this example embodiment, includes a PLL that adjusts and stabilizes the frequency of the clock signal (C3) based on the frequency of the reference clock signal. The data signal (D2) receiver 220e receives the data signal (D2) from the semiconductor chip 210. For example, the data signal (D2) receiver 220e includes a buffer circuit, a flip-flop circuit 220e', and a register circuit 220e". The buffer circuit of the data signal (D2) receiver 220e maintains the integrity of the data signal (D2) by amplifying the data signal (D2), providing isolation, reducing noise, and minimizing delay. The flip-flop circuit 220e' (e.g., a D-type flip-flop circuit, a JK flip-flop circuit, other suitable flip-flop circuit, or a combination thereof) holds or stores bits of the data signal (D2) in response to the clock signal (C2). Each stored bit is available at the output of the flip-flop circuit 220e' at the rising edge (or falling edge) of the clock signal (C3).

[0031] The register circuit 220e" outputs the bits of the data signal (D2) in the order of reception in response to the clock signals (C2, C3). For example, in some embodiments, the register circuit 220e" is a FIFO register circuit and outputs the bits of the data signal (D2) in the order of reception. In these embodiments, the clock signal (C2) controls the writing of the data signal (D2) to the register circuit 220e", while the clock signal (C3) controls the reading of the data signal (D2) from the register circuit 220e" by the data signal (D2) processor 220f. In this example embodiment, the clock signals (C2, C3) operate in different clock domains. For example, they have different frequencies, phases, or are independent of each other. In other embodiments, various configurations of the register circuit 220e" are contemplated. The data signal (D2) processor 220f (e.g., a CPU, a GPU, a mathematical co-processor (e.g., a FPU), a memory device, other device that generates a data signal, or a combination thereof) processes the data signal (D2).

[0032] A data signal processor 220g (e.g., a CPU, a GPU, a mathematical co-processor (e.g., an FPU), a memory device, other device that processes data signals, or a combination thereof) generates a data signal (D3). A clock tree 220c connects between a clock signal (C3) source 220d and a data signal (D3) transmitter 220h, distributes the clock signal (C3) to chip circuitry (e.g., the data signal D3 transmitter 220h) of the semiconductor chip 220, and ensures that the clock signal (C3) reaches the data signal transmitter at the same time or with minimal skew (i.e., timing difference). The data signal (D3) transmitter 220h transmits the data signal (D3) as a data signal (D4) to the semiconductor chip 210. For example, the data signal (D3) transmitter 220h includes a flip-flop circuit 220h’ and a buffer circuit. In response to the clock signal (C3), the flip-flop circuit 220h’ (e.g., a D-type flip-flop circuit, a JK flip-flop circuit, other suitable flip-flop circuit, or a combination thereof) holds or stores bits of the data signal (D3). Each stored bit is available at an output of the flip-flop circuit 220h’ at a rising edge (or a falling edge) of the clock signal (C3). The buffer circuit of the data signal (D3) transmitter 220h maintains the integrity of the data signal (D3) by amplifying the data signal (D3), providing isolation, reducing noise, and minimizing delay.

[0033] A clock signal (C3) transmitter 220i transmits the clock signal (C3) as a clock signal (C4) to the semiconductor chip 210. For example, the clock signal (C3) transmitter 220i includes an inverter and a buffer circuit. The inverter generates an inverted version of the clock signal (C3). The buffer circuit of the clock signal (C3) transmitter 220i maintains the integrity of the clock signal (C3) by amplifying the clock signal (C3), providing isolation, reducing noise, and minimizing delay.

[0034] In an example operation, the data signal (D1) processor 210a generates the data signal (D1), while the clock signal (C1) source 210c generates the clock signal (C1). The data signal (D1) transmitter 210f transmits the data signal (D1) as a data signal (D2) to the semiconductor chip 220 in response to the clock signal (C1). At this time, the clock signal (C1) transmitter 210g transmits the clock signal (C1) as a clock signal (C2) to the semiconductor chip 220.

[0035] Next, the clock signal (C3) source 220d generates a clock signal (C3). The data signal (D2) receiver 220e receives the data signal (D2) in response to the clock signals (C2, C3). Then, the data signal (D2) processor 220f processes the data signal (D2). Subsequently, the data signal (D3) processor 220g generates a data signal (D3). In response to the clock signal (C3), the data signal (D3) transmitter 220h transmits the data signal (D3) as the data signal (D4) to the semiconductor chip 210. At this time, the clock signal (C3) transmitter 220i transmits the clock signal (C3) as the clock signal (C4) to the semiconductor chip 210. In response to the clock signals (C1, C4), the data signal (D4) receiver 210i receives the data signal (D4). Thereafter, the data signal (D4) processor 210b processes the data signal (D4).

[0036] Figure 3 is a circuit / block diagram of another exemplary system 300 according to an embodiment of the present disclosure. Figure 3 As shown, exemplary system 300 (e.g., system 100) differs from system 200 in that system 300 further includes a delay circuit 310 and first and second multiplexers 320 and 330. Delay circuit 310 is connected between clock signal source 210c and multiplexer 320, introduces a propagation delay to clock signal (C1), and generates a delayed version of clock signal (C1). For example, delay circuit 310 simulates the propagation delay of clock signal (C1) transmitter 210g, interconnect 230, clock signal (C2) receiver 220a, clock signal (C3) transmitter 220i, and clock signal (C4) receiver 210h. In this exemplary embodiment, delay circuit 310 includes one or more inverters and / or one or more buffer circuits. In other embodiments, various configurations of delay circuit 310 are contemplated.

[0037] The multiplexer 320, in response to a control signal (e.g., received from a control signal generator), selects one of the delayed version of the clock signal (C1) and the clock signal (C4) and forwards the selected one of the delayed version of the clock signal (C1) and the clock signal (C4) to the data signal (D4) receiver 210i. For example, the multiplexer 320 has a first input connected to the delay circuit 310, a second input connected to the clock signal (C4) receiver 210h, and an output connected to the clock tree 210e. The multiplexer 330, in response to a control signal (e.g., received from a control signal generator), selects one of the clock signals (C2, C3) and forwards the selected one of the clock signals (C2, C3) to the data signal (D3) transmitter 220h. For example, the multiplexer 330 has a first input connected to a node between the clock signal (C2) receiver 220a and the clock tree 220b, a second input connected to the clock signal (C3) source 220d, and an output connected to a node between the clock signal (C3) transmitter 220i and the clock tree 220c.

[0038] In an exemplary operation, when the multiplexer 320 selects the delayed version of the clock signal (C1) and the multiplexer 330 selects the clock signal (C2), the data signal (D1) processor 210a generates the data signal (D1) while the clock signal (C1) source 210c generates the clock signal (C1). In response to the clock signal (C1), the data signal (D1) transmitter 210f transmits the data signal (D1) as the data signal (D2) to the semiconductor chip 220. At this time, the clock signal (C1) transmitter 210g transmits the clock signal (C1) as the clock signal (C2) to the semiconductor chip 220.

[0039] Next, the clock signal (C3) source 220d generates the clock signal (C3). The data signal (D2) receiver 220e receives the data signal (D2) in response to the clock signal (C2, C3). The data signal (D2) processor 220f then processes the data signal (D2) followed by the data signal (D3) processor 220g generating the data signal (D3). The data signal (D3) transmitter 220h transmits the data signal (D3) as the data signal (D4) to the semiconductor chip 210 in response to the clock signal (C2). At the same time, the clock signal (C2) transmitter 220i transmits the clock signal (C2) as the clock signal (C4) to the semiconductor chip 210. At this time, the delay circuit 310 generates the delayed version of the clock signal (C1). The data signal (D4) receiver 210i receives the data signal (D4) in response to the clock signal (D1) and the delayed version of the clock signal (C1). Thereafter, the data signal (D4) processor 210b processes the data signal (D4).

[0040] From the foregoing description, it is known that the propagation delay introduced by the delay circuit 310 is substantially equal to the sum of the propagation delays caused by the components 210g, 230, 220a, 220i, 210h because the delay circuit 310 simulates the propagation delays introduced by the clock signal (C1) sender 210g, the interconnect 230, the clock signal (C2) receiver 220a, the clock signal (C3) sender 220i, and the clock signal (C4) receiver 210h. Thus, the time at which the clock signal (C2) reaches the data signal (D2) receiver 220e is substantially the same as the time at which the delayed version of the clock signal (C1) reaches the data signal (D4) receiver 210i. This synchronization facilitates stable data communication between the semiconductor chips 210, 220. In certain embodiments, the clock signal (C1) reaches the data signal (D1) sender 210f substantially simultaneously with the delayed version of the clock signal (C1) reaching the data signal (D4) receiver 210i.

[0041] In another example operation, when the multiplexer 320 selects the clock signal (C4) and the multiplexer 330 selects the clock signal (C3), the data signal (D1) processor 210a generates the data signal (D1) while the clock signal (C1) source 210c generates the clock signal (C1). The data signal (D1) sender 210f sends the data signal (D1) as the data signal (D2) to the semiconductor chip 220 in response to the clock signal (C1). At the same time, the clock signal (C1) sender 210g sends the clock signal (C1) as the clock signal (C2) to the semiconductor chip 220.

[0042] Subsequently, the clock signal (C3) source 220d generates the clock signal (C3). The data signal (D2) receiver 220e receives the data signal (D2) in response to the clock signals (C2, C3). The data signal (D2) processor 220f then processes the data signal (D2). Next, the data signal (D3) processor 220g generates the data signal (D3). In response to the clock signal (C3), the data signal (D3) sender 220h sends the data signal (D3) as the data signal (D4) to the semiconductor chip 210. Substantially simultaneously, the clock signal (C3) sender 220i sends the clock signal (C3) as the clock signal (C4) to the semiconductor chip 210. In response to the clock signals (C1, C4), the data signal (D4) receiver 210i receives the data signal (D4). Thereafter, the data signal (D4) processor 210b processes the data signal (D4).

[0043] Figure 4 is a circuit / block diagram of another example system 400 in accordance with an embodiment of the present disclosure. As Figure 4As shown, example system 400 (e.g., system 100) differs from system 200 in that system 400 omits (i.e., does not include) clock signal (C4) receiver 210h, clock signal (C3) source 220d, and clock signal (C3) transmitter 220i. Clock signal (C1) source 210c is connected to a node between clock trees 210d, 210e. Clock signal (C2) receiver 220a is connected to a node between clock trees 220b, 220c.

[0044] In embodiments, data signal (D4) receiver 210i omits register circuit 210i”. In such embodiments, flip-flop circuit 210i’ can be replaced by a demultiplexer.

[0045] In example operation, data signal (D1) processor 210a generates data signal (D1), while clock signal (C1) source 210c generates clock signal (C1). Data signal (D1) transmitter 210f transmits data signal (D1) as data signal (D2) to semiconductor chip 220 in response to clock signal (C1). At this time, clock signal (C1) transmitter 210g transmits clock signal (C1) as clock signal (C2) to semiconductor chip 220.

[0046] Next, data signal (D2) receiver 220e receives data signal (D2) in response to clock signal (C2). Then, data signal (D3) processor 220g generates data signal (D3). Data signal (D3) transmitter 220h transmits data signal (D3) as data signal (D4) to semiconductor chip 210 in response to clock signal (C2). Data signal (D4) receiver 210i receives data signal (D4) in response to clock signal (C1). Thereafter, data signal (D4) processor 210b processes data signal (D4).

[0047] Figure 5 is a circuit / block diagram of another example system 500 according to embodiments of the present disclosure. As shown, example system 500 (e.g., system 100) differs from system 400 in that system 500 further includes delay circuit 510 and first and second multiplexers 520, 530. Delay circuit 510 is connected between clock signal (C1) source 210c and multiplexer 520, introduces a propagation delay to clock signal (C1), and generates a delayed version of clock signal (C1). For example, delay circuit 510 emulates the propagation delay of clock signal (C1) transmitter 210g, interconnect 230, and clock signal (C2) receiver 220a. In this example embodiment, delay circuit 510 includes one or more inverters and / or one or more buffer circuits. In other embodiments, various configurations of delay circuit 510 are contemplated. Figure 5 As shown, example system 500 (e.g., system 100) differs from system 400 in that system 500 further includes delay circuit 510 and first and second multiplexers 520, 530. Delay circuit 510 is connected between clock signal (C1) source 210c and multiplexer 520, introduces a propagation delay to clock signal (C1), and generates a delayed version of clock signal (C1). For example, delay circuit 510 emulates the propagation delay of clock signal (C1) transmitter 210g, interconnect 230, and clock signal (C2) receiver 220a. In this example embodiment, delay circuit 510 includes one or more inverters and / or one or more buffer circuits. In other embodiments, various configurations of delay circuit 510 are contemplated.

[0048] Multiplexer 520, responsive to a control signal (e.g., received from a control signal generator), selects a delayed version of clock signal (Cl) and forwards the selected delayed version of clock signal (Cl) to data signal (D4) receiver 210i. For example, multiplexer 520 has a first input connected to delay circuit 510, a second input floating or hardwired to a logic state (e.g., 0 or 1), and an output connected to clock tree 210e. Multiplexer 530, responsive to a control signal (e.g., received from a control signal generator), selects clock signal (C2) and forwards the selected clock signal (C2) to data signal (D3) transmitter 220h. For example, multiplexer 530 has a first input connected to clock signal (C2) receiver 220a, a second input floating or hardwired to a logic state (e.g., 0 or 1), and an output connected to clock tree 220c.

[0049] In an embodiment, data signal (D4) receiver 210i omits register circuit 210i”. In such an embodiment, flip-flop circuit 210i’ can be replaced by a demultiplexer.

[0050] In an exemplary operation, data signal (Dl) processor 210a generates data signal (Dl) while clock signal (Cl) source 210c generates clock signal (Cl). Responsive to clock signal (Cl), data signal (Dl) transmitter 210f transmits data signal (Dl) as data signal (D2) to semiconductor chip 220. At the same time, clock signal (Cl) transmitter 210g transmits clock signal (Cl) as clock signal (C2) to semiconductor chip 220.

[0051] Data signal (D2) receiver 220e receives data signal (D2) responsive to clock signal (C2). Next, data signal (D3) processor 220g generates data signal (D3). Data signal (D3) transmitter 220h transmits data signal (D3) as data signal (D4) to semiconductor chip 210 responsive to clock signal (C2). At this time, delay circuit 510 generates a delayed version of clock signal (Cl). Data signal receiver 210i receives data signal (D4) responsive to clock signal (Cl) and the delayed version of clock signal (Cl). Thereafter, data signal (D4) processor 210b processes data signal (D4).

[0052] As can be seen from the above description, since the delay circuit 510 emulates the propagation delay introduced by the clock signal (C1) sender 210g, the interconnect 230, and the clock signal (C2) receiver 220a, the propagation delay introduced by the delay circuit 310 is substantially equal to the sum of the propagation delays caused by these components 210g, 230, 220a. Thus, the time at which the clock signal (C2) reaches the data signal (D3) sender 220h is substantially the same as the time at which the delayed version of the clock signal (C1) reaches the data signal (D4) receiver 210i. This synchronization facilitates stable data communication between the semiconductor chips 210, 220. In certain embodiments, the clock signal (C1) reaches the data signal (D1) sender 210f substantially simultaneously with the delayed version of the clock signal (C1) reaching the data signal (D4) receiver 210i.

[0053] Figure 6 is a circuit / block diagram of another exemplary system 600 according to embodiments of the present disclosure. As shown, the exemplary system 600 (e.g., system 100) differs from the system 400 in that the system 600 also includes a delay circuit 610 connected between the clock signal source 210c and the clock tree 210e, introduces a propagation delay to the clock signal (C1), and generates a delayed version of the clock signal (C1). For example, the delay circuit 610 emulates the propagation delays of the clock signal (C1) sender 210g, the interconnect 230, and the clock signal (C2) receiver 220a. In this exemplary embodiment, the delay circuit 610 includes one or more inverters and / or one or more buffer circuits. In other embodiments, various configurations of the delay circuit 610 are contemplated. Figure 6

[0054] In embodiments, the data signal (D4) receiver 210i omits the register circuit 210i”. In such embodiments, the flip-flop circuit 210i’ can be replaced by a demultiplexer.

[0055] In exemplary operation, the data signal (D1) processor 210a generates the data signal (D1), while the clock signal (C1) source 210c generates the clock signal (C1). In response to the clock signal (C1), the data signal (D1) sender 210f sends the data signal (D1) as the data signal (D2) to the semiconductor chip 220. Now, the clock signal (C1) sender 210g sends the clock signal (C1) as the clock signal (C2) to the semiconductor chip 220.

[0056] ​Subsequently, the data signal (D2) receiver 220e receives the data signal (D2) in response to the clock signal (C2). Then, the data signal (D3) processor 220g generates the data signal (D3). The data signal transmitter 220h transmits the data signal (D3) as the data signal (D4) to the semiconductor chip 210 in response to the clock signal (C2). At this time, the delay circuit 610 generates a delayed version of the clock signal (C1). The data signal receiver 210i receives the data signal (D4) in response to the clock signal (C1) and the delayed version of the clock signal (C1). Thereafter, the data signal (D4) processor 210b processes the data signal (D4).

[0057] As can be seen from the above description, since the delay circuit 610 emulates the propagation delay introduced by the clock signal (C1) transmitter 210g, the interconnect 230, and the clock signal (C2) receiver 220a, the propagation delay introduced by the delay circuit 610 is substantially equal to the sum of the propagation delays caused by these components 210g, 230, 220a. As a result, the time at which the clock signal (C2) reaches the data signal (D3) transmitter 220h is substantially the same as the time at which the delayed version of the clock signal (C1) reaches the data signal (D4) receiver 210i. This synchronization facilitates stable data communication between the semiconductor chips 210, 220. In some embodiments, the clock signal (C1) reaches the data signal (D1) transmitter 210f substantially simultaneously with the delayed version of the clock signal (C1) reaching the data signal (D4) receiver 210i.

[0058] In other embodiments, various combinations of the semiconductor chips 210, 220 of the systems 200-600 are contemplated. For example, Figure 7 is a circuit / block diagram of another exemplary system 700 according to embodiments of the present disclosure. As Figure 7 shown, the exemplary system 700 (e.g., system 100) combines the semiconductor chip 210 from the system 300 with the semiconductor chip 220 from the system 200.

[0059] Since the operations of the semiconductor chips 210, 220 of the system 700 are similar to the operations described above with respect to the semiconductor chips 210, 220 of the systems 200, 300, for the sake of brevity, they will not be repeated here.

[0060] Figure 8 is a flowchart of an exemplary method 800 of data communication between semiconductor chips according to embodiments of the present disclosure. For ease of understanding, further reference is made to Figures 1-7 the exemplary system 700 described above with respect to Figures 1-7The method 800 can be implemented in any suitable hardware, software, firmware, or combination thereof. In embodiments, the method 800 can be implemented by a system including a first semiconductor chip and a second semiconductor chip. The first semiconductor chip can include a data signal (Dl) processor, a clock signal (Cl) source, a data signal (Dl) transmitter, and a clock signal (Cl) transmitter. The second semiconductor chip can include a data signal (D2) receiver, a data signal (D3) processor, a data signal (D3) transmitter, and a data signal (D4) receiver. The data signal (Dl) processor can generate a data signal (Dl). The clock signal (Cl) source can generate a clock signal (Cl). The data signal (Dl) transmitter can transmit the data signal (Dl) as a data signal (D2) to the second semiconductor chip in response to the clock signal (Cl). The clock signal (Cl) transmitter can transmit the clock signal (Cl) as a clock signal (C2) to the second semiconductor chip. The data signal (D2) receiver can receive the data signal (D2) in response to the clock signal (C2). The data signal (D3) processor can generate a data signal (D3). The data signal (D3) transmitter can transmit the data signal (D3) as a data signal (D4) to the first semiconductor chip in response to the clock signal (C2). The data signal (D4) receiver can receive the data signal (D4) in response to the clock signal (Cl) and a delayed version of the clock signal (Cl). The delayed version of the clock signal (Cl) can be generated by a delay circuit and selected by a multiplexer as an input / output of the multiplexer in response to a control signal.

[0061] In operation 810, the data signal (Dl) processor 210a generates a data signal (Dl), and the clock signal (Cl) source 210c generates a clock signal (Cl). In operation 820, the data signal (Dl) transmitter 210f transmits the data signal (Dl) as a data signal (D2) to the semiconductor chip 220 in response to the clock signal (Cl). At this time, in operation 830, the clock signal (Cl) transmitter 210g transmits the clock signal (Cl) as a clock signal (C2) to the semiconductor chip 220.

[0062] Subsequently, in operation 840, the data signal (D2) receiver 220e receives the data signal (D2) in response to the clock signal (C2). In operation 850, the data signal (D3) processor 220g generates a data signal (D3). In operation 860, the data signal (D3) transmitter 220h transmits the data signal (D3) as a data signal (D4) to the semiconductor chip 210 in response to the clock signal (C2).

[0063] Meanwhile, in operation 870, the delay circuit 310, 510 generates a delayed version of the clock signal (Cl), and the multiplexer 320, 530 selects the delayed version of the clock signal (Cl) as its input / output in response to a control signal. Thereafter, in operation 880, the data signal (D4) receiver 210i receives the data signal (D4) in response to the clock signal (Cl) and the delayed version of the clock signal (Cl).

[0064] In embodiments, a system includes a plurality of semiconductor chips stacked with each other, and includes first and second semiconductor chips. The first semiconductor chip includes a clock signal generation circuit, a transmission circuit, and a reception circuit. The clock signal generation circuit generates a clock signal and a delayed version of the clock signal. The transmission circuit transmits a first data signal in response to the clock signal. The reception circuit receives a second data signal in response to the delayed version of the clock signal. The reception circuit receives the delayed version of the clock signal at the same time as the transmission circuit receives the clock signal.

[0065] An embodiment of the present application provides a system comprising: a plurality of semiconductor chips stacked on each other, including a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip comprises: a clock signal generation circuit configured to generate a first clock signal and a delayed version of the first clock signal; a transmitting circuit configured to transmit a first data signal in response to the first clock signal; and a receiving circuit configured to receive a second data signal in response to the delayed version of the first clock signal, wherein the receiving circuit is configured to receive the delayed version of the first clock signal substantially simultaneously with the transmitting circuit being configured to receive the first clock signal.

[0066] In some embodiments, the clock signal generation circuit comprises: a clock signal source configured to generate the first clock signal; a clock signal transmitter configured to transmit the clock signal to the second semiconductor chip; and a delay circuit connected between the clock signal source and the receiving circuit, and the delay circuit is configured to generate the delayed version of the first clock signal.

[0067] In some embodiments, the receiving circuit comprises: a clock signal receiver configured to receive a fourth clock signal; a data signal receiver configured to receive a fourth data signal; and a multiplexer having a first input connected to the clock signal generation circuit, a second input connected to the clock signal receiver, and an output connected to the data signal receiver, and the multiplexer is configured to select one of the delayed version of the first clock signal and the fourth clock signal and forward the selected one of the delayed version of the first clock signal and the fourth clock signal to the data signal receiver.

[0068] In some embodiments, the receiving circuit comprises: a data signal receiver configured to receive a fourth data signal; and a multiplexer connected between the clock signal generation circuit and the data signal receiver, and the multiplexer is configured to select the delayed version of the first clock signal and forward the selected delayed version of the first clock signal to the data signal receiver.

[0069] In some embodiments, the receiving circuit comprises: a data signal receiver configured to receive a fourth data signal; and a delay circuit connected between the clock signal generation circuit and the data signal receiver, and the delay circuit is configured to generate the delayed version of the first clock signal.

[0070] In some embodiments, the clock signal generation circuit comprises a delay circuit in the form of one or more inverters and / or one or more buffer circuits.

[0071] In some embodiments, the sending circuit includes a data signal processor configured to generate the data signal, a clock signal source configured to generate the clock signal, a data signal sender configured to send the data signal to the second semiconductor chip in response to the clock signal, and a clock signal sender configured to send the clock signal to the second semiconductor chip.

[0072] In some embodiments, the second semiconductor chip includes a clock signal receiver configured to receive a second clock signal, a clock signal source configured to generate a third clock signal, a data signal receiver configured to receive a second data signal in response to the second clock signal and the third clock signal, a data signal sender configured to send a data signal, a clock signal sender, and a multiplexer having a first input connected to the clock signal receiver, a second input connected to the clock signal source, and an output connected to a node between the data signal sender and the clock signal sender, and the multiplexer is configured to select one of the second clock signal and the third clock signal and forward the selected one of the second clock signal and the third clock signal to the data signal sender and the clock signal sender.

[0073] In some embodiments, the second semiconductor chip includes a clock signal receiver configured to receive a second clock signal, a data signal receiver configured to receive a second data signal in response to the second clock signal, and a data signal sender configured to send a data signal in response to the second clock signal.

[0074] In some embodiments, the second semiconductor chip includes a clock signal receiver configured to receive a second clock signal, a data signal receiver configured to receive a second data signal in response to the second clock signal, and a data signal processor, a data signal sender configured to send a data signal, and a multiplexer connected between the clock signal receiver and the data signal sender, and the multiplexer is configured to select the second clock signal and forward the selected second clock signal to the data signal sender.

[0075] In some embodiments, the second semiconductor chip includes a data signal processor configured to generate the data signal, a clock signal source configured to generate the clock signal, a data signal sender configured to send the data signal to the second semiconductor chip in response to the clock signal, and a data signal processor configured to process the data signal.

[0076] In another embodiment, a semiconductor chip includes a clock signal source, a data signal transmitter, a clock signal transmitter, and a data signal receiver. The clock signal source generates a first clock signal. The data signal transmitter transmits a first data signal in response to the first clock signal. The clock signal transmitter transmits the first clock signal. The data signal receiver receives a second data signal in response to a delayed version of the first clock signal or a second clock signal.

[0077] In some embodiments, the semiconductor chip further includes a delay circuit connected between the clock signal source and the data signal receiver, the delay circuit configured to generate a delayed version of the first clock signal, wherein the data signal receiver is configured to receive the second data signal in response to the delayed version of the first clock signal.

[0078] In some embodiments, the semiconductor chip further includes a delay circuit connected to the clock signal source and configured to generate a delayed version of the first clock signal, and a multiplexer connected between the delay circuit and the data signal receiver, and the multiplexer is configured to select the delayed version of the first clock signal and forward the selected delayed version of the first clock signal to the data signal receiver, wherein the data signal receiver is configured to receive the second data signal in response to the delayed version of the first clock signal.

[0079] In some embodiments, the semiconductor chip further includes a delay circuit connected to the clock signal source and configured to generate a delayed version of the first clock signal, a clock signal receiver, and a multiplexer having a first input connected to the delay circuit, a second input connected to the clock signal receiver, and an output connected to the data signal receiver, and the multiplexer is configured to select one of the delayed version of the first clock signal and the clock signal and forward the selected one of the delayed version of the first clock signal and the clock signal to the data signal receiver.

[0080] In another embodiment, a data communication method includes generating, by a first semiconductor chip, a first clock signal, transmitting, in response to the first clock signal, a first data signal as a second data signal to a second semiconductor chip, transmitting the first clock signal as a second clock signal to the second semiconductor chip, receiving, by the second semiconductor chip, the second clock signal, transmitting, in response to the second clock signal, a third data signal as a fourth data signal to the first semiconductor chip, and receiving, by the first semiconductor chip, the fourth data signal in response to a delayed version of the first clock signal.

[0081] In some embodiments, the data communication method further includes receiving the delayed version of the first clock signal by a data signal receiver of the first semiconductor chip substantially simultaneously with receiving the second clock signal by a data signal receiver of the second semiconductor chip.

[0082] In some embodiments, the data communication method further includes generating the delayed version of the clock signal by simulating propagation delays of the first semiconductor chip and the second semiconductor chip.

[0083] In some embodiments, the data communication method further includes selecting, by a multiplexer of the first semiconductor chip, the delayed version of the first clock signal and forwarding the delayed version of the first clock signal to a data signal receiver of the first semiconductor chip.

[0084] In some embodiments, the data communication method further includes introducing a propagation delay to the first clock signal, the propagation delay being substantially equal to a sum of propagation delays introduced by the first semiconductor chip and the second semiconductor chip.

[0085] The components of several embodiments have been discussed above so that those skilled in the art can better understand the various embodiments of the present invention. It will be appreciated by those skilled in the art that the present invention can be easily used as a basis to design or modify other processes and structures to achieve the same purpose and / or advantages as the embodiments described herein. It will also be appreciated by those skilled in the art that these equivalent structures do not depart from the spirit and scope of the present invention, and that various variations, replacements, and changes may be made without departing from the spirit and scope of the present invention.

Claims

1. A system for data communication, comprising: A plurality of semiconductor chips stacked on each other include a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip includes: a clock signal generating circuit configured to generate a first clock signal and a delayed version of the first clock signal; a transmitting circuit configured to transmit a first data signal in response to the first clock signal; and A receiving circuit is configured to receive a second data signal in response to the delayed version of the first clock signal, wherein the receiving circuit is configured to receive the delayed version of the first clock signal substantially simultaneously with the transmitting circuit being configured to receive the first clock signal.

2. The system for data communication according to claim 1, wherein: The clock signal generating circuit comprises: a clock signal source configured to generate the first clock signal; a clock signal transmitter configured to transmit the clock signal to the second semiconductor chip; and A delay circuit is connected between the clock signal source and the receiving circuit, and the delay circuit is configured to generate the delayed version of the first clock signal.

3. The system for data communication according to claim 1, wherein: The receiving circuit includes: a clock signal receiver configured to receive a fourth clock signal; a data signal receiver configured to receive a fourth data signal; and a multiplexer having a first input connected to the clock signal generating circuit, a second input connected to the clock signal receiver, and an output connected to the data signal receiver, the multiplexer being configured to select one of the delayed version of the first clock signal and the fourth clock signal and forward the selected one of the delayed version of the first clock signal and the fourth clock signal to the data signal receiver.

4. The system for data communication according to claim 1, wherein: The receiving circuit includes: a data signal receiver configured to receive a fourth data signal; and A multiplexer is connected between the clock signal generating circuit and the data signal receiver, and the multiplexer is configured to select the delayed version of the first clock signal and forward the selected delayed version of the first clock signal to the data signal receiver.

5. The system for data communication according to claim 1, wherein: The receiving circuit includes: a data signal receiver configured to receive a fourth data signal; and A delay circuit is connected between the clock signal generating circuit and the data signal receiver, and the delay circuit is configured to generate the delayed version of the first clock signal.

6. The system for data communication according to claim 1, wherein: The clock signal generating circuit includes a delay circuit in the form of one or more inverters and / or one or more buffer circuits.

7. The system for data communication according to claim 1, wherein: The transmitting circuit (110b) comprises: a data signal processor configured to generate the data signal; a clock signal source configured to generate the clock signal; a data signal transmitter configured to transmit the data signal to the second semiconductor chip in response to the clock signal; and A clock signal transmitter is configured to transmit the clock signal to the second semiconductor chip.

8. The system for data communication according to claim 1, wherein: The second semiconductor chip includes: a clock signal receiver configured to receive a second clock signal; a clock signal source configured to generate a third clock signal; a data signal receiver configured to receive a second data signal in response to the second clock signal and the third clock signal; a data signal transmitter configured to transmit a data signal; a clock signal transmitter; and a multiplexer having a first input connected to the clock signal receiver, a second input connected to the clock signal source, and an output connected to a node located between the data signal transmitter and the clock signal transmitter, and the multiplexer is configured to select one of the second clock signal and the third clock signal and forward the selected one of the second clock signal and the third clock signal to the data signal transmitter and the clock signal transmitter.

9. A semiconductor chip comprising: a clock signal source configured to generate a first clock signal; a data signal transmitter configured to transmit a first data signal in response to the first clock signal; a clock signal transmitter, configured to transmit the first clock signal; as well as The data signal receiver is configured to receive a second data signal in response to a delayed version of the first clock signal or a second clock signal.

10. A data communication method, comprising: generating a first clock signal by a first semiconductor chip; sending the first data signal to the second semiconductor chip as a second data signal in response to the first clock signal; sending the first clock signal as a second clock signal to the second semiconductor chip; receiving the second clock signal by the second semiconductor chip; sending a third data signal to the first semiconductor chip as a fourth data signal in response to the second clock signal; as well as The first semiconductor chip receives the fourth data signal in response to a delayed version of the first clock signal.

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