A data processing method, device, apparatus, and storage medium

Abstract

The application provides a data processing method, device and equipment and a storage medium. The method is designed for a memory-computing integrated chip. A first processing mode for simultaneously performing in-memory computing and vector dot multiplication processing on target data in a storage array is designed. Specifically, if the current column input data is the last calculation for the input data, the first target row data is read from the current read address row, and the current column input data and the first target row data are calculated, and the second target row data is written to the current write address row. Since the current write address row is the previous row of the current read address row, the read data and the write data can be processed simultaneously. The application embodiment can improve the data processing efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, in particular, a data processing method and device, equipment and storage medium are provided. BACKGROUND

[0002] At present, the mainstream large language model computing hardware is a general-purpose graphics processing unit (GPGPU), which realizes high-performance computing through a large number of high-parallel computing cores, and realizes general matrix-matrix multiplication (GEMM) acceleration through special computing modules (such as Nvidia Tensor Core), but due to the traditional memory-computing separation architecture of GPGPU and the data-intensive application of neural network inference, the memory instruction becomes the performance and energy efficiency bottleneck of the system. To solve the above problems, the in-memory computing design integrates the logic unit into the storage chip, so that part of the computing function can be completed in the storage chip.

[0003] The GEMM calculation in the large model usually adopts dynamic weights, that is, frequent updates of weights are involved. In this scenario, the existing memory is greatly affected by the efficiency of weight update due to its own structure and refresh mode.

[0004] For example, static random access memory (SRAM) has become the most popular storage medium for in-memory computing design due to its high read / write speed and high logic compatibility. However, the storage density of SRAM is low, which cannot be used for large-scale neural networks, and there is a large leakage current under static conditions, resulting in significant static power consumption. In addition, the traditional SRAM only supports a single read / write port, so data reading and matrix calculation cannot be performed simultaneously during weight update, which greatly affects the computing efficiency.

[0005] Embedded dynamic random access memory (eDRAM) usually uses a periodic refresh method for all storage units to maintain data accuracy. This refresh process increases additional delay and energy consumption. In addition, the eDRAM refresh operation monopolizes the memory bandwidth, causing the computing unit to be idle, which affects the weight update efficiency and matrix calculation efficiency of the neural network. SUMMARY

[0006] Therefore, the present application provides a data processing method, device, equipment and storage medium to at least solve the problems in the related art.

[0007] Specifically, the application is realized by the following technical solutions:

[0008] The application provides a data processing method applied to a memory-computing integrated chip, the memory-computing integrated chip comprising a memory array, the memory array having a read bit line and a write bit line, and the read bit line and the write bit line being independent of each other; the memory array is used for storing target data, the target data comprising multiple rows of row data; the method comprises:

[0009] obtaining input data; the input data comprising multiple columns of column input data;

[0010] in response to the memory-computing integrated chip entering a first processing mode, sequentially reading the multiple columns of column input data; the first processing mode refers to a mode of simultaneously performing in-memory computing and data processing;

[0011] reading first target row data from a current read address row through the read bit line, and performing vector dot multiplication on the current column input data and the first target row data to obtain an output result; and

[0012] writing second target row data into a current write address row through the write bit line; the current write address row being a previous row of the current read address row;

[0013] incrementing the current read address row and the current write address row by one, in a case where the current read address row is not a terminal read address row, returning to the step of reading target row data from the current read address row through the read bit line, until the current read address row is the terminal read address row, resetting the current read address row to zero, and updating the input data;

[0014] in a case where the current write address row is a terminal write address row, returning to the step of sequentially reading the multiple columns of column input data, until the input data stops being updated.

[0015] In some embodiments, the first processing mode comprises a first strategy; the memory-computing integrated chip comprises a first data input interface; after the memory-computing integrated chip enters the first processing mode, the method further comprises:

[0016] for the current column input data, determining whether vector dot multiplication of the current column input data is a last vector dot multiplication for the input data, and if so, processing the target data by using the first strategy;

[0017] in the process of processing the target data by using the first strategy, the writing of the second target row data into the current write address row through the write bit line comprises:

[0018] acquire external target data through the first data input interface;

[0019] determine second target row data from the external target data, and write the second target row data to a current write address row through the write bit line; the second target row data is different from previously stored data of the current write address row.

[0020] In some embodiments, the first processing mode includes a second strategy, and the memory-compute integrated chip includes a second data input interface; the memory-compute integrated chip is provided with a refresh interval register and a refresh counter; the method further includes:

[0021] if the vector dot product of the current column input data is not the last vector dot product of the input data, reading a current data retention time of the target data after the last refresh from the refresh counter, and reading a refresh interval of the target data from the refresh interval register;

[0022] if the current data retention time is not less than the refresh interval of the target data, and the refresh interval of the target data is less than a single round iteration calculation time, processing the target data by using the second strategy; the single round iteration calculation time refers to a sum of a reading time and a calculation time of the target data, and the calculation time refers to a time consumed by performing vector dot products of each row data in the current column input data and each row data in the target data, respectively;

[0023] in the process of processing the target data by using the second strategy, the writing of the second target row data to the current write address row through the write bit line includes:

[0024] acquiring row data read in a last period from a read cache module through the second data input interface;

[0025] taking the row data read in the last period as the second target row data, and writing the second target row data to the current write address row through the write bit line.

[0026] In some embodiments, the memory-compute integrated chip is provided with a valid time register, and the valid time register is used to record a valid time of the target data; the valid time refers to a time required for completing calculation of the target data; the memory-compute integrated chip enters the first processing mode by the following method, including:

[0027] reading the valid time of the target data from the valid time register;

[0028] If the valid time of the target data is not less than the refresh interval of the target data and the refresh interval of the target data is less than the single round iteration calculation time, it is determined that the memory-computing integrated chip enters the first processing mode.

[0029] In some embodiments, the method further comprises:

[0030] If the valid time of the target data is greater than the refresh interval of the target data and the refresh interval of the target data is less than the single round iteration calculation time, it is determined that the memory-computing integrated chip enters a second processing mode; the second processing mode refers to a mode in which the target data is refreshed and the target data is not calculated;

[0031] In the second processing mode, the multiple column input data are read in sequence, if the current data retention time is not less than the refresh interval of the target data, first target row data of a current read address row are read from the memory array through the read bit line, and the read first target row data are written back to the current read address row through the write bit line;

[0032] In the case where the current data retention time is less than the refresh interval of the target data, first target row data are read from the current read address row through the read bit line, the current column input data and the first target row data are vector multiplied to obtain an output result, and the current read address row is incremented by one;

[0033] Returning to the step of reading target row data from the current read address row through the read bit line, until the current read address row is a terminal read address row, resetting the current read address row to zero, and updating the input data.

[0034] In some embodiments, the method further comprises:

[0035] If the valid time of the target data is less than the refresh interval of the target data, it is determined that the memory-computing integrated chip enters a third processing mode; the third processing mode refers to a mode in which the target data is updated and the target data is not refreshed;

[0036] In the third processing mode, the multiple column input data are read in sequence, if the vector multiplication of the current column input data is the last vector multiplication for the input data, first target row data are read from a current read address row through the read bit line, and the current column input data and the first target row data are vector multiplied to obtain an output result;

[0037] determining second target row data from the external target data, and writing the second target row data to a current write address row through the write bit line; the second target row data is different from previously stored data of the current write address row;

[0038] incrementing the current read address row and the current write address row by one, in a case that the current read address row is not a terminal read address row, returning to the step of reading target row data from the current read address row through the read bit line until the current read address row is the terminal read address row, resetting the current read address row to zero, and updating the input data;

[0039] in a case that the current write address row is a terminal write address row, returning to the step of sequentially reading the multiple-column input data until the input data stops updating.

[0040] In some embodiments, the method further comprises:

[0041] in a case that the vector dot product of the current column input data is not the last vector dot product for the input data, reading first target row data from the current read address row through the read bit line, performing a vector dot product of the current column input data and the first target row data to obtain an output result, and incrementing the current read address row by one;

[0042] in a case that the current read address row is not a terminal read address row, returning to the step of reading target row data from the current read address row through the read bit line until the current read address row is the terminal read address row, resetting the current read address row to zero, and returning to the step of sequentially reading the multiple-column input data until the vector dot product of the current column input data is the last vector dot product for the input data.

[0043] In some embodiments, the in-memory computing chip is provided with an iteration counter for recording a current iteration number of iteration calculation for the input data; whether the vector dot product of the current column input data is the last vector dot product for the input data is determined by:

[0044] obtaining a total column number of the input data;

[0045] reading the current iteration number from the iteration counter, and in a case that the current iteration number is the total column number of the input data, determining that the vector dot product of the current column input data is the last vector dot product for the input data.

[0046] In some embodiments, before the in-memory computing chip enters the first processing mode, the method further comprises:

[0047] in response to power-on of the memory-compute chip, controlling the memory-compute chip to enter an initialization mode; the initialization mode refers to a mode of initialization of the memory array, refresh counter, iteration counter, refresh interval register, and valid time register and no calculation of data in the memory array;

[0048] in the initialization mode, obtaining the target data, writing the target data into the memory array through the write bit line; and configuring data for the refresh interval register and the valid time register, and clearing the iteration counter and the refresh counter.

[0049] In some embodiments, the target data is weight data of a neural network.

[0050] The application also provides a memory-compute chip, comprising a memory array, a computing module, a control module, a read cache module, and a write cache module, the memory array has a read bit line and a write bit line, and the read bit line and the write bit line are independent of each other; the memory array is used for storing target data;

[0051] The computing module is used for obtaining input data, the input data comprising multiple column input data;

[0052] The control module is connected with the computing module, and is used for, in response to the memory-compute chip entering a first processing mode, controlling the computing module to read the multiple column input data in turn; the first processing mode refers to a mode of simultaneous in-memory computing and data processing;

[0053] The read cache module is used for reading first target row data from a current read address row through the read bit line, and sending the first target row data to the computing module;

[0054] The computing module is also used for vector dot multiplication of the current column input data and the first target row data to obtain an output result; and

[0055] The write cache module is used for writing second target row data to a current write address row through the write bit line; the current write address row is a previous row of the current read address row;

[0056] The control module is also used for adding one to the current read address row and the current write address row respectively, and in the case that the current read address row is not a terminal read address row, returning to execute the step of reading first target row data from a current read address row through the read bit line by the read cache module, and sending the first target row data to the computing module, until the current read address row is a terminal read address row, resetting the current read address row to zero, and updating the input data;

[0057] The control module is further configured to return to performing the step of controlling the calculation module to sequentially read the column input data of the plurality of columns until the input data stops updating, in the case that the current write address behavior terminates the write address row.

[0058] The technical scheme provided by the embodiment of the present application can include the following beneficial effects:

[0059] In the embodiment of the present application, since the storage structure that can support reading and writing at the same time is adopted, when the vector dot product calculation of the current column input data is the last vector dot product calculation of the input data, the vector dot product of the current column input data and the first target row data read at present is calculated to obtain the output result, and the second target row data is written to the current write address row (the row before the current read address row), which solves the problem that the writing data and the data reading and calculation cannot be performed at the same time in the in-memory computing design based on the traditional single-port storage, and the efficiency of the calculation can be improved.

[0060] Further, the above method is applied to the memory-computing integrated chip, and the processing performance of the chip can be improved.

[0061] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0062] Figure 1 FIG. 1 is a structural schematic diagram of a memory-computing integrated chip according to an example embodiment of the present application;

[0063] Figure 2 FIG. 2 is a structural schematic diagram of a memory unit according to an example embodiment of the present application;

[0064] Figure 3 FIG. 3 is a calculation schematic diagram of a calculation module according to an example embodiment of the present application;

[0065] Figure 4 FIG. 4 is a schematic diagram of matrix operation according to an example embodiment of the present application;

[0066] Figure 5 FIG. 5 is a circuit diagram of a write decoding driving module according to an example embodiment of the present application;

[0067] Figure 6 FIG. 6 is a flowchart of a data processing method according to an example embodiment of the present application;

[0068] FIG. 7 (A) is a flowchart of another data processing method according to an example embodiment of the present application;

[0069] FIG. 7(B) is a flowchart illustrating a second strategy for processing target data according to an example embodiment of the present application;

[0070] Figure 8 FIG. 1 is a hardware structure diagram of a computer device according to an example embodiment of the present application. DETAILED DESCRIPTION

[0071] The example embodiments will be described in detail with reference to the drawings, wherein like reference numerals refer to like elements throughout. The following detailed description is not intended to restrict the examples to any specific embodiments unless otherwise specifically stated. Rather, the following description is presented as an example of the described aspects of the examples.

[0072] The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in the present application and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or," as used herein, refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0073] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various information, the information should not be limited by these terms. These terms are used only to distinguish one piece of information from another. For example, a first information could be termed a second information, and, similarly, a second information could be termed a first information without departing from the scope of the present application. As used herein, the term "if' can be construed to mean "when" or "in response to determining" or "in response to a determination" depending on the context.

[0074] The relevant technical terms related to the present application will be introduced first as follows:

[0075] General Matrix-Matrix Multiplication, GEMM;

[0076] General-Purpose Graphical Processing Unit, GPGPU;

[0077] Static Random Access Memory, SRAM;

[0078] Embedded Dynamic Random Access Memory

[0079] RBL: Read Bit-line

[0080] RWL: Read Word-line

[0081] WBL: Write Bit-line

[0082] WWL: Write Word-line

[0083] Currently, the mainstream large language model computing hardware is general-purpose computing on graphics processing (GPGPU), which realizes high-performance computing through large-scale high-parallel computing cores and realizes general matrix-matrix multiplication (GEMM) acceleration through special computing modules (such as Nvidia Tensor Core), but since GPGPU still adopts the traditional memory-computing separation architecture and neural network inference is a data-intensive application, memory access instructions become the performance and energy efficiency bottleneck of the system. To solve the above problems, in-memory computing design integrates logic units into the memory chip, so that part of the computing function can be completed in the memory chip.

[0084] The GEMM calculation in the large model usually adopts dynamic weights, that is, it involves frequent updating of weights. In this scenario, the existing memory is greatly affected by the efficiency of weight update due to the limitations of its own structure and refresh method.

[0085] For example, static random access memory (SRAM) has become the most mainstream storage medium for in-memory computing design due to its high read / write speed and high logic compatibility, but the storage density of SRAM is low and cannot be used for large-scale neural networks, and there is a large leakage current under static conditions, resulting in significant static power consumption. In addition, the traditional SRAM only supports a single read / write port, so data reading and matrix calculation cannot be performed simultaneously during weight update, which greatly affects the computing efficiency.

[0086] Embedded Dynamic Random Access Memory (eDRAM) has high cell density and separate read and write ports, but generally uses a periodic refresh of all memory cells to maintain data accuracy, which increases additional delay and energy consumption, in addition, eDRAM refresh operations monopolize memory bandwidth, causing computing units to be idle, thereby affecting the efficiency of neural network weight updates and matrix calculations.

[0087] Based on the above research, the present application provides a data processing method, which is applied to a memory-computing integrated chip, the memory-computing integrated chip comprising a memory array, the memory array having a read bit line and a write bit line, and the read bit line and the write bit line being independent of each other; the memory array is used for storing target data, the target data comprising multiple rows of row data; specifically, the method acquires input data; the input data comprises multiple columns of column input data; in response to the memory-computing integrated chip entering a first processing mode, the multiple columns of column input data are sequentially read; the first processing mode refers to a mode of simultaneously performing in-memory computing and data processing; first target row data is read from a current read address row through the read bit line, the current column input data is vector dot multiplied with the first target row data to obtain an output result; and second target row data is written to a current write address row through the write bit line; the current write address row is a previous row of the current read address row; the current read address row and the current write address row are each incremented by one, in a case where the current read address row is not a terminal read address row, returning to the step of reading target row data from the current read address row through the read bit line until the current read address row is the terminal read address row, resetting the current read address row to zero and updating the input data; in a case where the current write address row is a terminal write address row, returning to the step of sequentially reading the multiple columns of column input data until the input data stops updating.

[0088] In the embodiments of the present application, data processing and in-memory computing can be performed simultaneously, specifically, when the vector dot multiplication calculation of the current column input data is the last vector dot multiplication calculation of the input data, the current column input data is vector dot multiplied with the first target row data read at present to obtain an output result, and the second target row data is written to the current write address row (a previous row of the current read address row) at the same time, solving the technical problems of related art that SRAM only supports single port, resulting in that writing data and calculation cannot be performed simultaneously, and eDRAM periodic refresh and refresh operation monopolizing memory bandwidth, which can improve the efficiency of calculation, save data waiting time, and thus improve the efficiency of data processing.

[0089] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

[0090] Please refer to the drawings of the present application Figure 1 A structure diagram of a memory-compute integrated chip is shown in an exemplary embodiment of the present application, as shown in Figure 1 The memory-compute integrated chip 100 includes a memory array 10, a compute module 20, a decode driving module 30, a control module 40, a read cache module 50, and a write cache module 60, and wherein the decode driving module 30 includes a read decode driving module 31 and a write decode driving module 32, and the memory array 10 includes a plurality of memory rows, and the memory array is used to store target data (in the neural network scenario, the target data is the weight data of the neural network), wherein the target data includes a plurality of row data, and each row of row data is stored in a corresponding memory row.

[0091] Each memory row includes a plurality of memory cells 11, and each memory row corresponds to a read word line (RWL) 12 (including RWL0, RWL1, … RWL15), a write word line (WWL) 13 (including WWL0, WWL1, … WWL15), a read bit line (RBL) 14 (including RBL0, RBL1, … RBL127), and a write bit line (WBL) 15 (including WBL0, WBL1, … WBL127). Please refer to Figure 2 A structure diagram of a memory cell is shown in an exemplary embodiment of the present application. As shown in Figure 2 The memory cell is a three-transistor (3T) structure, and each memory cell has a read word line RWL, a write word line WWL, a read bit line RBL, and a write bit line WBL.

[0092] The control module 40 is connected to the decode driving module 30, the read cache module 50, the write cache module 60, and the compute module 20, the read decode driving module 31 is connected to the memory array 10 through the read word line 12, the write decode driving module 32 is connected to the memory array 10 through the write word line 13, the read cache module 50 is connected to the memory array 10 through the read bit line 14 and connected to the compute module 20, and the write cache module 60 is connected to the memory array 10 through the write bit line 15, wherein the read bit line 14 and the write bit line 15 are independent of each other.

[0093] The decoding driving module 30 inputs a signal as a read address line or a write address line, the read address line is denoted as raddr, and the write address line is denoted as waddr. In addition, there are enable signals ren and wen. If the enable signal ren is 0, the electrical level of all read word lines corresponding to the read address line raddr is low. If the enable signal wen is 0, the electrical level of all write word lines corresponding to the write address line is low. When the enable signal ren is 1, the electrical level of the read word line RWL corresponding to the read address line is pulled high. When the enable signal wen is 1, the electrical level of the write word line WWL corresponding to the write address line is pulled high.

[0094] The write cache module 60 further has a first data input interface (not shown in the figure) and a second data input interface (not shown in the figure). The second data input interface is connected to the read cache module 50. The write cache module 60 can obtain external target data (in the neural network scenario, the external target data is new target data (i.e., new weight data)) through the first data input interface, and obtain read cache data from the read cache module 50 through the second data input interface, i.e., the read cache module 50 reads the target row data from the storage array.

[0095] The calculation module 20 has a first calculation data input interface (not shown in the figure) and a second calculation data input interface. The calculation module 20 obtains external input data (i.e., input data) through the first calculation data input interface. The calculation module 20 is further connected to the read cache module 50 and obtains read cache data from the read cache module 50. The calculation module 20 performs vector dot multiplication calculation on the external input data and the read cache data to obtain a calculation result.

[0096] Please refer to Figure 3 , a calculation schematic diagram of a calculation module provided by an example embodiment of the present application. As shown in the figure, Figure 3 , the calculation module 20 includes a multiplication module, an addition tree module, and a shift and accumulation module. In order to simplify the logic, the multiplication module in this example is assumed to perform multiplication calculation operation by bit input. The 7th to 0th bit data of the column input data { , , , } are sequentially multiplied with the read target row data { , , … }. In actual design, booth encoding and other methods can also be used to accelerate calculation. The partial product data generated by multiplication is transmitted to the addition tree module to obtain a partial sum. The partial sum data is transmitted to the shift and accumulation module to obtain the final output through shift and accumulation in each period.

[0097] In some embodiments, the storage-computing integrated chip 100 is further provided with a refresh interval register, a valid time register, an iteration counter and a refresh counter (not shown in the figure).

[0098] The refresh interval register is used to record the refresh interval of the target data.

[0099] The valid time register is used to record the valid time of the target data, where the valid time refers to the time required for the target data to complete the calculation, which can be obtained by multiplying the single iteration calculation time by the total number of columns of the input data.

[0100] The iteration counter is used to record the current iteration number of the iteration calculation for the input data. As known from the foregoing, when the target data and the input data are subjected to matrix calculation, it is actually a multiply-accumulate operation. Therefore, for each column of input data, multiply-accumulate operation needs to be performed with each row of data in the target data. For each column of input data, after the multiply-accumulate operation is completed between the column of input data and each row of data, it is considered that one iteration calculation is completed, at which time the iteration counter is incremented by one. For example, if the input data includes 10 columns, after the first column and all the row data complete the multiply-accumulate operation, the iteration counter is incremented by one. After the second column and all the row data complete the multiply-accumulate operation, the iteration counter is incremented by one again (to 2), and so on, until the multiply-accumulate operation is completed for all the 10 columns of input data, and the iteration counter is incremented to 10.

[0101] The refresh counter is used to record the data retention time after the last refresh is completed. The refresh counter is incremented by one at each clock cycle and is cleared when the refresh is completed or the weight data is updated.

[0102] In the present embodiment, the storage-computing integrated chip 100 can be an embedded dynamic random access memory (eDRAM). Specifically, it can be a 2T-eDRAM, a 3T-eDRAM or a 4T-eDRAM. The unit storage density of such a chip is higher than that of an SRAM, and the static power consumption is relatively small.

[0103] In the model training scenario, the calculation between the model input data and the model weight data is usually involved. Therefore, the above model weight data is usually stored in the storage array 10. The calculation module 20 obtains the input data through the first calculation data input interface and performs operation on the input data and the model weight data. Please refer to Figure 4 , which is a schematic diagram of matrix operation according to an embodiment of the present application. As shown in Figure 4 , in the neural network GEMM calculation, the input data is denoted as , and the weight data is denoted as For each column of input data in the input data, the respective row of data in the weight data is subjected to a vector dot product operation.

[0104] Please refer again to Figure 1 The storage array 10 has a size of 128x16, and the weight data (also referred to as a weight matrix) to be calculated is stored in the storage array 10, wherein the matrices in the same row of the weight matrix are stored in the same storage row, as shown in Figure 1 The weight data is a 16*16 matrix, and each cell stores a weight value. Since the data type of each weight value is INT8, the size of the storage array 10 is 128*16. Thus, the weight data The first k bit of the weight data .

[0105] In actual design, in order to ensure the read and write speed of the storage array, the storage array 10 can be split into multiple sub-arrays (such as 4 32x16 sub-arrays), but the weight storage mode remains the same, and the sub-arrays share a decoding and driving module.

[0106] In addition, in the GEMM scenario in the large model algorithm, dynamic weights are used, so frequent updates of the weights are involved, and both the input data and the weight data need to be updated.

[0107] The data processing method in the present application will be described below in combination with Figure 1 .

[0108] In the present application, the control module 40 is connected to an upper computer (not shown in the figure). The upper computer sends a control instruction to the control module 40 in the storage and computing integrated chip 100. The control instruction can be an instruction for powering on the storage and computing integrated chip 100. The upper computer can be a computer, a central processing unit (CPU), etc., which is not limited here.

[0109] Optionally, the upper computer is also connected to the write cache module 60, for sending target data to the write cache module 60.

[0110] Optionally, the upper computer is also connected to the computing module 20 of the storage and computing integrated chip 100, for sending input data to the computing module 20.

[0111] In this embodiment, the storage-computing integrated chip 100 has a first processing mode, a second processing mode, a third processing mode, and an initialization mode. The first processing mode refers to a mode in which in-memory computing and data processing are performed simultaneously, specifically, a mode in which vector dot product calculation is performed on current column input data and first target row data read from a current read address row, and second target row data is written into a current write address row (the current write address row is a row preceding the current read address row). In this mode, the data in the current write address row is updated and written, and the data in the current write address row is refreshed and written.

[0112] The second processing mode refers to a mode in which target data is refreshed without being calculated.

[0113] The third processing mode refers to a mode in which target data is updated without being refreshed.

[0114] The initialization mode refers to a mode in which target data in the storage array is initialized, the refresh counter, the iteration counter, the refresh interval register, and the valid time register are initialized, and the data in the storage array is not calculated, but only refreshed.

[0115] Specifically, after the control module 40 receives the control instruction of the host computer, the storage-computing integrated chip 100 is first controlled to enter the initialization mode. In the initialization mode, the host computer sends target data to the write cache module 60. After the write cache module 60 obtains the target data, the target data is written into the storage array 10 through the write bit line 15, the refresh interval register and the valid time register are configured with data, and the iteration counter and the refresh counter are emptied (i.e., the iteration counter and the refresh counter are configured to zero).

[0116] Further, the calculation module 20 obtains input data from the host computer, wherein the input data includes multiple column input data, as shown in formula (1):

[0117] (1)

[0118] wherein, , … are column input data.

[0119] After the storage-computing integrated chip 100 completes initialization, the control module 40 reads the valid time of the target data from the valid time register and reads the refresh interval of the target data from the refresh interval register. As known from the foregoing, the valid time refers to the time required for the target data to complete calculation, and the refresh interval register is used to record the refresh interval. If the control module 40 detects that the valid time of the target data is less than the refresh interval of the target data, it indicates that the target data does not need to be refreshed when the calculation is completed, and only needs to be updated. At this time, the control module 40 can control the storage-computing integrated chip 100 to enter the third processing mode.

[0120] In the third processing mode, the plurality of column input data of the input data are sequentially read. If the vector dot product of the current column input data is the last vector dot product of the input data, it indicates that the target data needs to be updated. Specifically, the first target row data is read from the current read address row through the read bit line, and the vector dot product of the current column input data and the first target row data is obtained to obtain the output result.

[0121] At the same time, the second target row data is determined from the external target data, and the second target row data is written to the current write address row through the write bit line. The second target row data is different from the previously stored data of the current write address row, and the current write address row is the previous row of the current read address row. In this way, the wrong row data processing is realized in the third mode.

[0122] After the writing is completed, the current read address row and the current write address row are incremented by one. In the case that the current read address row is not the termination read address row (indicating that the target data is not completely read), it needs to be continuously read, and thus the step of reading the target row data from the current read address row through the read bit line 14 by the read cache module 50 can be returned to continue to control. Until the current read address row is the termination read address row, the current read address row is reset to zero and the input data is updated. It can be understood that in the case that the current read address row is the termination read address row, it indicates that the vector dot product of the current column input data and each row of the target data is completed. Therefore, the current read address row needs to be reset to 0, and the vector dot product of the current column input data is the last vector dot product of the input data, indicating that the input data is also calculated. Therefore, the input data can be updated.

[0123] In the case that the current write address row is the termination write address row, the step of sequentially reading the plurality of column input data is returned to until the input data stops updating.

[0124] Here, if the current write address row is the termination write address row, it indicates that the data writing is completed, and the updated input data can be continuously processed. Therefore, the step of sequentially reading the plurality of column input data is returned to be executed until the input data stops updating, and the third processing mode is exited.

[0125] Optionally, in the third processing mode, if the vector dot product of the current column input data is not the last vector dot product of the input data, it means that there is still other column input data to be calculated, therefore, in this case, only the column input data needs to be calculated, and the target data does not need to be updated. Specifically, if the vector dot product of the current column input data is not the last vector dot product of the input data, the first target row data is read from the current read address row through the read bit line, the vector dot product of the current column input data and the first target row data is calculated to obtain the output result, and the current read address row is incremented by one. Further, in the case where the current read address row is not the termination read address row, the step of reading the target row data from the current read address row through the read bit line is returned to, until the current read address row is the termination read address row. At this time, it means that the calculation of the current column input data is completed, and other column input data needs to be calculated, and the current read address row needs to be reset to zero. The step of sequentially reading the multiple column input data is returned to, so as to read the next column input data, until the vector dot product of the current column input data is the last vector dot product of the input data, and the scheme of the error row update described in the foregoing embodiment is executed.

[0126] In some other embodiments, if the valid time of the target data is not less than the refresh interval of the target data, and the refresh interval of the target data is greater than the single round iteration calculation time, since the single round iteration calculation time is the sum of the reading and calculation time of the single column input data and all target row data, the data refresh of all target data rows can be completed at the same time as the row-by-row calculation is completed. In this case, the control module 40 controls the storage-computing integrated chip 100 to enter the first processing mode.

[0127] Further, in response to the storage-computing integrated chip 100 entering the first processing mode, the control module 40 controls the computing module 20 to sequentially read the multiple column input data, that is, the computing module 20 reads one column input data at a time. Then, the control module 40 controls the read cache module 50 to read the first target row data from the current read address row through the read bit line 14, and calculates the vector dot product of the current column input data and the first target row data to obtain the output result. Meanwhile, the control module 40 controls the write cache module 60 to write the second target row data to the current write address row through the write bit line 15, where the current write address row is the previous row of the current read address row.

[0128] Here, it can be understood that, since the current write address row is the previous row of the current read address row, the "error row processing" method is used, for example, the first target row data of the 8th row is read, and the vector dot product of the current column data and the first target row data of the 8th row is calculated, and the second target row data is written to the 7th row. In this way, the vector dot product and the data writing can be performed at the same time without interfering with each other.

[0129] Further, the control module 40 is further configured to add one to the current read address row and the current write address row respectively, and if the current read address row is not the end read address row, the control module 40 controls the read buffer module 50 to continue reading the target row data from the current read address row and performing the vector dot product calculation through the read bit line 14 until the current read address row is the end read address row, where the end read address row is the last row of the target data. It can be understood that if the current read address row is the end read address row, it means that there is no next address row to be read, and thus the current read address row can be reset to zero and the input data can be updated (i.e., the calculation for the updated input data needs to be prepared), and the iteration counter and the flush counter can be cleared.

[0130] Since the above-mentioned scheme is a "row error processing", when the current read address row is the end read address row, the current write address row can not be the end write address row, where the end write address row is the last row of the target data. Therefore, after the current read address row is reset and the input data is updated, the control module needs to determine whether the current write address row is the end write address row. In the case where the current write address row is the end write address row, it means that the updated input data needs to be processed accordingly, i.e., the control module 40 controls the calculation module 20 to perform the step of sequentially reading the multiple columns of input data of the updated input data until the input data stops updating, and exits the first processing mode.

[0131] According to the foregoing, the first processing mode in the embodiment includes a first strategy and a second strategy, where the first strategy is used to update the target data, and the second strategy is used to flush the target data. The above-mentioned strategies will be described in detail below.

[0132] Specifically, for the current column of input data, if the control module 40 determines that the vector dot product of the current column of input data is the last vector dot product of the input data, the control module 40 controls the calculation module 20 to process the target data using the first strategy.

[0133] In the process of processing the target data using the first strategy, the read buffer module 50 reads the first target row data from the current read address row through the read bit line 14, performs the vector dot product of the current column of input data and the first target row data to obtain the output result, and the control module 40 controls the current read address row to add one after the current vector dot product calculation is completed. Meanwhile, the write buffer module 60 obtains the external target data through the first data input interface, determines the second target row data from the external target data, and writes the second target row data to the current write address row through the write bit line 15, where the second target row data is different from the data (the data stored in the last period) stored in the current write address row in advance.

[0134] Exemplarily, the current column input data is I_1_16 (the last column of the input data), the target data includes 10 rows of row data, specifically W_1_1, W_1_2…W_1_10, the calculation process of the target data is divided into 10 periods, then the calculation of the first period is I_1_16* W_1_1, the calculation of the second period is I_1_16* W_1_2, in the calculation process of the second period, the first row of row data can be written into the second target row data, such as W_2_1, at the same time.

[0135] According to the above example, if the row data stored in the first row in the previous period (the last period) is [a1 b1 c1 d1 e1 f1 g1 h1], then in the first strategy, the second target row data is [a2 b2 c2 d2 e2 f2 g2 h2], wherein the elements in the second target row data are not completely the same as the elements in the row data stored in the previous period.

[0136] In the present application, the staggered row processing of data reading calculation and data updating is realized, so that the situation of calculation stagnation caused by data writing can be avoided, and the efficiency of data processing is improved.

[0137] Optionally, the storage-computing integrated chip 100 is also provided with an iteration counter (not shown in the figure), wherein the iteration counter is used to record the current iteration number of the iteration calculation for the input data. Specifically, when judging whether the vector dot product of the current column input data is the last vector dot product for the input data, the control module 40 can obtain the total column number of the input data, then read the current iteration number from the iteration counter, and in the case that the current number is the total column number of the input data, it is determined that the vector dot product of the current column input data is the last vector dot product for the input data.

[0138] According to the foregoing, the input data includes multiple column input data, and the calculation module 20 processes only one column of input data at a time, therefore, the iteration counter can be set to record the current number of vector dot products, and the iteration counter is incremented by one each time a column of input data is read and calculated. If the value of the iteration counter is the same as the total column number of the input data, it means that the current column input data is the last column of the input data, and therefore it can be determined that the vector dot product of the current column input data is the last vector dot product.

[0139] In some embodiments, if the control module 40 judges that the vector multiplication of the current column input data is not the last vector multiplication of the input data, the current data retention time is read from the refresh counter, and the refresh interval of the target data is read from the refresh interval register. If the current data retention time is not less than the refresh interval of the target data, the second strategy is used to process the target data. If the current data retention time is less than the refresh interval of the target data, it means that the refresh is not needed yet, so in this case, only the current data retention time of the target data needs to be updated (i.e. the refresh counter continues to increase), only the vector multiplication of the current column input data and the read first target row data needs to be calculated (the calculation has been completed), and the current read address row is incremented by one, and it is judged whether the current read address row is the terminal read address row. If it is the terminal read address row, the current read address row is reset to 0, and the next column input data is read, and further, if the current read address row is not the terminal read address row, the next column input data is read, and the vector multiplication of the current column input data and the read first target row data is calculated.

[0140] Here, since the vector multiplication of the current column input data is not the last vector multiplication of the input data, it means that the calculation of the input data has not been completed, so the calculation needs to be continued, and the refresh processing of the target data is needed.

[0141] Specifically, in the process of processing the target data using the second strategy, the row data read in the last cycle can be obtained from the read buffer module 50 through the second data input interface, and the row data read in the last cycle is taken as the second target row data, and the second target row data is written into the current write address row through the write bit line 15.

[0142] For example, if the current read address row is the 6th row, the target row data is read from the 6th row, and the vector multiplication of the target row data of the 6th row and the current column input data is performed, then the target row data read in the last cycle is the target row data of the 5th row, and the target row data read in the last cycle (i.e. the target row data of the 5th row read in the last cycle) is written back to the 5th row through the write bit line 15, so that the refresh of the data of the 5th row is completed through the error row processing.

[0143] After the refresh is complete, the control module 40 increments both the current read address row and the current write address row by one. If the current read address row is not the terminating read address row, it returns to the step of reading the target row data from the current read address row via the read bit line 14, until the current read address row becomes the terminating read address row. The current read address row is then reset to zero. Similarly, if the current write address row becomes the terminating write address row, the current write address row is reset to 0. The iteration counter and refresh counter are cleared, and the control module returns to the step of sequentially reading the multiple columns of input data until the vector dot product of the current column of input data is the last vector dot product of the input data. Then, the first strategy in the aforementioned embodiment is executed. Likewise, if the current write address row is not the terminating write address row, the control module returns to the step of writing the row data read in the previous cycle back to the current write address row via the write bit line.

[0144] Optionally, during the refresh of the target data, the target row data can also be read from the current read address row through the read bit line 14, and the current column input data and the target row data can be multiplied by a vector to obtain the output result. During the vector multiplication, the read target row data can be written back to the current read address row through the write bit line 15. That is, in this embodiment, the refresh operation can also be completed during the vector multiplication. In this case, the current write address row is the same as the current read address row.

[0145] As can be seen from the foregoing embodiments, since the first processing mode includes two strategies—updating and refreshing the target data—the sources of the second target row data written by the write-to-cache module for these two strategies are different. The following section, in conjunction with the aforementioned processing flow of the first processing mode, and... Figure 5 The working principle of the write decoding driver module will be explained. Figure 5 This is a circuit diagram of a write-decode driver module provided in an embodiment of this application. It should be noted that... Figure 5 The circuit structure shown corresponds to only one memory cell 11.

[0146] like Figure 5 As shown, in this circuit, the input data is selected based on the refresh signal rf_en and used as the drive signal for the write bit line WBL15. If rf_en is 1, the output data of the read buffer module 50 is selected as the input data of the write buffer module 60, denoted as... If rf_en is 0, then external target data is obtained through the first data input interface as input data for the write cache module 60 (i.e., new target data or new weight data), denoted as... .

[0147] To reduce the design energy consumption, the rf_en|w_last signal is used as an enable signal, and only when the enable signal is high, the write bit line WBL is charged / discharged according to the above input data; otherwise, the WBL remains 0. The read buffer module 50 is connected with the read bit line RBL in the storage array 10, and includes a sensitive amplifier and a data buffer. The full-amplitude read data is generated and buffered based on the voltage change of the read bit line RBL. To simplify the schematic diagram, it is assumed in this example that the refresh operation is completed when the calculation operation is performed (i.e., waddr = raddr during refresh); if the refresh operation is performed after the calculation operation is completed (similar to weight update, waddr = raddr-1), a data buffer needs to be added to store the target data of the previous row of the current read address row.

[0148] In combination with the foregoing embodiments, if the vector dot product of the current column input data is the last vector dot product of the input data, w_last = 1; if the vector dot product of the current column input data is not the last vector dot product of the input data, w_last = 0; if the vector dot product of the current column input data is not the last vector dot product of the input data and the current data retention time is not less than the refresh interval of the target data, rf_en = 1; if the vector dot product of the current column input data is not the last vector dot product of the input data and the current data retention time is less than the refresh interval of the target data, rf_en = 0.

[0149] According to the foregoing, in the embodiments of the present application, a second processing mode is also designed. In some embodiments, if the control module 40 detects that the valid time of the target data is greater than the refresh interval of the target data and the refresh interval of the target data is less than the single-round iterative calculation time, the control module 40 can control the storage-computing integrated chip 100 to enter the second processing mode.

[0150] Here, the valid time of the target data is greater than the refresh interval of the target data, which means that the target data needs to be kept valid for a time greater than the refresh interval, so the data calculation period needs to be refreshed not less than once. The refresh interval of the target data is less than the single-round iterative calculation time, which means that the refresh operation is more frequent than the single-round calculation iteration, that is, because the refresh interval is shorter, multiple refresh operations need to occur during a round of calculation iteration. Under this condition, the refresh and data calculation cannot be performed in parallel, and the calculation needs to be interrupted and the data needs to be refreshed. Therefore, in order to avoid affecting the subsequent calculation, the storage-computing integrated chip needs to be controlled to enter the second processing mode to prohibit the calculation of the target data when the target data is refreshed.

[0151] Specifically, in the second processing mode, if the current data retention time is not less than the refresh interval of the target data, it indicates that the current needs to be refreshed. The read cache module 50 can read the first target row data of the current read address row through the read bit line 14, the write cache module 60 obtains the first target row data from the read cache module, and writes the read first target row data back to the current read address row through the write bit line 15 to complete the data refresh, and then increments the current read address row until the current read address row is the termination read address row. The current read address row is reset to zero, and the refresh counter is cleared.

[0152] Further, if the current data retention time is less than the refresh interval of the target data, it indicates that the refresh has been completed at this time, so the calculation needs to continue. Specifically, the first target row data is read from the current read address row through the read bit line 14, the current column input data is vector dot multiplied with the first target row data to obtain an output result, and the current read address row is incremented, and then the following steps are returned to execute: in the case that the current read address row is not the termination read address row, returning to the step of reading the target row data from the current read address row by the read cache module 50 through the read bit line 14, until the current read address row is the termination read address row, the current read address row is reset to zero, and the input data is updated.

[0153] In order to facilitate the understanding of the above data processing process, the application provides a data processing method. The method is applied to the storage-computing integrated chip in the foregoing embodiments, as shown in the flowchart of the data processing method provided by an exemplary embodiment of the application, as shown in the flowchart of the data processing method provided by an exemplary embodiment of the application, the method can include the following steps S601-S606: Figure 6 Figure 6

[0154] S601: obtaining input data; the input data includes multiple column input data;

[0155] S602: in response to the storage-computing integrated chip entering a first processing mode, sequentially reading the multiple column input data; the first processing mode refers to a mode of simultaneously performing in-memory computing and data processing;

[0156] S603: reading first target row data from a current read address row through the read bit line, and vector dot multiplying the current column input data with the first target row data to obtain an output result; and

[0157] S604: writing second target row data to a current write address row through the write bit line; the current write address row is a previous row of the current read address row;

[0158] ​​S605: incrementing the current read address row and the current write address row by one, and returning to the step of reading the target row data from the current read address row through the read bit line until the current read address row is a termination read address row, resetting the current read address row to zero and updating the input data;

[0159] S606: returning to the step of sequentially reading the plurality of column input data until the input data stops updating, in a case that the current write address row is a termination write address row.

[0160] According to the foregoing, in the present application, in response to the storage-computing integrated chip entering the first processing mode, the plurality of column input data is sequentially read, the first target row data is read from the current read address row through the read bit line, the current column input data is vector dot-multiplied with the first target row data to obtain an output result, and the second target row data is written to the current write address row through the write bit line. Since the current write address row is a previous row of the current read address row, the above-mentioned method can realize staggered processing of data calculation and data writing, which is beneficial to improving data processing efficiency and further improving chip performance.

[0161] The detailed contents of steps S601-S606 have been described in the foregoing embodiments, and will not be repeated here.

[0162] The complete processing flow of the present application will be introduced below in combination with FIGS. 7(A)-7(B).

[0163] FIG. 7(A) is a flowchart of another data processing method according to an example embodiment of the present application, which includes the following steps S701-S712:

[0164] S701: in response to the storage-computing integrated chip entering an initialization mode, writing target data to a storage array.

[0165] S702: obtaining valid time of input data and target data and refresh interval of the target data.

[0166] S703: determining whether the valid time of the target data is less than the refresh interval of the target data, and if yes, performing step S715, and if no, performing step S704.

[0167] S704: determining whether the refresh interval of the target data is less than a single round iteration calculation time, and if yes, performing step S705, and if no, performing step S716.

[0168] S705: controlling the storage-computing integrated chip to enter a first processing mode, and sequentially reading a plurality of column input data of the input data.

[0169] S706: reading target row data from the current read address row through the read bit line, vector dot multiplying the current column input data with the target row data to obtain an output result, and adding one to the current read address row.

[0170] S707: judging whether the vector dot multiplication of the current column input data is the last vector dot multiplication for the input data, if yes, executing step S708, and if no, executing step S717.

[0171] S708: processing the target data by using a first strategy, and in the process of processing the target data by using the first strategy, writing new target row data into the current write address row through the write bit line; the current write address row is a previous row of the current read address row.

[0172] S709: adding one to the current read address row and the current write address row respectively, and judging whether the current read address row is a termination read address row, if yes, executing step S710, and if no, executing step S706.

[0173] S710: resetting the current read address row to zero and updating the input data.

[0174] S711: judging whether the current write address row is a termination write address row, if yes, executing step S712, and if no, executing step S708.

[0175] S712: resetting the current write address row to 0, emptying an iteration counter and a refresh counter.

[0176] S713: judging whether the input data has been updated, if yes, returning to execute step S706, and if no, executing step S714.

[0177] S714: exiting the first processing mode.

[0178] S715: processing the target data by using a third processing mode.

[0179] S716: processing the target data by using a second processing mode.

[0180] S717: processing the target data by using a second strategy.

[0181] Fig. 7 (B) is a flow chart of processing the target data by using the second strategy according to an example embodiment of the present application, which includes the following steps S718-S728.

[0182] S718: judging whether the current data retention time is less than a refresh interval of the target data, if yes, executing step S725, and if no, executing step S719.

[0183] S719: the target data is processed by using the second strategy, and in the process of processing the target data by using the second strategy, the row data read in the last cycle is written back to the current write address row through the write bit line, wherein the current write address row is the last row of the current read address row.

[0184] S720: the current read address row and the current write address row are added by one respectively, and it is judged whether the current read address row is the termination read address row, if yes, step S721 is executed, if not, step S724 is executed.

[0185] S721: the current read address row is reset to 0.

[0186] S722: it is judged whether the current write address row is the termination write address row, if yes, step S723 is executed, if not, step S719 is executed.

[0187] S723: the termination write address row is reset to 0, the iteration counter and the refresh counter are emptied, and step S706 is executed.

[0188] S724: step S706 is executed.

[0189] S725: the current data retention time of the target data is updated, and the current read address row is added by one.

[0190] S726: it is judged whether the current read address row is the termination read address row, if yes, step S727 is executed, if not, step S728 is executed.

[0191] S727: the current read address row is reset to 0, and step S706 is executed.

[0192] S728: step S706 is executed.

[0193] The detailed content of the above method has been described in detail in the foregoing embodiment, and will not be repeated here.

[0194] The implementation process of the functions and roles of each unit in the above device is specifically described in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0195] For the device embodiment, since it basically corresponds to the method embodiment, the relevant part is described in the method embodiment. The device embodiment described above is only illustrative, wherein the units described as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place or distributed on multiple network units. Some or all of the modules can be selected to achieve the purpose of the application according to actual needs. Those skilled in the art can understand and implement it without creative labor.

[0196] Corresponding to the above-mentioned data processing method, the embodiment of the disclosure also provides a computer device, as shown in Figure 8 The structure diagram of the computer device provided by the embodiment of the disclosure is shown in the figure, which includes:

[0197] The computer device 800 includes a processor 810, an internal bus 820, a memory 830, a network interface 840, and a non-volatile memory 850, and of course can also include other functionally required hardware. One or more embodiments of the present specification can be implemented in a software manner, such as reading the corresponding computer program from the non-volatile memory 850 into the memory 830 by the processor 810 and then running. Of course, in addition to the software implementation, one or more embodiments of the present specification do not exclude other implementation manners, such as logic devices or a combination of software and hardware, etc., that is, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0198] The memory 830 is also called a memory, which is used to temporarily store the operation data in the processor 810 and the data exchanged with the non-volatile memory 850 such as a hard disk, and the processor 810 exchanges data with the non-volatile memory 850 through the memory 830.

[0199] In the embodiment of the present application, the memory 830 is specifically used to store the application program code for executing the application scheme, and is controlled to execute by the processor 810. That is, when the computer device is running, the processor 810 communicates with the network interface 840, the memory 830, and the non-volatile memory 850 through the internal bus 820 respectively, so that the processor 810 executes the application program code stored in the memory 830 and the non-volatile memory 850, and then executes the data processing method described in the above-mentioned method embodiment.

[0200] The processor 810 can be an integrated circuit chip having a processing capability for signals. The processor described above can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; or can be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The disclosed methods, steps and logic block diagrams in the embodiments of the present application can be implemented or executed by the general processor. The general processor can be a microprocessor or the processor can also be any conventional processor.

[0201] It can be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the computer device 800. In some other embodiments of the present application, the computer device 800 can include more or fewer components than those illustrated, or combine some components, or split some components, or different arrangement of components. The illustrated components can be implemented in hardware, software or a combination of software and hardware.

[0202] The embodiments of the present disclosure further provide a computer readable storage medium, which stores a computer program. When the computer program is run by a processor, the steps of the data processing method in the above method embodiments are executed. The storage medium can be a volatile or non-volatile computer readable storage medium.

[0203] The embodiments of the present disclosure further provide a computer program product, which carries a program code. The instructions included in the program code can be used to execute the steps of the data processing method in the above method embodiments. For details, refer to the above method embodiments, which will not be repeated here.

[0204] The computer program product can be specifically implemented by hardware, software or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium. In another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) and the like.

[0205] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non-transitory program carrier for execution by, or to control the operation of, data processing apparatus. Alternatively or additionally, the program instructions can be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0206] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit), and the apparatus can be implemented as special purpose logic circuitry.

[0207] Computers suitable for the execution of a computer program include, by way of example, general and / or special purpose microprocessors, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read-only memory and / or a random access memory. The essential elements of a computer are a central processing unit for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive), to name just a few.

[0208] Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0209] While the specification contains many specifics, these should not be construed as limiting the scope of any invention or of what can be claimed, but as merely providing illustrations of some of the embodiments of the inventions. Certain features that are, for clarity, described above in the context of separate embodiments, can also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described above in the context of a single embodiment, can also be provided separately or in any suitable subcombination. In addition, while features can be described above as being implemented in digital electronic circuitry, one or more features also can be implemented in analog circuitry, in embodiments of the application. As used herein, the term "circuitry" refers to all of the following: (a) hardware-only circuitry implementations (which will be entirely analog in some embodiments, and / or entirely digital in some embodiments); (b) combinations of circuits and digital circuitry as well as software, such as (as applicable): (i) a combination of processor(s) or (ii) portions of circuits / matrices / processors and associated memory to implement software; as a non-limiting example, a software driver and / or firmware to control one or more processors or a combination of hardware, circuits, and logic for implementing at least a portion of the functionality of a device, system or component. For instance, a processor can execute instructions stored in a memory to implement at least a portion of the functionality of a device, system or component.

[0210] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring or implying that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing can be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0211] Accordingly, particular embodiments of the subject matter have been described. Other embodiments within the scope of the following claims can be apparent to those of ordinary skill in the art. In certain circumstances, acts recited in the claims can be performed in a different order than is recited in the claims, and still achieve desirable results. In some embodiments, processes depicted in the figures can not be required to be performed in the particular order depicted in the figures, or in sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing can be advantageous.

[0212] The above description is intended to be illustrative and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the application should, therefore, be determined not with reference to the above description, but instead with reference to the appended claims, along with their full scope of equivalents.

Claims

1. A data processing method, characterized by, The application is applied to a memory-compute integrated chip, the memory-compute integrated chip comprises a memory array, the memory array has a read bit line and a write bit line, and the read bit line and the write bit line are independent of each other; the memory array is used for storing target data, the target data comprises multiple rows of row data; the method comprises: obtaining input data; the input data comprises multiple columns of column input data; in response to the memory-compute integrated chip entering a first processing mode, sequentially reading the multiple columns of column input data; the first processing mode refers to a mode of simultaneously performing in-memory computing and data processing; reading first target row data from a current read address row through the read bit line, and performing vector dot multiplication on the current column input data and the first target row data to obtain an output result; and writing second target row data to a current write address row through the write bit line; the current write address row is a previous row of the current read address row; incrementing the current read address row and the current write address row by one, in a case where the current read address row is not a terminal read address row, returning to the step of reading target row data from the current read address row through the read bit line until the current read address row is the terminal read address row, resetting the current read address row to zero, and updating the input data; in a case where the current write address row is a terminal write address row, returning to the step of sequentially reading the multiple columns of column input data until the input data stops being updated.

2. The method of claim 1, wherein, The first processing mode comprises a first strategy; the memory-compute integrated chip comprises a first data input interface; after the memory-compute integrated chip enters the first processing mode, the method further comprises: for the current column input data, determining whether vector dot multiplication of the current column input data is a last vector dot multiplication for the input data, and if so, processing the target data by using the first strategy; in the process of processing the target data by using the first strategy, the writing of the second target row data to the current write address row through the write bit line comprises: obtaining external target data through the first data input interface; determining the second target row data from the external target data, and writing the second target row data to the current write address row through the write bit line; the second target row data is different from previously stored data of the current write address row.

3. The method of claim 2, wherein, The first processing mode comprises a second strategy, the memory-compute integrated chip comprises a second data input interface, the memory-compute integrated chip is provided with a refresh interval register and a refresh counter; the method further comprises: if the vector dot multiplication of the current column input data is not the last vector dot multiplication for the input data, reading a current data retention time of the target data after a last refresh from the refresh counter, and reading a refresh interval of the target data from the refresh interval register; If the current data retention time is not less than the refresh interval of the target data, and the refresh interval of the target data is less than a single round iteration calculation time, the second strategy is adopted to process the target data; the single round iteration calculation time refers to the sum of the reading time of the target data and the calculation time, and the calculation time refers to the time consumed by the vector dot product of the current column input data and each row data in the target data. In the process of processing the target data by adopting the second strategy, the writing of the second target row data to the current writing address row through the write bit line comprises: acquiring the row data read in the last cycle from the read cache module through the second data input interface; the row data read in the last cycle is taken as the second target row data, and the second target row data is written into the current writing address row through the write bit line.

4. The method of claim 3, wherein, The memory-computing integrated chip is provided with an effective time register, which is used to record the effective time of the target data; the effective time refers to the time required for the target data to complete calculation; The memory-computing integrated chip enters the first processing mode in the following way, comprising: reading the effective time of the target data from the effective time register; If the effective time of the target data is not less than the refresh interval of the target data and the refresh interval of the target data is less than the single round iteration calculation time, it is determined that the memory-computing integrated chip enters the first processing mode.

5. The method of claim 4, wherein, The method further comprises: If the effective time of the target data is greater than the refresh interval of the target data and the refresh interval of the target data is less than the single round iteration calculation time, it is determined that the memory-computing integrated chip enters the second processing mode; the second processing mode refers to a mode in which the target data is not calculated when the target data is refreshed; In the second processing mode, the multi-column column input data is read in turn, if the current data retention time is not less than the refresh interval of the target data, the first target row data of the current reading address row is read from the memory array through the read bit line, and the read first target row data is written back to the current reading address row through the write bit line; In the case where the current data retention time is less than the refresh interval of the target data, the first target row data is read from the current reading address row through the read bit line, the current column input data and the first target row data are subjected to vector dot product to obtain an output result, and the current reading address row is incremented by one; returning to execute the following steps: in the case where the current reading address row is not a terminal reading address row, returning to the step of reading the target row data from the current reading address row through the read bit line until the current reading address row is a terminal reading address row, resetting the current reading address row to zero, and updating the input data.

6. The method of claim 4, wherein, The method further comprises: If the valid time of the target data is less than the refresh interval of the target data, it is determined that the memory-computing integrated chip enters a third processing mode; the third processing mode refers to a mode in which the target data is updated and the target data is not refreshed. In the third processing mode, the plurality of column input data are sequentially read, if the vector dot product of the current column input data is the last vector dot product for the input data, first target row data are read from a current read address row through the read bit line, and the output result is obtained by performing vector dot product on the current column input data and the first target row data. Second target row data are determined from the external target data, and the second target row data are written to a current write address row through the write bit line; the second target row data are different from the data stored in the current write address row in advance. The current read address row and the current write address row are incremented by one, and in the case that the current read address row is not a terminal read address row, the step of reading target row data from the current read address row through the read bit line is returned to, until the current read address row is the terminal read address row, the current read address row is reset to zero, and the input data are updated. In the case that the current write address row is a terminal write address row, the step of sequentially reading the plurality of column input data is returned to, until the input data stop being updated.

7. The method of claim 6, wherein, The method further comprises: If the vector dot product of the current column input data is not the last vector dot product for the input data, first target row data are read from a current read address row through the read bit line, the output result is obtained by performing vector dot product on the current column input data and the first target row data, and the current read address row is incremented by one. In the case that the current read address row is not a terminal read address row, the step of reading target row data from the current read address row through the read bit line is returned to, until the current read address row is the terminal read address row, the current read address row is reset to zero, and the step of sequentially reading the plurality of column input data is returned to be executed, until the vector dot product of the current column input data is the last vector dot product for the input data.

8. The method of claim 1, wherein, The memory-computing integrated chip is provided with an iteration counter, and the iteration counter is used to record the current iteration number of the iteration calculation for the input data. Whether the vector dot product of the current column input data is the last vector dot product for the input data is determined by: The total column number of the input data is obtained. The current iteration number is read from the iteration counter, and in the case that the current iteration number is the total column number of the input data, it is determined that the vector dot product of the current column input data is the last vector dot product for the input data.

9. The method of claim 1, wherein, The method further comprises, before the memory-computing integrated chip enters the first processing mode: In response to power-on of the memory-compute integrated chip, the memory-compute integrated chip is controlled to enter an initialization mode; the initialization mode refers to a mode of initialization of the memory array, refresh counter, iteration counter, refresh interval register and valid time register and no calculation of data in the memory array; In the initialization mode, the target data is acquired, the target data is written into the memory array through the write bit line, and the refresh interval register and the valid time register are configured with data, and the iteration counter and the refresh counter are emptied.

10. The method according to any one of claims 1 to 9, characterized in that, The target data is weight data of a neural network.

11. A memory computing integrated chip, comprising: Comprise: a memory array, a calculation module, a control module, a read cache module and a write cache module, the memory array has a read bit line and a write bit line, and the read bit line and the write bit line are independent of each other; the memory array is used for storing target data, and the target data comprises multiple rows of row data; The calculation module is used for acquiring input data, and the input data comprises multiple columns of column input data; The control module is connected with the calculation module, and is used for controlling the calculation module to sequentially read the multiple columns of column input data in response to the memory-compute integrated chip entering a first processing mode; The first processing mode refers to a mode of simultaneous in-memory calculation and data processing; The read cache module is used for reading first target row data from a current read address row through the read bit line, and sending the first target row data to the calculation module; The calculation module is also used for performing vector dot multiplication on the current column input data and the first target row data to obtain an output result; and The write cache module is used for writing second target row data into a current write address row through the write bit line; the current write address row is a previous row of the current read address row; The control module is also used for adding one to the current read address row and the current write address row respectively, and in a case where the current read address row is not a terminal read address row, returning to execute the step of the read cache module reading first target row data from the current read address row through the read bit line and sending the first target row data to the calculation module until the current read address row is a terminal read address row, resetting the current read address row to zero and updating the input data; The control module is also used for, in a case where the current write address row is a terminal write address row, returning to execute the step of controlling the calculation module to sequentially read the multiple columns of column input data until the input data stops updating.

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