System and method for determining initial lineup and continuous time linear equalizer

Abstract

A system for determining a lineup in a list of all P-type transistors and all N-type transistors, the P-type transistors and the N-type transistors being slave elements in a pull-up-pull-down-inverter (PUDI) of a target group coupled in parallel, includes: a comparator coupled to the P-type transistors and the N-type transistors, the P-type transistors and the N-type transistors being slave elements in the Pull-up-Pull-down-inverter (PUDI) of the target group coupled in parallel; the comparator is used for comparing a reference voltage with an output of the target group. The controller performs an evaluation of one candidate lineup selected from the list, including setting a state of a P-type transistor selection signal and an N-type transistor selection signal according to the candidate lineup, and an operation based on the comparison, comprising setting the starting lineup as the candidate lineup or modifying the candidate lineup and repeating the evaluation and operation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a circuit, system and method, and more particularly to a system, method and continuous time linear equalizer for determining a starting lineup. BACKGROUND

[0002] The integrated circuit (IC) industry produces a variety of analog and digital semiconductor devices to solve problems in different fields. The development of semiconductor process technology nodes has gradually reduced the size of elements and tightened the pitch, resulting in a gradual increase in transistor density. ICs are gradually becoming smaller. SUMMARY

[0003] A system for determining a starting lineup in a roster, according to one aspect of the present disclosure, includes a comparator configured to compare between a reference voltage and an output of a subject group; the subject group includes pull-up-pull-down-inverters (PUDIs) coupled in parallel, each of the PUDIs including a master pass-gate metal-oxide-semiconductor (PMOS) field-effect transistor (FET) (PFET) and a slave pass-gate metal-oxide-semiconductor (PMOS) field-effect transistor (FET) (PFET), and a slave negative-channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET) (NFET) and a master negative-channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET) (NFET); for each of the PUDIs, each of the slave PFET and slave NFET transistors' control inputs are coupled to an input node of the PUDI, the master PFET transistor's control input is configured to receive a PFET selection signal, the PFET selection signal is PUDI-specific, and the master NFET transistor's control input is configured to receive a NFET selection signal, the NFET selection signal is PUDI-specific; the roster is composed of all slave PFETs and all slave NFETs in the subject group; and for the subject group, a controller is configured to evaluate a candidate lineup selected from the roster, the evaluation including: setting the subject group's PFET selection signals to PFET- enabled state or PFET-non-enabled state, respectively, setting the subject group's NFET selection signals to NFET-enabled state or NFET-non-enabled state, respectively; and performing an operation based on the comparison, including: setting the starting lineup to the candidate lineup; or modifying the candidate lineup and repeating the evaluation and operation.

[0004] A method of determining a starting lineup from a list includes: selecting a subject group from a plurality of pull-up-pull-down-inverter (PUDI) groups, each PUDI including slave positive channel metal-oxide-semiconductor (PMOS) field-effect transistors (PFETs) and slave PMOS FETs, and slave negative channel metal-oxide-semiconductor (NMOS) FETs (NFETs) and master NMOS FETs; coupling the PUDIs of the subject group in parallel; for each PUDI in the subject group: coupling a control input of each of the slave PFET and slave NFET transistors to an input node of the PUDI; configuring a control input of the master PFET transistor to receive a PFET select signal, the signal being PUDI-specific; and configuring a control input of the master NFET transistor to receive a NFET select signal, the signal being PUDI-specific; evaluating a candidate lineup of the subject group selected from the list, the list consisting of all slave PFETs and all slave NFETs in the subject group, the evaluating including: setting the PFET select signal to a PFET-activated state or a PFET-inactivated state, respectively, in accordance with the candidate lineup; setting the NFET select signal to a NFET-activated state or a NFET-inactivated state, respectively, in accordance with the candidate lineup; and using a comparator to compare a reference voltage and an output of the subject group; and performing an operation based on the comparison, including: setting the starting lineup to the candidate lineup; or modifying the candidate lineup and repeating the evaluating and operation.

[0005] A continuous time linear equalizer (CTLE) includes: a buffer having an output representative of an output of the CTLE; a first group of j pull-up-pull-down-inverters (PUDIs) coupled in parallel; a data input of each of the PUDIs in the first group coupled to an input node of the CTLE; the first group coupled between the input node of the CTLE and an input of the buffer; a first active inductor coupled to an output node of the first group; a first control input of each PUDI in the first group configured to receive a respective first conductivity type (FCT) select signal, the signal being PUDI-specific; a second control input of each of the PUDIs in the first group configured to receive a respective second conductivity type (SCT) select signal, the signal being PUDI-specific; and a controller configured to adaptively set the FCT select signals of the first group to be in a FCT-activated state or a FCT-inactivated state, respectively; and adaptively set the SCT select signals of the first group to be in a SCT-activated state or a SCT-inactivated state, respectively; and j and p are positive integers. BRIEF DESCRIPTION OF DRAWINGS

[0006] One or more embodiments are illustrated by way of example in the accompanying drawings in which like reference numbers indicate similar elements in the several views, by way of non-limiting example, in which: the drawings are not to scale unless otherwise specified.

[0007] FIG. 1A is a block diagram illustrating, by way of example, some embodiments;

[0008] FIG. 1B is a schematic diagram illustrating, by way of example, some embodiments;

[0009] FIG. 1C is a block diagram illustrating, by way of example, some embodiments;

[0010] FIG. 2 is a schematic diagram illustrating, by way of example, some embodiments;

[0011] FIGS. 3A-3D are corresponding schematic diagrams illustrating, by way of example, some embodiments;

[0012] FIGS. 4A-4B are flowcharts of corresponding methods illustrating, by way of example, some embodiments;

[0013] FIG. 4C is a table illustrating, by way of example, some embodiments;

[0014] FIGS. 5-7 are flowcharts of corresponding methods illustrating, by way of example, some embodiments;

[0015] FIG. 8 is a block diagram of an electronic design automation (EDA) system illustrating, by way of example, some embodiments;

[0016] FIG. 9 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith, illustrating, by way of example, some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components, materials, actions, operations, configurations or the like are described herein in order to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, configurations or the like are also contemplated as within the scope of the application. For instance, in the following description, formation of a first feature over or on a second feature can include embodiments in which the first and second features are formed directly contacting one another, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not directly contact one another. Furthermore, reference numbers and / or letters can be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not itself represent a relationship between various embodiments and / or configurations discussed.

[0018] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly. In some embodiments, the term standard cell structure refers to standardized building blocks included in various standard cell library. In some embodiments, various standard cell structures are selected from their library and used as elements in representing circuit layout.

[0019] In some embodiments, a continuous-time linear equalization system based on pull-up-pull-down inverters (PUDIs) (e.g., 108) is PUDI-based. The PUDI-based system (e.g., 100) is PVTA-adaptive, where the PVTA term will be discussed below. The system 100 includes a PUDI-based controller (e.g., 106), a PUDI-based continuous-time linear equalizer (CTLE) (e.g., 102), and a lineup setter (e.g., 104). The controller is included as part of the PUDI-based CTLE and the lineup setter. The PUDI-based CTLE includes a group of PUDIs. The lineup setter is configured to determine / set the lineup of PFETs and / or NFETs. The PFET and NFET terms will be discussed below. For a given group of PUDIs, the lineup setter is configured to reduce the negative impact of PVTA variation on the operation of the group of PUDIs. For a given group of PUDIs, the list of all slave PFETs and all slave NFETs in the group represents the roster of the group. The lineup setter is configured to achieve this by selecting which, if any, slave PFETs and / or slave NFETs on the roster will be enabled for operation, i.e., by determining / setting the lineup of slave PFETs and / or slave NFETs selected from the roster. For a given group of PUDIs, the PUDI-based CTLE is configured to implement the lineup (determined by the lineup setter) by enabling operation of one or more slave PFETs and / or one or more slave NFETs in the PUDI-based CTLE included in the lineup, and by preventing operation of the remaining slave PFETs and / or slave NFETs on the roster but not included in the lineup.

[0020] Another system approach provides a counterpart system that is a counterpart of the PUDI-based continuous-time linear equalization system according to some embodiments. The counterpart system includes: a counterpart inverter-based CLTE that is a counterpart of the PUDI-based CTLE according to some embodiments; and a counterpart PVTA compensator that is a counterpart of the lineup setter according to some embodiments. The counterpart inverter-based CLTE includes a group of tri-state inverters. The counterpart PVTA compensator attempts to reduce the impact of PVTA variations on the counterpart inverter-based CLTE by performing CTLE-level adaptive control of the drive strength of the inverters in the counterpart inverter-based CLTE, albeit at a CTLE-level precision (granularity) that is a lower / smaller degree of precision than the group-level precision (granularity). The counterpart PVTA compensator attempts to perform the CTLE-level adaptive control by adjusting a ground reference voltage (VSS) provided to all elements of the counterpart inverter-based CLTE. The counterpart PVTA compensator attempts to adjust the VSS by using a high-speed VSS management circuit that includes a high-frequency ring oscillator. According to other system approaches, the high frequency of the VSS management circuit: occupies a large area (has a large footprint); and suffers from high oscillation-related current consumption.

[0021] In contrast, the PUDI-based CTLE according to some embodiments provides group-level precision (granularity) by including a group of PUDIs, thus enabling more precise (more nuanced) control that achieves better performance (in terms of reducing the impact of PVTA variations) than the CTLE-level precision (granularity) provided by other system approaches. Moreover, the lineup setter according to some embodiments is not oscillator-based, thus occupying significantly less area (having a significantly smaller footprint) and suffering from significantly lower oscillation-related current consumption than the counterpart PVTA compensator in other system approaches.

[0022] Figure 1A is a block diagram of a system 100 according to some embodiments.

[0023] The system 100 is a PUDI-based continuous-time linear equalization system, i.e., the system 100 is based on pull-up-pull-down-inverters (PUDIs) (see Figure 1B ). The system 100 is PVTA adaptive, where PVTA (to be discussed below) is an acronym for PVT and aging variations, and PVT itself is an acronym for process, supply voltage and temperature variations.

[0024] System 100 includes a controller 106 (see Figure 2 and 3A ); a PUDI-based continuous-time-linear equalizer (CTLE) 102 (see Figure 2 ); and a PFET and NFET lineup setter 104 (see Figure 3A ), which is configured to determine / set a lineup of PFETs and / or NFETs. The terms PFET and NFET are discussed below. Controller 106 is included as part of each of PUDI-based CTLE 102 and lineup setter 104.

[0025] For a given PUDI group, the list of all slave PFETs and all slave NFETs in the group represents a roster for the group. For a given group, lineup setter 104 is configured to select which, if any, slave PFETs and / or slave NFETs on the roster are to be enabled for operation, i.e., to determine / set a lineup of selected slave PFETs and / or slave NFETs from the roster. For a given PUDI group, PUDI-based CTLE 102 is configured to enforce the lineup by enabling operation of one or more slave PFETs and / or one or more slave NFETs included in the lineup, and by preventing operation of the remaining slave PFETs and / or slave NFETs that are on the roster but not included in the lineup.

[0026] In some embodiments, lineup setter 104 operates when system 100 is powered on, and then shuts down. In some embodiments, lineup setter 104 operates when system 100 is powered on, and then operates periodically. In some embodiments, lineup setter 104 operates periodically when system 100 is on.

[0027] Both the terms PFET and NFET assume a context of field-effect transistors (FETs). PFET is an abbreviation for P-type FET, where a P-type FET is configured using P-type dopants as used in positive-channel metal-oxide semiconductor (PMOS) transistor technology. NFET is an abbreviation for N-type FET, where an N-type FET is configured using N-type dopants as used in negative-channel metal-oxide semiconductor (NMOS) transistor technology. For example, complementary metal-oxide semiconductor (CMOS) transistor technology includes PFETs and NFETs.

[0028] With respect to process aspects in PVT, during fabrication of a semiconductor base device (e.g., a device including PFETs and NFETs), fabrication tolerances can cause variations in the device from its idealized design (process variations). Examples of process parameters that experience process variations include source impurity (dopant) concentration, pressure, temperature, implant impurity (dopant) density, implant impurity (dopant) diffusion depth, oxide thickness, transistor channel width, transistor channel length, etc.

[0029] With respect to supply voltage aspects in PVT, supply voltage fluctuations can affect the operation of a semiconductor base device (e.g., a device including PFETs and NFETs). Causes of supply voltage fluctuations include ohmic losses, noise due to current rate of change (di / dt noise), etc. Examples of ohmic losses include voltage reduction (IR drop) as current flows through parasitic resistances of a power grid, etc. Examples of di / dt noise include losses due to parasitic inductance, parasitic capacitance, etc.

[0030] With respect to temperature aspects in PVT, temperature fluctuations can affect the operation of a semiconductor base device (e.g., a device including PFETs and NFETs). Operation of transistors consumes power, generates heat, and increases temperature in the vicinity of the transistors. Not all PFETs and NFETs experience the same degree of activity. Each PFET and NFET contributes a respective temperature fluctuation to the device environment. A device includes millions or even billions of PFETs and NFETs. Areas in a device that experience high activity of a large number of PFETs and / or NFETs experience significant or even substantial localized temperature fluctuations (sometimes referred to as hot spots). In addition, carrier mobility is inversely proportional to temperature, resistance of conductive paths (wiring) is inversely proportional to temperature, etc.

[0031] With respect to aging, in some embodiments, the transistor characteristics of a semiconductor base device are described as initially having reference values at the time of manufacture. Over time, the transistor characteristics of the device change, typically degrading as compared to the corresponding reference values. In some embodiments, the effects of aging are referred to as wear-out effects. Examples of wear-out effects include hot carrier injection increase, bias temperature instability, etc.

[0032] The PUDI-based CTLE 102 includes PUDI groups (see FIG. 2). In each such group, the PUDIs are coupled in parallel. Each PUDI includes a PFET and a NFET (see FIG. IB). The performance of each PUDI, and thus the PUDI-based CTLE 102, is affected by PVTA variation.

[0033] Each PUDI group (see FIG. 2) has a roster that includes all slave PFETs (see FIG. IB) and all slave NFETs (see FIG. IB) in the PUDI group. Since the CTLE system 100 is PVTA adaptive, not all slave PFETs (see FIG. IB) and not all slave NFETs (see FIG. IB) in the PUDI group are necessarily enabled for operation. Rather, only selected slave PFETs and selected slave NFETs in the PUDI group are enabled for operation. The selected slave PFETs and the selected slave NFETs in the PUDI group represent the lineup of the PUDI group, i.e., the lineup is selected from the roster.

[0034] Each selected slave PFET, i.e., each slave PFET in the lineup, is enabled for operation by a corresponding master PFET. Each slave PFET not in the lineup is disabled for operation by the corresponding master PFET. Each selected slave NFET, i.e., each slave NFET in the lineup, is enabled for operation by a corresponding master NFET. Each slave NFET not in the lineup is disabled for operation by the corresponding master NFET.

[0035] For each PUDI group, in terms of the lineup setter 104 (see FIG. 3A) as part of the controller 106, the controller 106 is configured to reduce the negative effects of PVTA variation by determining / setting the lineup to improve operation of the PUDI group. Thus, the lineup setter 104 is PVTA adaptive. Further, for each PUDI group, in terms of the PUDI-based CLTE 102 as part of the controller 106, the controller 106 is configured to control the master PFETs and the master NFETs in accordance with the lineup to reduce the negative effects of PVTA variation to improve operation of the PUDI group. Thus, the PUDI-based CLTE 102 is PVTA adaptive.

[0036] FIG. 1B is a schematic diagram of a PUDI 108, according to some embodiments.

[0037] PUDI 108 is an example of each PUDI in the PUDI group included in PUDI-based CTLE 102 in FIG. 1A. Thus, PUDI 108 is referred to as the i-th (or the i_th) PUDI, i.e., PUDI(i). The control signal received by PUDI(i) 108 is referred to as the corresponding i-th (or the i_th) control signal.

[0038] Through the exploded view 110, each PUDI(i) 108 includes: a master PFET P11; a slave PFET P12; a slave NFET N11; and a master NFET N12.

[0039] Master P11 and slave P12 are coupled in series between a first reference voltage (e.g., VDD) and an output node OUT of PUDI(i) 108. Slave N11 and master N12 are coupled between the output node OUT and a second reference voltage (e.g., VSS). The gate terminals of slave P12 and slave N11 are each coupled to an input node IN of PUDI(i) 108.

[0040] The gate terminal of master P11 is configured to receive a PFET selection signal ENP(i) specific to PUDI(i) 108. Thus, signal ENP(i) is described as PUDI-specific. In some embodiments, ENP is an abbreviation for enable PFET. The gate terminal of master N12 is configured to receive a NFET selection signal ENN(i) specific to PUDI(i) 108. Thus, signal ENN(i) is described as PUDI-specific. In some embodiments, ENN is an abbreviation for enable NFET. Signals ENP(i) and ENN(i) are generated by controller 106.

[0041] Master P11 is controlled by signal ENP(i) to enable or block the operation of slave P12. Master N12 is controlled by signal ENN(i) to enable or block the operation of slave N11. For each PUDI(i), master P11 and master N12 are independently controlled such that master P11 and master N12 have one of the following four paired states: (P11_ON, N12_ON); (P11_ON, N12_OFF); (P11_OFF, N12_ON); and (P11_OFF, N12_OFF). The four paired states correspond to four operating modes of PUDI(i) 108, as described below.

[0042] In the inverter mode, the controller 106 configures the signal ENP(i) to a PFET- enabled state and the signal ENN(i) to a NFET-enabled state, respectively turning on the main P 11 and the main N 12. When turned on, the main P 11 enables the slave P 12 to operate. When turned on, the main N 12 enables the slave N 11 to operate. In the inverter mode, the PUDI(i) 108 operates as an inverter. The inverter mode corresponds to the paired state (P11_ON, N12_ON).

[0043] In the pull-up mode, the controller 106 configures the signal ENP(i) to a PFET- enabled state and the signal ENN(i) to a NFET non-enabled state, respectively turning on the main P 11 and turning off the main N 12. When turned off, the main N 12 prevents the slave N 11 from operating, causing the slave N 11 to present a high impedance between the input node IN and the output node OUT. In the pull-up mode, the PUDI(i) 108 operates as a pull-up circuit, including: pulling up the voltage on the output node OUT to a value representing a logic high (logic one) in response to a voltage on the input node IN representing a logic low (logic zero); and not significantly affecting the voltage value on the output node OUT in response to a voltage on the input node IN representing a logic high (logic one). The pull-up mode corresponds to the paired state (P11_ON, N12_OFF).

[0044] In the pull-down mode, the controller 106 configures the signal ENP(i) to a PFET non-enabled state and the signal ENN(i) to a NFET-enabled state, respectively turning off the main P 11 and turning on the main N 12. When turned off, the main P 11 prevents the slave P 12 from operating, causing the slave P 12 to present a high impedance between the input node IN and the output node OUT. In the pull-down mode, the PUDI(i) 108 operates as a pull-down circuit, including: pulling down the voltage on the output node OUT to a value representing a logic low (logic zero) in response to a voltage on the input node IN representing a logic high (logic one); and not significantly affecting the voltage value on the output node OUT in response to a voltage on the input node IN representing a logic low (logic zero). The pull-down mode corresponds to the paired state (P11_OFF, N12_ON).

[0045] In the high impedance mode, the controller 106 configures the signal ENP(i) to a PFET non-enabled state and the signal ENN(i) to a NFET non-enabled state, respectively turning off the main P 11 and the main N 12. In the high impedance mode, the PUDI(i) 108 presents a high impedance between the input node IN and the output node OUT, regardless of whether a voltage on the input node IN represents a logic low (logic zero) or a logic high (logic one). The high impedance mode corresponds to the paired state (P11_OFF, N12_OFF).

[0046] According to another system approach, a tri-state inverter is a counterpart of the PUDI(i) 108. The counterpart tri-state inverter includes elements corresponding to the master P 11, the slave P 12, the master N 12, and the slave N 11 of the PUDI(i) 108. According to the another system approach, the element corresponding to the master P 11 and the element corresponding to the master N 12 can only have two paired states, namely (corresponding_P11_ON, corresponding_N12_ON) and (corresponding_P11_OFF, corresponding_N12_OFF). Thus, the counterpart tri-state inverter has only two operating modes, namely the inverter mode or the high-impedance mode. In contrast, according to some embodiments, the PUDI(i) 108 has four operating modes, namely two more operating modes than the counterpart tri-state inverter in the another system approach. According to some embodiments, the two extra operating modes give the PUDI(i) 108 greater operational flexibility than the counterpart tri-state inverter in the another system approach. According to some embodiments, the two extra operating modes give the PUDI(i) 108 greater operational flexibility that helps the controller 106, in the context of the lineup setter 104 (see FIG. 3A), to be configured to reduce the negative impact of the PVTA variation, thereby improving the operation of the PUDI group by determining / setting the corresponding lineup; and the controller 106, in the context of the PUDI-based CLTE 102, to be configured to reduce the negative impact of the PVTA variation, thereby improving the operation of the PUDI group by controlling the master PFET and the master NFET according to the corresponding lineup.

[0047] FIG. 1C is a block diagram of a system 116, according to some embodiments.

[0048] The system 116 is a multi-die system. In some embodiments, a die is a result of decomposing (or disassembling or separating) a system-on-chip (SOC) into elements representing corresponding basic functions.

[0049] The system 116 includes dies 118(1) and 118(2) and a channel 122. The die 118(1) includes (among other elements) a driver 120. The die 118(2) includes (among other elements) the PUDI-based CTLE system 100. The driver 120 is coupled to the CTLE system 100 through the channel 122. The die 118(1) uses the driver 120 to communicate with the die 118(2), i.e., to send signals to the die 118(2), and the die 118(2) uses the CTLE system 100 to receive the signals from the die 118(1). In some embodiments, the channel 122 is a high-frequency wide serial transmission line.

[0050] In some embodiments, small die 118(1) includes a processor (not shown) and small die 118(2) includes a compute-in-memory (CIM) system (not shown). In these embodiments, the processor of small die 118(1) communicates with the CIM system of small die 118(2) through driver 120, channel 122, and CTLE system 100.

[0051] In some embodiments, small die 118(1) includes a compute-in-memory (CIM) system (not shown) and small die 118(2) includes a processor (not shown). In these embodiments, the CIM system of small die 118(1) communicates with the processor of small die 118(2) through driver 120, channel 122, and CTLE system 100.

[0052] In some embodiments, small die 118(1) includes a second instance of CTLE system 100 (not shown) and small die 118(2) includes a second instance of driver 120 (not shown). In some embodiments, multi-small-die system 116 is an artificial intelligence (AI) system.

[0053] In some embodiments, the reference voltages of small die 118(1) are substantially the same as the corresponding reference voltages of small die 118(2). For example, in some embodiments, the reference voltages VDD and VSS of small die 118(1) are substantially the same as the reference voltages VDD and VSS of small die 118(2). In these embodiments, small dies 118(1) and 118(2) are described as being tightly coupled. In some embodiments in which small die 118(1) is tightly coupled to small die 118(2), VDD is about 0.80 volts, VDD is about 0.70 volts, or similar values. In cases where the tight coupling would otherwise exist, process, voltage, temperature, and aging (PVTA) variations can reduce the degree of tight coupling of small dies 118(1) and 118(2).

[0054] In some embodiments, one or more reference voltages of small die 118(1) differ significantly, even substantially, from corresponding reference voltages of small die 118(2). For example, in some embodiments, (A) VDD of small die 118(1) is approximately 0.85 volts, while VDD of small die 118(2) is approximately 0.75 volts, or vice versa; (B) VDD of small die 118(1) is approximately 0.75 volts, while VDD of small die 118(2) is approximately 0.65 volts, or vice versa; or similar cases. In these embodiments, small dies 118(1) and 118(2) are described as non-tightly coupled. In the case of non-tightly coupling, process, voltage, temperature and aging (PVTA) variations typically exacerbate the degree of non-tightly coupling of small dies 118(1) and 118(2).

[0055] Figure 2 is a schematic diagram of a PUDI-based CTLE 202 according to some embodiments.

[0056] PUDI-based CTLE 202 is Figure 1A one example of a PUDI-based CTLE 102. Thus, in some embodiments, PUDI-based CTLE 102 is included in a PUDI-based system, such as Figure 1A system 100 of In embodiments of these systems, CTLE 202 coexists with a lineup setter, such as Figure 1A lineup setter 104 of

[0057] For a particular PUDI lineup in a given PUDI group, CTLE 202 is configured to enable operation of one or more slave PFETs and / or one or more slave NFETs included in the lineup, and to prevent operation of the remaining slave PFETs and / or slave NFETs on the list but not included in the lineup. The particular lineup is determined by a lineup setter, such as Figure 1A lineup setter 104 of Figure 3A lineup setter 304 of

[0058] PUDI-based CTLE 202 includes: a PUDI group 230(1)-230(4); a group of active inductors 236(1)-236(4); a buffer 231; and a controller 206. Each PUDI in PUDI group 230(1)-230(4) is Figure 1B one example of PUDI(i) 108 of Controller 206 isFigure 1A An example of the controller 106 in FIG.

[0059] PUDI groups 230(1)-230(4) are coupled in series between node nd11 and node nd15. PUDI group 230(1) is coupled between node nd11 and node nd12. Node nd11 represents an input node of PUDI-based CTLE 202. PUDI group 230(2) is coupled between node nd12 and node nd13. PUDI group 230(3) is coupled between node nd13 and node nd14. PUDI group 230(4) is coupled between node nd14 and node nd15. Buffer 231 is coupled between node nd15 and node nd16. Node nd16 represents an output node of PUDI-based CTLE 202.

[0060] exist Figure 2 In the PUDI group 230(1)-230(4), each PUDI is Figure 1B , j-1} and NFET select signals ENN230(1) {0, ..., j-1} from the controller 206. The controller 206 selects the PUDIs of the PUDI group 230(1) based on the lineup it determines for the PUDI group 230(1) (see FIG. Figure 3A ), configure the signals ENP230(1){0, ..., j-1} and ENN230(1){0, ..., j-1} to be in the enabled or disabled state respectively.

[0061] The PUDI group 230(2) includes k PUDIs, namely PUDI(0), ..., PUDI(k-1), which are coupled in parallel between nodes nd12 and nd13, where k is a positive integer. In some embodiments, j=8. The PUDIs of the PUDI group 230(2) are configured to receive PFET selection signals ENP230(2) {0, ..., k-1} and NFET selection signals ENN230(2) {0, ..., k-1} from the controller 206, which are group-specific and PUDI-specific within the group. The controller 206 selects the PUDIs based on the lineup it determines for the PUDI group 230(2) (see Figure 3A{0,..., k-1} and ENN230(2) {0,..., k-1} are configured to be in an enabled or non-enabled state, respectively, in accordance with the lineup determined by controller 206 for PUDI group 230(2) (see Table 2).

[0062] PUDI group 230(3) includes q PUDIs, namely PUDI(0),..., PUDI(q-1), coupled in parallel between nodes nd13 and nd14, where q is a positive integer. In some embodiments, q = 8. The PUDIs of PUDI group 230(3) are configured to receive PFET select signals ENP230(3) {0,..., q-1} and NFET select signals ENN230(3) {0,..., q-1} from controller 206, respectively, which are group-specific and PUDI-specific within the group. Controller 206 configures signals ENP230(3) {0,..., q-1} and ENN230(3) {0,..., q-1} to be in an enabled or non-enabled state, respectively, in accordance with the lineup determined by controller 206 for PUDI group 230(3) (see Table 3). Figure 3A

[0063] PUDI group 230(4) includes n PUDIs, namely PUDI(0),..., PUDI(n-1), coupled in parallel between nodes nd14 and nd15, where n is a positive integer. In some embodiments, n = 8. The PUDIs of PUDI group 230(4) are configured to receive PFET select signals ENP230(4) {0,..., n-1} and NFET select signals ENN230(4) {0,..., n-1} from controller 206, respectively, which are group-specific and PUDI-specific within the group. Controller 206 configures signals ENP230(4) {0,..., n-1} and ENN230(4) {0,..., n-1} to be in an enabled or non-enabled state, respectively, in accordance with the lineup determined by controller 206 for PUDI group 230(4) (see Table 4). Figure 3A

[0064] In Figure 2 each of active inductors 236(1)-236(4) includes a PUDI group and a resistor, respectively. The PUDIs of each of active inductors 236(1)-236(4) are Figure 1B ​​An example of a primary PUDI (i) 108. Active inductor 236(1) includes a PUDI group 230(11) and a resistor 238(11). Resistor 238(11) and the PUDIs of PUDI group 230(11) are coupled in parallel between nodes nd21 and nd22. Node nd22 is coupled to node nd12. PUDI group 230(11) contains p PUDIs, namely PUDI(0),..., PUDI(p-1), where p is a positive integer. In some embodiments, p = 4.

[0065] The PUDIs of PUDI group 230(11) are configured to receive PFET select signals ENP230(11) {0,...,p-1} and NFET select signals ENN230(11) {0,...,p-1} from controller 206, respectively, which are group-specific and PUDI-specific within the group. Controller 206 configures signals ENP230(11) {0,...,p-1} and ENN230(11) {0,...,p-1} to be in an enabled or non-enabled state, respectively, according to the lineup it determines for PUDI group 230(11) (see Figure 3A ).

[0066] Active inductors 236(2)-236(4) (discussed below) are replicas of active inductor 236(1). The PUDI groups in active inductors 236(2)-236(4) are replicas of PUDI group 230(11). The resistors in active inductors 236(2)-236(4) are replicas of resistor 238(11).

[0067] Active inductor 236(2) includes a PUDI group 230(12) and a resistor 238(12). Resistor 238(12) and the PUDIs of PUDI group 230(12) are coupled in parallel between nodes nd23 and nd24. Node nd24 is coupled to node nd13. PUDI group 230(12) contains p PUDIs, namely PUDI(0),..., PUDI(p-1).

[0068] The PUDIs of PUDI group 230(12) are configured to receive PFET select signals ENP230(12) {0,...,p-1} and NFET select signals ENN230(12) {0,...,p-1} from controller 206, respectively, which are group-specific and PUDI-specific within the group. Controller 206 configures signals ENP230(12) {0,...,p-1} and ENN230(12) {0,...,p-1} to be in an enabled or non-enabled state, respectively, according to the lineup it determines for PUDI group 230(12) (see Figure 3A), configure the signals ENP230(12){0, ..., p-1} and ENN230(12){0, ..., p-1} to be in an enabled or disabled state respectively.

[0069] Active inductor 236(3) includes a PUDI group 230(13) and a resistor 238(13). Resistor 238(13) and the PUDI of PUDI group 230(13) are coupled in parallel between nodes nd25 and nd26. Node nd26 is coupled to node nd14. PUDI group 230(13) includes p PUDIs, namely, PUDI(0), ..., PUDI(p-1).

[0070] The PUDIs of the PUDI group 230 (13) are configured to receive the PFET selection signals ENP 230 (13) {0, ..., p-1} and NFET selection signals ENN 230 (13) {0, ..., p-1}, which are group-specific and PUDI-specific within the group, from the controller 206, respectively. The controller 206 selects the PUDIs according to the lineup it determines for the PUDI group 230 (13) (see Figure 3A ), configure the signals ENP230(13){0, ..., p-1} and ENN230(13){0, ..., p-1} to be in an enabled or disabled state respectively.

[0071] Active inductor 236(4) includes a PUDI group 230(14) and a resistor 238(14). Resistor 238(14) and the PUDI of PUDI group 230(14) are coupled in parallel between nodes nd27 and nd28. Node nd28 is coupled to node nd15. PUDI group 230(14) includes p PUDIs, namely PUDI(0), ..., PUDI(p-1).

[0072] The PUDIs of the PUDI group 230 (14) are configured to receive the PFET selection signals ENP 230 (14) {0, ..., p-1} and NFET selection signals ENN 230 (14) {0, ..., p-1}, which are group-specific and PUDI-specific within the group, from the controller 206, respectively. The controller 206 selects the PUDIs according to the lineup it determines for the PUDI group 230 (14) (see Figure 3A ), configure the signals ENP230(14){0, ..., p-1} and ENN230(14){0, ..., p-1} to be in an enabled or disabled state respectively.

[0073] According to another system approach, a counterpart of the PUDI-based CTLE 202 is an inverter-based CTLE. This counterpart CTLE includes groups of tri-state inverters coupled in parallel, which correspond to the groups of PUDIs in the PUDI-based CTLE 202, e.g., 230(1). The tri-state inverters of the counterpart CTLE are examples of the tri-state inverters according to another system approach (as described above). Another system approach attempts to reduce the effects of process, voltage, temperature and aging (PVTA) variations on the counterpart CTLE by adjusting the overall ground reference voltage (i.e., VSS) of all the counterpart inverter groups. However, according to another system approach, not all of the counterpart inverter groups exhibit the same degree of PVTA variations. Therefore, the CTLE-level precision (granularity) according to another system approach limits the overall effectiveness of the counterpart CTLE in reducing the effects of PVTA variations. In contrast, the controller 206 not only provides group-level precision (granularity) by using group-specific PFET select signals and NFET select signals, but also provides PUDI-level precision (granularity) by using PUDI-specific PFET select signals within a group and PUDI-specific NFET select signals within a group. Therefore, the PUDI-based CTLE 202 achieves more precise (finer-granularity) control and thus better performance in reducing the effects of PVTA variations than the CTLE-level precision (granularity) provided by the counterpart inverter-based CTLE in another system approach.

[0074] Regardless of the high-impedance mode, according to another system approach, all of the counterparts to the elements from P12 in the PUD(i)s 108 and all of the counterparts to the elements from N11 are enabled to operate and thus consume power accordingly. In contrast, the PUDI-based CTLE 202 typically has a CTLE-level lineup of fewer than all of the slave PFETs and slave NFETs on the CTLE-level roster and thus fewer than all of the slave PFETs and slave NFETs consume power accordingly. As a result, the PUDI-based CTLE 202 typically consumes less power than the counterpart CTLE in another system approach.

[0075] Figure 3A is a schematic diagram of a PFET & NFET lineup setter 304 according to some embodiments.

[0076] The lineup setter 304 is Figure 1AOne example of a lineup setter 104. Thus, in some embodiments, the lineup setter 304 is included in a PUDI-based system, such as the system 100 of Figure 1A In embodiments of these systems, the lineup setter 304 coexists with a PUDI-based continuous-time linear equalizer (CTLE), such as the CTLE 102 of Figure 1A

[0077] For a given PUDI group having a roster of all slave PFETs and all slave NFETs in the group, the lineup setter 304 is configured to select which, if any, of the slave PFETs and / or slave NFETs on the roster are to be enabled for operation, i.e., to determine / set a lineup of slave PFETs and / or slave NFETs selected from the roster. The lineup determined by the lineup setter 304 is executed by a corresponding PUDI-based CTLE, such as the PUDI-based CTLE 102, which is also included in the PUDI-based system 100 of Figure 1A

[0078] The lineup setter 304 includes: PUDI groups 330(1)-330(4); a multiplexer (MUX) 340; a double-pole double-throw (DPDT) switch circuit 342A; a comparator 332; a multiplexer 334; a voltage generator 336 and controller 306; and a controller 306. Each PUDI in the PUDI groups 330(1)-330(4) is an example of a PUDI(i) 108 in the PUDI group 230 of Figure 1B The controller 306 is an example of the controller 306 in Figure 1A For brevity, in the following description, double-pole double-throw switch circuits will be referred to as DPDTs, e.g., the double-pole double-throw switch circuit 342A will be referred to as the DPDT 342A in the following description.

[0079] The PUDI groups 330(1)-330(4) are corresponding copies (or clones) of PUDI groups in a corresponding PUDI-based CTLE. For example, the PUDI groups 330(1)-330(4) are corresponding copies of the PUDI groups 230(1)-230(4) of the CTLE 202 in Figure 2 Thus, each PUDI in the groups 330(1)-330(4) is an example of a PUDI(i) 108 in the PUDI group 230 of Figure 1B ​​Examples of PUDI(i) 108. Likewise: PUDI group 330(1) contains j PUDIs; PUDI group 330(2) contains k PUDIs; PUDI group 330(3) contains q PUDIs; and PUDI group 330(4) contains n PUDIs. PUDI group 330(5) represents Figure 2 replicas (or clones) of each of PUDI groups 230(11)-230(14) of CTLE 202. Thus, the PUDIs in group 330(5) are Figure 1B Examples of PUDI(i) 108. Likewise: PUDI group 330(5) contains p PUDIs.

[0080] DPDT 342A (see Figures 3B-3D ) includes first and second inputs and first and second outputs. The first input of DPDT 342A is connected to node nd31, where node nd31 has reference voltage VREF (discussed below in the context of voltage generator 336 and multiplexer 334). The second input of DPDT 342A is connected to the output of multiplexer 340. The first and second outputs of DPDT 342A are connected to the non-inverting and inverting inputs, respectively, of comparator 332. The output of comparator 332 is connected to an input of controller 306.

[0081] Multiplexer 340 has five inputs, corresponding to the outputs connected to PUDI groups 330(1)-330(5), respectively. The input of each of PUDI groups 330(1)-330(5) is connected to node nd31.

[0082] Multiplexer 340 is configured to receive a selection signal SEL_1 from controller 306, according to which multiplexer 340 is controlled to switch / provide the output of one of PUDI groups 330(1)-330(5) to the second input of DPDT 342A.

[0083] PUDI groups 330(1)-330(5) are configured to receive respective PFET selection signals ENP330(Θ) {0,...,Φ-1} and NFET selection signals ENN330(Θ) {0,...,Φ-1} from controller 306, where Θ and Φ are respective positive integers, Θ = {0, 1, 2, 3, 4, 5} and Φ = {j, k, q, n, p}. For example, PUDI group 330(1) receives signals ENP330(1) {0,...,j-1} and NFET selection signals ENN330(1) {0,...,j-1}.

[0084] DPDT 342A is configured to receive switch control signals sw_EN and sw_ENB from controller 306. Depending on signals sw_EN and sw_ENB, DPDT 342A is controlled (see Figures 3B-3D ) to route signals in one of two ways, referred to as an alpha routing mode and a beta routing mode. In some embodiments, the alpha and beta modes are described as being invoked by controller 306. In the alpha mode, the first and second inputs of DPDT 342A are connected to the first and second outputs of DPDT 342A, respectively. In the beta mode, the first and second inputs of DPDT 342A are connected to the second and first outputs of DPDT 342A, respectively. In some embodiments, the beta mode is described as being the inverse of the alpha mode. The alpha and beta modes are mutually exclusive.

[0085] Before discussing other aspects of Figure 3A , we will consider DPDT 342A in more detail by discussing Figures 3B-3D .

[0086] Figure 3B and 3C are respective schematic diagrams of DPDT 342B according to some embodiments.

[0087] DPDT 342B is Figure 3A an example of DPDT 342A in Figures 3A-3B . Signal paths for alpha mode 338B and beta mode 338C of DPDT 342B are illustrated, respectively.

[0088] In alpha mode 338B of Figure 3B , signals sw_EN and sw_ENB are configured to be in the enabled state and the disabled state, respectively. In the alpha mode, VREF is coupled to the inverting input of comparator 332, while the output of multiplexer 340 is coupled to the non-inverting input of comparator 332.

[0089] In beta mode 338C of Figure 3C , signals sw_EN and sw_ENB are configured to be in the disabled state and the enabled state, respectively. In the beta mode, VREF is coupled to the non-inverting input of comparator 332, while the output of multiplexer 340 is coupled to the inverting input of comparator 332.

[0090] Figure 3D is a transistor-level schematic diagram of DPDT 342D according to some embodiments.

[0091] DPDT 342D is Figure 3AOne example of DPDT 342A. DPDT 342D includes N-type metal-oxide-semiconductor field-effect transistors (NFETs) N31, N32, N33, and N34. In some embodiments, one or more of the NFETs N31-N34 are replaced with corresponding P-type metal-oxide-semiconductor field-effect transistors (PFETs) P31-P34 (not shown in the figure).

[0092] NFET N31 is coupled between node nd31 and the non-inverting input of comparator 332. Again, node nd31 has voltage VREF. NFET N32 is coupled between node nd31 and the inverting input of comparator 332. NFET N33 is coupled between the output of multiplexer 340 and the non-inverting input of comparator 332. NFET N34 is coupled between the output of multiplexer 340 and the inverting input of comparator 332. The gate terminals of NFETs N32 and N33 are each configured to receive signal sw_EN. The gate terminals of NFETs N31 and N34 are each configured to receive signal sw_ENB.

[0093] Returning to the discussion of Figure 3A , the VREF value selected by controller 306, i.e., the VREF value received at the first input of DPDT 342A and at the input of each PUDI group 330(1)-330(5), depends on whether lineup setter 304 is operating in a tight-coupling scenario or a non-tight-coupling scenario.

[0094] It is recalled that, in some embodiments, (i) lineup setter 304 is included in a PUDI-based system, such as PUDI-based system 100 of Figure 1A , and (ii) system 100 is included in a lineup setting system, such as lineup setting system 200 of Figure 1CIn these system embodiments, the cast setter 304 coexists with a PUDI-based continuous-time linear equalizer (CTLE) (e.g., 102). In these embodiments, the chiplets 118(1) and 118(2) are either tightly coupled or non-tightly coupled. Accordingly, the voltage generator 336 and the multiplexer 334 are included in the cast setter 304 to accommodate (i) the case where the chiplets 118(1) and 118(2) are tightly coupled, or (ii) the case where the chiplets 118(1) and 118(2) are non-tightly coupled. Since both the tightly coupled and non-tightly coupled scenarios are subject to process, voltage, temperature and aging (PVTA) variations (as described above), the inclusion of the voltage generator 336, the multiplexer 334, and the associated functions of the controller 306, in part, explain why the cast setter 304 is described as having PVTA adaptability.

[0095] The voltage generator 336 is configured to receive a reference voltage V_chpl from the first chiplet, e.g., the chiplet 118(1), and a reference voltage V_chp2 from the second chiplet, e.g., the chiplet 118(2), where the cast setter 304 is included in the second chiplet. The voltage generator 336 is configured to generate the reference voltages Vref_upr, Vref_mid, and Vref_lwr. Figure 1A Figure 1A The voltage generator 336 is configured to receive a reference voltage V_chpl from the first chiplet, e.g., the chiplet 118(1), and a reference voltage V_chp2 from the second chiplet, e.g., the chiplet 118(2), where the cast setter 304 is included in the second chiplet. The voltage generator 336 is configured to generate the reference voltages Vref_upr, Vref_mid, and Vref_lwr.

[0096] The multiplexer 334 is configured to receive the voltages Vref_upr, Vref_mid, and Vref_lwr from the voltage generator 336. The multiplexer 334 is configured to receive a selection signal SEL_2 from the controller 306, which controls the multiplexer 334 to switch / provide one of the voltages Vref_upr, Vref_mid, and Vref_lwr to the node nd31, in accordance with the signal.

[0097] ​With respect to the non-tightly coupled scenario, in some embodiments, the controller 306 is configured to select the value of VREF in the following manner: when determining the lineup of PUDI group 330(1), VREF is set equal to Vref upr; when determining the lineup of PUDI group 330(2), VREF is set equal to Vref lwr; and when determining the lineup of each of PUDI groups 330(3)-330(5), VREF is set equal to Vref mid. In some embodiments, the use of Vref upr for PUDI group 330(1) and Vref lwr for PUDI group 330(2) is described more particularly as an accommodation for the difference between Vchpl and Vchp2.

[0098] A first example of the non-tightly coupled scenario is that Vchpl is approximately 0.85 volts and Vchp2 is approximately 0.75 volts. With respect to the first example, in some embodiments, the voltage generator 336 is configured to generate Vref upr, Vref mid, and Vref lwr in the following manner: Vref upr = (Vchp2 / 2) + (Vchpl - Vchp2) / 4;

[0099] Vref mid = (Vchp2 / 2);

[0100] Vref lwr = (Vchp2 / 2) - (Vchpl - Vchp2) / 4.

[0101] With respect to the first example of the non-tightly coupled scenario, in some embodiments, the voltage generator 336 is configured to swap the calculations of Vref upr and Vref lwr, thereby generating Vref upr, Vref mid, and Vref lwr in the following manner:

[0102] Vref upr = (Vchp2 / 2) - (Vchpl - Vchp2) / 4;

[0103] Vref mid = (Vchp2 / 2);

[0104] Vref lwr = (Vchp2 / 2) + (Vchpl - Vchp2) / 4.

[0105] A second example of the non-tightly coupled scenario is that Vchpl is approximately 0.75 volts and Vchp2 is approximately 0.65 volts. With respect to the second example, in some embodiments, the voltage generator 336 is configured to generate Vref upr, Vref mid, and Vref lwr in the following manner: Vref upr = (Vchp2 / 2) + (Vchpl - Vchp2) / 3;

[0106] Vref mid = (Vchp2 / 2);

[0107] Vref lwr = (Vchp2 / 2) - (Vchp1-Vchp2) / 3.

[0108] With respect to the second example of a non-tightly coupled scenario, in some embodiments, the voltage generator 336 is configured to swap the roles of Vref upr and Vref lwr, such that Vref upr, Vref mid, and Vref lwr are generated in the following manner:

[0109] Vref upr = (Vchp2 / 2) - (Vchp1-Vchp2) / 3;

[0110] Vref mid = (Vchp2 / 2);

[0111] Vref lwr = (Vchp2 / 2) + (Vchp1-Vchp2) / 3.

[0112] With respect to a tightly coupled scenario, Vchp1 is substantially equal to Vchp2, such that the Vref mid version based on Vchp1 is substantially equal to the Vref mid version based on Vchp2. In some embodiments, the controller 306 is configured to select VREF equal to Vref mid when determining the lineup for each of the PUDI groups 330(1)-330(5). In some embodiments, the voltage generator 336 is configured to generate Vref mid = (Vchp2 / 2). In some embodiments, the voltage generator 336 is configured to generate Vref mid = (Vchp1 / 2).

[0113] To determine the lineup for a given one of the PUDI groups 330(1)-330(5), referred to herein as group 330(x), the operations of the controller 306 will be described in terms of the method 404 in the flowchart of Figure 4A and the method 420 of Figure 4B .

[0114] The lineup produced by the PUDI-based CTLE 304 represents not only group-level precision (granularity) because the lineup is specific to the PUDI group. In addition, the lineup produced by the PUDI-based CTLE 304 also represents PUDI-level precision (granularity) because the lineup facilitates the production of PUDI-specific PFET select signals and PUDI-specific NFET select signals within the group. Thus, the lineup setter 304 enables more precise (finer-granularity) control compared to the CTLE-level precision (granularity) provided by other system approaches, resulting in better performance (in terms of reducing the impact of PVTA variation). The corresponding PVTA compensator attempts to adjust VSS using a high-speed VSS management circuit that contains a high-frequency ring oscillator. According to other system approaches, the high-frequency nature of the VSS management circuit: occupies a large area (has a large footprint); and suffers from high-oscillation-related current consumption. In contrast, the lineup setter 304 is not oscillator-based, and thus: occupies significantly less area (has a significantly smaller footprint) compared to the corresponding PVTA compensator of other system approaches; and suffers from significantly less oscillation-related current consumption compared to the corresponding PVTA compensator of other system approaches.

[0115] FIG. 4A is a flowchart of a method 404, according to some embodiments.

[0116] The method 404 is an example of a method for the controller 306 (as shown in FIG. 3A) to determine a lineup of the PUDI group 330(x) (as described above). The method 404 includes blocks 406-414. The flow of the method 404 starts at block 406.

[0117] At block 406, the alpha mode is initiated for the DPDT 324A (as described above). From block 406, the flow proceeds to block 408.

[0118] At block 408, an alpha lineup (a-lineup) of the group 330(x) is determined when the DPDT 324A is in the alpha mode. The a-lineup is an intermediate lineup. The determination of the a-lineup of the group 330(x) at block 408 is a recursive process. Block 408 will be discussed in more detail in the context of FIG. 4B. From block 408, the flow proceeds to block 410.

[0119] At block 410, the beta mode is initiated for the DPDT 324A (as described above). From block 410, the flow proceeds to block 412.

[0120] At block 412, a beta lineup (β-lineup) for pod 330(x) is determined when DPDT 324A is in beta mode. The β-lineup is an intermediate lineup. Determining the β-lineup for pod 330(x), block 412, is a recursive process similar to determining the a-lineup for pod 330(x). Block 412 will be discussed in more detail in the context of FIG. 4B. From block 412, flow proceeds to block 414.

[0121] At block 414, a final lineup for pod 330(x) is determined based on the a-lineup and the β-lineup. Typically, the a-lineup and the β-lineup will agree, and thus they will be the same. However, in some cases, a disagreement can arise, such that the a-lineup differs from the β-lineup. In some embodiments, when a disagreement arises, the intermediate lineup containing more slave PFETs and slave NFETs is adopted as the final lineup for pod 330(x). In these embodiments, if the a-lineup contains more slave PFETs and slave NFETs than the β-lineup, then the a-lineup is adopted as the final lineup for pod 330(x). If the β-lineup contains more slave PFETs and slave NFETs than the a-lineup, then the β-lineup is adopted as the final lineup for pod 330(x).

[0122] FIG. 4B is a flowchart of a method 420, according to some embodiments.

[0123] Method 420 is an example of a method by which controller 306 operates to determine an intermediate lineup for PUDI-pod 330(x) (as described above) in FIG. 3A. Thus, method 420 is an example of block 408 or 412 in FIG. 4A, or the like. Method 420 is used in both alpha mode and beta mode. In alpha mode (as described above), the intermediate lineup determined by method 420 is the a-lineup, or the like. In beta mode (as described above), the intermediate lineup determined by method 420 is the β-lineup, or the like.

[0124] Method 420 includes blocks 422-434. Flow according to method 420 begins at block 422.

[0125] At block 422, an initial configuration of candidate lineups is selected. Examples of initial configurations of candidate lineups will be discussed below.

[0126] Method 420 generally proceeds in the following order: block 424 -> block 426 -> block 432 -> block 434, as described below. After exiting block 422, method 420 begins its first iteration, such that the iteration count γ is γ = 1, where γ is a positive integer. From block 422, flow proceeds to block 424.

[0127] At block 424, the selection signals are configured in accordance with the candidate configuration. More specifically, the P-type field effect transistor selection signals ENP330(x) {0,..., Φ-1} are configured as P-type field effect transistor enabled or P-type field effect transistor disabled, respectively, in accordance with the candidate configuration, while the N-type field effect transistor selection signals ENN330(x) {0,..., Φ-1} are configured as N-type field effect transistor enabled or N-type field effect transistor disabled, respectively, in accordance with the candidate configuration. Examples of selection signal configurations will be discussed in the context of FIG. 4C. From block 424, flow proceeds to block 426.

[0128] At block 426, which is a decision block, it is determined whether comparator 332 indicates that the voltage at its non-inverting input is equal to or greater than the voltage at its inverting input, i.e., whether the output of comparator 332 represents a logic high (logic 1). In alpha mode (as described above), the output of multiplexer 340 and VREF correspond to the non-inverting and inverting inputs of comparator 332, respectively. In beta mode (as described above), VREF and the output of multiplexer 340 correspond to the non-inverting and inverting inputs of comparator 332, respectively.

[0129] If the decision at block 426 is negative, then flow proceeds to block 428. However, if the decision at block 426 is positive, then flow proceeds to block 432.

[0130] In other words, if it is determined at block 426 that the voltage at the non-inverting input is actually less than the voltage at the inverting input, such that the output of comparator 332 actually represents a logic low (logic 0), then flow proceeds to block 428. However, if it is determined at block 426 that the voltage at the non-inverting input is actually greater than the voltage at the inverting input, such that the output of comparator 332 actually represents a logic high (logic 1), then flow proceeds to block 432.

[0131] At block 428, the intermediate configuration is set up / established. However, the current candidate configuration, i.e., the (γ)th candidate configuration, is not used as the intermediate configuration. Rather, the (γ-1)th candidate configuration is employed as the intermediate configuration. In alpha mode (as described above), the intermediate configuration being determined is the α-configuration. In beta mode (as described above), the intermediate configuration being determined is the β-configuration. From block 428, flow proceeds to block 430, where flow stops.

[0132] At block 432, the candidate lineup is modified to produce a modified version thereof. The candidate lineup is modified in a manner that will reduce the output of the programmable unit driver current group 330(x), even if the voltage received at the non-inverting input of the comparator 332 is less than the voltage received at the inverting input of the comparator 332. From block 432, the flow proceeds to block 434.

[0133] At block 434, the (γ+1)th candidate lineup is generated by overwriting the (γ)th candidate lineup with the modified version. From block 434, the process loops back to block 424, resulting in another recursion of blocks 424-426.

[0134] In some embodiments, the recursive process of FIG. 4B is based on the assumption that the recursion progresses from a smaller candidate lineup to a larger candidate lineup. The candidate lineup is represented as 330(x)(Σ_PFET, Σ_NFET), where Σ_PFET represents the number of enabled slave PFETs and Σ_NFET represents the number of enabled slave NFETs. In some embodiments, each programmable unit driver current-group (PUDI-group) is an instance of PUDI(i) 108 in FIG. 1B and, therefore, is subject to process, voltage, temperature, and aging variations (PVTA-variations): all instances of master P11 are substantially identical; all instances of slave P11 are substantially identical; all instances of slave N11 are substantially identical; and all instances of master N12 are substantially identical. In some embodiments, it is further assumed that the current driving / sourcing capability / capacity of slave P12 is less than the current driving / sourcing capability / capacity of slave N12. In some embodiments, the recursive process of FIG. 4B is based on one or more assumptions other than the assumption that the recursion progresses from a smaller candidate lineup to a larger candidate lineup.

[0135] In some embodiments, assuming that the recursion progresses from smaller candidate teams to larger candidate teams, the candidate team is modified in block 432 as follows. A determination is made: is Σ PFET equal to Σ NFET? If so, then Σ PFET is increased by 1, so that Σ PFET = Σ PFET + 1, resulting in the modified version of the candidate team mod_330(x)(Σ PFET, Σ NFET) as follows: mod_330(x)(Σ PFET, Σ NFET) = 330(x)(Σ PFET + 1, Σ NFET). If not, i.e., if Σ PFET ≠ Σ NFET, then Σ NFET is increased by 1, so that Σ NFET = Σ NFET + 1, resulting in the modified version of the candidate team as follows: mod_330(x)(Σ PFET, Σ NFET) = 330(x)(Σ PFET, Σ NFET + 1). In these embodiments, candidate teams for which Σ PFET < Σ NFET are not used, due to the assumptions that (1) the recursion progresses from smaller candidate teams to larger candidate teams, and (2) the current drive / source capability / capacity from P12 is less than the current drive / source capability / capacity from N12. Thus, in these embodiments, the case of Σ PFET ≠ Σ NFET means that Σ NFET < Σ PFET.

[0136] In some embodiments, assuming that the recursion progresses from smaller candidate teams to larger candidate teams, the initial configuration of the candidate team is set to 330(x)(Σ PFET = 1, Σ NFET = 0) in block 422. While 330(x)(Σ PFET = 0, Σ NFET = 0) is the smallest possible candidate team, when Σ PFET = 0 and Σ NFET = 0, the output of the group 330(x) will be substantially zero, and thus always less than VREF, resulting in unnecessary recursion. Thus, it is common to exclude the use of 300(x)(Σ PFET = 0, Σ NFET = 0) as the initial value in block 422.

[0137] In some embodiments, the recursive process of FIG. 4B is based on the assumption that recursion proceeds from larger candidate teams to smaller candidate teams. In these embodiments, the initial configuration of candidate teams is set to 330(x) (Σ PFET > 1, Σ NFET > 1) in block 422. In some embodiments, a positive integer minimum value min P is set for Σ PFET such that 0 < min P < Σ PFET. In some embodiments, this minimum value min P is referred to as a PFET guard band. In some embodiments, a positive integer minimum value min N is set for Σ NFET such that 0 < min N < Σ NFET. In some embodiments, this minimum value min N is referred to as a NFET guard band. In some embodiments, it is further assumed that the current driving / source capability / capacity from P12 is less than the current driving / source capability / capacity from N12, such that Σ NFET < Σ PFET (see discussion above). In some cases, when the (γ)th candidate team is 330(x) (Σ PFET > 1, Σ NFET = min N), such that the (γ + 1)th candidate team would otherwise be disallowed to become 330(x) (Σ PFET > 1, Σ NFET = (min N - 1)) in block 432, then the (γ)th candidate team 330(x) (Σ PFET > 1, Σ NFET = min N) is adopted as the intermediate team, and the flow proceeds to block 430 instead of block 434.

[0138] In some embodiments, the number of possible candidate teams σ is σ = (Φ**2). When method 420 is applied to group 330(5), i.e., group 330(5) is treated as group 330(x), then Φ = p. Likewise, when method 420 is applied to groups 330(1)-330(4), then Φ = j, Φ = k, Φ = q, and Φ = n, respectively. Similarly, when method 420 is applied to groups 330(1)-330(4), Φ = p.

[0139] FIG. 4C is a table 437 in accordance with some embodiments.

[0140] Table 437 is an example of how recursion of method 420 in FIG. 4B proceeds from smaller candidate teams to larger candidate teams in accordance with some embodiments. Table 37 assumes a scenario in which method 420 is applied to PUDI-group 330(5) of FIG. 3A. PUDI-group 330(5) contains 5 PUDIs, so group 330(5) contains 5 from PFET P12 instances and 5 from NFET N11 instances. FIG. 4B assumes that method 420 is performed for 6 of the possible 8 recursions.

[0141] With respect to the example of table 437, in the fifth iteration of method 420, i.e., iteration count γ = 5, the candidate team is 300(5) (Σ PFET = 3, Σ NFET = 2). In block 426, it is determined that the output of comparator 332 represents a logic high (logic one), i.e., the voltage at the non-inverting input of comparator 332 is equal to or greater than the voltage at its inverting input. Accordingly, flow proceeds along the YES exit / path of decision block 426 to block 432.

[0142] With respect to the example of table 437, in block 432, the current candidate team, i.e., 300(5) (Σ PFET = 3, Σ NFET = 2), is modified to mod_300(5) (Σ PFET = 3, Σ NFET = 2) = 300(5) (Σ PFET = 3, Σ NFET = 2 + 1). From block 423, flow proceeds to block 434. In block 434, the next candidate team, i.e., the (γ + 1)th candidate team, is generated by overwriting the (γ)th candidate team with the modified version, such that the candidate team for the sixth iteration (γ = 6) will be 300(5) (Σ PFET = 3, Σ NFET = 3). From block 434, flow loops back to block 424 to begin the sixth iteration (γ = 6).

[0143] With respect to the example of table 437, in the sixth (γ = 6) iteration of method 420, the candidate team is 300(5) (Σ PFET = 3, Σ NFET = 3). When flow reaches decision block 426, it is determined that the output of comparator 332 represents a logic low (logic zero), i.e., the voltage at the non-inverting input of comparator 332 is less than the voltage at its inverting input. Accordingly, flow proceeds along the 'NO' exit / path of decision block 426 to block 428.

[0144] With respect to the example of table 437, in the sixth (γ = 6) iteration of method 420, the intermediate team is set / established in block 428. However, the current candidate team, i.e., the (γ = 6)th candidate team, is not used as the intermediate team. Rather, the (γ - 1 = 5)th candidate team is employed, such that the intermediate team is set to 300(5) (Σ PFET = 3, Σ NFET = 2). From block 428, flow proceeds to block 430, where flow stops. Accordingly, the seventh and eighth iterations of method 420 are not performed for the example of table 437.

[0145] FIG. 5 is a flowchart of a method 504 of operating a programmable up-down inductor (PUDI), according to some embodiments.

[0146] One example of a programmable up-down inductor (PUDI) operated according to the method 504 is a PUDI(i) 108 in Figure 1B or a similar device.

[0147] The method 504 includes a block 504-532. In the block 506, a main PFET and a slave PFET are coupled in parallel between a first reference voltage and an output node of the PUDI. One example of the main PFET is a main P11 in Figure 1B or a similar device. One example of the slave PFET is a slave P12 in Figure 1B or a similar device. One example of the first reference voltage is VDD or a similar voltage. One example of the output node of the PUDI is an output node OUT in Figure 1B or a similar node. From the block 506, the flow proceeds to a block 508.

[0148] In the block 508, a slave NFET and a main NFET are coupled in parallel between the output node and a second reference voltage. One example of the slave NFET is a slave N11 in Figure 1B or a similar device. One example of the main NFET is a main N12 in Figure 1B or a similar device. One example of the second reference voltage is VSS or a similar voltage. From the block 508, the flow proceeds to a block 510.

[0149] In the block 510, a control input of each of the slave PFET and the slave NFET is coupled to an input node of the PUDI. One example of the input node of the PUDI is an input node IN in Figure 1B or a similar node. From the block 510, the flow proceeds to a block 512.

[0150] In the block 512, a control input of the main PFET is configured to receive a PFET selection signal. One example of the control input of the main PFET is a gate terminal of the main P11 in Figure 1B or a similar terminal. One example of the PFET selection signal is a signal ENP(i) in Figure 1B or a similar signal. From the block 512, the flow proceeds to a block 514.

[0151] In the block 514, a control input of the main NFET is configured to receive a NFET selection signal. One example of the control input of the main NFET is a gate terminal of the main N12 in Figure 1B or a similar terminal. One example of the NFET selection signal is a signal ENN(i) in Figure 1B or a similar signal. From the block 514, the flow proceeds to a block 516.

[0152] In block 516, PUDI group lineup setting is performed, including lineup setting of PUDI(i) in the PUDI group. One example of PUDI group lineup setting is 300(5)(∑_PFET=3,∑_NFET=2), as discussed in the example of Figure 4C , or similar settings.

[0153] Block 516 includes blocks 518, 522, 524, and 530. Depending on the lineup setting of PUD(i), flow enters one of blocks 518, 522, 524, and 530 from block 516. From each of blocks 518, 522, 524, and 530, flow exits block 516 and loops back to the entrance of block 516. In some embodiments, this looping through block 516 is in response to a change in lineup setting, e.g., a signal being sent by a corresponding lineup setter (e.g., 102 in Figure 1A ) to a corresponding PUDI-based CTLE system (e.g., 102 in Figure 1A ).

[0154] In block 518, PUDI(i) is controlled to operate as an inverter. Block 518 includes block 520. In block 520, the PFET select signal of the main PFET and the NFET select signal of the main NFET are set to PFET enabled state and NFET enabled state, respectively. Flow proceeds from block 520 to exit block 516.

[0155] In block 522, PUDI(i) is controlled to operate as a pull-up device. Block 522 includes block 524. In block 524, the PFET select signal of the main PFET and the NFET select signal of the main NFET are set to PFET enabled state and NFET disabled state, respectively. Flow proceeds from block 522 to exit block 516.

[0156] In block 526, PUDI(i) is controlled to operate as a pull-down device. Block 526 includes block 528. In block 528, the PFET select signal of the main PFET and the NFET select signal of the main NFET are set to PFET disabled state and NFET enabled state, respectively. Flow proceeds from block 528 to exit block 516.

[0157] In block 530, PUDI(i) is controlled to represent a high impedance state. Block 530 includes block 532. In block 532, the PFET select signal of the main PFET and the NFET select signal of the main NFET are set to PFET disabled state and NFET disabled state, respectively. Flow proceeds from block 532 to exit block 516.

[0158] Figure 5The flowchart of the method 504 shows the order of the blocks 506-512 as follows: block 506→block 508→block 510→block 512→block 514. In some embodiments, the blocks 506-514 can have other orders than the above-mentioned order.

[0159] Figure 6 is a flowchart of a PUDI-based CTLE operation method 604 according to some embodiments.

[0160] An example of a PUDI-based CTLE operating according to the method 504 is Figure 1A the CTLE 102 of Figure 2 the CTLE 202 or the like. The method 604 includes blocks 606-620. In block 606, a plurality of PUDIs of a group of PUDIs (PUDI group) are coupled in parallel. An example of a PUDI is Figure 1A the PUDI(i) 108 of Figure 2 the PUDI group 230(1) of or the like. From block 606, the flow proceeds to block 608.

[0161] In block 608, a data input of each PUDI of the PUDI group is coupled to a first node representing an input of the PUDI group. An example of a data input of a PUDI is Figure 1B the input node IN of the PUDI(i) 108 of Figure 2 the node nd11 of or the like. From block 608, the flow proceeds to block 610.

[0162] In block 610, a data output of each PUDI of the PUDI group is coupled to a second node representing an output of the PUDI group. An example of a data output of a PUDI is Figure 1B the output node OUT of the PUDI(i) 108 of Figure 2 the node nd12 of or the like. From block 610, the flow proceeds to block 612.

[0163] In block 612, an active inductor is coupled to the second node. An example of an active inductor is Figure 2 the active inductor 236(1) of or the like. It is recalled that the active inductor 236(1) includes the PUDI group 230(11) coupled in parallel to the resistor 238(11). From block 612, the flow proceeds to block 614.

[0164] In block 614, a first control input of the PUDI in the PUDI group is configured to receive a corresponding PUDI-specific first conductivity type (FCT) selection signal. With respect to the PUDI example provided in the context of block (e.g., 606), PUDI(i) 108, which includes a main PFET P11 and a main NFET N11, an example of the first conductivity type is P-type, and thus an example of the FCT selection signal is PFET selection signal ENP(i) or the like. From block 614, flow proceeds to block 616.

[0165] In block 616, a second control input of the PUDI in the PUDI group is configured to receive a corresponding PUDI-specific second conductivity type (SCT) selection signal. With respect to the PUDI example provided in the context of block (e.g., 606), PUDI(i) 108, which includes a main PFET P11 and a main NFET N11, an example of the second conductivity type is N-type, and thus an example of the SCT selection signal is NFET selection signal ENN(i) or the like. From block 616, flow proceeds to block 618.

[0166] In block 618, the FCT selection signal of the group is set to be in a FCT- enabled state or a FCT-non-enabled state, respectively. Examples of the FCT-enabled and FCT-non-enabled states of the FCT selection signal correspond to the PFET-enabled and PFET-non-enabled states of the signal ENP(i) in Figure 1B , or the like, respectively. From block 618, flow proceeds to block 620.

[0167] In block 620, the SCT selection signal of the group is set to be in a SCT- enabled state or a SCT-non-enabled state, respectively. Examples of the SCT-enabled and SCT-non-enabled states of the SCT selection signal correspond to the NFET-enabled and NFET-non-enabled states of the signal ENN(i) in Figure 1B , or the like, respectively.

[0168] In Figure 6 , method 604 shows the order of blocks 618-620 as follows: block 618→ block 620. In some embodiments, blocks 618-620 have an order that is the reverse of the above order, i.e., block 620→ block 618.

[0169] In Figure 6 , method 604 shows the order of blocks 618-620 as follows: block 618→ block 620. In some embodiments, blocks 618-620 have an order that is the reverse of the above order, i.e., block 620→ block 618.

[0170] FIG. 7 is a flowchart of a method 700 of fabricating a system or integrated circuit device, in accordance with some embodiments.

[0171] In accordance with some embodiments, the method 700 can be implemented, for example, using the EDA system 800 (FIG. 8, discussed below) and the integrated circuit (IC) fabrication system 900 (FIG. 9, discussed below). Examples of systems or integrated circuit devices that can be fabricated in accordance with the method 700 include the systems or integrated circuit devices disclosed herein, or the like.

[0172] In FIG. 7, the method of the flowchart 700 includes blocks 702-704. In block 702, a layout is generated, including one or more layouts corresponding to one or more systems or integrated circuit devices disclosed herein, or the like. In accordance with some embodiments, block 702 can be implemented using the EDA system 800 (FIG. 8, discussed below). From block 702, the flow proceeds to block 704.

[0173] In block 704, based on the layout, at least one of the following is performed: (A) one or more lithography exposures are performed, or (B) one or more semiconductor masks are fabricated, or (C) one or more components of a layer of a semiconductor device are fabricated. See the following discussion of the integrated circuit fabrication system 900 in FIG. 9, below.

[0174] FIG. 8 illustrates a block diagram of an electronic design automation (EDA) system 800, in accordance with some embodiments.

[0175] In some embodiments, the EDA system 800 includes an automatic placement and routing (APR) system. In some embodiments, the EDA system 800 is a general purpose computing device, including a hardware processor 802 and a non-transitory computer- readable storage medium 804. The storage medium 804 is encoded, among other things, to store computer program code 806, i.e., a set of executable instructions. The hardware processor 802 executing the instructions 806 represents (at least in part) an EDA tool that implements, in whole or in part, one or more embodiments, such as the methods of generating a layout disclosed herein, the methods of generating a layout as disclosed herein or a layout corresponding to an integrated circuit device disclosed herein, or the like (hereinafter referred to as the claimed processes and / or methods).

[0176] The storage medium 804 stores, among other things, a layout 811, such as a layout disclosed herein, or the like.

[0177] The processor 802 is electrically coupled to the computer-readable storage medium 804 via a bus 808. The processor 802 is also electrically coupled to the I / O interface 810 via the bus 808. The network interface 812 is also electrically connected to the processor 802 via the bus 808. The network interface 812 is connected to the network 814 so that the processor 802 and the computer-readable storage medium 804 can be connected to external elements via the network 814. The processor 802 is configured to execute the computer program code 806 encoded in the computer-readable storage medium 804 to make the EDA system 800 operable to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the processor 802 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0178] In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a hard disk drive, and / or a compact disk-read only memory (CD-ROM). In one or more embodiments using an optical disk, the computer-readable storage medium 804 includes a compact disk-read / write (CD-R / W) and / or a digital video disc (DVD).

[0179] In one or more embodiments, the storage medium 804 stores computer program code 806 configured to make the EDA system 800 (where such execution represents at least in part an EDA tool) operable to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 804 also stores information that facilitates performing part or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 804 stores a library of standard cells 807, which includes standard cells as disclosed herein. In some embodiments, the storage medium 804 stores one or more layout maps 811.

[0180] EDA system 800 includes I / O interface 810. I / O interface 810 is coupled to external circuits. In one or more embodiments, I / O interface 810 includes a keyboard, keypad, mouse, trackball, touchpad, touch screen, and / or cursor direction keys for communicating information and commands to processor 802.

[0181] EDA system 800 also includes network interface 812 coupled to processor 802. Network interface 812 allows EDA system 800 to communicate with network 814, to which one or more other computer systems are connected. Network interface 812 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as ETHERNET, USB, or IEEE- 1364. In one or more embodiments, portions or all of the processes and / or methods described are implemented in two or more EDA systems 800.

[0182] EDA system 800 is configured to receive information through I / O interface 810. The information received through I / O interface 810 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 802. The information is transferred to processor 802 via bus 808. EDA system 800 is configured to receive information related to a user interface (UI) through I / O interface 810. The information is stored in computer-readable medium 804 as UI 842.

[0183] In some embodiments, portions or all of the processes and / or methods described are implemented as a stand-alone software application executed by a processor. In some embodiments, portions or all of the processes and / or methods described are implemented as a software application that is part of an additional software application. In some embodiments, portions or all of the processes and / or methods described are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods described is implemented as a software application that is part of an EDA tool. In some embodiments, portions or all of the processes and / or methods described are implemented as a software application used by EDA system 800. In some embodiments, a layout including standard cells is generated using a tool such as CADENCE® Virtuoso® from CADENCE DESIGN SYSTEMS, INC. or another suitable layout generation tool.

[0184] ​In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of the following: an optical disc such as a DVD; a magnetic disc such as a hard drive; a semiconductor memory such as a ROM, RAM, a memory card; and the like.

[0185] Figure 9 is a block diagram of an integrated circuit (IC) manufacturing system 900 and an associated IC manufacturing process according to some embodiments.

[0186] In some embodiments, based on Figure 6 The IC manufacturing system 900 implements the layout diagram generated by block 602. Figure 7 Block 704 of the present invention includes fabricating at least one of the following items using the fabrication system 900: (A) one or more semiconductor masks or (B) at least one component in a layer of an unfinished semiconductor integrated circuit. In some embodiments, the IC fabrication system 900 implements Figure 7 Flowchart of the process.

[0187] exist Figure 9 In the present disclosure, IC manufacturing system 900 includes entities that interact with each other during the design, development, and manufacturing cycles and / or services related to manufacturing IC devices 960, such as design company 920, mask shop 930, and IC manufacturer / fab ("fab") 950. The entities in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of design company 920, mask shop 930, and IC fabrication fab 950 are owned by a single larger company. In some embodiments, two or more of design company 920, mask shop 930, and IC fabrication fab 950 coexist in a common facility and use common resources.

[0188] A design company (or design team) 920 produces an IC design layout 922. The IC design layout 922 includes various geometric patterns designed for the IC device 960. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up various elements of the IC device 960 to be fabricated. Various layers are combined to form various IC features. For example, a portion of the IC design layout 922 includes various IC features, such as active regions, gate terminals, source and drain, metal lines or vias for interlayer interconnects, and openings for bond pads, to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. A source / drain region can refer to a source or a drain, alone or collectively, depending on the context. The design company 920 implements appropriate design procedures to form the IC design layout 922. The design procedures include one or more of logic design, physical design, or layout routing. The IC design layout 922 is represented in one or more data files with information of geometric patterns. For example, the IC design layout 922 can be represented in a GDSII file format or a DFII file format.

[0189] The mask shop 930 includes data preparation 932 and mask production 934. The mask shop 930 uses the IC design layout 922 to fabricate one or more masks 935 that will be used to fabricate various layers of the IC device 960 according to the IC design layout 922. The mask shop 930 performs mask data preparation 932 in which the IC design layout 922 is converted to representative data files ("RDFs"). The mask data preparation 932 provides the RDFs to the mask production 934. The mask production 934 includes a mask writer. The mask writer converts the RDFs to an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The design layout is manipulated by the mask data preparation 932 to conform to specific characteristics of the mask writer and / or requirements of the IC fabrication facility 950. In some embodiments, the mask data preparation 932 and the mask production 934 are collectively referred to as mask data preparation. Figure 9 In some embodiments, the mask data preparation 932 and the mask production 934 are collectively referred to as mask data preparation.

[0190] In some embodiments, the mask data preparation 932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for imaging errors, such as those that can result from diffraction, interference, other process effects, and the like. The OPC adjusts the IC design layout 922. In some embodiments, the mask data preparation 932 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats the OPC as an inverse imaging problem.

[0191] In some embodiments, the mask data preparation 932 includes a mask rule checker (MRC), which checks the IC design layout that has been processed in the OPC against a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability of the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the IC design layout to compensate for limitations during the mask production 934, which can undo some of the modifications performed by the OPC in order to satisfy the mask creation rules.

[0192] In some embodiments, the mask data preparation 932 includes lithography process checking (LPC), which simulates the processing to be performed by the IC foundry 950 to manufacture the IC devices 960. The LPC simulates the processing based on the IC design layout 922 to manufacture a simulated manufactured device, such as the IC devices 960. The processing parameters in the LPC simulation can include parameters related to various processes of the IC manufacturing cycle, parameters related to tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or combinations thereof. In some embodiments, after the simulated manufactured device is manufactured by the LPC, if the shapes of the simulated device are not close enough to satisfy the design rules, then the OPC and / or the MRC are repeated to further refine the IC design layout 922.

[0193] It should be appreciated that the above description of reticle preparation 932 is simplified for clarity purposes. In some embodiments, reticle preparation 932 includes additional features such as logic operations (LOPs) to modify the IC design layout according to fabrication rules. Moreover, the processes applied to the IC design layout 922 during reticle preparation 932 can be performed in various different orders.

[0194] After reticle preparation 932 and during reticle production 934, a reticle 935 or a set of reticles 935 is manufactured based on the modified IC design layout. In some embodiments, based on the modified IC design layout, an electron-beam (e-beam) or multiple e-beams mechanism is used to form a pattern on a reticle (reticle or intermediate reticle). The reticle is formed in various technologies. In some embodiments, the reticle is formed using binary technology. In some embodiments, the reticle pattern includes opaque regions and transparent regions. A beam of radiation (e.g., a beam of ultraviolet (UV) light) used to expose a layer of image-sensitive material (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary reticle includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the reticle. In another example, the reticle is formed using phase shift technology. In a phase shift reticle (PSM), various features in the pattern formed on the reticle are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase shift reticle is an attenuated PSM or an alternating PSM. The reticle(s) generated by reticle production 934 are used for various processes. For example, such reticle(s) are used in ion implantation processes to form various doped regions in a semiconductor wafer, in etching processes to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0195] IC foundry 950 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC foundry 950 is a semiconductor foundry. For example, there can be one manufacturing facility for front-end manufacturing (Front-end-of-line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (Back-end-of-line (BEOL) manufacturing) for interconnection and packaging of the IC products, and a third manufacturing facility can provide other services for the foundry business.

[0196] IC fabrication facility 950 uses the mask (or masks) 935, manufactured by the mask shop 930, to fabricate integrated circuit devices 960 using fabrication tools 952. Thus, the IC fabrication facility 950 uses the IC design layout 922, at least indirectly, to fabricate integrated circuit devices 960. In some embodiments, a semiconductor wafer 953 is manufactured by the IC fabrication facility 950 using the mask (or masks) 935 to form integrated circuit devices 960. The semiconductor wafer 953 includes a silicon substrate or other suitable substrate having material layers formed thereon. The semiconductor wafer further includes one or more various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0197] In some embodiments, a system (for determining a starting lineup) includes: a comparator configured to compare between a reference voltage and an output of a population group; the population group includes pull-up-pull-down-inverters (PUDIs) coupled in parallel, each PUDI including master and slave positive-channel metal oxide semiconductor (PMOS) field-effect transistors (FETs) (PFETs) and slave and master negative-channel metal oxide semiconductor (NMOS) FETs (NFETs); for each PUDI, each control input of the slave PFET and slave NFET transistors is coupled to an input node of the PUDI, a control input of the master PFET transistor is configured to receive a PUDI-specific PFET select signal, and a control input of the master NFET transistor is configured to receive a PUDI-specific NFET select signal; a roster consisting of all slave PFETs and all slave NFETs in the population group; and (for the population group), a controller configured to evaluate a candidate lineup selected from the roster, the evaluation including: setting the PFET select signals of the population group to PFET- enabled or PFET-non-enabled states, respectively, setting the NFET select signals of the population group to NFET-enabled or NFET-non-enabled states, respectively; and performing an operation based on the comparison, including setting the starting lineup to the candidate lineup, or modifying the candidate lineup and repeating the evaluation and operation.

[0198] In some embodiments, the system further comprises a double-pole double-throw (DPDT) switching circuit configured to receive the reference voltage and the output of the subject group and having first and second outputs coupled to non-inverting and inverting inputs of the comparator, respectively, the DPDT switching circuit being further configured to: in a first mode, couple the first and second outputs of the DPDT switching circuit to (A) the reference voltage and (B) the output of the subject group, respectively, in accordance with an enabled state of a first mode signal; and in a second mode, couple the first and second outputs of the DPDT switching circuit to (B) the output of the subject group and (A) the reference voltage, respectively, in accordance with an enabled state of a second mode signal; and the controller is further configured to generate the first mode signal and the second mode signal.

[0199] In some embodiments, the subject group is included in a continuous-time-linear equalizer (CTLE).

[0200] In some embodiments, the double-pole double-throw (DPDT) switching circuit comprises: a first field effect transistor (FET) coupled between a first node and a non-inverting input of the comparator, the first node being configured to receive the reference voltage; a second FET coupled between the first node and an inverting input of the comparator; a third FET coupled between a second node and the non-inverting input of the comparator, the second node being configured to receive the output of the subject group; and a fourth FET coupled between the second node and the inverting input of the comparator; each control input of the first and fourth FETs being configured to receive the first mode signal; and each control input of the second and third FETs being configured to receive the second mode signal.

[0201] In some embodiments, in the first mode, the comparator is further configured to perform a first comparison to arrive at a first mode result; in the second mode, the comparator is further configured to perform a second comparison to arrive at a second mode result; the controller is further configured to: perform a first recursive evaluation of the candidate lineup in the first mode, perform a second recursive evaluation of the candidate lineup in the second mode, and perform an operation based on the first mode result and the second mode result.

[0202] In some embodiments, the system further comprises a first group of j programmable unit delay inverters (PUDIs) coupled in parallel, a second group of k programmable unit delay inverters (PUDIs) coupled in parallel, where k is a positive integer, j and k are respective positive integers and k < j, and a multiplexer. The multiplexer is configured to: receive outputs of the first group and outputs of the second group; and adaptively provide the outputs of the first group or the outputs of the second group as an output of a subject group to the comparator according to a selection signal. The controller is further configured to generate the selection signal.

[0203] In some embodiments, a method (of determining a starting lineup) comprises: selecting one from a plurality of pull-up-pull-down-inverter (PUDI) groups as a subject group, each PUDI comprising a main positive-channel metal oxide semiconductor (PMOS) field-effect transistor (FET) (PFET) and a slave PFET and a main negative-channel metal oxide semiconductor (NMOS) FET (NFET) and a slave NFET; coupling the PUDIs of the subject group in parallel; for each PUDI in the subject group, coupling each control input of the slave PFET and slave NFET transistors to an input node of the PUDI, configuring a control input of the main PFET transistor to receive a PUDI-specific PFET selection signal, and configuring a control input of the main NFET transistor to receive a PUDI-specific NFET selection signal; evaluating a candidate lineup for the subject group selected from a roster consisting of all slave PFETs and all slave NFETs in the subject group, the evaluating comprising setting the PFET selection signals to respective PFET-activated or PFET-inactivated states according to the candidate lineup, setting the NFET selection signals to respective NFET-activated or NFET-inactivated states according to the candidate lineup, and comparing a reference voltage and an output of the subject group using a comparator; and performing an operation based on a comparison result, comprising setting a starting lineup to the candidate lineup, or modifying the candidate lineup and repeating the evaluating and operation.

[0204] In some embodiments, the method further comprises: generating a first mode signal corresponding to the first mode; in the first mode, coupling (A) the output of the subject group and (B) the reference voltage to the non-inverting input and the inverting input, respectively, of the comparator in accordance with an enabled state of the first mode signal; generating a second mode signal corresponding to the second mode; and in the second mode, coupling (B) the reference voltage and (A) the output of the subject group to the non-inverting input and the inverting input, respectively, of the comparator in accordance with an enabled state of the second mode signal.

[0205] In some embodiments, the method further comprises: coupling a first field-effect transistor (FET) between a first node and the non-inverting input of the comparator; configuring the first node to receive the reference voltage; coupling a second FET between the first node and the inverting input of the comparator; coupling a third FET between a second node and the non-inverting input of the comparator; configuring the second node to receive the output of the subject group; coupling a fourth FET between the second node and the inverting input of the comparator; configuring each control input of the first and fourth FETs to receive the first mode signal; and configuring each control input of the second and third FETs to receive the second mode signal.

[0206] In some embodiments, the method further comprises: in the first mode, controlling the comparator to perform a first comparison to generate a first mode result; in the second mode, controlling the comparator to perform a second comparison to generate a second mode result; in the first mode, performing a first recursion on the evaluation candidate lineup; in the second mode, performing a second recursion on the evaluation candidate lineup; and performing the operation comprises performing the operation based on the first mode result and the second mode result.

[0207] In some embodiments, selecting one from a group of programmable unique device identifiers (PUDIs) comprises: receiving an output of a first group of j PUDIs coupled in parallel; receiving an output of a second group of k PUDIs coupled in parallel, where j and k are respective positive integers and k < j; generating a selection signal; and based on the selection signal, providing the output of the first group or the output of the second group as an output of a subject group to a comparator.

[0208] In some embodiments, the subject group represents a respective group of PUDIs contained in a continuous-time-linear equalizer (CTLE).

[0209] In some embodiments, a continuous-time-linear equalizer (CTLE) includes: a buffer having an output representative of an output of the CTLE; a first group of j pull-up-pull-down-inverters (PUDIs) coupled in parallel; a data input of each PUDI in the first group coupled to an input node of the CTLE; the first group coupled between the input node of the CTLE and an input of the buffer; a first active inductor coupled to output nodes of the first group; a first control input of each PUDI in the first group configured to receive a first conductivity type (FCT) selection signal specific to the corresponding PUDI; a second control input of each PUDI in the first group configured to receive a second conductivity type (SCT) selection signal specific to the corresponding PUDI; and a controller configured to perform operations including adaptively setting the FCT selection signals of the first group to be in a FCT enabled state or a FCT disabled state, respectively, and adaptively setting the SCT selection signals of the first group to be in a SCT enabled state or a SCT disabled state, respectively, wherein j and p are positive integers.

[0210] In some embodiments, p < j.

[0211] In some embodiments, each PUDI includes a positive-channel metal oxide semiconductor (PMOS) field-effect transistor (FET) and a negative-channel metal oxide semiconductor (NMOS) FET (NFET); a list of FETs of the first group consists of all PFETs and all NFETs in the first group; and the controller is further configured to perform operations including determining a starting lineup of FETs from the list of FETs of the first group, adaptively setting the FCT selection signals of the first group to be in a FCT enabled state or a FCT disabled state, respectively, according to the starting lineup, and adaptively setting the SCT selection signals of the first group to be in a SCT enabled state or a SCT disabled state, respectively, according to the starting lineup.

[0212] In some embodiments, the CTLE further comprises a second group of k PUDIs coupled in parallel and a second active inductor coupled to a second group output node; the first group and the second group are coupled in series between an input of the CTLE and an input of the buffer; a first control input of each PUDI in the second group is configured to receive a corresponding PUDI-specific FCT selection signal; a second control input of each PUDI in the second group is configured to receive a corresponding PUDI-specific SCT selection signal; and the controller is further configured to perform operations comprising adaptively setting the FCT selection signals of the second group to be in a FCT- enabled state or a FCT-non-enabled state, respectively, and adaptively setting the SCT selection signals of the second group to be in a SCT-enabled state or a SCT-non-enabled state, respectively, wherein k is a positive integer; k < j; and p < k.

[0213] In some embodiments, each PUDI comprises a positive-channel metal oxide semiconductor (PMOS) field-effect transistor (FET) and a negative-channel metal oxide semiconductor (NMOS) FET (NFET); a roster of FETs of the second group consists of all slave PFETs and all slave NFETs in the second group; and the controller is further configured to perform operations comprising determining a starting lineup of FETs from the roster of the second group, adaptively setting the FCT selection signals of the second group to be in a FCT-enabled state or a FCT-non-enabled state, respectively, according to the starting lineup, and adaptively setting the SCT selection signals of the second group to be in a SCT-enabled state or a SCT-non-enabled state, respectively, according to the starting lineup.

[0214] In some embodiments, the CTLE further comprises a third group of q PUDIs coupled in parallel and a third active inductor coupled to a third group output node; the first group, the second group, and the third group are coupled in series between an input of the CTLE and an input of the buffer; a first control input of each PUDI in the third group is configured to receive a corresponding PUDI-specific FCT selection signal; a second control input of each PUDI in the third group is configured to receive a corresponding PUDI-specific SCT selection signal; and the controller is further configured to perform operations comprising adaptively setting the FCT selection signals of the third group to be in a FCT-enabled state or a FCT-non-enabled state, respectively, and adaptively setting the SCT selection signals of the third group to be in a SCT-enabled state or a SCT-non-enabled state, respectively; wherein q is a positive integer; q < j; and p < q.

[0215] In some embodiments, each PUDI includes a positive-channel metal oxide semiconductor (PMOS) field-effect transistor (FET) and a negative-channel metal oxide semiconductor (NMOS) FET (NFET); a roster of FETs of the third group consists of all pass PFETs and all pass NFETs in the third group; and the controller is further configured to perform operations comprising: determining a starting lineup of FETs from the roster of the third group, adaptively setting the FCT select signals of the third group to be in the FCT enabled state or the FCT non-enabled state, respectively, in accordance with the starting lineup, and adaptively setting the SCT select signals of the third group to be in the SCT enabled state or the SCT non-enabled state, respectively, in accordance with the starting lineup.

[0216] In some embodiments, the first active inductor includes a second group of p PUDIs coupled in parallel, and a resistor coupled between a common input node of the p PUDIs and a common output node of the p PUDIs; each PUDI includes a positive-channel metal oxide semiconductor (PMOS) field-effect transistor (FET) and a negative-channel metal oxide semiconductor (NMOS) FET (NFET); a roster of FETs of the second group consists of all pass PFETs and all pass NFETs in the second group; and the controller is further configured to perform operations comprising: determining a starting lineup of FETs from the second group, adaptively setting the FCT select signals of the second group to be in the FCT enabled state or the FCT non-enabled state, respectively, in accordance with the starting lineup, and adaptively setting the SCT select signals of the second group to be in the SCT enabled state or the SCT non-enabled state, respectively, in accordance with the starting lineup.

[0217] One of ordinary skill in the art will readily see, after reading the foregoing specification, that various changes, substitutions, equivalents, and alterations can be made to the disclosed embodiments without departing from the scope of the application. It is intended that the following claims be interpreted to embrace all such changes, substitutions, equivalents, and alterations.

Claims

1. A system for determining a starting lineup in a roster, characterized in that: The system comprises: a comparator configured to perform a comparison between a reference voltage and an output of the subject group; The main body group includes pull-up-pull-down inverters coupled in parallel, each of the pull-up-pull-down inverters including a master positive channel metal oxide semiconductor field effect transistor (master P-type transistor) and a slave positive channel metal oxide semiconductor field effect transistor (slave P-type transistor), and a slave negative channel metal oxide semiconductor field effect transistor (slave N-type transistor) and a master negative channel metal oxide semiconductor field effect transistor (master N-type transistor); For each of the pull-up-pull-down-inverters, each control input of the slave P-type transistor and the slave N-type transistor is coupled to an input node of the pull-up-pull-down-inverter, the control input of the master P-type transistor is configured to receive a P-type transistor select signal, the P-type transistor select signal being dedicated to the pull-up-pull-down-inverter, and the control input of the master N-type transistor is configured to receive an N-type transistor select signal, the N-type transistor select signal being dedicated to the pull-up-pull-down-inverter; The list consists of all slave P-type transistors and all slave N-type transistors in the subject group; and For the subject group, the controller is configured to evaluate a candidate lineup selected from the list, the evaluation comprising: The P-type transistor selection signal of the main group is set to a P-type transistor enabled state or a P-type transistor disabled state accordingly, Setting the N-type transistor selection signal of the main group to an N-type transistor enabled state or an N-type transistor disabled state accordingly; and Performing an operation based on the comparison includes: Setting the starting lineup to the candidate lineup; or The candidate lineup is modified and the evaluation and operation are repeated.

2. The system according to claim 1, further comprising: a dual-axis dual-cut switch circuit configured to receive the reference voltage and the output of the main body group and having first and second outputs respectively coupled to the non-inverting and inverting inputs of the comparator; as well as in: The dual-axis dual-cut switch circuit is further configured to operate as follows, including: In a first mode, the first and second outputs of the dual-axis dual-cut switch circuit are coupled to (A) the reference voltage and (B) the output of the main group, respectively, according to an enabled state of a first mode signal; and In a second mode, the first and second outputs of the dual-axis dual-cut switch circuit are coupled to (B) the output of the main group and (A) the reference voltage, respectively, according to an enabled state of a second mode signal; and The controller is further configured to generate the first mode signal and the second mode signal.

3. The system of claim 2, wherein: The dual-axis dual-cut switch circuit includes: a first transistor coupled between a first node and the non-inverting input of the comparator, the first node being configured to receive the reference voltage; a second transistor coupled between the first node and the inverting input of the comparator; a third transistor coupled between a second node configured to receive the output of the body group and a non-inverting input of the comparator; and a fourth transistor coupled between the second node and the inverting input of the comparator; a control input of each of the first and fourth transistors configured to receive the first mode signal; and A control input of each of the second and third transistors is configured to receive the second mode signal.

4. The system of claim 2, wherein: In the first mode, the comparator is further configured to perform a first comparison and generate a first mode result; In the second mode, the comparator is further configured to perform a second comparison and generate a second mode result; as well as The controller is further configured to perform the following operations, including: performing a first recursive evaluation of the candidate lineup in the first mode; performing a second recursive evaluation of the candidate lineup in the second mode; and The operation is performed based on the first mode result and the second mode result.

5. A method for determining a starting lineup from a list, characterized in that: The method comprises: selecting one from a plurality of pull-up-pull-down-inverter groups as a main group, each pull-up-pull-down-inverter including a master positive channel metal oxide semiconductor field effect transistor (master P-type transistor) and a slave positive channel metal oxide semiconductor field effect transistor (slave P-type transistor), and a slave negative channel metal oxide semiconductor field effect transistor (slave N-type transistor) and a master negative channel metal oxide semiconductor field effect transistor (master N-type transistor); coupling the pull-up-pull-down-inverters of the main group in parallel; For each pull-up-pull-down-inverter in the body group: coupling a control input of each of the slave P-type transistor and the slave N-type transistor to an input node of the pull-up-pull-down-inverter; configuring a control input of the main P-type transistor to receive a P-type transistor select signal, the signal being specific to the pull-up-pull-down-inverter; and configuring a control input of the main N-type transistor to receive an N-type transistor select signal, the signal being specific to the pull-up-pull-down-inverter; evaluating a candidate lineup of the subject group selected from the list, the list consisting of all slave P-type transistors and all slave N-type transistors in the subject group, the evaluation comprising: According to the candidate lineup, the P-type transistor selection signal is correspondingly set to a P-type transistor enabled state or a P-type transistor disabled state; According to the candidate lineup, the N-type transistor selection signal is set to an N-type transistor enabled state or an N-type transistor disabled state accordingly; and comparing a reference voltage and the output of the subject group using a comparator; and Performing an operation based on the comparison includes: Setting the starting lineup to the candidate lineup; or The candidate lineup is modified and the evaluation and operation are repeated.

6. The method of claim 5, wherein selecting one of the plurality of pull-up-pull-down inverter groups comprises: receiving outputs of a first group of j parallel-coupled pull-up-pull-down inverters; receiving an output of a second group of k pull-up-pull-down inverters coupled in parallel; j and k are corresponding positive integers, and k <j; generating a selection signal; as well as Based on a selection signal, the output of the first group or the output of the second group is provided to the comparator as the output of the subject group.

7. The method according to claim 5, wherein: The subject group represents a corresponding group of pull-up-pull-down-inverters included in a continuous-time linear equalizer.

8. A continuous-time linear equalizer, characterized in that include: a buffer having an output representing an output of the continuous-time linear equalizer; a first group of j parallel-coupled pull-up-pull-down inverters; The data input of each of the pull-up-pull-down-inverters in the first group is coupled to an input node of the continuous-time linear equalizer; the first group being coupled between the input node of the continuous-time linear equalizer and an input of the buffer; a first active inductor coupled to an output node of the first group; a first control input of each pull-up-pull-down-inverter in the first group configured to receive a corresponding first conductivity type selection signal, the signal being specific to the pull-up-pull-down-inverter; The second control input of each of the pull-up-pull-down-inverters in the first group is configured to receive a corresponding second conductivity type selection signal, the signal being specific to the pull-up-pull-down-inverter; as well as The controller is configured to perform the following operations, including: Adaptively setting the first conductive type selection signal of the first group to be in a first conductive type enabled state or a first conductive type non-enabled state respectively; and Adaptively setting the second conductivity type selection signal of the first group to be in a second conductivity type enabled state or a second conductivity type non-enabled state respectively; and Both j and p are positive integers.

9. The continuous-time linear equalizer of claim 8, wherein: p <j。 10. The continuous-time linear equalizer of claim 8, wherein: The first active inductor comprises: a second group of p pull-up-pull-down inverters coupled in parallel; and a resistor coupled between an input node common to each of the p pull-up-pull-down-inverters and an output node common to each of the p pull-up-pull-down-inverters; Each of the pull-up-pull-down inverters includes a positive channel metal oxide semiconductor field effect transistor (P-type transistor) and a negative channel metal oxide semiconductor field effect transistor (N-type transistor); the second group of transistors consists of all slave P-type transistors and all slave N-type transistors in the second group; and The controller is further configured to perform the following operations, including: determining a transistor starting lineup from the second group; Adaptively setting the first conductivity type selection signal of the second group according to the starting lineup to be in the first conductivity type enabled state or the first conductivity type disabled state accordingly; and According to the starting lineup, the second conductive type selection signal of the second group is adaptively set to be in the second conductive type enabled state or the second conductive type disabled state accordingly.

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