Clock tree clustering method, system and device, medium and product

Abstract

The invention relates to the field of EDA algorithm design, in particular to a clock tree clustering method, system and device, a medium and a product. The clock tree clustering method comprises the following steps: inputting an initial clock tree, extracting the position and capacitance parameters of a to-be-driven element, and constructing a minimum spanning tree based on the position of the element; and deleting the edges with the length greater than the clustering cost f in the tree to obtain a spanning tree set. Converting the spanning tree into a binary tree, verifying whether sub-trees meet design constraints or not, and separating child sub-trees with the maximum total cost; and continuing to verify the remaining sub-trees until all the sub-trees reach the standard. Taking each subtree as a cluster, and adding a driver at the top end to generate a clustering cluster; and regarding the cluster as a new clock tree, repeatedly iterating until the number of clusters is unchanged or exceeds the upper limit of iteration, finally adding a clock source to the top layer, and outputting the clock tree. The system, the computer equipment, the computer readable storage medium and the computer program product have the same beneficial effects as a clock tree clustering method.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of EDA algorithm design, and particularly relates to a clock tree clustering method, system, device, medium and product. BACKGROUND

[0002] In the electronic design automation (EDA) process, with the increase of chip integration, clock signal synchronization is increasingly critical. Clock tree synthesis technology emerges as the times require, and is used for constructing an efficient clock distribution network to guarantee the timing performance of a chip.

[0003] In the clock tree synthesis stage, the primary problem is how to properly cluster and divide clock elements to obtain an initial clock tree structure. Subsequent adjustment and balancing of the clock tree are based on the initial clock tree, and the initial clock tree will greatly affect the quality of the final clock tree.

[0004] The prior art adopts general clustering methods such as multiple rounds of K-means and hierarchical clustering to process the clock tree clustering problem. For example, the K-means algorithm is used to divide the elements to be divided into several large clusters, a driver is inserted for each large cluster, and the large clusters are recursively divided until the generated clusters meet the design constraints. The main disadvantage of this kind of general algorithm is that it cannot directly guide clustering according to various constraints and optimization objectives in clock tree synthesis, the target is not clear when clustering, and problems such as waste of driving ability and design rule violation are prone to occur. SUMMARY

[0005] To solve the technical problems that the existing clock tree clustering method cannot directly guide clustering according to various constraints and optimization objectives in clock tree synthesis, the target is not clear when clustering, and problems such as waste of driving ability and design rule violation are prone to occur, the present application provides a clock tree clustering method, system, device, medium and product.

[0006] The technical problem of the present application is solved by providing a clock tree clustering method, comprising the following steps: inputting an initial clock tree, extracting the positions and capacitance parameters of the to-be-driven elements therein, constructing a minimum spanning tree based on the positions of the to-be-driven elements, deleting all edges in the minimum spanning tree with a length greater than a clustering cost f to obtain a spanning tree set, converting all spanning trees into binary trees, verifying whether the sub-trees of each binary tree satisfy a design constraint, if the child sub-trees of a sub-tree of a binary tree all satisfy the design constraint but the sub-tree itself does not satisfy the design constraint, separating the child sub-trees as independent clusters and continuing to verify the remaining sub-trees of the binary tree, repeating the verification process until all sub-trees of the binary tree satisfy the design constraint, regarding each sub-tree as a cluster, adding a driver at the top of the cluster to generate a clustered cluster, regarding the clustered cluster as a new to-be-driven element of the clock tree, repeating the above steps until the number of clustered clusters is unchanged or the iteration number reaches a preset upper limit, obtaining a final clustered cluster, adding a clock source at the top layer of the final clustered cluster, and outputting a clock tree.

[0007] Preferably, verifying whether the sub-trees of each binary tree satisfy the design constraint comprises the following steps: traversing the binary tree from bottom to top to find the root node of a sub-tree that violates the design constraint, wherein the child sub-trees of the sub-tree all satisfy the design constraint; deleting the edge between the root node of the sub-tree and the child sub-tree with the largest total cost, so that the child sub-tree is separated from the whole binary tree, and the separated child sub-tree is processed as an independent cluster; continuing to traverse the remaining sub-trees of the binary tree from bottom to top and separate the child sub-trees of the sub-trees that violate the design constraint until all sub-trees satisfy the design constraint; The total cost formula of the sub-tree is:

[0008] wherein n represents the number of nodes in the sub-tree T, C(v i ) represents the capacitance value of the node vi, Q(e) represents the length of the edge e of the sub-tree T, and E T represents the set of edges in the sub-tree T.

[0009] Preferably, the clustering cost is equal to the driver capacitance; or, The clustering cost is calculated by the following formula:

[0010] wherein f represents the clustering cost, P driver represents the driver power consumption, and ω represents a compromise coefficient, and ω∈[0.2, 1].

[0011] Preferably, the formula of the edge between two points in the minimum spanning tree is:

[0012] wherein Q(e) denotes the length of edge e, d1(u,v) denotes the 1-norm distance between points u and v forming edge e, and C0denotes the network capacitance per unit length of wire.

[0013] Preferably, the design constraints include a maximum fanout and / or a maximum drive capacitance. A sub-tree violates the design constraints when the number of elements it contains exceeds the maximum fanout, and / or the total capacitance of the sub-tree exceeds the maximum drive capacitance.

[0014] Preferably, the design constraints include a maximum fanout and / or a maximum drive capacitance. A sub-tree violates the design constraints when the number of elements it contains exceeds the maximum fanout, and / or the total capacitance of the sub-tree exceeds the maximum drive capacitance.

[0015] Preferably, the clustering process is optimized to minimize the following global objective function:

[0016]

[0017] wherein min Cost is the optimization objective function balancing the total capacitance and the number of drivers; k denotes the total number of clusters, denotes the i-th cluster, and denote the total capacitance of the element pins and the total capacitance of the interconnection network of the i-th cluster, respectively, denotes the number of elements contained in the i-th cluster, f denotes the clustering cost determined by the parameters of the drivers, max_fanout denotes the maximum fanout in the design constraints, and max_cap denotes the maximum drive capacitance in the design constraints.

[0018] Preferably, the conversion of the spanning tree into a binary tree includes: optionally rooting and orienting the edges, and virtually splitting nodes with an out-degree greater than 2 into multiple nodes with an out-degree equal to 2.

[0019] The application also provides a clock tree clustering system, which comprises a user terminal and a micro-service terminal in communication connection; the micro-service terminal receives a to-be-processed command input by the user terminal and executes the steps of the above clock tree clustering method according to the to-be-processed command.

[0020] Preferably, the to-be-processed command is stored in a script file, and when the preset command does not uniquely match the to-be-processed command and / or there is no preset command matching the to-be-processed command, the execution of the script file is interrupted.

[0021] The application further provides a computer device comprising a storage, a processor and a computer program stored on the storage, wherein the processor executes the computer program to implement the steps of the clock tree clustering method.

[0022] The application further provides a computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the clock tree clustering method.

[0023] The application further provides a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the steps of the clock tree clustering method.

[0024] Compared with the prior art, the clock tree clustering method, system, device, medium and product provided by the application have the following advantages: 1. The clock tree clustering method provided by the embodiment of the application overcomes the technical problem that the existing clock tree clustering method cannot guide clustering according to various constraints and optimization targets in clock tree synthesis, and the driving capacity is easily wasted and the design rules are easily violated. Specifically, the clock tree clustering method maximizes the utilization of drivers under the premise of ensuring design constraints through a bottom-up iterative minimum spanning tree partition mechanism; the cutting boundary of the sub-tree is accurately controlled by the clustering cost, which maximizes the driving capacity of the drivers to the greatest extent, and the binary tree verification process takes the maximum fan-out and maximum capacitance as hard partition conditions, thereby avoiding design constraint violations from the root cause.

[0025] Further, by verifying whether the sub-tree of the binary tree satisfies the design constraints and finding the deepest sub-tree, i.e., the sub-tree with the maximum hierarchical depth, that violates the design constraints to split the child sub-tree, the driving capacity of the drivers can be maximized under the premise that each independent cluster satisfies the design constraints, thereby avoiding too many drivers from being inserted.

[0026] It should be noted that the method also has the advantages of strong scalability and fast running speed. The scalability mainly reflects in two aspects. First, the scheme is not coupled with specific design constraints, i.e., the restrictions on the clustering cluster, such as the maximum input waveform conversion time and other common constraints in the industry, can be freely added without changing the algorithm flow. In addition, the single-layer algorithm and the overall structure of the algorithm are separated, based on which the overall logic or the single-layer algorithm can be modified separately to meet actual needs without the need for full modification.

[0027] 2. The clock tree clustering method provided in the embodiment of the present application verifies whether the sub-tree of each binary tree satisfies the design constraint, preferentially cuts the sub-tree with the largest total cost by traversing the binary tree from bottom to top and based on the separation strategy of the total cost of the sub-tree, can guarantee that the child sub-tree satisfies the design constraint while avoiding the generation of a low-load cluster, and realizes deterministic convergence. Further, the separation judgment is performed by taking all the capacitances of the nodes and the length of the edge as the cost, which can simultaneously optimize the electrical load.

[0028] 3. The clock tree clustering method provided in the embodiment of the present application, wherein the design constraint comprises a maximum fan-out and / or a maximum drive capacitance; when the number of elements contained in the sub-tree exceeds the maximum fan-out, and / or the total capacitance of the sub-tree exceeds the maximum drive capacitance, the sub-tree violates the design constraint.

[0029] Understandably, by limiting the design constraint to the maximum fan-out and / or the maximum drive capacitance, the maximum fan-out constraint prevents signal quality deterioration, and the maximum capacitance constraint prevents driver overload, and the two are complementary to form an integrity protection closed loop.

[0030] 4. The clock tree clustering method provided in the embodiment of the present application, wherein the clustering cost is equal to the drive capacitance; or, The clustering cost is calculated by the following formula:

[0031] Wherein, f represents the clustering cost, P driver represents the driver power consumption, and ω represents a compromise coefficient, and ω∈[0.2, 1].

[0032] Understandably, by adjusting the clustering cost to be equal to the drive capacitance, the high-capacitance long edge is preferentially cut when pruning the initial minimum spanning tree, thereby directly reducing the total capacitance and realizing the minimum total capacitance of the clock tree; when the clustering cost is adjusted to be the product of the driver power consumption and the compromise coefficient, the capacitance and the power consumption are automatically balanced, and by selecting a suitable compromise coefficient, the capacitance and the power consumption of the clock tree are relatively balanced.

[0033] 5. The clock tree clustering method provided in the embodiment of the present application, wherein the length formula of the edge between two points in the minimum spanning tree is:

[0034] Wherein, Q(e) represents the length of the edge e, d1(u, v) represents the 1-norm distance of the point u and the point v constituting the edge e, and C0represents the network capacitance of the unit length conductor.

[0035] Understandably, by defining the length formula of two points by the 1-norm distance, that is, the Manhattan distance, and the network capacitance of the unit length conductor, the length value can be more consistent with the physical implementation rules of the chip, and directly reflects the interconnection line capacitance, which is a key electrical indicator.

[0036] It should be noted that the Manhattan distance is the sum of the distances between two points in a plane along the coordinate axis direction, that is, the horizontal or vertical direction, and the calculation formula is the sum of the absolute values of the coordinate difference of the two points. In clock tree clustering, the Manhattan distance is an important indicator for measuring the layout correlation between different clock nodes. Since the transmission path of the clock signal in the chip layout is limited by the wiring channel, it can usually only extend along the horizontal or vertical direction, which is highly consistent with the calculation logic of the Manhattan distance. In the clustering process, the spatial aggregation degree of the nodes can be quickly judged by calculating the Manhattan distance between the nodes: the smaller the distance, the closer the nodes are in the layout, and grouping them into the same cluster can effectively shorten the wiring length of the clock tree branch, reduce signal transmission delay and power consumption.

[0037] Further, by limiting the length formula, the capacitance of the to-be-driven element and the network capacitance are defined as specific weights of points and edges, so that the clock tree clustering method can directly perceive the design constraints and avoid the blind division caused by the lack of physical parameter perception of traditional general clustering algorithms such as the K-means clustering algorithm.

[0038] 6、The clock tree clustering method provided by the embodiment of the application has an optimization target of minimizing a global objective function, the optimization objective function includes two parts of element capacitance and network capacitance, and the fan-out of the clustering cluster is limited to be less than the limited maximum fan-out, and the sum of the element capacitance and the network capacitance of the clustering cluster is limited to be less than the limited maximum capacitance, so that the design constraints of the clustering cluster are guaranteed. Further, through the constraint term of kf, that is, the product of the total number of clustering clusters and the clustering cost, the number of clustering clusters is as small as possible, so that the driving capability of the driver is maximally exerted.

[0039] 7、The clock tree clustering method provided by the embodiment of the application includes: optionally selecting a root node and orienting an edge, and virtually splitting a node with an out-degree greater than 2 into a plurality of nodes with an out-degree equal to 2.

[0040] Understandably, by virtually splitting the node with an out-degree greater than 2 into a plurality of two-degree nodes, the arbitrary tree structure is forcibly converted into a standard binary tree. This conversion eliminates the interference of irregular topologies such as star connection on the traversal algorithm. The virtual node does not introduce physical load, and the capacitance calculation accuracy is maintained; the electrical characteristics of the original tree structure are completely retained in the binary tree model, ensuring the reliability of the verification result.

[0041] 8、The embodiment of the application further provides a clock tree clustering system, the system includes a user terminal and a micro-service terminal in communication connection; the micro-service terminal receives a to-be-processed command input by the user terminal, and executes the steps of the above-mentioned clock tree clustering method according to the to-be-processed command.

[0042] It should be noted that the clock tree clustering system provided by the present application has the same beneficial effects as the clock tree clustering method described above, and will not be repeated here.

[0043] 9、The embodiment of the present application further provides a computer device, including a storage, a processor and a computer program stored on the storage, and the processor executes the computer program to realize the steps of the clock tree clustering method.

[0044] It should be noted that the computer device provided by the present application has the same beneficial effects as the clock tree clustering method described above, and will not be repeated here.

[0045] 10、The embodiment of the present application further provides a computer readable storage medium, which stores a computer program, and the computer program realizes the steps of the clock tree clustering method when executed by a processor.

[0046] It should be noted that the computer readable storage medium provided by the present application has the same beneficial effects as the clock tree clustering method described above, and will not be repeated here.

[0047] 11、The embodiment of the present application further provides a computer program product, including a computer program, and the computer program realizes the steps of the clock tree clustering method when executed by a processor.

[0048] It should be noted that the computer program product provided by the present application has the same beneficial effects as the clock tree clustering method described above, and will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0050] Figure 1 is a flowchart of steps S1 to S6 in a clock tree clustering method provided by the embodiment of the present application.

[0051] Figure 2 is a flowchart of steps S31 to S33 in a clock tree clustering method provided by the embodiment of the present application.

[0052] Figure 3 is a framework diagram of a clock tree clustering system provided by the embodiment of the present application.

[0053] Figure 4 is a framework diagram of a computer device provided by the embodiment of the present application.

[0054] Figure 5 Fig. 1 is a schematic diagram of a computer readable storage medium according to an embodiment of the present application.

[0055] Figure 6 Fig. 2 is a schematic diagram of a computer program product according to an embodiment of the present application.

[0056] Brief Description of the Drawings 1. clock tree clustering system; 11. user end; 12. micro-service end; 2. computer device; 21. storage; 22. processor; 3. computer readable storage medium; 4. computer program product; 100. computer program. DETAILED DESCRIPTION

[0057] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0058] In the embodiments provided in the present application, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that the determination of B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

[0059] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. Those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0060] In various embodiments of the present application, it should be understood that the size of the serial number of the above-mentioned processes does not mean the inevitable sequence of execution, and the execution sequence of the processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0061] The flow diagrams and block diagrams in the drawings of the present application illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flow diagrams or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. Such variations will depend on the implementation be involved and will be apparent to those with skill in the art. It should be particularly noted that each block of the block diagrams and / or flow diagrams, and combinations of blocks in the block diagrams and / or flow diagrams, can be implemented by specialized hardware-based systems that perform the specified functions or acts, or can be implemented by a combination of specialized hardware and computer instructions.

[0062] In the clock tree clustering stage, the prior art generally uses multi-round K-means, hierarchical clustering and other general clustering methods to process the clock tree clustering problem. The main disadvantage of this kind of general algorithm is that it cannot directly guide the clustering according to various constraints and optimization objectives in clock tree synthesis, and the target is not clear when clustering, which is prone to problems such as wasting driving capability and violating design rules.

[0063] To solve the technical problems that the existing clock tree clustering method cannot directly guide the clustering according to various constraints and optimization objectives in clock tree synthesis, the target is not clear when clustering, and it is prone to problems such as wasting driving capability and violating design rules, the present application provides a clock tree clustering method, system, device, medium and product.

[0064] First, please refer to Figure 1 The embodiment of the present application provides a clock tree clustering method, comprising the following steps: S1: inputting an initial clock tree, extracting the positions and capacitance parameters of to-be-driven elements in the clock tree, and constructing a minimum spanning tree based on the positions of the to-be-driven elements; S2: deleting all edges with a length greater than a clustering cost in the minimum spanning tree to obtain a spanning tree set; S3: converting all spanning trees into binary trees, verifying whether the sub-trees of each binary tree satisfy design constraints, if the child sub-trees of a binary tree all satisfy the design constraints, but the sub-tree itself does not satisfy the design constraints, separating the child sub-trees as independent clusters; S4: continuously verifying the remaining sub-trees of the binary tree; repeating step S3 until all sub-trees of the binary tree satisfy the design constraints; S5: regarding each sub-tree as a cluster, and adding a driver at the top of the cluster to generate a clustering cluster; S6: regarding the clustering cluster as a new clock tree, repeating the iteration of the above S1-S5 steps until the number of clustering clusters is unchanged or the iteration number reaches a preset upper limit, obtaining a final clustering cluster, adding a clock source at a top layer of the final clustering cluster, and outputting the clock tree.

[0065] It can be understood that the clock tree clustering method provided by the embodiment of the application overcomes the problem that the existing clock tree clustering method cannot guide clustering according to various constraints and optimization targets in clock tree synthesis, and is prone to problems such as waste of driving capability and design rule violation. Specifically, the clock tree clustering method maximizes the utilization rate of the driver under the premise of ensuring the design constraint through the minimum spanning tree partition mechanism of the bottom-up iteration; the cutting boundary of the sub-tree is accurately controlled by the clustering cost, elements that are too far apart are not forced to be connected in the same cluster, and the additional wiring capacitance and resistance introduced by long-distance interconnection are avoided, thereby maximizing the driving capability of the driver to the greatest extent, and the binary tree verification process takes the maximum fan-out / maximum capacitance and other designs as hard division conditions, thereby avoiding design constraint violations from the root.

[0066] Further, by verifying whether the sub-tree of the binary tree satisfies the design constraint and finding the deepest, i.e., the largest hierarchical depth, sub-tree that violates the design constraint in the binary tree to split the child sub-tree, the driving capability of the driver can be maximized under the premise that each independent cluster satisfies the design constraint, thereby avoiding too many drivers from being inserted.

[0067] It should be noted that the method also has the advantages of strong scalability and fast running speed. The scalability mainly reflects in two aspects. First, the scheme is not coupled with specific design constraints, that is, other constraints such as the maximum input waveform conversion time and other common constraints in the industry can be freely added without changing the algorithm process. In addition, the single-layer algorithm and the overall structure of the algorithm are separated, based on which the overall logic or the single-layer algorithm can be modified separately to meet actual needs without full modification.

[0068] The specific steps S1 to S6 of the clock tree clustering method will be described below.

[0069] First, in step S1, the positions and capacitance parameters of the to-be-driven elements of the initial clock tree are input, and the network capacitance per unit length and the clustering cost are obtained.

[0070] According to the positions of the to-be-driven elements, a minimum spanning tree MST is constructed, all to-be-driven elements are connected as nodes through edges, and the total length of the edges connecting all nodes is the shortest. Thus, under the premise that the network capacitance per unit length is fixed, the total wiring capacitance required to connect all to-be-driven elements is minimized.

[0071] The length of the edge is defined as the 1-norm distance, that is, the Manhattan distance. The Manhattan distance is the sum of the absolute values of the coordinate differences between two points in a plane, and the calculation formula is the sum of the absolute values of the coordinate differences between two points. In clock tree clustering, the Manhattan distance is an important indicator for measuring the layout correlation between different clock nodes. Since the transmission path of the clock signal in the chip layout is limited by the routing channel, it can only extend along the horizontal or vertical direction, which is highly consistent with the calculation logic of the Manhattan distance.

[0072] Secondly, in step S2, all edges in the minimum spanning tree MST whose distances are greater than the clustering cost are deleted to obtain a set of spanning trees {T1, T2, T3, …}.

[0073] The calculation formula of the length of the edge in the minimum spanning tree MST is as follows:

[0074] Wherein, Q(e) represents the length of the edge e, d1(u, v) represents the 1-norm distance between the points u and v constituting the edge e, and C0 represents the network capacitance per unit length of the conductor.

[0075] Further, the clustering cost is a constant representing the clustering cost, which is determined by the parameters of the driver and the optimization target of the clock tree as a whole.

[0076] When the total capacitance of the clock tree is expected to be the smallest, the value of the clustering cost is equal to the driver capacitance value, and the unit of the driver capacitance is pF. At this time, when the edges with lengths greater than the clustering cost are deleted in step S2 for clustering, the influence of the two operations of increasing the network capacitance and increasing the driver capacitance on the total capacitance can be accurately balanced, so as to guide the selection of the clustering scheme with smaller total capacitance in the pruning process, thereby inhibiting the increase of the total capacitance and power consumption from the source.

[0077] When the capacitance and power consumption of the clock tree are expected to be balanced, the clustering cost is calculated by the following formula:

[0078] Wherein, f represents the clustering cost; P driver represents the driver power consumption, the unit of the driver power consumption is pW; ω represents the compromise coefficient, and ω ∈ [0.2, 1], the unit of the compromise coefficient is pF / pW.

[0079] It should be noted that when the clustering cost f is calculated based on the power consumption, the unit of the power consumption needs to be converted to the electrical unit consistent with the capacitance through the conversion coefficient. The conversion coefficient is determined by the power consumption-capacitance mapping relationship of the driver in the chip process library, or calculated and deduced based on the clock frequency, that is, the formula power consumption = capacitance × frequency × voltage², or obtained by using the commonly used process parameter fitting formula, which is not described here.

[0080] At this time, when the edges with lengths greater than the clustering cost are deleted in the clustering in step S2, the actual process is to compare the extra interconnection power consumption expected to be brought by keeping the long edge with the equivalent power consumption of the newly added driver. When the length of the edge is greater than the clustering cost, disconnecting the edge is considered to be more beneficial to the overall power consumption optimization and balance under the power consumption model.

[0081] Further, the selection of the compromise coefficient ω can be 0.2, 0.5, 0.8, etc. according to different design target emphases and constraint strictness. The smaller the value of ω, such as ω = 0.2, the smaller the value of the clustering cost, which means that the tolerance to long-distance interconnection lines in the clustering process is lower, and it tends to disconnect the long edge and insert a driver earlier and more frequently. This is usually used in the scene where the number of drivers is relatively loose, but the local interconnection length needs to be strictly controlled to meet the timing. The larger the value of ω, such as ω = 0.8, the larger the value of the clustering cost, which means that the tolerance to long-distance interconnection lines in the clustering process is higher, and it tends to keep the long edge and reduce the insertion of the driver. This is usually used in the critical path design which needs to minimize the number of drivers to save area and cost.

[0082] By the above length formula and the definition of the clustering cost f, the capacitance of the to-be-driven element and the network capacitance are defined as the specific weights of the points and edges, so that the clock tree clustering method can directly perceive the design constraints and avoid the blind division caused by the lack of physical parameter perception of the traditional general clustering algorithm, such as the K-means clustering algorithm.

[0083] In step S3, all the spanning trees are converted into binary trees. When the spanning tree is converted into a binary tree, the nodes with an out-degree greater than 2 are virtually split into multiple nodes with an out-degree equal to 2 by selecting a root node and orienting the edges. That is, a point is selected as a root node, and then the direction of each edge is marked as from the point close to the root to the point away from the root. For the nodes with an out-degree greater than 2 in the tree, they are regarded as a plurality of coincident points, and the out-degree of each point is 2.

[0084] By virtually splitting the nodes with an out-degree greater than 2 into multiple nodes with an out-degree of 2, the arbitrary tree structure is forced to be converted into a standard binary tree. This conversion eliminates the interference of irregular topologies, such as star connection, on the traversal algorithm. The virtual node does not introduce physical load, and the capacitance value of the virtual node is 0, which does not participate in the calculation of the tree cost, thereby maintaining the accuracy of the capacitance calculation. The electrical characteristics of the original tree structure are completely retained in the binary tree model, ensuring the reliability of the verification result.

[0085] Further, it is verified whether the sub-tree of each binary tree satisfies the design constraint. If the child sub-trees of a binary tree all satisfy the design constraint, but the sub-tree itself does not satisfy the design constraint, the child sub-trees are separated as independent clusters. At this time, the child sub-trees have been separated from the original binary tree, and as independent clusters, they necessarily satisfy the design constraint.

[0086] When a sub-tree violates the design constraint but its child sub-trees all satisfy the design constraint, it is known that the root of the violation is not the overloading of the internal load of the child sub-trees, but the driving capability of the root node of the sub-tree is insufficient to cover the cumulative load of all the sub-trees under it, or the interconnection line capacitance between the sub-tree and the child sub-trees causes the cascade load to exceed the standard.

[0087] Based on the above knowledge, separating the child sub-trees satisfying the constraint into independent clusters is the optimal solution. This operation directly cuts off the edge of the child sub-tree connected to the root node and having the largest total cost, while eliminating the violation of the current level sub-tree and maintaining the original load balancing state of the child sub-tree. It not only avoids redundant splitting of the internal child sub-trees satisfying the design constraint, but also ensures that each new independent cluster satisfies the design constraint, achieving the minimum structural adjustment.

[0088] In this embodiment, when the number of elements contained in the sub-tree exceeds the maximum fan-out, or the total capacitance of the sub-tree exceeds the maximum driving capacitance, the sub-tree violates the design constraint. In some embodiments, only when the number of elements contained in the sub-tree exceeds the maximum fan-out, and the total capacitance of the sub-tree exceeds the maximum driving capacitance, it is determined that the sub-tree violates the design constraint.

[0089] It can be understood that by limiting the design constraint to the maximum fan-out and / or the maximum driving capacitance, the maximum fan-out constraint prevents signal quality degradation, and the maximum capacitance constraint prevents driver overload, and the two are complementary to form a complete integrity protection loop.

[0090] In step S4, the remaining sub-trees after the binary tree separates the child sub-trees are verified, and the above step S3 is repeated until all the sub-trees satisfy the design constraint. The operations of steps S3 and S4 are performed for each binary tree to ensure that the sub-trees of each binary tree and the separated child sub-trees satisfy the design constraint.

[0091] In step S5, each sub-tree obtained after step S4 is taken as a cluster, and the top of the cluster and the top of the independent cluster separated from the child sub-trees are added to the driver to generate a clustered cluster.

[0092] In step S6, the clustered cluster obtained after step S5 is taken as a new clock tree to be driven element, and the above steps S1-S5 are iterated until the number of clustered clusters is unchanged or the iteration number reaches a preset upper limit, to obtain a final clustered cluster. A clock source is added to the top layer of the final clustered cluster, and a clock tree is output.

[0093] It can be understood that after each execution of steps S1-S5, a driver is inserted into each cluster, so that the clock tree has one more level, and the newly added driver replaces the to-be-driven element and becomes the new top-level element. The top-level element gradually decreases with the number of iterations, and when the number of cluster groups does not change or the number of iterations reaches a preset upper limit, each cluster group of the current level has reached or approached the upper limit of the design constraint, and the number of top-level elements cannot be further reduced by further clustering, forming an efficient multi-level driving architecture. It can be ensured that each cluster group meets the design constraint, maximizes the driving capability of the driver, and avoids excessive number of driver insertions.

[0094] Finally, after the iteration ends, the final cluster is obtained, and a clock source is added to the top level of the final cluster to output the final clock tree.

[0095] It should be noted that in other embodiments, the number of cluster groups and / or the corresponding clock tree clustering scheme can be output based on the above steps S1-S6.

[0096] When performing the above steps S1-S6, it is necessary to ensure that the number of obtained cluster groups is as small as possible without violating the design constraint, that is, the newly added driver is as small as possible. Therefore, in this embodiment, the following optimization function is proposed, and the clustering process takes minimizing the following global objective function as the optimization target:

[0097]

[0098] Wherein, min Cost is the optimization target function, which is used to balance the total capacitance and the number of drivers; k represents the total number of cluster groups, represents the i-th cluster group, and represents the total capacitance of the element pins and the total capacitance of the interconnection network of the i-th cluster group, represents the number of elements contained in the i-th cluster group, f represents the clustering cost, which is determined by the parameters of the driver, max fanout represents the maximum fanout in the design constraint, and max cap represents the maximum driving capacitance in the design constraint.

[0099] It can be understood that the optimization target function includes two parts of element capacitance and network capacitance, and limits the fanout of the cluster group to be less than the limited maximum fanout, and limits the sum of the element capacitance and the network capacitance of the cluster group to be less than the limited maximum capacitance, so as to ensure that the cluster group does not violate the design constraint. Further, through the constraint term kf, that is, the product of the total number of cluster groups and the clustering cost, the number of cluster groups is as small as possible, so as to maximize the driving capability of the driver.

[0100] The clock tree clustering method provided by the embodiment of the application solves the technical problems that the existing clock tree clustering method cannot directly guide clustering according to various constraints and optimization targets in clock tree synthesis, the target is not clear when clustering, and waste of driving capability and design rule violation are prone to occur.

[0101] Please refer to Figure 2 , verify whether the sub-tree of each binary tree satisfies the design constraint, including the following steps: S31: traverse the binary tree from bottom to top to find the root node of the sub-tree that violates the design constraint, wherein the child sub-trees of the sub-tree all satisfy the design constraint; S32: delete the edge between the root node of the sub-tree and the child sub-tree with the maximum total cost, so that the child sub-tree is separated from the whole binary tree, and the separated child sub-tree is processed as an independent cluster; S33: continue to traverse the remaining sub-trees of the binary tree from bottom to top, and separate the child sub-trees of the sub-tree that violates the design constraint, until all sub-trees satisfy the design constraint; It can be understood that, by traversing the binary tree from bottom to top and based on the separation strategy of the total cost of the sub-tree, the sub-tree with the maximum total cost is preferentially cut, which can ensure that the child sub-trees satisfy the design constraint while avoiding the generation of low-load clusters, and deterministic convergence is achieved.

[0102] The specific steps S31 to S33 of the clock tree clustering method will be described below.

[0103] Firstly, in step S31, each binary tree is traversed from bottom to top to find the root node corresponding to the deepest sub-tree, i.e., the sub-tree with the maximum hierarchical depth, that violates the design constraint, and the left and right child sub-trees of the sub-tree must satisfy the design constraint.

[0104] By traversing the binary tree from bottom to top, it can be ensured that when any sub-tree is processed, its descendant sub-trees, i.e., sub-trees at a lower level, have been previously checked and processed, the deepest and most local sub-tree that violates the design constraint is preferentially solved, each operation accurately eliminates a minimum violation unit, the utilization efficiency of driving capability is maximized, and unnecessary cluster splitting is minimized.

[0105] Secondly, in step S32, after traversing the deepest sub-tree that violates the design constraint, instead of directly separating the left and right child sub-trees, the edge between the root node of the sub-tree and the child sub-tree with the maximum total cost is deleted, so that the child sub-tree on one side is separated from the whole binary tree, and the separated child sub-tree is processed as an independent cluster.

[0106] It should be noted that the total cost formula of the sub-tree is:

[0107] wherein n represents the number of nodes in the sub-tree T, C(v i ) represents the capacitance value of the node v T represents the set of edges in the sub-tree T.

[0108] That is, the total cost of the sub-tree is the sum of the capacitance values of all the points in the sub-tree plus the sum of the lengths of all the edges in the minimum spanning tree.

[0109] By deleting the edge between the root node of the sub-tree and the child sub-tree with the largest total cost, the load module that contributes most to the current violation of the design constraint can be removed. Separating the high-cost sub-tree can significantly reduce the load pressure on the remaining part, making it easier to meet the design constraint. At the same time, the separated high-cost sub-tree itself already meets the constraint and can be directly used as an independent cluster with high efficiency, avoiding the waste of driver capacity, thereby optimizing the overall driving efficiency and load balancing of the cluster while solving the violation.

[0110] Finally, in step S33, the remaining sub-trees of the binary tree are continuously traversed from bottom to top, and the child sub-trees of the sub-trees that violate the design constraint are separated, that is, the operations of S31 and S32 are continuously performed on the remaining sub-trees until all the sub-trees meet the design constraint.

[0111] Through the above clock tree clustering method, the to-be-driven elements of the initial clock tree are subjected to minimum spanning tree generation, pruning, and generation tree set obtaining; further, binary tree conversion and bottom-up traversal of the binary tree are performed on the generation tree set to separate the clock tree into clusters and insert drivers, and finally the clock tree is output.

[0112] In the clustering process of the clock tree clustering method, the design constraint is always taken as the bottom line to ensure that the clustered clock tree meets the design constraint. By traversing each binary tree from bottom to top, the sub-tree with the largest load but meeting the design constraint is found for cluster separation, effectively avoiding redundant partitioning of the sub-tree and redundant insertion of the driver, and efficiently utilizing the driving capacity of each driver.

[0113] Referring to Figure 3 , the embodiment of the present application also provides a clock tree clustering system, which comprises a user terminal 11 and a micro-service terminal 12 connected in communication; the micro-service terminal 12 receives a to-be-processed command input by the user terminal 11 and executes the steps of the above clock tree clustering method according to the to-be-processed command.

[0114] It can be understood that the micro-service terminal 12 is responsible for executing the steps of the above clock tree clustering method, and after executing the related steps, outputs a preset command uniquely matched with the to-be-processed command to the user terminal 11, which submits the preset command to an interpreter for verification and analysis, and finally executes by EDA software.

[0115] It should be noted that the clock tree clustering method provided in the aforementioned embodiment is implemented using a microservice-based clock tree clustering system 1. Microservices specifically separate module units with a single function from the original, fully functional monolithic application, making the original software architecture clearer and simpler, so as to facilitate the updating, maintenance and further iterative improvement of the functions that can be achieved by the single module unit.

[0116] Specifically, the clock tree clustering system 1 of the embodiment of the present invention separates the clock tree clustering function in the EDA software to form a microservice end 12. Through this design, professionals in this field or users who are proficient in EDA software only need to deploy a set of clock tree clustering microservices in advance, and then they can request the microservice on different versions of EDA software within the local area network, and then realize clock tree clustering through the microservice end 12, and reduce the occupation of memory resources.

[0117] In some embodiments, the command to be processed is stored in a script file. When the preset command does not uniquely match the command to be processed, and / or there is no preset command matching the command to be processed, the execution of the script file is interrupted.

[0118] See also Figure 4 An embodiment of the present invention further provides a computer device 2, comprising a memory 21, a processor 22, and a computer program 100 stored on the memory 21, wherein the processor 22 executes the computer program 100 to implement the steps of the above-mentioned clock tree clustering method.

[0119] It can be understood that when the computer device 2 provided by the embodiment of the present invention is running, the clock tree clustering method described in the above embodiment can be implemented when the processor 22 executes the computer program 100. The computer device 2 provided by the embodiment of the present invention has the same beneficial effects as the clock tree clustering method provided by the above embodiment.

[0120] In some embodiments, the computer device 2 is a computer device applied in the field of EDA software application technology, including but not limited to obtaining the driven components and capacitance values ​​of the initial clock tree, generating an initial minimum spanning tree, traversing the binary tree and verifying whether it complies with the design constraints, etc., which will not be elaborated here. In theory, the method steps involved in the technical solution of the present invention can all be realized through the participation of the computer device 2 in the control, and the relevant parameters involved can also be adjusted accordingly through the computer device 2, where the relevant parameters include but are not limited to parameters such as a preset command set and a preset option set.

[0121] In some embodiments, the processor 22 provided by the embodiments of the present application is a general processor, which is a microprocessor or any conventional processor, such as a central processing unit (CPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application.

[0122] In some embodiments, the method steps disclosed by the embodiments of the present application can be implemented by a hardware processor or a combination of hardware and software modules in the processor 22.

[0123] Referring to Figure 5 The embodiments of the present application also provide a computer readable storage medium 3, which stores a computer program 100, and the computer program 100 implements the steps of the clock tree clustering method when executed by a processor.

[0124] It can be understood that the computer readable storage medium 3 provided by the embodiments of the present application stores the computer program 100, and the computer program 100 can be called by a processor to execute the clock tree clustering method described in the above embodiments.

[0125] It should be noted that the computer readable storage medium 3 provided by the embodiments of the present application has the same beneficial effects as the clock tree clustering method provided by the above embodiments, and will not be described here.

[0126] Specifically, the computer readable storage medium 3 can include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, etc.

[0127] In some embodiments, the computer readable storage medium 3 includes a non-volatile computer readable storage medium, which can be used to store non-volatile software programs, non-volatile computer executable programs and modules.

[0128] Specifically, the computer readable storage medium 3 has a storage space for the computer program 100 to execute any method steps of the above clock tree clustering method, and these programs can be read from one or more computer program products or written into the one or more computer program products.

[0129] In some embodiments, the computer program 100 can be compressed in a suitable form.

[0130] Referring to Figure 6 The embodiment of the present application also provides a computer program product 4 comprising a computer program 100 which, when executed by a processor, implements the steps of the clock tree clustering described above.

[0131] It can be understood that the computer program product 4 provided by the embodiment of the present application comprises the computer program 100, and the computer program 100 can be called by the processor to execute the clock tree clustering method described in the above embodiment, which will not be described here.

[0132] The clock tree clustering method, clock tree clustering system, device, medium and product disclosed by the embodiment of the present application are described in detail above, and the principle and implementation mode of the present application are described by applying specific examples. The above embodiment is only used to help understand the method and core idea of the present application.

[0133] Meanwhile, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation mode and application range, and the above description should not be understood as a limitation of the present application. Any modification, equivalent replacement and improvement within the principle of the present application should be included in the protection scope of the present application.

Claims

1. A clock tree clustering method, characterized in that: The following steps are involved: Input the initial clock tree, extract the position and capacitance parameters of the components to be driven, and build a minimum spanning tree based on the positions of the components to be driven: Delete all edges in the minimum spanning tree whose length is greater than the clustering cost to obtain a set of spanning trees; Convert all spanning trees into binary trees and verify whether the subtrees of each binary tree meet the design constraints. If the child subtrees of a binary tree subtree all meet the design constraints, but the subtree itself does not meet the design constraints, separate the child subtrees as independent clusters and continue to verify the remaining subtrees of the binary tree. Repeat the verification process until all subtrees of the binary tree meet the design constraints. Treat each subtree as a cluster and add a driver to the top of the cluster to generate a cluster; Treat the cluster as a new clock tree to be driven element, repeat the above steps until the number of clusters remains unchanged or the number of iterations reaches the preset upper limit, and then obtain the final cluster. Add the clock source to the top layer of the final cluster and output the clock tree.

2. The clock tree clustering method according to claim 1, wherein: Verify that each subtree of a binary tree meets the design constraints, including the following steps: Traverse the binary tree from bottom to top and find the root node of the subtree that violates the design constraint, where all the child subtrees of the subtree satisfy the design constraint; Delete the edge between the root node of the subtree and the child subtree with the largest total cost, so that the child subtree is separated from the entire binary tree. The separated child subtree is treated as an independent cluster; Continue to traverse the remaining subtrees of the binary tree from bottom to top, and separate the child subtrees of the subtree that violates the design constraints until all subtrees meet the design constraints; The total cost formula of the subtree is: Among them, n represents the number of nodes in the subtree T, C(v i ) represents node v i The capacitance value, Q(e) represents the length of the edge e of the subtree T, E T Represents the set of edges in subtree T.

3. The clock tree clustering method according to claim 1, wherein: The design constraints include maximum fan-out and / or maximum drive capacitance; A subtree violates a design constraint when the number of components it contains exceeds the maximum fan-out, and / or the total capacitance of the subtree exceeds the maximum driver capacitance.

4. The clock tree clustering method according to claim 1, wherein: The clustering cost is equal to the driver capacitance; Or, the clustering cost is calculated using the following formula: Among them, f represents the clustering cost, P driver represents the driver power consumption, ω represents the trade-off coefficient, and ω∈[0.2,1].

5. The clock tree clustering method according to claim 1, wherein: The formula for the length of an edge between two points in a minimum spanning tree is: Where Q(e) represents the length of edge e, d1(u,v) represents the 1-norm distance from point u to point v that constitutes edge e, and C0 represents the network capacitance per unit length of wire.

6. The clock tree clustering solution according to claim 4, wherein: The clustering process is optimized to minimize the following global objective function: Among them, min Cost is the optimization objective function, which is used to balance the total capacitance and the number of drivers; k represents the total number of clusters, represents the i-th cluster, and Represent the total capacitance of component pins and the total capacitance of interconnection network of the i-th cluster respectively, represents the number of components contained in the i-th cluster, f represents the clustering cost, which is determined by the parameters of the driver, max_fanout represents the maximum fan-out in the design constraint, and max_cap represents the maximum driver capacitance in the design constraint.

7. The clock tree clustering method according to claim 1, wherein: Converting the spanning tree into a binary tree comprises: Select any root node and direct the edges, and virtually split the nodes with out-degree greater than 2 into multiple points with out-degree equal to 2.

8. A clock tree clustering system, characterized by: The clock tree clustering system includes a user end and a microservice end in communication connection; The microservice end receives the pending command input by the user end, and executes the steps of the clock tree clustering method according to any one of claims 1 to 7 according to the pending command.

9. The clock tree clustering system according to claim 8, wherein: The command to be processed is stored in a script file. When the preset command does not uniquely match the command to be processed, and / or there is no preset command matching the command to be processed, the execution of the script file is interrupted.

10. A computer device comprising a memory, a processor, and a computer program stored on the memory, wherein: The processor executes the computer program to implement the steps of the clock tree clustering method according to any one of claims 1 to 7.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the computer program implements the steps of the clock tree clustering method according to any one of claims 1 to 7.

12. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the computer program implements the steps of the clock tree clustering method according to any one of claims 1 to 7.

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