Method and system for optimizing low-warpage solder ball array in FC-BGA (Fiber Channel-Ball Grid Array) packaging of glass substrate

Abstract

The invention relates to the technical field of solder ball array optimization, in particular to a low-warpage solder ball array optimization method and system in FC-BGA packaging of a glass substrate, and the method comprises the steps: determining the glass substrate and a plurality of solder balls, designing a preliminary array layout, creating a three-dimensional geometric model, carrying out the thermal loading simulation of the three-dimensional geometric model, and obtaining a plurality of thermal stress distribution nephograms; and executing the following operations on each thermal stress distribution cloud picture in the plurality of thermal stress distribution cloud pictures: obtaining a maximum thermal stress region from the thermal stress distribution cloud picture, obtaining a region position and a maximum thermal stress value according to the maximum thermal stress region, obtaining an optimal array layout, summarizing the optimal array layout, and obtaining the thermal stress distribution cloud picture. A plurality of thermal stress distribution cloud pictures are obtained, a plurality of optimal array layouts corresponding to the thermal stress distribution cloud pictures are obtained, the optimal array layout is obtained, the voidage of the welding spots is calculated based on the optimal array layout, and optimization of the low-warpage welding ball array in FC-BGA packaging of the glass substrate is completed based on the voidage of the welding spots. According to the invention, the optimization precision and efficiency of the solder ball layout can be improved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of solder ball array optimization, in particular to a low-warp solder ball array optimization method and system in glass substrate FC-BGA packaging. BACKGROUND

[0002] The glass substrate refers to a kind of base material for electronic packaging.FC-BGA packaging refers to a kind of packaging in which the chip is placed upside down on the substrate, and the bumps on the chip are in direct contact with the pads on the substrate and are welded to realize the electrical connection between the chip and the substrate.Low-warp solder ball array optimization refers to an optimization method for the layout design of solder balls in FC-BGA packaging, aiming to reduce the warp deformation in the packaging process and improve the reliability and performance of the packaging.

[0003] Traditional optimization methods are usually based on experience or simple numerical simulation, lack of precise mathematical models and optimization algorithms, and it is difficult to achieve global optimization of solder ball layout.Secondly, the influence of factors such as thermal performance parameters, mechanical performance parameters and microstructure parameters of packaging materials on warp deformation is not considered comprehensively.Therefore, how to improve the optimization accuracy and efficiency of solder ball layout is a technical problem to be solved. SUMMARY

[0004] The application provides a low-warp solder ball array optimization method in glass substrate FC-BGA packaging and a computer readable storage medium, which aims to improve the optimization accuracy and efficiency of solder ball layout.

[0005] To achieve the above-mentioned purpose, the application provides a low-warp solder ball array optimization method in glass substrate FC-BGA packaging, which comprises:

[0006] Confirm the glass substrate and the plurality of solder balls, and obtain the thermal performance parameters, mechanical performance parameters and microstructure parameters according to the glass substrate;

[0007] Obtain the glass substrate size, chip pin distribution and electrical performance, and design a preliminary array layout according to the preset solder ball spacing, plurality of solder balls, glass substrate size, chip pin distribution and electrical performance, wherein the glass substrate size comprises the glass substrate thickness, glass substrate length and glass substrate width;

[0008] Create a three-dimensional geometric model according to the preliminary array layout, thermal performance parameters, mechanical performance parameters and microstructure parameters;

[0009] According to the preset plurality of heating parameters, the three-dimensional geometric model is subjected to thermal loading simulation, and a plurality of thermal stress distribution cloud images are obtained, wherein the thermal stress distribution cloud image comprises the glass substrate thermal stress distribution and the solder ball thermal stress distribution, and the heating temperature corresponding to each heating parameter in the plurality of heating parameters is different;

[0010] performing the following operations on each of the plurality of thermal stress distribution clouds:

[0011] obtaining a maximum thermal stress region from the thermal stress distribution cloud, obtaining a region position and a maximum thermal stress value according to the maximum thermal stress region, and obtaining an optimal array layout based on the region position and the maximum thermal stress value;

[0012]

[0013] obtaining an optimal array layout according to the plurality of optimal array layouts, wherein the optimal array layout is an optimal array layout corresponding to a minimum suboptimal warping deformation amount in the plurality of optimal array layouts;

[0014] calculating a solder void ratio based on the optimal array layout, and completing low warping solder ball array optimization in the glass substrate FC-BGA packaging based on the solder void ratio.

[0015] Optionally, the obtaining of the thermal performance parameters, the mechanical performance parameters, and the microstructure parameters from the glass substrate comprises:

[0016] cutting out a thermal performance test sample, a mechanical performance test sample, and a microstructure test sample from the glass substrate, and setting a pre-constructed thermal analyzer with preset test parameters to obtain a preset thermal analyzer, wherein the test parameters include a test temperature rise rate, a test temperature interval, and a test temperature range;

[0017] measuring the thermal performance test sample by using the preset thermal analyzer to obtain a sample length set and a test temperature set, and obtaining a sample test group set according to the sample length set and the test temperature set, wherein the sample test group set includes a plurality of sample test groups, and each sample test group includes a sample length and a test temperature;

[0018] calculating an average linear thermal expansion coefficient according to the sample test group set, measuring the thermal conductivity of the thermal performance test sample to obtain the thermal conductivity, and taking the average linear thermal expansion coefficient and the thermal conductivity as the thermal performance parameters;

[0019] performing mechanical performance testing on the mechanical performance test sample by using a preset loading rate to obtain a sample load displacement curve;

[0020] calculating an elastic modulus and a yield strength according to the sample load displacement curve, and taking the elastic modulus and the yield strength as the mechanical performance parameters;

[0021] performing a cleaning and film coating operation on the microstructure test sample to obtain a cleaned test sample, obtaining an AFM image according to the cleaned test sample, obtaining a sample surface roughness according to the AFM image, and taking the sample surface roughness as the microstructure parameter.

[0022] ​Optionally, the calculating the average linear thermal expansion coefficient according to the sample test group set comprises:

[0023] sequentially extracting a sample test group from the sample test group set, extracting a preceding test group and a subsequent test group from the sample test group according to the sample test group, wherein the preceding test group comprises a preceding sample length and a preceding test temperature, and the subsequent test group comprises a subsequent sample length and a subsequent test temperature;

[0024] calculating a linear thermal expansion coefficient of the sample test group according to the preceding test group and the subsequent test group, wherein a calculation formula of the linear thermal expansion coefficient is as follows:

[0025]

[0026] wherein α(T i ) represents the linear thermal expansion coefficient of the sample test group, L i+1 represents the subsequent sample length, L i-1 represents the preceding sample length, L i represents a sample length in the sample test group, T i+1 represents the subsequent test temperature, T i-1 represents the preceding test temperature, and i represents an index of the sample test group in the sample test group set;

[0027] taking the subsequent test group as the sample test group, returning to the step of sequentially extracting the sample test group from the sample test group set until the sample test group set is empty;

[0028] summarizing the linear thermal expansion coefficients to obtain a linear thermal expansion coefficient set, and calculating the average linear thermal expansion coefficient according to the linear thermal expansion coefficient set.

[0029] Optionally, the obtaining the optimal array layout based on the region position and the maximum thermal stress value comprises:

[0030] comparing the maximum thermal stress value with a preset normal thermal stress threshold value;

[0031] if the maximum thermal stress value is greater than or less than the preset normal thermal stress threshold value, optimizing the preliminary array layout according to the region position and the maximum thermal stress value to obtain a suboptimal array layout, and respectively calculating a preliminary warping deformation amount of the preliminary array layout and a suboptimal warping deformation amount of the suboptimal array layout;

[0032] comparing the suboptimal warping deformation amount with the preliminary warping deformation amount;

[0033] if the suboptimal warping deformation amount is greater than or equal to the preliminary warping deformation amount, returning to the step of optimizing the preliminary array layout according to the region position and the maximum thermal stress value;

[0034] If the suboptimal warping deformation is less than the preliminary warping deformation, the suboptimal warping deformation is taken as the optimal warping deformation, and the suboptimal array layout is taken as the optimal array layout.

[0035] If the maximum thermal stress value is equal to the preset normal thermal stress threshold, the preliminary array layout corresponding to the maximum thermal stress value is taken as the optimal array layout.

[0036] Optionally, the separately calculating the preliminary warping deformation and the suboptimal warping deformation of the preliminary array layout and the suboptimal array layout comprises:

[0037] The preliminary warping deformation is calculated according to the preliminary array layout, wherein the calculation formula of the preliminary warping deformation is as follows:

[0038]

[0039] Wherein, W represents the preliminary warping deformation, σ represents the maximum thermal stress value, U represents the length of the glass substrate, E represents the elastic modulus of the glass substrate, D represents the thickness of the glass substrate, m represents the number of the solder balls in the plurality of solder balls, d represents the preset solder ball diameter, β1 represents the linear thermal expansion coefficient of the glass substrate, β0 represents the preset solder ball thermal expansion coefficient, and s represents the solder ball pitch.

[0040] The suboptimal warping deformation is calculated based on the suboptimal array layout.

[0041] Optionally, the calculating the solder joint void ratio based on the optimal array layout comprises:

[0042] An oxidation-resistant coating paint is obtained, and the glass substrate is coated by using a pre-constructed coating device and the oxidation-resistant coating paint to obtain an oxidation-resistant glass substrate, wherein the coating speed and the paint flow rate are preset in the coating device.

[0043] A solder paste glass substrate is constructed according to the optimal array layout and the oxidation-resistant glass substrate, and the plurality of solder balls are attached to the solder paste glass substrate to obtain a glass substrate FC-BGA packaging sample.

[0044] The glass substrate FC-BGA packaging sample is reflow soldered to obtain a soldered and formed substrate, and the soldered and formed substrate is subjected to multi-slice tomography to obtain an X-ray image set, and the solder joint void ratio is calculated according to the X-ray image set.

[0045] Optionally, the reflow soldering of the glass substrate FC-BGA packaging sample to obtain the soldered and formed substrate comprises:

[0046] The thermal stress distribution cloud images are sequentially extracted from the plurality of thermal stress distribution cloud images, and the temperature upper limit and the temperature lower limit of the thermal stress distribution cloud image are obtained.

[0047] The reflow soldering furnace temperature zones are set according to the upper temperature limit and the lower temperature limit, and the reflow soldering furnace temperature zone set is obtained by collecting the reflow soldering furnace temperature zones;

[0048] The reflow soldering furnace temperature zone set is sorted in ascending order to obtain a reflow soldering furnace temperature zone sequence, and the temperature rising rate is set according to the average linear thermal expansion coefficient;

[0049] The reflow soldering furnace temperature zones are extracted from the reflow soldering furnace temperature zone sequence in sequence, and the following operations are performed on the extracted reflow soldering furnace temperature zones:

[0050] The pre-constructed reflow soldering furnace is started according to the temperature rising rate, the reflow soldering furnace, the preset inert gas and the reflow soldering furnace temperature zone are used to perform reflow soldering on the glass substrate FC-BGA packaging sample, and real-time monitoring is performed to obtain the soldering furnace temperature and the initial soldering sample;

[0051] It is judged whether the soldering furnace temperature is located in the reflow soldering furnace temperature zone;

[0052] If the soldering furnace temperature is not located in the reflow soldering furnace temperature zone, the soldering furnace temperature is compared with the upper temperature limit, and the soldering furnace temperature and the lower temperature limit are compared;

[0053] If the soldering furnace temperature is greater than the upper temperature limit, a first temperature difference between the soldering furnace temperature and the upper temperature limit is calculated, and the first temperature difference is compared with the preset normal temperature difference threshold;

[0054] If the first temperature difference is greater than the preset normal temperature difference threshold, the temperature of the started reflow soldering furnace is adjusted until the first temperature difference is not greater than the preset normal temperature difference threshold, and a first adjusted temperature is obtained;

[0055] If the soldering furnace temperature is less than the lower temperature limit, a second temperature difference between the soldering furnace temperature and the lower temperature limit is calculated, and the second temperature difference is compared with the normal temperature difference threshold;

[0056] If the second temperature difference is greater than the preset normal temperature difference threshold, the temperature of the started reflow soldering furnace is adjusted until the second temperature difference is not greater than the preset normal temperature difference threshold, and a second adjusted temperature is obtained;

[0057] The first adjusted temperature or the second adjusted temperature is taken as an adjusted temperature, and the initial soldering sample is continuously soldered by using the adjusted temperature to obtain an initial soldered substrate;

[0058] The initial soldered substrate is collected to obtain a soldered substrate, and the soldered substrate is subjected to cooling treatment to obtain a soldered formed substrate.

[0059] Optionally, the solder joint cavity rate is calculated according to the X-ray image set, including:

[0060] The multi-layer fault thickness, the multi-layer cavity cross-sectional area and the multi-layer solder joint cross-sectional area are obtained based on the X-ray image set, wherein the fault thickness, the cavity cross-sectional area and the solder joint cross-sectional area are one-to-one corresponding;

[0061] The average fault thickness is calculated based on the multi-layer fault thickness, and the solder void rate is calculated based on the average fault thickness, the multi-layer void cross-sectional area, and the multi-layer solder point cross-sectional area. The calculation formula for the solder void rate is as follows:

[0062]

[0063] Among them, R represents the void ratio of solder joints, A 1,j represents the cross-sectional area of ​​the void in the i-th layer, A 2,j represents the cross-sectional area of ​​the solder joint in layer i, n represents the number of layers in the tomographic scan, and t j represents the thickness of the j-th fault layer, represents the average fault thickness, and j represents the index of the layer number.

[0064] Optionally, obtaining multi-layer slice thickness, multi-layer cavity cross-sectional area, and multi-layer solder joint cross-sectional area based on the X-ray image set includes:

[0065] Denoising is performed on each X-ray image in the X-ray image set to obtain a denoised X-ray image set;

[0066] Extracting denoised X-ray images from the denoised X-ray image set in sequence, gray-scaling the denoised X-ray images to obtain gray-scale images, wherein the gray-scale image includes: a plurality of pixels, each pixel corresponding to a grayscale value;

[0067] Extracting pixels from a plurality of pixels in sequence, identifying grayscale values ​​corresponding to the extracted pixels, and comparing the grayscale values ​​with a preset grayscale threshold;

[0068] If the grayscale value is greater than the preset grayscale threshold, the pixel corresponding to the grayscale value is marked as a white pixel;

[0069] If the grayscale value is less than or equal to the preset grayscale threshold, the pixel corresponding to the grayscale value is marked as a black pixel;

[0070] Summarize the white pixels and black pixels to obtain a white pixel set and a black pixel set, use the area corresponding to the black pixel set as the background area, and use the area corresponding to the white pixel set as the solder joint area;

[0071] The background area and the solder joint area are summarized respectively to obtain a background area set and a solder joint area set, and multiple void areas are identified from the solder joint area set;

[0072] The multi-layer void cross-sectional areas are determined based on the multiple void regions, and the multi-layer solder joint cross-sectional areas and multi-layer fault thicknesses are obtained based on the solder joint region set, the background region set, and the multiple void regions.

[0073] To achieve the above object, the application further provides a low-warp ball array optimization system in a glass substrate FC-BGA package, comprising:

[0074] A preliminary array layout design module is configured to confirm a glass substrate and a plurality of balls, acquire thermal performance parameters, mechanical performance parameters and microstructure parameters from the glass substrate, acquire glass substrate dimensions, chip pin distribution and electrical performance, and design a preliminary array layout according to a preset ball spacing, the plurality of balls, the glass substrate dimensions, the chip pin distribution and the electrical performance, wherein the glass substrate dimensions include a glass substrate thickness, a glass substrate length and a glass substrate width.

[0075] A thermal loading simulation module is configured to create a three-dimensional geometric model according to the preliminary array layout, the thermal performance parameters, the mechanical performance parameters and the microstructure parameters, perform thermal loading simulation on the three-dimensional geometric model according to a plurality of preset heating parameters, and obtain a plurality of thermal stress distribution maps, wherein the thermal stress distribution maps include glass substrate thermal stress distribution and ball thermal stress distribution, and the heating temperature corresponding to each heating parameter in the plurality of heating parameters is different.

[0076] An optimal array layout acquisition module is configured to perform the following operations on each thermal stress distribution map in the plurality of thermal stress distribution maps: acquire a maximum thermal stress region from the thermal stress distribution map, acquire a region position and a maximum thermal stress value according to the maximum thermal stress region, acquire an optimal array layout based on the region position and the maximum thermal stress value, and aggregate the optimal array layouts to obtain a plurality of optimal array layouts corresponding to the plurality of thermal stress distribution maps.

[0077] A ball void rate calculation module is configured to acquire an optimal array layout according to the plurality of optimal array layouts, wherein the optimal array layout is an optimal array layout corresponding to a minimum suboptimal warp deformation amount in the plurality of optimal array layouts, calculate a ball void rate based on the optimal array layout, and complete low-warp ball array optimization in the glass substrate FC-BGA package based on the ball void rate.

[0078] To solve the above problems, the application further provides an electronic device, which comprises:

[0079] A memory is configured to store at least one instruction.

[0080] A processor is configured to execute the instruction stored in the memory to implement the low-warp ball array optimization method in the glass substrate FC-BGA package.

[0081] To solve the above problems, the application further provides a computer readable storage medium, which stores at least one instruction, and the at least one instruction is executed by a processor in an electronic device to implement the low-warp ball array optimization method in the glass substrate FC-BGA package.

[0082] The application is to solve the problems described in the background art. The application confirms the glass substrate and the plurality of solder balls, obtains the thermal performance parameters, mechanical performance parameters and microstructure parameters according to the glass substrate. The thermal performance parameters help to understand the thermal response characteristics of the glass substrate when the temperature changes, so as to accurately predict the thermal stress distribution. The mechanical performance parameters can be used to analyze the deformation of the glass substrate when it is stressed. In the optimization of the solder ball array layout, the packaging failure caused by insufficient mechanical performance can be avoided. The microstructure parameters reflect the internal structure characteristics of the glass substrate, which plays an important role in understanding its physical properties and failure mechanism. The size of the glass substrate, the chip pin distribution and the electrical performance are obtained. According to the preset solder ball spacing, the plurality of solder balls, the glass substrate size, the chip pin distribution and the electrical performance, a preliminary array layout is designed. The glass substrate size includes the glass substrate thickness, the glass substrate length and the glass substrate width. The glass substrate size ensures that the solder balls can be reasonably distributed on the glass substrate, avoiding the layout exceeding the substrate range. The chip pin distribution determines the electrical connection mode between the solder balls and the chip. Accurate acquisition of the pin distribution information helps to design a solder ball array that meets the electrical connection requirements. According to the electrical performance, the solder ball array can ensure that the electrical performance of the packaging meets the design standard. According to the preliminary array layout, the thermal performance parameters, the mechanical performance parameters and the microstructure parameters, a three-dimensional geometric model is created. The application combines the thermal performance parameters, the mechanical performance parameters and the microstructure parameters to more realistically simulate the physical behavior of the glass substrate and the solder balls in actual work, improving the accuracy of the simulation results. According to the plurality of preset heating parameters, the three-dimensional geometric model is simulated for thermal loading, obtaining a plurality of thermal stress distribution maps. The thermal stress distribution map includes the glass substrate thermal stress distribution and the solder ball thermal stress distribution. Each heating parameter in the plurality of heating parameters corresponds to a different heating temperature. The different heating temperatures simulate the thermal response of the glass substrate in different working environments. Through the plurality of heating parameters, the distribution rule of the thermal stress can be more comprehensively understood. For each thermal stress distribution map in the plurality of thermal stress distribution maps, the following operations are performed: obtaining the maximum thermal stress area from the thermal stress distribution map, obtaining the area position and the maximum thermal stress value according to the maximum thermal stress area, and obtaining the best array layout based on the area position and the maximum thermal stress value. The maximum thermal stress area is the part of the packaging that is most likely to fail. Accurate acquisition of the position and stress value of this area helps to optimize the solder ball array layout and adjust the distribution of the solder balls, which can effectively reduce the thermal stress of this area and improve the reliability of the packaging. The best array layouts are summarized to obtain a plurality of best array layouts corresponding to the plurality of thermal stress distribution maps. The best array layouts are summarized under different heating parameters to provide a plurality of candidate schemes for subsequent selection of the optimal array layout. According to the plurality of best array layouts, the optimal array layout is obtained. The optimal array layout is the best array layout corresponding to the smallest suboptimal warping deformation amount in the plurality of best array layouts.By comparing the suboptimal warpage values ​​corresponding to multiple optimal array layouts and selecting the layout with the minimum warpage value as the optimal array layout, this method effectively reduces glass substrate warpage and improves package flatness and reliability. The solder void rate is calculated based on the optimal array layout, and this is used to optimize the low-warpage solder ball array in glass substrate FC-BGA packages. By calculating the solder void rate, the present invention can assess soldering quality under the optimal array layout. Therefore, the present invention can improve the accuracy and efficiency of solder ball layout optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Figure 1 A schematic flow chart of a method for optimizing a low-warpage solder ball array in a glass substrate FC-BGA package according to one embodiment of the present invention;

[0084] Figure 2 This is a functional module diagram of a low-warpage solder ball array optimization system for glass substrate FC-BGA packaging provided by one embodiment of the present invention;

[0085] Figure 3 A schematic structural diagram of an electronic device for implementing the method for optimizing low-warpage solder ball arrays in glass substrate FC-BGA packaging provided by an embodiment of the present invention.

[0086] Description of reference numerals:

[0087] 1. Electronic device; 10. Processor; 11. Memory; 12. Bus.

[0088] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0089] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0090] The present embodiment provides a method for optimizing low-warpage solder ball arrays in glass substrate FC-BGA packages. The method can be performed by at least one of a server, a terminal, or other electronic device capable of executing the method provided by the present embodiment. In other words, the method can be executed by software or hardware installed on a terminal or server device, where the software can be a blockchain platform. The server can include, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0091] Reference Figure 1As shown, it is a flowchart of the low warping solder ball array optimization method in the glass substrate FC-BGA package provided by an embodiment of the present application. In this embodiment, the low warping solder ball array optimization method in the glass substrate FC-BGA package comprises the following steps.

[0092] S1, confirm the glass substrate and the plurality of solder balls, and obtain the thermal performance parameters, mechanical performance parameters and microstructure parameters according to the glass substrate.

[0093] It can be understood that the glass substrate refers to a substrate material used for electronic packaging, which is usually used to support chips and other electronic components and provide electrical connection and physical support. The solder ball refers to a component used to realize electrical connection between the chip and the substrate in the FC-BGA package. In the packaging process, the solder ball is connected to the pad on the substrate through the reflow soldering process to form a reliable electrical connection.

[0094] In detail, the thermal performance parameters, mechanical performance parameters and microstructure parameters obtained according to the glass substrate include the following steps.

[0095] Cut the thermal performance test sample, the mechanical performance test sample and the microstructure test sample from the glass substrate, and set the pre-constructed thermal analyzer with the preset test parameters to obtain the preset thermal analyzer, wherein the test parameters include the test temperature interval, the test temperature interval and the test temperature interval.

[0096] Measure the thermal performance test sample by using the preset thermal analyzer to obtain the sample length set and the test temperature set, and obtain the sample test group set according to the sample length set and the test temperature set, wherein the sample test group set includes a plurality of sample test groups, and the sample test group includes the sample length and the test temperature.

[0097] Calculate the average linear thermal expansion coefficient according to the sample test group set, measure the thermal conductivity of the thermal performance test sample, obtain the thermal conductivity, and take the average linear thermal expansion coefficient and the thermal conductivity as the thermal performance parameters.

[0098] Perform mechanical performance test on the mechanical performance test sample by using the preset loading rate to obtain the sample load displacement curve.

[0099] Calculate the elastic modulus and the yield strength according to the sample load displacement curve, and take the elastic modulus and the yield strength as the mechanical performance parameters.

[0100] Perform cleaning and film coating operation on the microstructure test sample to obtain the cleaned test sample, obtain the AFM image according to the cleaned test sample, obtain the sample surface roughness according to the AFM image, and take the sample surface roughness as the microstructure parameter.

[0101] It should be explained that the thermal performance test sample refers to a sample cut from a glass substrate for testing thermal performance. The mechanical performance test sample refers to a sample cut from a glass substrate for testing mechanical performance. The microstructure test sample refers to a sample cut from a glass substrate for testing microstructure performance. The thermal analyzer refers to an instrument for measuring the thermal performance of a material, and the coefficient of linear thermal expansion of the thermal performance test sample is calculated by measuring the length change of the thermal performance test sample at different temperatures. The preset thermal analyzer refers to a thermal analyzer after the test parameters are set. The test temperature rising rate refers to the speed of the sample temperature rising in the thermal performance test. The test temperature interval refers to the preset temperature interval. The test temperature range refers to the temperature range that the sample experiences in the test. The measurement of the thermal conductivity of the thermal performance test sample is the prior art and will not be described here. The sample length set refers to the set of all lengths of the thermal performance test sample recorded at different temperatures in the thermal performance test. The test temperature set refers to the set of all temperatures of the sample recorded at different temperature points in the thermal performance test. The measurement of the thermal conductivity of the thermal performance test sample refers to the measurement of the thermal conductivity of the thermal performance test sample by the thermal conductivity tester. The thermal conductivity refers to the ability of a material to conduct heat, and the higher the thermal conductivity, the better the heat dissipation performance of the material. The loading rate refers to the speed of the load change applied to the mechanical performance test sample in the mechanical performance test. The mechanical performance test of the mechanical performance test sample with the preset loading rate refers to the mechanical performance test of the mechanical performance test sample by the universal material testing machine and the loading rate. The sample load displacement curve refers to the displacement change curve of the mechanical performance test sample recorded at different loads in the mechanical performance test. The steps of calculating the elastic modulus and the yield strength according to the sample load displacement curve are as follows: obtaining the initial length and the initial cross-sectional area of the mechanical performance test sample, obtaining the yield point, the load change and the displacement change from the sample load displacement curve, calculating the elastic modulus according to the initial length, the load change and the displacement change, and the calculation formula is as follows:

[0102]

[0103] wherein E represents the elastic modulus, ΔF represents the load change, ΔL represents the displacement change, and L0 represents the initial length.

[0104] The yield point load is obtained according to the yield point, and the yield strength is calculated according to the initial cross-sectional area and the yield point load, and the calculation formula is as follows:

[0105]

[0106] wherein γ represents the yield strength, F y represents the yield point load, and A0 represents the initial cross-sectional area.

[0107] It should be further explained that the initial length refers to the length of the mechanical property test sample before the test starts. The initial cross-sectional area refers to the cross-sectional area of the mechanical property test sample before the test starts. The yield point refers to the point on the load-displacement curve at which the material transitions from elastic deformation to plastic deformation. The yield point is obtained by analyzing the load-displacement curve using the data analysis software according to the embodiments of the present application. The load change refers to the change in the load experienced by the mechanical property test sample during the test, i.e., the difference between the final load and the initial load. The displacement change refers to the change in the length of the mechanical property test sample during the test, i.e., the difference between the final length and the initial length. The yield point load refers to the load experienced by the mechanical property test sample at the yield point. The cleaning and coating operation performed on the microstructure test sample refers to first cleaning the microstructure test sample and then coating the surface of the cleaned microstructure test sample with a layer of conductive film. The cleaned test sample refers to the sample obtained after performing the cleaning and coating operation on the microstructure test sample. The AFM image refers to a high-resolution surface topography image used to observe the microstructure and topography of the surface of the microstructure test sample. The step of obtaining the surface roughness of the sample from the AFM image is prior art and will not be described here.

[0108] In detail, the calculation of the average linear thermal expansion coefficient from the sample test group set comprises:

[0109] extracting a sample test group from the sample test group set in sequence, and extracting a preceding test group and a subsequent test group from the sample test group according to the sample test group, wherein the preceding test group comprises a preceding sample length and a preceding test temperature, and the subsequent test group comprises a subsequent sample length and a subsequent test temperature;

[0110] calculating the linear thermal expansion coefficient of the sample test group according to the preceding test group and the subsequent test group, wherein the calculation formula of the linear thermal expansion coefficient is as follows:

[0111]

[0112] wherein α(T i ) represents the linear thermal expansion coefficient of the sample test group, L i+1 represents the subsequent sample length, L i-1 represents the preceding sample length, L i represents the sample length in the sample test group, T i+1 represents the subsequent test temperature, T i-1 represents the preceding test temperature, and i represents the index of the sample test group in the sample test group set;

[0113] taking the subsequent test group as the sample test group, returning to the step of extracting the sample test group from the sample test group set in sequence, and repeating until the sample test group set is empty;

[0114] The bus thermal expansion coefficients are aggregated to obtain a set of linear thermal expansion coefficients, and an average linear thermal expansion coefficient is calculated according to the set of linear thermal expansion coefficients.

[0115] It should be explained that the previous test group refers to the sample test group that is adjacent to the previous sample test group in the sample test group set. The subsequent test group refers to the sample test group that is adjacent to the subsequent sample test group in the sample test group set. For example, the sample test group set is {(L1, T1), (L2, T2), (L3, T3)}, (L2, T2) is the current sample test group, (L1, T1) is the previous test group, and (L3, T3) is the subsequent test group. The linear thermal expansion coefficient refers to the physical quantity of the length change of the material per unit temperature change. The previous sample length refers to the sample length in the previous test group. The previous test temperature refers to the test temperature in the previous test group. The subsequent sample length refers to the sample length in the subsequent test group. The subsequent test temperature refers to the test temperature in the subsequent test group. The average linear thermal expansion coefficient refers to the average value of all linear thermal expansion coefficients in the set of linear thermal expansion coefficients.

[0116] S2, obtain the glass substrate size, chip pin distribution and electrical performance, and design a preliminary array layout according to the preset solder ball pitch, multiple solder balls, glass substrate size, chip pin distribution and electrical performance.

[0117] Specifically, the glass substrate size includes the glass substrate thickness, the glass substrate length and the glass substrate width.

[0118] It should be explained that the glass substrate thickness refers to the thickness of the glass substrate. The glass substrate length refers to the length of the glass substrate. The glass substrate width refers to the width of the glass substrate. The chip pin distribution refers to the position and arrangement of each pin on the chip, and the pin distribution determines the connection mode of the chip and the external circuit. The electrical performance refers to the electrical characteristics of the chip and the substrate, including resistance, capacitance, inductance and other parameters, which determine the quality and efficiency of signal transmission. The preliminary array layout is designed according to the preset solder ball pitch, multiple solder balls, glass substrate size, chip pin distribution and electrical performance, which means that according to the chip pin distribution, the solder balls are placed on the substrate pads corresponding to the pins, according to the electrical performance, the signal line length is reduced to reduce signal delay, and the number of solder balls of power supply and ground line is increased to improve power supply stability, and a preliminary array layout is designed.

[0119] S3, creating a three-dimensional geometric model according to the preliminary array layout, thermal performance parameters, mechanical performance parameters and microstructure parameters.

[0120] It should be explained that the creating a three-dimensional geometric model according to the preliminary array layout, the thermal performance parameters, the mechanical performance parameters and the microstructure parameters refers to creating a substrate geometric model according to the preliminary array layout and a three-dimensional modeling software, and inputting the thermal performance parameters, the mechanical performance parameters and the microstructure parameters into the three-dimensional modeling software to create a three-dimensional geometric model.

[0121] S4, performing thermal loading simulation on the three-dimensional geometric model according to the plurality of preset heating parameters to obtain a plurality of thermal stress distribution maps.

[0122] Specifically, the thermal stress distribution map includes a glass substrate thermal stress distribution and a solder ball thermal stress distribution, and each of the plurality of heating parameters corresponds to a different heating temperature.

[0123] It should be explained that the heating parameter refers to a parameter preset in the thermal loading simulation for controlling temperature change in the simulation process, and the parameter includes a heating temperature rise rate, a heating temperature interval and a heating temperature range. Each of the plurality of heating parameters is different. The thermal loading simulation on the three-dimensional geometric model according to the plurality of preset heating parameters refers to applying temperature change to the three-dimensional geometric model by using a finite element analysis software to simulate the operation of the material under thermal load. The thermal stress distribution map refers to a visualization tool for showing the thermal stress distribution of the material under thermal load, and the concentrated area of the thermal stress can be directly identified by the cloud map.

[0124] S5, performing the following operation on each of the plurality of thermal stress distribution maps: obtaining a maximum thermal stress area from the thermal stress distribution map, obtaining a region position and a maximum thermal stress value according to the maximum thermal stress area, and obtaining an optimal array layout based on the region position and the maximum thermal stress value.

[0125] It should be explained that the maximum thermal stress area refers to the area with the highest thermal stress value in the thermal stress distribution map. The region position refers to the coordinates of the maximum thermal stress area in the three-dimensional geometric model. The maximum thermal stress value refers to the maximum value of the thermal stress in the maximum thermal stress area.

[0126] In detail, the obtaining the optimal array layout based on the region position and the maximum thermal stress value includes:

[0127] comparing the maximum thermal stress value with a preset normal thermal stress threshold value;

[0128] If the maximum thermal stress value is greater than or less than the preset normal thermal stress threshold value, the preliminary array layout is optimized according to the region position and the maximum thermal stress value to obtain a suboptimal array layout, and the preliminary warping deformation amount and the suboptimal warping deformation amount of the preliminary array layout and the suboptimal array layout are calculated respectively.

[0129] comparing the suboptimal warping deformation amount with the preliminary warping deformation amount;

[0130] If the sub-optimal warping deformation is greater than or equal to the preliminary warping deformation, then returning to the step of optimizing the preliminary array layout according to the region position and the maximum thermal stress value;

[0131] If the sub-optimal warping deformation is less than the preliminary warping deformation, then taking the sub-optimal warping deformation as the optimal warping deformation and taking the sub-optimal array layout as the optimal array layout.

[0132] If the maximum thermal stress value is equal to the preset normal thermal stress threshold, then taking the preliminary array layout corresponding to the maximum thermal stress value as the optimal array layout.

[0133] It should be explained that the normal thermal stress threshold refers to a preset thermal stress value for evaluating whether the stress level of the material under thermal load is below the normal thermal stress threshold. The optimization of the preliminary array layout according to the region position and the maximum thermal stress value refers to that if the maximum thermal stress value is greater than the preset normal thermal stress threshold, then the number of solder balls in the maximum thermal stress region is increased to enhance the heat conduction and mechanical support of the region, and if the maximum thermal stress value is less than the preset normal thermal stress threshold, then the pitch of the solder balls in the maximum thermal stress region is reduced. The sub-optimal array layout refers to the layout after the optimization of the preliminary array layout. The preliminary warping deformation refers to the warping deformation obtained in the thermal load simulation of the preliminary array layout. The sub-optimal warping deformation refers to the warping deformation obtained in the thermal load simulation of the sub-optimal array layout. The optimal warping deformation refers to the minimum value of the warping deformation in all optimized array layouts. The optimal array layout refers to the preliminary array layout corresponding to the maximum thermal stress value equal to the normal thermal stress threshold.

[0134] In detail, the calculation of the preliminary warping deformation and the sub-optimal warping deformation of the preliminary array layout and the sub-optimal array layout respectively includes:

[0135] The preliminary warping deformation is calculated according to the preliminary array layout, and the calculation formula of the preliminary warping deformation is as follows:

[0136]

[0137] Wherein, W represents the preliminary warping deformation, σ represents the maximum thermal stress value, U represents the length of the glass substrate, E represents the elastic modulus of the glass substrate, D represents the thickness of the glass substrate, m represents the number of solder balls in the plurality of solder balls, d represents the preset diameter of the solder ball, β1 represents the linear thermal expansion coefficient of the glass substrate, β0 represents the preset thermal expansion coefficient of the solder ball, and s represents the pitch of the solder ball.

[0138] The sub-optimal warping deformation is calculated based on the sub-optimal array layout.

[0139] It should be explained that the solder ball diameter refers to the diameter of the solder ball. The solder ball thermal expansion coefficient refers to the degree of change in size (length, area or volume) of the solder ball material when the temperature changes. The solder ball spacing refers to the center distance between adjacent solder balls in the preliminary array layout. The method for calculating the suboptimal warping deformation amount based on the suboptimal array layout is the same as the method for calculating the preliminary warping deformation amount based on the preliminary array layout, and will not be described here.

[0140] S6, aggregate the optimal array layout to obtain a plurality of optimal array layouts corresponding to a plurality of thermal stress distribution clouds.

[0141] It should be explained that each thermal stress distribution cloud corresponds to an optimal array layout.

[0142] S7, obtaining the optimal array layout from the plurality of optimal array layouts, wherein the optimal array layout is the optimal array layout corresponding to the smallest suboptimal warping deformation amount in the plurality of optimal array layouts.

[0143] It should be explained that the optimal array layout obtained from the plurality of optimal array layouts refers to comparing the suboptimal warping deformation amount of each optimal array layout in the plurality of optimal array layouts to obtain the optimal array layout.

[0144] S8, calculating the solder joint void rate based on the optimal array layout, and completing the low warping solder ball array optimization in the glass substrate FC-BGA packaging based on the solder joint void rate.

[0145] In detail, the calculation of the solder joint void rate based on the optimal array layout comprises:

[0146] An oxidation-resistant coating paint is obtained, and the glass substrate is coated using a pre-constructed coating device and the oxidation-resistant coating paint to obtain an oxidation-resistant glass substrate, wherein the coating speed and paint flow are pre-set in the coating device.

[0147] A solder paste glass substrate is constructed according to the optimal array layout and the oxidation-resistant glass substrate, a plurality of solder balls are attached to the solder paste glass substrate to obtain a glass substrate FC-BGA packaging sample.

[0148] The glass substrate FC-BGA packaging sample is reflow soldered to obtain a soldered formed substrate, and the soldered formed substrate is subjected to multi-slice scanning to obtain an X-ray image set, and the solder joint void rate is calculated according to the X-ray image set.

[0149] It should be explained that the anti-oxidation coating refers to a coating for protecting the surface of a glass substrate from oxidation. For example, the anti-oxidation coating is a nano-composite anti-oxidation coating. The coating device is a device for uniformly coating the anti-oxidation coating on the surface of the glass substrate. The anti-oxidation glass substrate refers to a glass substrate coated with the anti-oxidation coating. In order to prevent the glass substrate from being oxidized during high-temperature soldering, protect the surface quality and electrical performance of the substrate, the anti-oxidation coating is coated. The solder paste glass substrate constructed according to the optimal array layout and the anti-oxidation glass substrate refers to that the solder paste is accurately printed on the pads of the anti-oxidation glass substrate according to the optimal array layout to obtain the solder paste glass substrate. The glass substrate FC-BGA packaging sample refers to the glass substrate after solder ball mounting. The multi-layer tomography of the solder-formed substrate refers to starting the X-ray tomography device to scan layer by layer from the bottom of the solder-formed substrate to the top, record the X-ray image of each layer, and form an X-ray image set.

[0150] In detail, the reflow soldering of the glass substrate FC-BGA packaging sample to obtain the solder-formed substrate includes:

[0151] The temperature upper limit and the temperature lower limit of the thermal stress distribution cloud atlas are obtained by sequentially extracting the thermal stress distribution cloud atlas from the plurality of thermal stress distribution cloud atlases.

[0152] The reflow soldering temperature zone is set according to the temperature upper limit and the temperature lower limit, the reflow soldering temperature zones are summarized to obtain a reflow soldering temperature zone set;

[0153] The reflow soldering temperature zone set is sorted in ascending order to obtain a reflow soldering temperature zone sequence, and the heating rate is set according to the average line thermal expansion coefficient.

[0154] The reflow soldering temperature zone is sequentially extracted from the reflow soldering temperature zone sequence, and the following operations are performed on the extracted reflow soldering temperature zone:

[0155] The pre-constructed reflow soldering furnace is started according to the heating rate, the glass substrate FC-BGA packaging sample is reflow soldered by using the started reflow soldering furnace, the pre-set inert gas and the reflow soldering temperature zone, and real-time monitoring is performed to obtain the soldering furnace temperature and the initial soldering sample.

[0156] It is judged whether the soldering furnace temperature is located in the reflow soldering temperature zone;

[0157] If the soldering furnace temperature is not located in the reflow soldering temperature zone, the soldering furnace temperature is compared with the temperature upper limit, and the soldering furnace temperature and the temperature lower limit are compared;

[0158] If the soldering furnace temperature is greater than the temperature upper limit, a first temperature difference between the soldering furnace temperature and the temperature upper limit is calculated, and the first temperature difference is compared with a pre-set normal temperature difference threshold;

[0159] If the first temperature difference is greater than the preset normal temperature difference threshold, the temperature of the started reflow soldering furnace is adjusted until the first temperature difference is not greater than the preset normal temperature difference threshold, and a first adjusted temperature is obtained.

[0160] If the temperature of the reflow soldering furnace is less than the temperature lower limit, a second temperature difference between the temperature of the reflow soldering furnace and the temperature lower limit is calculated, and the second temperature difference is compared with the normal temperature difference threshold.

[0161] If the second temperature difference is greater than the preset normal temperature difference threshold, the temperature of the started reflow soldering furnace is adjusted until the second temperature difference is not greater than the preset normal temperature difference threshold, and a second adjusted temperature is obtained.

[0162] The first adjusted temperature or the second adjusted temperature is taken as an adjusted temperature, and the initial soldering sample is continuously soldered by using the adjusted temperature, and an initial soldering substrate is obtained.

[0163] The initial soldering substrates are summarized to obtain a soldering substrate, and the soldering substrate is subjected to a cooling treatment to obtain a soldering formed substrate.

[0164] It should be explained that the temperature upper limit refers to the temperature corresponding to the maximum thermal stress value in the thermal stress distribution cloud map. The temperature lower limit refers to the minimum value of the temperature corresponding to the minimum thermal stress value in the thermal stress distribution cloud map. The reflow soldering furnace temperature range refers to the temperature range composed of the temperature upper limit and the temperature lower limit. The reflow soldering furnace temperature range set refers to the set of reflow soldering furnace temperature ranges corresponding to the temperature upper limit and the temperature lower limit in all thermal stress distribution cloud maps. The purpose of sorting the reflow soldering furnace temperature range set in ascending order is to ensure that the temperature gradually increases during the soldering process, thereby reducing thermal stress concentration. The reflow soldering furnace temperature range sequence refers to the sequence formed by arranging the temperature ranges in the reflow soldering furnace temperature range set in ascending order of temperature. The setting of the heating rate according to the average line thermal expansion coefficient refers to the artificial setting of the heating rate according to the average line thermal expansion coefficient. For example, if the average line thermal expansion coefficient is 5x10 - 6 1 / K, the heating rate can be set to 3℃ / min, and if the thermal expansion coefficient is 10x10 -61 / K, the heating rate is set to 2℃ / min. The reflow soldering furnace refers to a device for electronic packaging and soldering, which realizes the melting and solidification of solder by controlling temperature change. The inert gas refers to the gas used in the soldering process. For example, the inert gas is nitrogen or argon. The inert gas in the embodiment of the present application is used to exclude oxygen in the soldering area to prevent solder oxidation. The furnace temperature refers to the actual temperature reached by the reflow soldering furnace during the soldering process. The initial soldering sample refers to a sample that has experienced part of the temperature stage but has not completed the entire soldering process during the reflow soldering process. The first temperature difference refers to the temperature difference between the furnace temperature and the upper temperature limit. The normal temperature difference threshold refers to a pre-set temperature difference value for evaluating the furnace temperature. The first adjusted temperature refers to the adjusted reflow soldering furnace temperature when the furnace temperature exceeds the upper temperature limit. The second temperature difference refers to the temperature difference between the furnace temperature and the lower temperature limit. The second adjusted temperature refers to the adjusted reflow soldering furnace temperature when the furnace temperature is lower than the lower temperature limit. The adjusted temperature refers to the adjusted reflow soldering furnace temperature, which can be the first adjusted temperature or the second adjusted temperature. By adjusting the temperature, it is ensured that the solder can be fully melted during the soldering process, reducing soldering defects. The initial soldering substrate refers to the substrate obtained by continuously soldering the initial soldering sample using the adjusted temperature. The soldering substrate refers to the substrate after the reflow soldering furnace temperature sequence soldering process. The cooling process of the soldering substrate refers to the soldering formed substrate obtained by forced cooling of the soldering substrate using a cooling device (such as a fan, a cooling tunnel). The forced cooling speed is fast, which can reduce the residence time of the soldering substrate at high temperature and improve the production efficiency.

[0165] In detail, the solder joint porosity is calculated according to the X-ray image set, comprising:

[0166] The multi-layer fault thickness, the multi-layer hole cross-sectional area and the multi-layer solder joint cross-sectional area are obtained based on the X-ray image set, wherein the fault thickness, the hole cross-sectional area and the solder joint cross-sectional area are one-to-one corresponding;

[0167] The average fault thickness is calculated according to the multi-layer fault thickness, and the solder joint porosity is calculated according to the average fault thickness, the multi-layer hole cross-sectional area and the multi-layer solder joint cross-sectional area, wherein the calculation formula of the solder joint porosity is as follows:

[0168]

[0169] Wherein, R represents the solder joint porosity, A 1,j represents the jth layer hole cross-sectional area, A 2,j represents the jth layer solder joint cross-sectional area, n represents the number of layers of the fault scan, t j represents the jth layer fault thickness, represents the average fault thickness, and j represents the index of the number of layers.

[0170] It should be explained that the average slice thickness refers to the average value of all slice thicknesses in multi-slice tomography. The average slice thickness in the embodiment of the present application is used to standardize the cross-sectional area of the voids and the cross-sectional area of the welds of different layers, so as to facilitate the calculation of the void rate of the welds. The void rate of the welds is an important indicator for evaluating the welding quality, and the lower the void rate, the better the welding quality. The number of layers of tomography refers to the number of layers of tomography for the welds in multi-slice tomography. The more the number of layers of tomography, the more detailed information about the internal structure of the welds can be obtained, and the accuracy of the calculation of the void rate of the welds is improved.

[0171] In detail, the multi-layer slice thickness, the multi-layer cross-sectional area of the voids and the multi-layer cross-sectional area of the welds are obtained based on the X-ray image set, comprising:

[0172] Each X-ray image in the X-ray image set is denoised to obtain a denoised X-ray image set;

[0173] The denoised X-ray images in the denoised X-ray image set are sequentially extracted, and the denoised X-ray images are grayed to obtain grayed images, wherein the grayed images comprise a plurality of pixels, and one pixel corresponds to one gray value;

[0174] The pixels are sequentially extracted from the plurality of pixels, and the gray values corresponding to the extracted pixels are identified, and the gray values are compared with the preset gray threshold value;

[0175] If the gray value is greater than the preset gray threshold value, the pixel corresponding to the gray value is marked as a white pixel;

[0176] If the gray value is less than or equal to the preset gray threshold value, the pixel corresponding to the gray value is marked as a black pixel;

[0177] The white pixels and the black pixels are respectively summarized to obtain a white pixel set and a black pixel set, the region corresponding to the black pixel set is taken as a background region, and the region corresponding to the white pixel set is taken as a weld region;

[0178] The background region and the weld region are respectively summarized to obtain a background region set and a weld region set, and a plurality of void regions are identified from the weld region set;

[0179] The multi-layer cross-sectional area of the voids is confirmed according to the plurality of void regions, and the multi-layer cross-sectional area of the welds and the multi-layer slice thickness are obtained according to the weld region set, the background region set and the plurality of void regions.

[0180] It should be explained that the denoising of each X-ray image in the X-ray image set to obtain the denoised X-ray image set means that each X-ray image in the X-ray image set is denoised by using a filtering algorithm to obtain the denoised X-ray image set. For example, the denoising algorithm is median filtering, Gaussian filtering, bilateral filtering, etc. The gray-scale processing of the denoised X-ray image means that the denoised X-ray image is gray-scaled by using the weighted average method. The gray-scaled image means the image after the color image is converted into a gray-scaled image, and each pixel in the gray-scaled image is represented by a gray value. The gray threshold means a preset gray value, which is used to distinguish different regions in the gray-scaled image. The white pixel means a pixel with a gray value greater than the preset gray threshold. The black pixel means a pixel with a gray value less than or equal to the preset gray threshold. The white pixel set means a set composed of all white pixels. The black pixel set means a set composed of all black pixels. The background region means a part in the gray-scaled image that does not belong to the solder joint region. The solder joint region means a region in the gray-scaled image where the solder joint is located. The background region set means a set composed of all background regions. The solder joint region set means a region composed of all solder joint regions. The identification of the plurality of hollow regions from the solder joint region set means that each solder joint region in the solder joint region set is segmented by using an image processing algorithm (such as connected component analysis, morphological operation), and the plurality of hollow regions are identified. The hollow cross-sectional area means the cross-sectional area of the hollow region. The solder joint cross-sectional area means the cross-sectional area of the solder joint region. The cross-sectional area means in geometry, the cross-sectional area means the two-dimensional projection area of an object on a certain plane. The thickness of the fault means in multi-layer fault scanning, the actual physical thickness represented by each layer of image.

[0181] The application is to solve the problems described in the background art. The application confirms the glass substrate and the plurality of solder balls, obtains the thermal performance parameters, mechanical performance parameters and microstructure parameters according to the glass substrate. The thermal performance parameters help to understand the thermal response characteristics of the glass substrate when the temperature changes, so as to accurately predict the thermal stress distribution. The mechanical performance parameters can be used to analyze the deformation of the glass substrate when it is stressed. In the optimization of the solder ball array layout, the packaging failure caused by insufficient mechanical performance can be avoided. The microstructure parameters reflect the internal structure characteristics of the glass substrate, which plays an important role in understanding its physical properties and failure mechanism. The size of the glass substrate, the chip pin distribution and the electrical performance are obtained. According to the preset solder ball spacing, the plurality of solder balls, the glass substrate size, the chip pin distribution and the electrical performance, a preliminary array layout is designed. The glass substrate size includes the glass substrate thickness, the glass substrate length and the glass substrate width. The glass substrate size ensures that the solder balls can be reasonably distributed on the glass substrate, avoiding the layout exceeding the substrate range. The chip pin distribution determines the electrical connection mode between the solder balls and the chip. Accurate acquisition of the pin distribution information helps to design a solder ball array that meets the electrical connection requirements. According to the electrical performance, the solder ball array can ensure that the electrical performance of the packaging meets the design standard. According to the preliminary array layout, the thermal performance parameters, the mechanical performance parameters and the microstructure parameters, a three-dimensional geometric model is created. The application combines the thermal performance parameters, the mechanical performance parameters and the microstructure parameters to more realistically simulate the physical behavior of the glass substrate and the solder balls in actual work, improving the accuracy of the simulation results. According to the plurality of preset heating parameters, the three-dimensional geometric model is simulated for thermal loading, obtaining a plurality of thermal stress distribution maps. The thermal stress distribution map includes the glass substrate thermal stress distribution and the solder ball thermal stress distribution. Each heating parameter in the plurality of heating parameters corresponds to a different heating temperature. The different heating temperatures simulate the thermal response of the glass substrate in different working environments. Through the plurality of heating parameters, the distribution rule of the thermal stress can be more comprehensively understood. For each thermal stress distribution map in the plurality of thermal stress distribution maps, the following operations are performed: obtaining the maximum thermal stress area from the thermal stress distribution map, obtaining the area position and the maximum thermal stress value according to the maximum thermal stress area, and obtaining the best array layout based on the area position and the maximum thermal stress value. The maximum thermal stress area is the part of the packaging that is most likely to fail. Accurate acquisition of the position and stress value of this area helps to optimize the solder ball array layout and adjust the distribution of the solder balls, which can effectively reduce the thermal stress of this area and improve the reliability of the packaging. The best array layouts are summarized to obtain a plurality of best array layouts corresponding to the plurality of thermal stress distribution maps. The best array layouts are summarized under different heating parameters to provide a plurality of candidate schemes for subsequent selection of the optimal array layout. According to the plurality of best array layouts, the optimal array layout is obtained. The optimal array layout is the best array layout corresponding to the smallest suboptimal warping deformation amount in the plurality of best array layouts.The optimal array layout is selected as the optimal array layout corresponding to the minimum deformation amount by comparing the suboptimal warping deformation amounts corresponding to multiple optimal array layouts, the warping deformation of the glass substrate can be effectively reduced, the flatness and reliability of the package are improved, the solder void ratio is calculated based on the optimal array layout, and the low warping solder ball array optimization in the glass substrate FC-BGA package is completed based on the solder void ratio, the welding quality under the optimal array layout can be evaluated by calculating the solder void ratio, and therefore, the optimization precision and efficiency of the solder ball layout can be improved.

[0182] As shown in Figure 2 is a functional module diagram of a low warping solder ball array optimization system in a glass substrate FC-BGA package provided by an embodiment of the application.

[0183] The low warping solder ball array optimization system 100 in the glass substrate FC-BGA package can be installed in an electronic device. According to the functions to be realized, the low warping solder ball array optimization system 100 in the glass substrate FC-BGA package can include a preliminary array layout design module 101, a thermal loading simulation module 102, an optimal array layout acquisition module 103, and a solder void ratio calculation module 104. The modules of the application can also be referred to as units, which refer to a series of computer program segments that can be executed by an electronic device processor and can complete a fixed function, and are stored in the memory of the electronic device.

[0184] The preliminary array layout design module 101 is configured to confirm a glass substrate and a plurality of solder balls, acquire thermal performance parameters, mechanical performance parameters, and microstructure parameters from the glass substrate, acquire glass substrate dimensions, chip pin distribution, and electrical performance, and design a preliminary array layout according to a preset solder ball pitch, the plurality of solder balls, the glass substrate dimensions, the chip pin distribution, and the electrical performance. The glass substrate dimensions include a glass substrate thickness, a glass substrate length, and a glass substrate width.

[0185] The thermal loading simulation module 102 is configured to create a three-dimensional geometric model according to the preliminary array layout, the thermal performance parameters, the mechanical performance parameters, and the microstructure parameters, perform thermal loading simulation on the three-dimensional geometric model according to a plurality of preset heating parameters, and obtain a plurality of thermal stress distribution maps, wherein the thermal stress distribution maps include glass substrate thermal stress distribution and solder ball thermal stress distribution, and the heating temperature corresponding to each heating parameter in the plurality of heating parameters is different.

[0186] The optimal array layout obtaining module 103 is configured to perform the following operations on each thermal stress distribution nephogram in the plurality of thermal stress distribution nephograms: obtaining a maximum thermal stress region from the thermal stress distribution nephogram, obtaining a region position and a maximum thermal stress value according to the maximum thermal stress region, obtaining an optimal array layout based on the region position and the maximum thermal stress value, and summarizing the optimal array layouts to obtain a plurality of optimal array layouts corresponding to the plurality of thermal stress distribution nephograms.

[0187] The solder void rate calculating module 104 is configured to obtain an optimal array layout according to the plurality of optimal array layouts, wherein the optimal array layout is an optimal array layout corresponding to a minimum suboptimal warping deformation amount in the plurality of optimal array layouts, to calculate a solder void rate based on the optimal array layout, and to complete the low warping ball grid array optimization in the glass substrate FC-BGA packaging based on the solder void rate.

[0188] In detail, the modules in the glass substrate FC-BGA packaging low warping ball grid array optimization system 100 in the embodiment of the present application adopt the same technical means as the glass substrate FC-BGA packaging low warping ball grid array optimization method in the above Figure 1 , and can produce the same technical effects, which will not be described here.

[0189] As shown in Figure 3 , it is a structural schematic diagram of an electronic device for implementing the glass substrate FC-BGA packaging low warping ball grid array optimization method according to an embodiment of the present application.

[0190] The electronic device 1 can include a processor 10, a memory 11 and a bus 12, and can further include a computer program stored in the memory 11 and executable on the processor 10, such as a glass substrate FC-BGA packaging low warping ball grid array optimization method program.

[0191] The memory 11 includes at least one type of readable storage medium, such as a flash memory, a mobile hard disk, a multimedia card, a card-type memory (e.g., an SD or DX memory, etc.), a magnetic memory, a disk, an optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as a mobile hard disk of the electronic device 1. In other embodiments, the memory 11 can also be an external storage device of the electronic device 1, such as a plug-in mobile hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 1. Further, the memory 11 includes both an internal storage unit and an external storage device of the electronic device 1. The memory 11 can be used to store application software and various data installed on the electronic device 1, such as the code of the glass substrate FC-BGA package low-warp solder ball array optimization method program, and can also be used to temporarily store data that has been output or will be output.

[0192] The processor 10 can be composed of an integrated circuit in some embodiments, such as a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more combinations of a central processing unit (CPU), a microprocessor, a digital processing chip, a graphics processor, and various control chips, etc. The processor 10 is the control unit of the electronic device, which connects various components of the entire electronic device through various interfaces and lines, executes programs or modules stored in the memory 11 (such as the glass substrate FC-BGA package low-warp solder ball array optimization method program, etc.), and calls data stored in the memory 11, to perform various functions and process data of the electronic device 1.

[0193] The bus 12 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize the connection and communication between the memory 11 and at least one processor 10, etc.

[0194] Figure 3 Only the electronic device with components is shown, and those skilled in the art can understand that, Figure 3The illustrated structure does not constitute a limitation on the electronic device 1, and can include fewer or more components than illustrated, or combine certain components, or different component arrangements.

[0195] For example, although not shown, the electronic device 1 can also include a power source (such as a battery) to power the various components, and preferably the power source can be logically connected to the at least one processor 10 through a power management device, so that the power management device can implement functions such as charge management, discharge management, and power consumption management. The power source can also include one or more DC or AC power sources, recharging devices, power failure detection circuits, power converters or inverters, power status indicators, and any other components. The electronic device 1 can also include various sensors, Bluetooth modules, Wi-Fi modules, and the like, which are not described here.

[0196] Further, the electronic device 1 can also include a network interface, which can optionally include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), and is typically used to establish a communication connection between the electronic device 1 and other electronic devices.

[0197] Optionally, the electronic device 1 can also include a user interface, which can be a display (Display), an input unit (such as a keyboard (Keyboard)), and optionally a standard wired interface, a wireless interface. Optionally, in some embodiments, the display can be an LED display, a liquid crystal display, a touch liquid crystal display, and an OLED (Organic Light-Emitting Diode) touch, etc. The display can also be appropriately referred to as a display screen or a display unit, and is used to display information processed in the electronic device 1 and to display a visualized user interface.

[0198] The glass substrate FC-BGA package low-warp solder ball array optimization method program stored in the memory 11 in the electronic device 1 is a combination of multiple instructions, which, when executed in the processor 10, can achieve:

[0199] Confirming the glass substrate and the plurality of solder balls, obtaining thermal performance parameters, mechanical performance parameters, and microstructure parameters from the glass substrate;

[0200] Obtaining glass substrate size, chip pin distribution, and electrical performance, and designing a preliminary array layout according to the predetermined solder ball pitch, the plurality of solder balls, the glass substrate size, the chip pin distribution, and the electrical performance, wherein the glass substrate size includes glass substrate thickness, glass substrate length, and glass substrate width;

[0201] According to the preliminary array layout, the thermal performance parameters, the mechanical performance parameters and the microstructure parameters, a three-dimensional geometric model is created;

[0202] According to the preset plurality of heating parameters, the three-dimensional geometric model is simulated for thermal loading, and a plurality of thermal stress distribution clouds are obtained, wherein the thermal stress distribution cloud includes: glass substrate thermal stress distribution and solder ball thermal stress distribution, wherein the heating temperature corresponding to each heating parameter in the plurality of heating parameters is different;

[0203] For each thermal stress distribution cloud in the plurality of thermal stress distribution clouds, the following operations are performed:

[0204] The maximum thermal stress area is obtained from the thermal stress distribution cloud, the area position and the maximum thermal stress value are obtained according to the maximum thermal stress area, and the best array layout is obtained based on the area position and the maximum thermal stress value;

[0205] The best array layout is summarized, and a plurality of best array layouts corresponding to the plurality of thermal stress distribution clouds are obtained;

[0206] According to the plurality of best array layouts, an optimal array layout is obtained, wherein the optimal array layout is the best array layout corresponding to the minimum suboptimal warping deformation amount in the plurality of best array layouts;

[0207] Based on the optimal array layout, the solder joint void rate is calculated, and the low warping solder ball array optimization in the glass substrate FC-BGA packaging is completed based on the solder joint void rate.

[0208] Specifically, the specific implementation method of the processor 10 to the above instructions can refer to Figures 1 to 3 The description of related steps in the corresponding embodiments will not be repeated here.

[0209] Further, the modules / units integrated in the electronic device 1 can be stored in a computer readable storage medium if they are realized in the form of software function units and sold or used as independent products. The computer readable storage medium can be volatile or non-volatile. For example, the computer readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory).

[0210] The application also provides a computer readable storage medium, which stores a computer program, and the computer program can realize the following when executed by a processor of an electronic device:

[0211] Confirming the glass substrate and the plurality of solder balls, obtaining the thermal performance parameters, the mechanical performance parameters and the microstructure parameters according to the glass substrate;

[0212] Obtaining a glass substrate size, a chip pin distribution and an electrical performance, and designing a preliminary array layout according to a preset solder ball pitch, a plurality of solder balls, the glass substrate size, the chip pin distribution and the electrical performance, wherein the glass substrate size comprises a glass substrate thickness, a glass substrate length and a glass substrate width;

[0213] Creating a three-dimensional geometric model according to the preliminary array layout, a thermal performance parameter, a mechanical performance parameter and a microstructure parameter;

[0214] Performing thermal loading simulation on the three-dimensional geometric model according to a plurality of preset heating parameters to obtain a plurality of thermal stress distribution cloud diagrams, wherein the thermal stress distribution cloud diagram comprises a glass substrate thermal stress distribution and a solder ball thermal stress distribution, and the heating temperature corresponding to each heating parameter in the plurality of heating parameters is different;

[0215] Each thermal stress distribution cloud diagram in the plurality of thermal stress distribution cloud diagrams is subjected to the following operations:

[0216] Obtaining a maximum thermal stress region from the thermal stress distribution cloud diagram, obtaining a region position and a maximum thermal stress value according to the maximum thermal stress region, and obtaining an optimal array layout based on the region position and the maximum thermal stress value;

[0217] Summarizing the optimal array layout to obtain a plurality of optimal array layouts corresponding to the plurality of thermal stress distribution cloud diagrams;

[0218] Obtaining an optimal array layout according to the plurality of optimal array layouts, wherein the optimal array layout is an optimal array layout corresponding to a minimum suboptimal warping deformation amount in the plurality of optimal array layouts;

[0219] Calculating a solder joint void rate based on the optimal array layout, and completing low warping solder ball array optimization in glass substrate FC-BGA packaging based on the solder joint void rate.

[0220] In several embodiments provided in the present application, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the above-described system embodiments are only illustrative, and actual implementation can have another division way.

[0221] The modules described as separate components can or can not be physically separated, and the components shown as modules can or can not be physical units, that is, they can be located in one place, or they can be distributed on a plurality of network units. According to actual needs, part or all of the modules can be selected to achieve the purpose of the present embodiment.

[0222] In addition, each function module in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of hardware plus software function module.

[0223] It is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be realized in other specific forms without departing from the spirit or essential characteristics of the present application.

[0224] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not limiting. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A method for optimizing low warpage solder ball arrays in glass substrate FC-BGA packaging, characterized in that: The method comprises: Identify the glass substrate and multiple solder balls, and obtain thermal performance parameters, mechanical performance parameters, and microstructure parameters based on the glass substrate; Obtaining the glass substrate dimensions, chip pin distribution, and electrical performance, and designing a preliminary array layout based on a preset solder ball pitch, a plurality of solder balls, the glass substrate dimensions, the chip pin distribution, and electrical performance, wherein the glass substrate dimensions include: glass substrate thickness, glass substrate length, and glass substrate width; Create a three-dimensional geometric model based on preliminary array layout, thermal performance parameters, mechanical performance parameters and microstructure parameters; Performing a thermal loading simulation on the three-dimensional geometric model according to a plurality of preset heating parameters to obtain a plurality of thermal stress distribution cloud maps, wherein the thermal stress distribution cloud maps include: thermal stress distribution of the glass substrate and thermal stress distribution of the solder balls, wherein each of the plurality of heating parameters corresponds to a different heating temperature; Perform the following operations on each of the multiple thermal stress distribution cloud maps: Obtain the maximum thermal stress area from the thermal stress distribution cloud map, obtain the area position and maximum thermal stress value based on the maximum thermal stress area, and obtain the optimal array layout based on the area position and maximum thermal stress value; Summarizing the optimal array layouts to obtain multiple optimal array layouts corresponding to multiple thermal stress distribution cloud maps; Obtaining an optimal array layout according to the multiple optimal array layouts, wherein the optimal array layout is the optimal array layout corresponding to the minimum suboptimal warping deformation among the multiple optimal array layouts; The solder joint void ratio is calculated based on the optimal array layout, and the low warpage solder ball array in the glass substrate FC-BGA package is optimized based on the solder joint void ratio.

2. The method for optimizing low warpage solder ball array in glass substrate FC-BGA package according to claim 1, characterized in that: The obtaining of thermal performance parameters, mechanical performance parameters and microstructure parameters based on the glass substrate includes: Cutting thermal performance test samples, mechanical performance test samples, and microstructure test samples from a glass substrate, and setting a pre-built thermal analyzer using preset test parameters to obtain a preset thermal analyzer, wherein the test parameters include: a test heating rate, a test temperature interval, and a test temperature range; Using a preset thermal analyzer to measure the thermal performance test sample, obtain a sample length set and a test temperature set, and obtain a sample test group set according to the sample length set and the test temperature set, wherein the sample test group set includes multiple sample test groups, and the sample test group includes: sample length and test temperature; Calculate the average linear thermal expansion coefficient based on the sample test set, measure the thermal conductivity of the thermal performance test sample to obtain the thermal conductivity, and use the average linear thermal expansion coefficient and thermal conductivity as thermal performance parameters; Performing mechanical property tests on the mechanical property test samples using a preset loading rate to obtain a load-displacement curve of the sample; Calculate the elastic modulus and yield strength according to the sample load-displacement curve, and use the elastic modulus and yield strength as mechanical performance parameters; A cleaning and coating operation is performed on the microstructure test sample to obtain a clean test sample, an AFM image is obtained based on the clean test sample, and the surface roughness of the sample is obtained based on the AFM image, and the surface roughness of the sample is used as a microstructure parameter.

3. The method for optimizing low warpage solder ball array in glass substrate FC-BGA package according to claim 2, characterized in that: Calculating the average linear thermal expansion coefficient based on the sample test set includes: Extracting sample test groups from the sample test group set in sequence, and extracting a preceding test group and a subsequent test group from the sample test group set according to the sample test groups, wherein the preceding test group includes: a preceding sample length and a preceding test temperature, and the subsequent test group includes: a subsequent sample length and a subsequent test temperature; The linear thermal expansion coefficient of the sample test group is calculated based on the preceding test group and the following test group. The calculation formula of the linear thermal expansion coefficient is as follows: Among them, α(T i ) represents the linear thermal expansion coefficient of the sample test group, L i+1 Indicates the length of the subsequent sample, L i-1 Indicates the length of the preceding sample, L i Indicates the sample length in the sample test group, T i+1 Indicates the subsequent test temperature, T i-1 represents the previous test temperature, i represents the index of the sample test group in the sample test group set; Taking the subsequent test group as the sample test group, returning to the step of sequentially extracting the sample test groups from the sample test group set until the sample test group set is an empty set; The linear thermal expansion coefficients are summarized to obtain a linear thermal expansion coefficient set, and an average linear thermal expansion coefficient is calculated based on the linear thermal expansion coefficient set.

4. The method for optimizing a low warpage solder ball array in a glass substrate FC-BGA package according to claim 3, wherein: The obtaining of the optimal array layout based on the regional position and the maximum thermal stress value includes: comparing the maximum thermal stress value with a preset normal thermal stress threshold; If the maximum thermal stress value is greater than or less than the preset normal thermal stress threshold, the preliminary array layout is optimized according to the regional position and the maximum thermal stress value to obtain a suboptimal array layout, and the preliminary warping deformation and suboptimal warping deformation of the preliminary array layout and the suboptimal array layout are calculated respectively; Compare the suboptimal warpage with the preliminary warpage; If the suboptimal warpage deformation is greater than or equal to the preliminary warpage deformation, returning to the step of optimizing the preliminary array layout according to the regional position and the maximum thermal stress value; If the suboptimal warping deformation is smaller than the preliminary warping deformation, the suboptimal warping deformation is taken as the optimal warping deformation, and the suboptimal array layout is taken as the optimal array layout; If the maximum thermal stress value is equal to the preset normal thermal stress threshold, the preliminary array layout corresponding to the maximum thermal stress value is used as the optimal array layout.

5. The method for optimizing low warpage solder ball array in glass substrate FC-BGA package according to claim 4, characterized in that: The calculating of the preliminary warping deformation amount and the suboptimal warping deformation amount of the preliminary array layout and the suboptimal array layout respectively includes: The preliminary warpage deformation is calculated based on the preliminary array layout, where the calculation formula of the preliminary warpage deformation is as follows: Wherein, W represents the initial warpage deformation, σ represents the maximum thermal stress value, U represents the length of the glass substrate, E represents the elastic modulus of the glass substrate, D represents the thickness of the glass substrate, m represents the number of solder balls in the plurality of solder balls, d represents the preset solder ball diameter, β1 represents the linear thermal expansion coefficient of the glass substrate, β0 represents the preset solder ball thermal expansion coefficient, and s represents the solder ball spacing; Calculate suboptimal warpage based on suboptimal array layout.

6. The method for optimizing low warpage solder ball array in glass substrate FC-BGA package according to claim 5, characterized in that: The calculating of solder joint void ratio based on the optimal array layout includes: Obtaining an anti-oxidation coating paint, and coating a glass substrate with the anti-oxidation coating paint using a pre-built coating device and the anti-oxidation coating paint to obtain an anti-oxidation glass substrate, wherein the coating device is preset with a coating speed and a coating flow rate; A solder paste glass substrate was constructed based on the optimal array layout and the anti-oxidation glass substrate, and multiple solder balls were mounted on the solder paste glass substrate to obtain a glass substrate FC-BGA package sample. Reflow soldering was performed on a glass substrate FC-BGA package sample to obtain a soldered substrate. Multi-layer tomography was performed on the soldered substrate to obtain an X-ray image set, and the solder joint void rate was calculated based on the X-ray image set.

7. The method for optimizing a low warpage solder ball array in a glass substrate FC-BGA package according to claim 6, wherein: The method of reflow soldering the glass substrate FC-BGA package sample to obtain a soldered formed substrate comprises: Extract thermal stress distribution cloud maps from multiple thermal stress distribution cloud maps in sequence to obtain the upper and lower temperature limits of the thermal stress distribution cloud maps; Set the reflow oven temperature zone according to the upper temperature limit and the lower temperature limit, summarize the reflow oven temperature zones, and obtain a reflow oven temperature zone set; Sorting the reflow oven temperature zone set in ascending order to obtain a reflow oven temperature zone sequence, and setting a heating rate according to the average linear thermal expansion coefficient; Extract reflow oven temperature zones from the reflow oven temperature zone sequence in sequence, and perform the following operations on each extracted reflow oven temperature zone: The pre-built reflow oven is started according to the heating rate. The glass substrate FC-BGA package sample is reflow soldered using the started reflow oven, the preset inert gas and the reflow oven temperature zone. The reflow oven temperature and the initial soldering sample are obtained by real-time monitoring. Determine whether the soldering furnace temperature is within the reflow oven temperature zone; If the soldering oven temperature is not within the reflow oven temperature zone, compare the soldering oven temperature with the upper temperature limit and the soldering oven temperature with the lower temperature limit; If the soldering furnace temperature is greater than the upper temperature limit, a first temperature difference between the soldering furnace temperature and the upper temperature limit is calculated, and the first temperature difference is compared with a preset normal temperature difference threshold; If the first temperature difference is greater than a preset normal temperature difference threshold, the temperature of the reflow oven after startup is adjusted until the first temperature difference is no greater than the preset normal temperature difference threshold, thereby obtaining a first set temperature; If the soldering furnace temperature is lower than the lower temperature limit, a second temperature difference between the soldering furnace temperature and the lower temperature limit is calculated, and the second temperature difference is compared with a normal temperature difference threshold; If the second temperature difference is greater than the preset normal temperature difference threshold, the temperature of the reflow oven after startup is adjusted until the second temperature difference is no greater than the preset normal temperature difference threshold, thereby obtaining a second set temperature; Using the first setting temperature or the second setting temperature as the setting temperature, and continuously welding the initial welding sample at the setting temperature to obtain an initial welding substrate; The initial welding substrates are collected to obtain a welding substrate, and the welding substrates are cooled to obtain a welding forming substrate.

8. The method for optimizing a low warpage solder ball array in a glass substrate FC-BGA package according to claim 7, wherein: Calculating the solder joint void rate based on the X-ray image set includes: Obtaining multi-layer fault thickness, multi-layer void cross-sectional area, and multi-layer solder joint cross-sectional area based on the X-ray image set, wherein the fault thickness, void cross-sectional area, and solder joint cross-sectional area correspond to each other one by one; The average fault thickness is calculated based on the multi-layer fault thickness, and the solder void rate is calculated based on the average fault thickness, the multi-layer void cross-sectional area, and the multi-layer solder point cross-sectional area. The calculation formula for the solder void rate is as follows: Among them, R represents the void ratio of solder joints, A 1,j represents the cross-sectional area of ​​the void in the jth layer, j represents the cross-sectional area of ​​the solder joint in the jth layer, n represents the number of layers of tomography, and t j represents the thickness of the j-th fault layer, represents the average fault thickness, and j represents the index of the layer number.

9. The method for optimizing a low warpage solder ball array in a glass substrate FC-BGA package according to claim 8, wherein: The method of obtaining multi-layer slice thickness, multi-layer cavity cross-sectional area and multi-layer solder joint cross-sectional area based on the X-ray image set includes: Denoising is performed on each X-ray image in the X-ray image set to obtain a denoised X-ray image set; Extracting denoised X-ray images from the denoised X-ray image set in sequence, gray-scaling the denoised X-ray images to obtain gray-scale images, wherein the gray-scale image includes: a plurality of pixels, each pixel corresponding to a grayscale value; Extracting pixels from a plurality of pixels in sequence, identifying grayscale values ​​corresponding to the extracted pixels, and comparing the grayscale values ​​with a preset grayscale threshold; If the grayscale value is greater than the preset grayscale threshold, the pixel corresponding to the grayscale value is marked as a white pixel; If the grayscale value is less than or equal to the preset grayscale threshold, the pixel corresponding to the grayscale value is marked as a black pixel; Summarize the white pixels and black pixels to obtain a white pixel set and a black pixel set, use the area corresponding to the black pixel set as the background area, and use the area corresponding to the white pixel set as the solder joint area; The background area and the solder joint area are summarized respectively to obtain a background area set and a solder joint area set, and multiple void areas are identified from the solder joint area set; The multi-layer void cross-sectional areas are determined based on the multiple void regions, and the multi-layer solder joint cross-sectional areas and multi-layer fault thicknesses are obtained based on the solder joint region set, the background region set, and the multiple void regions.

10. A low warpage solder ball array optimization system for glass substrate FC-BGA packaging, characterized in that: The system comprises: A preliminary array layout design module is used to identify a glass substrate and multiple solder balls, obtain thermal performance parameters, mechanical performance parameters, and microstructure parameters based on the glass substrate, obtain the glass substrate size, chip pin distribution, and electrical performance, and design a preliminary array layout based on the preset solder ball pitch, multiple solder balls, glass substrate size, chip pin distribution, and electrical performance. The glass substrate size includes: glass substrate thickness, glass substrate length, and glass substrate width; A thermal loading simulation module is used to create a three-dimensional geometric model based on the preliminary array layout, thermal performance parameters, mechanical performance parameters, and microstructure parameters, and to perform thermal loading simulation on the three-dimensional geometric model according to multiple preset heating parameters to obtain multiple thermal stress distribution cloud maps, wherein the thermal stress distribution cloud maps include: thermal stress distribution of the glass substrate and thermal stress distribution of the solder balls, wherein each of the multiple heating parameters corresponds to a different heating temperature; an optimal array layout acquisition module, configured to perform the following operations on each of the multiple thermal stress distribution cloud maps: obtaining a maximum thermal stress region from the thermal stress distribution cloud map, obtaining a region position and a maximum thermal stress value based on the maximum thermal stress region, obtaining an optimal array layout based on the region position and the maximum thermal stress value, and summarizing the optimal array layouts to obtain multiple optimal array layouts corresponding to the multiple thermal stress distribution cloud maps; The solder joint void rate calculation module is used to obtain the optimal array layout based on multiple optimal array layouts, wherein the optimal array layout is the optimal array layout corresponding to the minimum suboptimal warpage deformation among the multiple optimal array layouts. The solder joint void rate is calculated based on the optimal array layout, and the low warpage solder ball array optimization in the glass substrate FC-BGA package is completed based on the solder joint void rate.

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