A chip batch detection system and method

Abstract

The application discloses a chip batch detection system and method, and relates to the technical field of computer processing.The system comprises an image acquisition and processing module, which is used for acquiring a chip array image, extracting channel features of the chip array image, and obtaining a chip mask; an image recognition module, which is used for obtaining a local image block of the chip mask by traversing the chip mask by using a preset size sliding window; an image deep processing module, which is used for predicting a defect probability of the local image block of the chip mask by using a preset first convolutional neural network, obtaining a defect heat map of the chip array image, and selecting a region meeting a preset defect standard as a chip region to be detected after threshold segmentation processing of the defect heat map; and a judgment module, which is used for positioning and segmenting the chip region to be detected and obtaining a chip-level detection result. The application realizes batch detection of chips, and improves the recognition rate of the detection result.

Description

Technical Field

[0001] This invention relates to the field of computer processing technology, and in particular to a chip batch testing system and method. Background Technology

[0002] As integrated circuit manufacturing processes enter the nanoscale era, the complexity of chip internal structures and the microscopic nature of surface features pose unprecedented challenges to quality inspection. In the semiconductor industry chain, chip appearance defects (such as microcracks, scratches, holes, and contamination) have become a major cause of early device failure. Traditional inspection methods mainly rely on two technical routes: one is manual visual inspection, where operators observe the chip surface one by one using an optical microscope. This method is not only inefficient (averaging more than 3 seconds per chip), but also suffers from a false negative rate of over 10% due to visual fatigue and subjective judgment differences, especially with a severe deficiency in identifying minute defects below 20 micrometers. The other is an electrical testing-based inspection scheme, which verifies the functional integrity of the chip by applying specific electrical signals. However, this technology cannot capture non-functional appearance defects, such as invisible scratches on the silicon wafer surface or resin contamination during the packaging process. Although these defects do not affect the initial electrical parameters, they can trigger chain reactions such as metal migration or thermal failure during long-term use.

[0003] While machine vision inspection technology, which has emerged in recent years, has partially solved the above problems, it still has significant limitations in practical applications. Conventional image processing solutions often use linear filtering (such as mean filtering) for noise reduction, which blurs the edge features of the chip, especially reducing its sensitivity to fracture defects in the pin array. At the feature extraction level, solutions relying solely on edge detection algorithms (such as the Sobel operator) struggle to identify texture defects (such as chemical stains on the wafer surface), while methods using only texture analysis are susceptible to artifacts caused by uneven lighting. More importantly, traditional classification models (such as decision trees or K-nearest neighbors) lack generalization ability when facing high-dimensional feature spaces. When the production line switches chip models or new defects appear, the false detection rate often rises to over 8%. Industry reports (SEMI Standard 2023) show that existing automated inspection systems have an accuracy of less than 65% in identifying sub-pixel level cracks, and the system requires hundreds of labeled samples for retraining, severely restricting the flexible production needs of production lines. The main reasons for these problems are that mainstream industrial cameras tend to produce a halo effect when capturing highly reflective metal surfaces, and the uneven illumination of conventional LED light sources creates localized shadows that can obscure micron-sized pores. Furthermore, image blurring caused by mechanical vibration of the stage is particularly pronounced at magnifications exceeding 100X. These factors collectively make it difficult for existing inspection systems to balance speed and accuracy in mass production environments, becoming a key obstacle to improving chip yield. Summary of the Invention

[0004] To address the aforementioned technical problems, the present invention provides a chip batch inspection system, comprising:

[0005] An image acquisition and processing module is used to acquire chip array images, extract channel features from the chip array images, and obtain a chip mask;

[0006] The image recognition module uses a sliding window of a preset size to traverse the chip mask and obtain a local image block of the chip mask.

[0007] The image deep processing module uses a preset first convolutional neural network to predict the defect probability of local image blocks of the chip mask, obtains a defect heat map of the chip array image, performs threshold segmentation processing on the defect heat map, and selects the area that meets the preset defect standard as the chip area to be inspected.

[0008] The judgment module locates and segments the chip area to be inspected to obtain chip-level detection results.

[0009] The evaluation module quantifies and evaluates the chip-level test results to obtain a batch-level chip quality score Qb, and determines the pass / fail status of the batch of chips based on the batch-level chip quality score.

[0010] Preferably, the image acquisition and processing module includes:

[0011] Adaptive thresholding is performed on the RGB channels and L and A channels in the LAB color space of the chip array image to obtain the RGB channel segmentation result M. RGB And LAB channel segmentation result M LAB ;

[0012] A morphological opening operation is performed on the RGB channel segmentation results to obtain the first processing result M. open ;

[0013] Perform a logical OR operation between the first processing result and the LAB channel segmentation result to obtain the chip mask M. mask :

[0014] M mask =M open ∪M LAB .

[0015] Preferably, the determination module includes:

[0016] The coordinates of the chip region under test are corrected to obtain a standardized image block I. norm ;

[0017] A preset second convolutional neural network is used to classify the defect types of the standardized image blocks, and the classification result C={c1,c2,c3,c4} is obtained, where c1 represents pin defects, c2 represents pad defects, c3 represents substrate scratches, and c4 represents surface contamination.

[0018] The standardized image block is segmented at the pixel level using a preset U-Net network to obtain the segmentation result S={s1,s2,s3}, where s1 represents the normal region, s2 represents the repairable defect, and s3 represents the unrepairable defect.

[0019] A chip-level detection report R is generated based on the classification results and the segmentation results.

[0020] Preferably, the preset U-Net network is obtained by training an improved ResNet-34 backbone network. The training process is as follows: a feature extraction network based on an attention mechanism is trained using the Dice loss function, and the feature extraction network is combined with a multi-scale feature fusion module to generate a spatial attention map A. spatial ;

[0021] The spatial attention map is used as a segmentation guidance signal to train the U-Net network through transfer learning, resulting in a preset U-Net network. The Dice loss function is defined as follows:

[0022] ;

[0023] in, To predict probabilities, For real labels, This represents the total number of pixels.

[0024] Preferably, generating a chip-level inspection report based on the classification result and the segmentation result includes: merging adjacent pixel regions marked as s2 in the segmentation result into a composite defect region s based on the identified repairable defect type c4. compound The recommended repair process parameter P should be noted in the inspection report. repair The chip-level test report R={C,S,s} is obtained. compound ,P repair}

[0025] Preferably, the evaluation module includes: constructing a defect distribution map D based on the chip-level detection results. defect The chips in the defect distribution map are weighted and scored:

[0026] ;

[0027] in, This refers to the total number of chips in the batch. The first The severity of pin defects, pad defects, and substrate scratches on each chip is scored. .

[0028] Preferably, determining the pass / fail status of the batch of chips based on the batch-level chip quality score includes:

[0029] Q of all chips in the batch batch The scores are fitted with a normal distribution to obtain the score distribution curve. ;

[0030] According to the preset quantiles The scoring distribution curve is divided into a passing interval [0, Q] using a dynamic threshold method. th and non-compliant range (Q) th

[100] , where the threshold Q th The calculation formula is: In the formula, These are the mean and standard deviation of the rating distribution, respectively. The quantiles of the standard normal distribution; if the proportion of non-compliant intervals p exceeds the preset threshold p. th If so, the batch is determined to be a substandard batch;

[0031] The preset threshold p th It is trained using historical data. The training process is as follows: collect M batches of historical detection data. Build a training dataset;

[0032] The kernel density estimation method was used to fit the score distribution curves for each batch:

[0033] ;

[0034] Where K is the Gaussian kernel function and h is the bandwidth parameter;

[0035] The optimal boundary point Q was determined using a grid search method. opt Starting with an initial threshold ρ0 = 0.15, iterative optimization is performed with a step size of Δρ = 0.01. The batch misclassification rate E(ρ) after each iteration is calculated:

[0036] ;

[0037] In the formula, FP represents the number of false positive batches and FN represents the number of false negative batches;

[0038] When the false positive rate reaches a local minimum, the corresponding threshold ρ is output. th ;

[0039] Backtesting is performed on the validation set using the target preset threshold. When the accuracy Ace ≥ 95%, this threshold is confirmed as the final preset threshold.

[0040] ;

[0041] In the formula, TP represents the number of true positive batches, and TN represents the number of true negative batches.

[0042] A method for batch chip inspection, applied to the batch chip inspection system described above, is characterized by comprising the following steps:

[0043] S01. Acquire a chip array image, extract channel features from the chip array image, and obtain a chip mask;

[0044] S02. After traversing the chip mask using a sliding window of a preset size, a local image block of the chip mask is obtained. A preset first convolutional neural network is used to predict the defect probability of the local image block of the chip mask to obtain a defect heat map of the chip array image. After threshold segmentation processing of the defect heat map, the area that meets the preset defect standard is selected as the chip area to be inspected.

[0045] S03. The chip area to be inspected is located and segmented to obtain chip-level inspection results;

[0046] S04. Quantitatively evaluate the chip-level test results to obtain a batch-level chip quality score, and determine the qualification status of the batch of chips based on the batch-level chip quality score.

[0047] The present invention has at least the following beneficial effects:

[0048] 1. A five-dimensional feature fusion model was constructed by adaptive threshold segmentation of the RGB channels and the L / A channels of the LAB color space. This technique overcomes the limitations of traditional single-channel detection, achieving a detection accuracy of 0.05mm. 2 It maintains a high detection rate even in scenarios with minute defects;

[0049] 2. By adopting a defect type weighted scoring mechanism, the different impacts of pin defects, pad defects, and substrate scratches on chip reliability are quantified, thereby controlling the batch quality assessment error rate to an extremely low range.

[0050] 3. An improved U-Net network trained with the Dice loss function achieves an IoU of 92.4% in chip surface defect segmentation. Furthermore, the network innovatively integrates residual features from the ResNet-34 backbone network with a spatial attention module, minimizing boundary localization errors for complex defects. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a module diagram provided in Embodiment 1 of the present invention;

[0053] Figure 2 A flowchart provided for Embodiment 1 of the present invention;

[0054] Figure 3 This is a diagram of the SOA substrate provided in Embodiment 1 of the present invention;

[0055] Figure 4 This is a GC substrate diagram provided in Embodiment 1 of the present invention. Detailed Implementation

[0056] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0057] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0058] Example 1

[0059] This embodiment provides a chip batch inspection system, which mainly inspects the chip types, specifically the dimensions of SOA substrates and GC substrates.

[0060] SOA substrate size ( Figure 3 ): 1700um×1770um×540um; SOA chip size: 2000um×320um×100um;

[0061] GC substrate size ( Figure 4 ): 1330um×920um×540um; GC chip size: 1000um×320um×100um;

[0062] The present invention provides a detection method for detecting the above two types of substrates, comprising:

[0063] The image acquisition and processing module is used to acquire images of the chip array, extract channel features from the chip array images, and obtain a chip mask.

[0064] Specifically, the steps to obtain the chip mask include: performing adaptive thresholding on the RGB channels of the chip array image and the L and A channels in the LAB color space, respectively, to obtain the RGB channel segmentation result M. RGB And LAB channel segmentation result M LAB ;

[0065] Morphological opening is performed on the RGB channel segmentation results to obtain the first processing result M. open ;

[0066] Perform a logical OR operation between the first processing result and the LAB channel segmentation result to obtain the chip mask M. mask :

[0067] M mask =M open ∪M LAB .

[0068] The above-mentioned raw images of the chip array were acquired using an industrial camera, with a focus on extracting features from the three channels of the RGB color space and the L (luminance) and A (red-green hue) channels of the LAB color space. Adaptive threshold segmentation technology was used to process each of the five channels separately, generating preliminary chip region segmentation results, providing a basis for accurate chip mask positioning in subsequent processing.

[0069] Furthermore, a dual-color space collaborative analysis strategy is employed to address the issue of metallic reflective interference. First, features are simultaneously extracted from the chip array image using the RGB three-channel and L (luminance) and A (red-green hue) channels of the LAB color space, forming a five-dimensional feature matrix. The RGB channels are initially used for adaptive threshold segmentation to locate the chip outline; however, uneven illumination easily leads to hole noise. Therefore, morphological opening operations (3×3 circular structural elements are first eroded and then expanded) are used to smooth the edges and fill minor fractures, outputting an optimized M-shaped structure. open The L channel in the LAB color space enhances the contrast between light and dark areas, while the A channel effectively suppresses color shift caused by metallic reflections. The two are then thresholded to generate the M channel. mask Finally, the dual feature sources (M) are fused through a logical OR operation. mask =M open ∪MLAB This maximizes the detection rate of micron-sized cracks.

[0070] The image recognition module uses a sliding window of a preset size to traverse the chip mask and obtain a local image block of the chip mask.

[0071] The above method involves using a sliding window of a preset size to perform a traversal scan on the chip mask, dividing the entire image into local image blocks. This block-segmentation strategy can focus on microscopic defect areas while reducing the amount of data processed per cycle and improving detection efficiency.

[0072] The image deep processing module uses a preset first convolutional neural network to predict the defect probability of local image blocks of the chip mask, obtains a defect heatmap of the chip array image, performs threshold segmentation on the defect heatmap, and selects the area that meets the preset defect standard as the chip area to be inspected;

[0073] The image distortion effect is eliminated by standardizing the coordinates of the region to be inspected. Then, two tasks are executed in parallel:

[0074] A second CNN was used to classify defect types (pin defects / pad defects / substrate scratches / surface contamination).

[0075] Achieving pixel-level defect segmentation (normal / repairable / unrepairable regions) using an improved U-Net network.

[0076] The final chip-level inspection report includes the defect type, location, and repair recommendations.

[0077] Furthermore, the aforementioned pre-trained first convolutional neural network (CNN) analyzes each local image patch, outputs a defect probability value, and generates a full-image defect heatmap. A dynamic threshold segmentation algorithm is used to filter out regions exceeding a preset defect probability threshold, which are then marked as "chip regions to be inspected." Figure 3 and Figure 4 "Zoom in on the area" to achieve precise location of suspicious areas.

[0078] The judgment module locates and segments the area of ​​the chip to be inspected, and obtains chip-level detection results.

[0079] The detailed steps include:

[0080] Coordinate correction is performed on the chip region to be inspected to obtain a standardized image block I. norm ;

[0081] A pre-defined second convolutional neural network is used to classify the defect types of standardized image blocks, and the classification result C={c1,c2,c3,c4} is obtained, where c1 represents pin defects, c2 represents pad defects, c3 represents substrate scratches, and c4 represents surface contamination.

[0082] The standardized image blocks are segmented at the pixel level using a pre-defined U-Net network to obtain the segmentation result S={s1,s2,s3}, where s1 represents the normal region, s2 represents the repairable defect, and s3 represents the unrepairable defect.

[0083] A chip-level detection report R is generated based on the classification and segmentation results.

[0084] The preset U-Net network in the above embodiments is obtained by training an improved ResNet-34 backbone network. The training process is as follows: a feature extraction network based on an attention mechanism is trained using the Dice loss function, and the feature extraction network is combined with a multi-scale feature fusion module to generate a spatial attention map A. spatial ;

[0085] Using the spatial attention map as a segmentation guidance signal, the U-Net network is trained through transfer learning to obtain a pre-defined U-Net network, where the Dice loss function is defined as:

[0086] ;

[0087] in, To predict probabilities, For real labels, This represents the total number of pixels.

[0088] Furthermore, a chip-level inspection report is generated based on the classification and segmentation results, including: merging adjacent pixel regions marked as s2 in the segmentation results into a composite defect region s based on the identified repairable defect type c4. compound The recommended repair process parameter P should be noted in the inspection report. repair The chip-level test report R={C,S,s} is obtained. compound ,P repair}

[0089] A dual-path neural network parallel architecture is adopted: on the one hand, a second CNN (ResNet-50 backbone) is used to classify four types of defects in normalized image patches. Among them, pin breakage (c1) and pad oxidation (c2) are pre-trained models using transfer learning, while substrate scratches (c3) and surface contamination (c4) are enhanced by introducing an attention mechanism to strengthen feature focusing; on the other hand, pixel-level segmentation is achieved based on an improved U-Net. Its encoder uses ResNet-34 to extract multi-scale features, and the spatial attention map A is fused in the decoding stage. spatial Precise boundary positioning is achieved. The key innovation lies in the dynamic processing of repairable defects: when surface contamination (c4) is detected, the system automatically merges adjacent s2 (repairable) pixel regions to form a composite defect domain s. compoundAnd generate repair parameters P by associating with the process database. repair (e.g., contaminated area > 0.1 mm) 2 (Time-triggered laser cleaning power 70W / duration 15ms). This mechanism maximizes the accuracy of identifying repairable defects in SOA substrates.

[0090] Furthermore, the improved U-Net achieves this through a three-stage training process: the first stage uses the Dice loss function to train the feature extraction network, which optimizes the prediction probability. With real labels The intersection-union ratio significantly improves the sensitivity of small object segmentation; in the second stage, a multi-scale feature pyramid is constructed, and the outputs of the conv3x to conv5x layers of ResNet-34 are combined with the spatial attention module (CBAM) to generate a weight heatmap A. spatial Strengthen defect boundary response; the third stage freezes the backbone network weights, with A spatial The prior knowledge was used to guide the U-Net decoder in transfer learning. After training with 2000 labeled samples, the model achieved an IoU of 92.4% in the 20μm crack segmentation task, with the boundary localization error controlled within ±3 pixels.

[0091] The evaluation module quantifies the chip-level test results to obtain a batch-level chip quality score Qb, and determines the pass / fail status of the batch of chips based on the batch-level chip quality score.

[0092] This involves constructing a batch defect distribution map based on the inspection results of all chips, and then calculating a quality score for each chip based on a weighted average of defect types (pin defects 0.5, pad defects 0.3, substrate scratches 0.2). The batch score Qb is aggregated and combined with a dynamic threshold method to determine the batch's pass / fail status.

[0093] In detail, a defect distribution map D is constructed based on the chip-level inspection results. defect Weighted scoring is applied to the chips in the defect distribution map:

[0094] ;

[0095] in, This refers to the total number of chips in the batch. The first The severity of pin defects, pad defects, and substrate scratches on each chip is scored. .

[0096] Furthermore, determining the pass / fail status of a batch of chips based on batch-level chip quality scores includes:

[0097] Q of all chips in the batch batch The scores are fitted with a normal distribution to obtain the score distribution curve. ;

[0098] According to the preset quantiles The scoring distribution curve is divided into the qualified interval [0, Q] using the dynamic threshold method. th and non-compliant range (Q) th

[100] , where the threshold Q th The calculation formula is: In the formula, These are the mean and standard deviation of the rating distribution, respectively. The quantiles of the standard normal distribution; if the proportion of non-compliant intervals p exceeds the preset threshold p. th If so, the batch is determined to be a substandard batch;

[0099] Preset threshold p th It is trained using historical data. The training process is as follows: collect M batches of historical detection data. Build a training dataset;

[0100] The kernel density estimation method was used to fit the score distribution curves for each batch:

[0101] ;

[0102] Where K is the Gaussian kernel function and h is the bandwidth parameter;

[0103] The optimal boundary point Q was determined using a grid search method. opt Starting from the initial threshold ρ0=0.15, Iterative optimization is performed on the step size, and the batch misclassification rate E(ρ) is calculated after each iteration:

[0104] ;

[0105] In the formula, FP represents the number of false positive batches and FN represents the number of false negative batches;

[0106] When the false positive rate reaches a local minimum, the corresponding threshold ρ is output. th ;

[0107] Backtesting was performed on the validation set using the target preset threshold. When the accuracy Ace ≥ 95%, this threshold was confirmed as the final preset threshold.

[0108] ;

[0109] In the formula, TP represents the number of true positive batches, and TN represents the number of true negative batches.

[0110] For single-chip scoring, the weighting coefficients are determined based on failure analysis experiments to identify faults (e.g., pin defects have a 62% probability of causing failure). After batch scoring, a dynamic threshold is used for determination: first, a normal distribution N of the scores is fitted, and Q is calculated. th Furthermore, a probabilistic model of historical data is constructed through kernel density estimation. Optimize the misjudgment function using grid search The threshold ρ is locked when the validation set accuracy Ace ≥ 95%. th To reduce the false positive rate.

[0111] This embodiment constructs a five-dimensional feature fusion model through adaptive threshold segmentation of the RGB channels and the L / A channels of the LAB color space. This technology overcomes the limitations of traditional single-channel detection, achieving a detection accuracy of 0.05mm. 2 It maintains a high detection rate even in scenarios with minute defects; secondly, by employing a defect type-weighted scoring mechanism to quantify the different impacts of pin defects, pad defects, and substrate scratches on chip reliability, it achieves batch quality assessment error rate control within an extremely low range; furthermore, by introducing an improved U-Net network trained with the Dice loss function, it achieves an IoU value of 92.4% in chip surface defect segmentation tasks. Moreover, by innovatively integrating the residual features of the ResNet-34 backbone network with a spatial attention module, it minimizes the boundary localization error of complex defects.

[0112] Example 2

[0113] This invention provides a non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, which is loaded and executed by a processor to implement the steps ( Figure 2 ):

[0114] Acquire chip array images, extract channel features from the chip array images to obtain chip masks;

[0115] After traversing the chip mask using a sliding window of a preset size, a local image block of the chip mask is obtained. A preset first convolutional neural network is used to predict the defect probability of the local image block of the chip mask, and a defect heat map of the chip array image is obtained. After threshold segmentation processing of the defect heat map, the area that meets the preset defect standard is selected as the chip area to be inspected.

[0116] The chip area to be inspected is located and segmented to obtain chip-level inspection results;

[0117] The chip-level test results are quantitatively evaluated to obtain a batch-level chip quality score, and the pass / fail status of the batch of chips is determined based on the batch-level chip quality score.

[0118] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0119] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0120] Example 3

[0121] This invention provides an electronic device, including a processor and a memory, wherein the memory stores at least one instruction or at least one program segment, and the at least one instruction or the at least one program segment is loaded and executed by the processor to implement the steps ( Figure 2 ):

[0122] Acquire chip array images, extract channel features from the chip array images to obtain chip masks;

[0123] After traversing the chip mask using a sliding window of a preset size, a local image block of the chip mask is obtained. A preset first convolutional neural network is used to predict the defect probability of the local image block of the chip mask, and a defect heat map of the chip array image is obtained. After threshold segmentation processing of the defect heat map, the area that meets the preset defect standard is selected as the chip area to be inspected.

[0124] The chip area to be inspected is located and segmented to obtain chip-level inspection results;

[0125] The chip-level test results are quantitatively evaluated to obtain a batch-level chip quality score, and the pass / fail status of the batch of chips is determined based on the batch-level chip quality score.

[0126] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A chip batch inspection system, characterized in that, include: An image acquisition and processing module is used to acquire chip array images, extract channel features from the chip array images, and obtain a chip mask; The image recognition module uses a sliding window of a preset size to traverse the chip mask and obtain a local image block of the chip mask. The image deep processing module uses a preset first convolutional neural network to predict the defect probability of local image blocks of the chip mask, obtains a defect heat map of the chip array image, performs threshold segmentation processing on the defect heat map, and selects the area that meets the preset defect standard as the chip area to be inspected. The judgment module locates and segments the chip area to be inspected to obtain chip-level detection results. The evaluation module quantifies and evaluates the chip-level test results to obtain a batch-level chip quality score Qb, and determines the pass / fail status of the batch of chips based on the batch-level chip quality score. The determination of the pass / fail status of a batch of chips based on the batch-level chip quality score includes: Q of all chips in the batch batch The scores are fitted with a normal distribution to obtain the score distribution curve. ; According to the preset quantiles The scoring distribution curve is divided into a passing interval [0, Q] using a dynamic threshold method. th and non-compliant range (Q) th [100], where the threshold Q th The calculation formula is: In the formula, These are the mean and standard deviation of the rating distribution, respectively. The quantiles of the standard normal distribution; if the proportion of non-compliant intervals p exceeds the preset threshold p. th If so, the batch is determined to be a substandard batch; The preset threshold p th It is trained using historical data. The training process is as follows: collect M batches of historical detection data. Build a training dataset; The kernel density estimation method was used to fit the score distribution curves for each batch: ； Where K is the Gaussian kernel function and h is the bandwidth parameter; The optimal boundary point Q was determined using a grid search method. opt Starting with an initial threshold ρ0 = 0.15, iterative optimization is performed with a step size of Δρ = 0.

01. The batch misclassification rate E(ρ) after each iteration is calculated: ； In the formula, FP represents the number of false positive batches and FN represents the number of false negative batches; When the false positive rate reaches a local minimum, the corresponding threshold ρ is output. th ; Backtesting was performed on the validation set using the target preset threshold. When the accuracy Ace ≥ 95%, this threshold was confirmed as the final preset threshold. ； In the formula, TP represents the number of true positive batches, and TN represents the number of true negative batches.

2. The chip batch testing system according to claim 1, characterized in that, The image acquisition and processing module includes: Adaptive thresholding is performed on the RGB channels and L and A channels in the LAB color space of the chip array image to obtain the RGB channel segmentation result M. RGB And LAB channel segmentation result M LAB ; A morphological opening operation is performed on the RGB channel segmentation results to obtain the first processing result M. open ; Perform a logical OR operation between the first processing result and the LAB channel segmentation result to obtain the chip mask M. mask : M mask =M open ∪M LAB 。 3. The chip batch testing system according to claim 1, characterized in that, The judgment module includes: The coordinates of the chip region under test are corrected to obtain a standardized image block I. norm ; A preset second convolutional neural network is used to classify the defect types of the standardized image blocks, and the classification result C={c1,c2,c3,c4} is obtained, where c1 represents pin defects, c2 represents pad defects, c3 represents substrate scratches, and c4 represents surface contamination. The standardized image block is segmented at the pixel level using a preset U-Net network to obtain the segmentation result S={s1,s2,s3}, where s1 represents the normal region, s2 represents the repairable defect, and s3 represents the unrepairable defect. A chip-level detection report R is generated based on the classification results and the segmentation results.

4. The chip batch testing system according to claim 3, characterized in that, The preset U-Net network is obtained by training an improved ResNet-34 backbone network. The training process is as follows: a feature extraction network based on an attention mechanism is trained using the Dice loss function, and the feature extraction network is combined with a multi-scale feature fusion module to generate a spatial attention map A. spatial ; The spatial attention map is used as a segmentation guidance signal to train the U-Net network through transfer learning, resulting in a preset U-Net network. The Dice loss function is defined as follows: ； in, To predict probabilities, For real labels, This represents the total number of pixels.

5. The chip batch testing system according to claim 3, characterized in that, The step of generating a chip-level inspection report based on the classification result and the segmentation result includes: merging adjacent pixel regions marked as s2 in the segmentation result into a composite defect region s based on the identified repairable defect type c4. compound The recommended repair process parameter P should be noted in the inspection report. repair The chip-level test report R={C,S,s} is obtained. compound ,P repair } 6. The chip batch testing system according to claim 1, characterized in that, The evaluation module includes: constructing a defect distribution map D based on the chip-level detection results. defect The chips in the defect distribution map are weighted and scored: ； in, This refers to the total number of chips in the batch. The first The severity of pin defects, pad defects, and substrate scratches on each chip is scored. .

7. A method for batch chip inspection, applied to the batch chip inspection system according to any one of claims 1-6, characterized in that, Includes the following steps: S01. Acquire a chip array image, extract channel features from the chip array image, and obtain a chip mask; S02. After traversing the chip mask using a sliding window of a preset size, a local image block of the chip mask is obtained. A preset first convolutional neural network is used to predict the defect probability of the local image block of the chip mask to obtain a defect heat map of the chip array image. After threshold segmentation processing of the defect heat map, the area that meets the preset defect standard is selected as the chip area to be inspected. S03. The chip area to be inspected is located and segmented to obtain chip-level inspection results; S04. Quantitatively evaluate the chip-level test results to obtain a batch-level chip quality score, and determine the qualification status of the batch of chips based on the batch-level chip quality score.

8. A non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the chip batch testing system as described in any one of claims 1-6.

9. An electronic device, characterized in that, It includes a processor and a memory, wherein the memory stores at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by the processor to implement the chip batch testing system as described in any one of claims 1-6.

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