Display driving circuit system integrated with dynamic latch unit, display device and embedded touch panel device

Abstract

The invention belongs to the technical field of display driving circuits, and discloses a display driving circuit system integrated with a dynamic latch unit, a display device and an embedded touch panel device. The dynamic latch circuit comprises a dynamic latch unit, a double-capacitor array and a setting drive circuit. The dynamic latch unit generates a latch control signal and an input control signal triggered by an asynchronous clock through the control signal generation circuit, high-speed amplification and latch of the signals are achieved through the controllable input circuit and the positive feedback latch circuit, and the output buffer enhances the driving capacity and generates a shift signal. The capacitor array adopts HP / LP and HN / LN polar plate groups which are complementarily configured, and each group of lower polar plate is integrated with a positive feedback reset holding circuit. And the setting driving circuit drives the complementary polar plate in a time-sharing manner through PB / PX and NB / NX differential signal pairs. Through precise time sequence matching, voltage autonomous maintenance and a split type driving structure, the signal integrity in a high-refresh-rate scene is remarkably improved, the system power consumption is reduced, and the circuit is suitable for embedded touch display integrated equipment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display driving circuit, in particular to a display driving circuit system integrated with a dynamic latch unit, a display device and an embedded touch panel device. BACKGROUND

[0002] In the field of display driving circuit, especially in the application of high-resolution dynamic display device and embedded touch display integrated system, the core challenge of the driving circuit is to realize high-speed and low-noise signal transmission and latching between the front-end signal processing module and the back-end capacitor array. With the continuous improvement of display refresh rate, the driving circuit needs to complete the fast latching, amplification and stable output of differential signal in a very short pixel refresh period, and at the same time needs to maintain the absolute stability of the lower plate voltage of the capacitor array in the touch detection stage.

[0003] The traditional dynamic latch circuit faces many technical bottlenecks in high-speed latching and driving ability: the timing accuracy and latching speed are insufficient, the existing latch unit mostly adopts static logic or simple dynamic logic structure, the synchronization of the latching control signal and the input signal is easily affected by parasitic capacitance and signal path delay; the reset noise and voltage holding capacity are insufficient, the traditional reset circuit relies on the reset signal to directly control the on / off of the switch tube, and when the reset signal fails, the lower plate voltage of the capacitor is easily affected by external noise or switch tube leakage current and drifts; the driving signal load and power consumption are contradictory, in the traditional driving circuit, the latch output needs to directly drive the switch tube of multiple groups of capacitor lower plate, which leads to a significant increase in the load capacitance of the latch output terminal.

[0004] In view of the above problems, the prior art tries to improve the performance by optimizing the latch structure or adding redundant reset switches, but there are still technical limitations such as signal path delay accumulation caused by separate design of the latch circuit and the driving circuit, state maintenance by the reset circuit relying on continuous reset signal, and driving signal load not effectively split.

[0005] In view of the above problems, the prior art needs to be improved. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a display driving circuit system integrated with a dynamic latch unit, a display device and an embedded touch panel device, which has the advantages of high-speed latching, low-noise interference, low power consumption and high integration.

[0007] To achieve the above-mentioned purposes and other related purposes, the present application provides a display driving circuit system integrated with a dynamic latch unit, and the technical scheme is as follows: It comprises a dynamic latch unit, a capacitor array and a set driving circuit. The dynamic latch unit comprises: a control signal generation circuit configured to generate a latch control signal CLK and an input control signal SW based on an asynchronous clock signal and a shift state signal QX; a controllable input circuit configured to control the connection of an input signal to the latch circuit by the SW signal; a positive feedback latch circuit configured to amplify and latch the quantization result of the input signal when the CLK is low; an output buffer configured to enhance the driving capability of the latch result and generate a shift signal QOUT; a capacitor array comprising: a first capacitor array composed of a plurality of capacitor groups, each capacitor group containing two capacitors connected in parallel, the lower plates of which are high and low plates HP and LP respectively, and the upper plates of which are connected to a common node VP; a second capacitor array composed of a plurality of capacitor groups, each capacitor group containing two capacitors connected in parallel, the lower plates of which are high and low plates HN and LN respectively, and the upper plates of which are connected to a common node VN; wherein the lower plate of each capacitor group is configured with a positive feedback reset holding circuit controlled by a reset signal RES, for maintaining the voltage state of the plate after the reset signal RES is disabled; a set drive circuit comprising: a PB / PX control circuit for driving the HP plate of the first capacitor array and the LN plate of the second capacitor array by the differential output signals PB / PX respectively; a NB / NX control circuit for driving the HN plate of the second capacitor array and the LP plate of the first capacitor array by the differential output signals NB / NX respectively; the capacitor array is connected to the set drive circuit through the positive feedback reset holding circuit, for maintaining the voltage state of the plate under the control of the reset signal RES, and driving the plate to charge and discharge through the differential output signals in the set phase.

[0008] Optionally, the control signal generation circuit comprises a PMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3, a PMOS transistor M5 and a PMOS transistor M6, wherein: the gate of M1 is connected to the shift state signal QX, the source is connected to the power supply VDD, and the drain outputs the latch control signal CLK; the gate of M2 is connected to the gate of M1, the drain is connected to the drain of M1, and the source is connected to the drain of M3; the gate of M3 is connected to the asynchronous clock signal CLKC, and the source is connected to the ground; the gate of M5 is connected to the latch state node X, the source is connected to the power supply VDD, and the drain is connected to the input control signal SW; M6 is connected to the input control signal SW at the gate, to the power supply VDD at the source, and to the output buffer at the drain; The CLK signal is generated by the delay logic of M1-M3, and the input control signal SW is generated by M5-M6 and then fed back to the controllable input circuit through an inverter after being delayed.

[0009] Optionally, the controllable input circuit comprises PMOS M5, PMOS M6 and NMOS M9, wherein: M9 is connected to the latch state node X at the gate, to the drain of M5 through the input control signal SW at the drain, and to the ground at the source; When the input control signal SW is low, M6 is turned on and charges the source of M11 to the power supply VDD, and M9 is turned off to isolate the input signal; when the input control signal SW is high, M6 is turned off, and M9 is turned on to pass the input signal to the positive feedback latch circuit.

[0010] Optionally, the positive feedback latch circuit comprises PMOS M4, PMOS M7, NMOS M8 and NMOS M9, wherein: M4 is connected to the latch control signal CLK at the gate, to the power supply VDD at the source, and to the source of M7 at the drain, as a tail current source of the positive feedback latch circuit; M7 is connected to the asynchronous clock signal CLKC at the gate, to the drain of M4 at the source, and to the latch state node X at the drain; M8 is connected to the latch control signal CLK at the gate, to the ground at the source, and to the drain of M7 and the drain of M9 through the latch state node X; The positive feedback latch circuit is configured to trigger a latch operation at the falling edge of CLK, and the CLK signal is inversely related to the asynchronous clock CLKC Optionally, the output buffer comprises NMOS M10, PMOS M11 and NMOS M12, wherein: M10 is connected to the input control signal SW at the gate, to the drain of the shift signal QOUT at the drain, and to the ground at the source; M11 is connected to the latch result signal QRES at the gate, to the drain of M6 at the source, and to the shift signal QOUT at the drain; M12 is connected to the latch result signal QRES at the gate, to the shift signal QOUT at the drain, and to the ground at the source; After the shift signal QOUT passes through the level conversion circuit, two pairs of differential output signals PB / PX and NB / NX are generated.

[0011] Optionally, the PB / PX control circuit comprises PMOS M13, PMOS M14, NMOS M15, NMOS M16 and NMOS M17: M13 is connected to the differential output PB at the gate, to VP at the source, and to the LN plate at the drain; M14, gate connected to LN plate, source connected to VP, drain connected to HP plate; M15, gate connected to reset signal RES, source connected to VN, drain connected to LN plate; M16, gate connected to HP, source connected to VN, drain connected to LN plate; M17, gate connected to differential output PX, source connected to VN, drain connected to drain of M14 and gate of M16 through HP plate.

[0012] Optionally, the NB / NX control circuit includes PMOS M18, PMOS M19, NMOS M20, NMOS M21 and NMOS M22, wherein: M18, gate connected to LP plate, source connected to VP, drain connected to HN plate; M19, gate connected to differential output NB, source connected to VP, drain connected to LP plate; M20, gate connected to differential output NX, source connected to VN, drain connected to HN plate; M21, gate connected to HN plate, source connected to VN, drain connected to LP plate; M22, gate connected to RES signal, source connected to VN, drain connected to gate of M18, drain of M19 and drain of M21 through LP plate; When NB / NX is high, M19 / M20 is turned on and charges HN / LP plate, and M21 self-maintains LP reset state through HN voltage.

[0013] The application also proposes a display device, comprising: the display driving circuit system described above; A capacitor array, whose lower plate HP / LN is driven by PB / PX signal, and HN / LP is driven by NB / NX signal; A display panel, receiving the output of the capacitor array to drive pixel units.

[0014] The application also proposes an in-cell touch panel device, comprising: The display driving circuit system described above; A touch detection module, including a differential amplifier, for detecting voltage changes of HP-LN plate of the first capacitor array and HN-LP plate of the second capacitor array, and identifying touch signals by comparing voltage differences.

[0015] From the above, the application provides a display driving circuit system integrated with a dynamic latch unit, a display device, and an embedded touch panel device. Through the cooperative design of the dynamic latch unit, the capacitor array, and the set driving circuit, the positive feedback reset holding circuit is used to maintain the plate voltage after the reset signal is disabled, and the differential signal is used to drive the plate to charge and discharge, thereby improving the latch speed and accuracy, reducing the reset noise, enhancing the voltage holding capacity, and optimizing the driving load distribution, which has significant performance advantages. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A logic block diagram of a display driving circuit system integrated with a dynamic latch unit of the application is shown. Figure 2 A circuit schematic diagram of a dynamic latch unit of the application is shown. Figure 3 A timing waveform diagram of the dynamic latch unit of the application is shown. Figure 4 A structural schematic diagram of a first capacitor array of the application is shown. Figure 5 A structural schematic diagram of a second capacitor array of the application is shown. Figure 6 A circuit schematic diagram of a PB / PX control circuit of the application is shown. Figure 7 A circuit schematic diagram of a NB / NX control circuit of the application is shown. Figure 8 A waveform diagram of the working process of a positive feedback reset holding circuit of the application is shown. Figure 9 A timing waveform diagram of the differential signal of a set driving circuit of the application is shown. DETAILED DESCRIPTION

[0017] The embodiments of the application are described below through specific and concrete examples, and those skilled in the art can easily understand other advantages and effects of the application from the disclosure. The application can also be implemented or applied through other different specific embodiments, and each detail in the specification can be modified or changed based on different views and applications without departing from the spirit of the application.

[0018] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The shapes, number and proportions of the components in actual implementation can be arbitrarily changed, and the component layout pattern can be more complex. The structures, proportions, sizes and the like shown in the diagrams attached to the present specification are only used to cooperate with the content disclosed in the specification, so as to be understood and read by those skilled in the art, and do not define the limiting conditions for implementing the present application, and therefore do not have technical substantive significance. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" in the present specification are only for the convenience of clear description, and are not used to limit the scope of implementation of the present application. The change or adjustment of the relative relationship, without substantially changing the technical content, is also considered as the scope of implementation of the present application.

[0019] In the prior art, high-resolution dynamic display devices and embedded touch display integrated systems have higher requirements for the high-speed signal processing and stable voltage maintaining capability of the driving circuit. The traditional dynamic latch circuit is easily affected by the parasitic capacitance when latching at high speed, resulting in timing deviation. The voltage of the capacitor plate in the reset stage drifts due to the leakage current or feedthrough effect. Meanwhile, the latching output directly drives multiple sets of capacitor lower plate switch tubes, resulting in increased load and rising power consumption. These problems will cause display signal latching delay, touch detection baseline noise and system energy efficiency decline in high refresh rate scenarios.

[0020] In order to solve the above problems, a display driving scheme is needed, which can quickly complete signal amplification and holding in the latching stage, maintain the stability of the capacitor plate voltage in the reset stage, and optimize the driving load distribution. By integrating the dynamic latch unit with the capacitor array and the set driving circuit, a separate positive feedback reset holding circuit is designed to eliminate the voltage drift after reset, and a split driving structure is adopted to split the complementary signal load, which can systematically solve the contradiction between timing synchronization, voltage stability and driving efficiency.

[0021] Therefore, the present application proposes a display driving circuit system integrated with a dynamic latch unit, as shown in Figure 1 The dynamic latch unit includes a control signal generation circuit, a controllable input circuit, a positive feedback latch circuit and an output buffer. The capacitor array is composed of a first capacitor array and a second capacitor array, and the lower plate of each capacitor group is configured with a positive feedback reset holding circuit. The set driving circuit drives different capacitor plates through differential output signals, and cooperates with the positive feedback reset holding circuit.

[0022] The dynamic latch unit is a circuit module that generates a latch control signal and an input control signal through an asynchronous clock signal and a shift state signal, and uses a positive feedback structure to latch the signal, which functions to shorten the signal amplification time and enhance the latch stability. The capacitor array is a charge storage structure composed of multiple parallel capacitors, and the first capacitor array and the second capacitor array use complementary configurations of high and low plate electrodes, which functions to provide the required amount of charge for differential signal driving. The positive feedback reset holding circuit is a voltage maintenance circuit controlled by a reset signal, which functions to offset the influence of leakage current through a positive feedback mechanism after the reset signal is disabled, and maintain the plate voltage state. The set driving circuit is a charge control module that drives different plate electrodes through differential signals, which functions to split the complementary signal load to reduce the driving pressure of the latch output terminal.

[0023] Specifically, the control signal generation circuit generates a latch control signal and an input control signal based on an asynchronous clock signal and a shift state signal, and controls the connection state of the input signal and the latch circuit. The positive feedback latch circuit amplifies the input signal and latches the result when the latch control signal is low, and the output buffer enhances the driving capability of the latch result and generates a shift signal. The lower plate of each capacitor group in the capacitor array maintains the voltage state through the positive feedback reset holding circuit, and the set driving circuit drives the plate to charge and discharge through the differential output signal in the set phase. The high plate of the first capacitor array and the low plate of the second capacitor array are driven by the PB / PX control circuit, and the high plate of the second capacitor array and the low plate of the first capacitor array are driven by the NB / NX control circuit, and the two groups of driving circuits work independently to reduce the load of the latch output.

[0024] Compared with the prior art, the separation of the latch circuit and the driving circuit in the traditional scheme leads to the accumulation of signal path delay, while the integrated design of the dynamic latch unit and the set driving circuit in the present scheme realizes precise timing matching; the traditional reset circuit relies on a continuous reset signal to maintain the plate voltage, while the present scheme uses the positive feedback reset holding circuit to maintain the voltage autonomously after the reset signal is disabled; in the traditional driving circuit, the latch output needs to drive the complementary signal pair at the same time, while in the present scheme, the PB / PX and NB / NX driving paths are split to reduce the load of a single path.

[0025] Through the above technical scheme, the speed and stability of the latch operation can be improved, the touch detection error caused by the voltage drift of the capacitor plate during the reset phase can be avoided, and the load distribution of the latch output terminal can be optimized through the split driving structure, thereby adapting to the needs of high refresh rate display and embedded touch integrated system.

[0026] As Figure 2As shown, the application further proposes a display driving circuit system integrated with a dynamic latch unit, the control signal generation circuit includes PMOS tube M1, NMOS tube M2, NMOS tube M3, PMOS tube M5 and PMOS tube M6, wherein: M1 gate connects the shift state signal QX, source connects the power supply VDD, drain outputs the latch control signal CLK; M2 gate and M1 gate share the shift state signal QX, drain and M1 drain share the CLK node, source connects the drain of M3; M3 gate connects the asynchronous clock signal CLKC, source connects the ground; M5 gate connects the latch state node X, source connects the power supply VDD, drain connects the input control signal SW; M6 gate connects the input control signal SW, source connects the power supply VDD, drain connects to the output buffer; the CLK signal is generated through the delay logic of M1-M3, and after the input control signal SW is generated through M5-M6, it is fed back to the controllable input circuit through the inverter.

[0027] Wherein, PMOS tube M1 refers to the transistor for controlling the generation of CLK signal by receiving shift state signal QX through the gate, which can be specifically implemented by P-channel metal oxide semiconductor field effect transistor, and its source is connected with the power supply to make it conductive when QX is low, and to pull CLK to high level. NMOS tube M2 refers to the transistor connected in parallel with M1, which can be specifically implemented by N-channel device, and it is conductive when QX is high and forms a pull-down path with M3 to pull CLK to low level. NMOS tube M3 refers to the ground path switch controlled by asynchronous clock CLKC, which can be specifically implemented by device with threshold voltage lower than logic high level, and it is conductive when CLKC is high to establish the pull-down path of CLK signal. PMOS tubes M5 and M6 refer to the complementary pair of tubes for generating input control signal SW based on latch state node X, which can be specifically implemented by P-type transistors with matched size, and the generation and buffering of SW signal are realized by cross-connection of the gates.

[0028] As Figure 3The dynamic latch unit working timing waveform diagram is shown, and L and H respectively represent logic low level and high level. Specifically, the shift state signal QX is input to the gate of M1 and M2. When QX is at a low level, M1 is turned on to pull CLK high. At this time, M2 is turned off due to the low level of QX, and the CLK signal is directly output to high level through M1. When QX becomes high, M1 is turned off, and M2 and M3 are turned on during the high level of CLKC to pull the CLK node to ground level. The asynchronous clock CLKC controls the falling edge trigger timing of the CLK signal through M3, so that the CLK and CLKC form an inverse correlation. The latch state node X controls the generation of the SW signal through the M5 gate. When X is at a low level, M5 is turned on to pull SW high. At this time, M6 is turned off due to the high level of SW, and the input control signal SW is fed back to the controllable input circuit after being delayed by an inverter. The circuit is connected through the direct path of M1-M3 to reduce the number of signal transmission stages, and the CLK signal generation does not require additional inverters, reducing the path delay.

[0029] Compared with the prior art, the traditional control signal generation circuit usually uses a multi-stage inverter chain to realize CLK signal delay, which increases the level of the signal path and makes it difficult to match the timing. The present scheme directly generates the CLK signal through the parallel structure of M1-M3, and uses the characteristic that M3 is controlled by the asynchronous clock CLKC to make the falling edge of the CLK signal accurately align with the rising edge of CLKC. At the same time, the SW signal is directly generated by the complementary pair of M5-M6, avoiding the additional delay caused by independent logic gates in the traditional scheme, thereby shortening the setup time of the input control signal.

[0030] Through the above technical scheme, the timing mismatch between the latch control signal and the asynchronous clock is effectively solved, and the number of signal transmission paths is reduced, so that the generation delay of the CLK signal and the input control signal SW is significantly reduced. The structure quickly switches the CLK state when the QX signal jumps, ensuring that the positive feedback latch circuit completes signal latching within a sub-microsecond time window, meeting the timing accuracy requirements of high refresh rate display driving. At the same time, the generation and buffering functions of the SW signal are integrated in M5-M6, avoiding the additional parasitic capacitance introduced by the buffer circuit in the traditional scheme, thereby reducing the risk of charge leakage during signal transmission.

[0031] The present application further proposes a controllable input circuit comprising a PMOS tube M5, a PMOS tube M6 and a NMOS tube M9, the gate of M9 is connected to the latch state node X, the drain is fed back to the drain of M5 through the input control signal SW, and the source is connected to the ground.

[0032] The PMOS tube M5 refers to a pull-up switch for generating an input control signal SW, and can be specifically implemented by a PMOS tube with a gate connected to a latch state node X, a source connected to a power supply VDD, and a drain outputting the input control signal SW, and the generation of the input control signal SW is controlled by a voltage change of the latch state node X.

[0033] The PMOS tube M6 refers to a level conversion device for the input control signal SW to an output buffer, and can be specifically implemented by a PMOS tube with a gate connected to the input control signal SW, a source connected to the power supply VDD, and a drain connected to the output buffer, and is used for converting a high level of the input control signal SW into a driving voltage of the output buffer.

[0034] The NMOS tube M9 refers to a pull-down control device for an input signal path, and can be specifically implemented by an NMOS tube with a gate connected to the latch state node X, a drain connected to the M5 drain through the input control signal SW, and a source connected to the ground, and the grounding state of the input signal path is controlled by a voltage change of the latch state node X.

[0035] Specifically, when the latch state node X is at a low level, the PMOS tube M5 is turned on, the input control signal SW is pulled up to the power supply voltage, at this time, the PMOS tube M6 is turned off due to the high level of SW, the NMOS tube M9 is turned off due to the low level of X, and the input signal is connected to the latch circuit through the controllable input circuit; when the latch state node X jumps to a high level, the PMOS tube M5 is turned off, the input control signal SW is rapidly pulled down to the ground potential through the pull-down action of the NMOS tube M9, at this time, the PMOS tube M6 is turned on due to the low level of SW, and the power supply voltage is transmitted to the output buffer, and at the same time, the input signal path is cut off. In this process, the rapid switching of the input control signal SW is realized through the complementary action of M5-M9, and the voltage change of the latch state node X directly controls the turn-on and turn-off of the input signal path.

[0036] Compared with the prior art, the traditional controllable input circuit only uses a single switch tube to control the input path, which is prone to cause input control signal delay due to parasitic capacitance when the latch state is switched, and the lack of a pull-down path causes residual charge of the input signal to be unable to be rapidly discharged. The present scheme actively pulls down the SW signal through M9 when the latch state is switched, and eliminates the charge residue of the input path; the complementary switching action of M5 and M6 further shortens the rise and fall time of the input control signal, and avoids the competition risk of the input signal and the latch circuit in the critical state.

[0037] By the technical solution, the application solves the signal path competition problem caused by the latch state switching delay of the input control signal, the connection state of the input signal and the latch circuit can be quickly switched according to the voltage change of the latch state node X, the falling edge of the input control signal SW is realized by the active pull-down of M9 to achieve sub-nanosecond switching speed, and the conduction of M6 provides stable high-level driving capability for the output buffer, thereby ensuring the output signal integrity of the latch result.

[0038] The application further provides a positive feedback latch circuit including a PMOS tube M4, a PMOS tube M7, an NMOS tube M8 and an NMOS tube M9, the gate of the M4 is connected to a latch control signal CLK, the source is connected to a power supply VDD, and the drain is connected to the source of the M7 as a tail current source of the positive feedback latch circuit; the gate of the M7 is connected to an asynchronous clock signal CLKC, the source is connected to the drain of the M4, and the drain is connected to a latch state node X; the gate of the M8 is connected to the latch control signal CLK, the source is connected to the ground, and the drain is connected to the drain of the M7 and the drain of the M9 through the latch state node X; the positive feedback latch circuit is configured to trigger a latch operation at the falling edge of the CLK, and the CLK signal and the asynchronous clock CLKC are kept in an inverse correlation.

[0039] The tail current source refers to a constant current source circuit composed of the PMOS tube M4, and specifically can be realized by a PMOS tube with the gate voltage controlled by the CLK signal. The structure controls the on-off of the tail current by adjusting the CLK signal level to provide a stable bias current for the latch operation. The latch state node X refers to a common node connected to the drains of the M7, M8 and M9, and specifically can be realized by a metal interconnection line. The node serves as a latch result temporary storage point, and its voltage state is quickly established through a positive feedback mechanism. The inverse correlation of the CLK and CLKC refers to a phase difference of 180 degrees between the two signals, and specifically can be realized by a logic inverter or a complementary clock generation circuit. The design ensures that the latch trigger time is synchronized with the clock signal jump, and avoids timing conflicts.

[0040] Specifically, when the CLK signal jumps from a high level to a low level, the M4 is turned on to form a tail current path, and the CLKC signal is at a high level to turn on the M7. At this time, the potential of the latch state node X is determined by the amount of charge injected by the input signal through the controllable input circuit. When the input signal is at a high level, the M9 is turned on to pull down the node X to a low level, triggering a positive feedback process: the M8 is turned on at the low level of the CLK to accelerate the discharge of the node X, and the M7 is maintained in the conduction state when the CLKC is at a high level. This cross-coupled structure enables the latch state to be quickly established after the falling edge of the CLK, and enhances the stability of the latch result through the parallel conduction path of the M8 and M9. The inverse correlation of the CLK and CLKC further ensures that the CLKC jumps to a low level to cut off the conduction path of the M7 after the latch phase is completed, preventing the latch state from being disturbed by subsequent signals.

[0041] Compared with the prior art, the conventional positive feedback latch circuit usually adopts a single clock signal to control the tail current source and the latch trigger, resulting in that the latch setup time is limited by the delay of the rising edge of the clock signal. In the scheme, the tail current control signal CLK is separated from the latch trigger signal CLKC, and the two are kept in an inverse correlation relationship, so that the tail current source is immediately turned on at the falling edge of CLK, and the high level of CLKC maintains the current path in the latch trigger stage. The timing separation design effectively shortens the latch setup time and avoids the competition risk caused by the edge overlap of the clock signal in the conventional scheme. In addition, the parallel structure of M8 and M9 forms a double discharge path in the latch stage, which can reduce the equivalent resistance of node X compared with the conventional single tube discharge structure, and accelerate the voltage jump speed.

[0042] Through the above technical scheme, the application can realize sub-microsecond fast signal latching after the falling edge of the latch control signal triggers, through the cooperation of the separated tail current control and the latch trigger signal. The cross-coupled structure of M7 and M8 in the positive feedback latch circuit effectively suppresses the latch state drift caused by process deviation or temperature change, and ensures the stability of the quantization result in the high refresh rate scene. At the same time, the inverse correlation design of CLK and CLKC eliminates the problem of narrowing of the latch window caused by phase deviation of the clock signal in the conventional scheme, and provides reliable timing margin for high refresh rate display driving.

[0043] The application further proposes that the output buffer comprises an NMOS tube M10, a PMOS tube M11 and an NMOS tube M12, wherein the gate of M10 is connected to the input control signal SW, the drain is connected to the output shift signal QOUT, and the source is connected to the ground; the gate of M11 is connected to the latch result signal QRES, the source is connected to the drain of M6, and the drain is connected to the shift signal QOUT; the gate of M12 is connected to the latch result signal QRES, the drain is connected to the shift signal QOUT, and the source is connected to the ground; the shift signal QOUT generates two pairs of differential output signals PB / PX and NB / NX after passing through the level conversion circuit.

[0044] The output buffer refers to a driving capability enhancement module constructed by a plurality of transistors, which can be implemented by using the complementary structure of NMOS and PMOS, and the conduction states of M10, M11 and M12 are used to convert the latch result signal into a shift signal with sufficient driving capability. The level conversion circuit refers to an interface module for converting a single-ended signal into a differential signal, which can be implemented by using a cross-coupled transistor network, and is used to convert the QOUT signal into complementary PB / PX and NB / NX signal pairs to adapt to the driving requirements of the capacitor array. The latch result signal QRES refers to the quantization result output by the positive feedback latch circuit, which can be represented by the high and low levels of the node voltage, and is connected to the output buffer through the gates of M11 and M12 to control the conduction state of the complementary transistor to generate a stable output.

[0045] Specifically, the output buffer forms a pull-down path by turning on M10 under the action of the input control signal SW, and M11 and M12 are turned on complementarily based on the QRES signal to drive the QOUT node from the power supply and ground path, respectively. When QRES is high, M11 is turned on to transmit the power supply voltage to QOUT, and M12 is turned off to avoid short circuit to ground; when QRES is low, M12 is turned on to pull down QOUT to ground, and M11 is turned off to save power consumption. After the QOUT signal passes through the level conversion circuit, two pairs of complementary PB / PX and NB / NX signals are generated by adjusting the signal amplitude and phase to drive the high and low plates of the capacitor array. Thus, the output buffer not only improves the driving capability of the latched signal, but also reduces the charging and discharging current of a single path by splitting the load path.

[0046] Compared with the prior art, in the traditional scheme, the latched output needs to directly drive multiple groups of capacitor plate switches, resulting in a multiplication of the load capacitance of the output end, a significant increase in signal transition delay, and high power consumption. In the present scheme, the output buffer and the level conversion circuit are introduced to split the single driving path into a pair of complementary signals, so that each signal only needs to drive the corresponding plate switch, effectively reducing the load capacitance of a single path. In addition, the complementary driving structure can cancel the common-mode noise and avoid signal distortion caused by asymmetric load.

[0047] Through the above technical scheme, the present application can reduce the driving load of the latched output end in a high refresh rate scenario, improve the signal transmission speed, suppress common-mode interference through complementary signal driving, and enhance the voltage stability during the setting phase of the capacitor array. In addition, the complementary transistor structure of the output buffer can dynamically adjust the conduction state according to the latching result, avoiding the generation of invalid current paths, thereby optimizing the overall power consumption.

[0048] As shown in Figures 4-7 The PB / PX control circuit further includes PMOS transistor M13, PMOS transistor M14, NMOS transistor M15, NMOS transistor M16, and NMOS transistor M17: the gate of M13 is connected to the differential output PB, the source receives the differential reference voltage VREFP, and the drain is connected to the LN plate; the gate of M14 is connected to the LN plate, the source receives the differential reference voltage VREFP, and the drain is connected to the HP plate; the gate of M15 is connected to the reset signal RES, the source receives the differential reference voltage VREFN, and the drain is connected to the LN plate; the gate of M16 is connected to the HP plate, the source receives the differential reference voltage VREFN, and the drain is connected to the LN plate; the gate of M17 is connected to the differential output PX, the source receives the differential reference voltage VREFN, and the drain is connected to the gate of M14 through the HP plate.

[0049] Wherein, the differential reference voltage VREFP and VREFN refer to the complementary reference voltage for driving the capacitor array, which can be generated by a voltage dividing resistor network or a reference voltage source, and the differential output signal PB / PX and NB / NX realizes the fast charging and discharging of the capacitor plate through the driving capability. The reset signal RES refers to a logic signal for controlling the working state of the positive feedback reset holding circuit, which can be a pulse signal generated by a shift register, and the capacitor plate voltage is pulled to the preset reference voltage in the reset stage. The positive feedback reset holding circuit refers to the cross-coupled structure composed of PMOS and NMOS tubes, specifically the cross-coupled structure of M14 and M16, and the cross-coupled structure of M18 and M21, that is, the drain of M14 is connected to the gate of M16 through the HP plate, the drain of M16 is connected to the gate of M14 through the LN plate, the drain of M18 is connected to the gate of M21 through the HN plate, and the drain of M21 is connected to the gate of M18 through the LP plate. After the reset signal is disabled, the plate voltage state is maintained through the positive feedback mechanism.

[0050] Specifically, the working of the PB / PX control circuit is divided into a reset stage and a set stage. As shown in the positive feedback reset holding circuit working process waveform diagram, Figure 8 As shown in the positive feedback reset holding circuit working process waveform diagram, in the diagram, ΔV refers to the self-maintaining capability of the plate voltage after reset, ΔV < 5 mV / 10 μs, in the reset stage, the reset signal RES is at an effective level, M15 is turned on, and the LN plate is pulled to VREFN; at the same time, M17 is turned off, and the HP plate is connected to VREFP through the source-drain path of M14. At this time, the voltages of the HP and LN plates are reset to VREFP and VREFN, respectively. When the reset signal is disabled, M15 is turned off, and the LN plate voltage is maintained stable through the positive feedback loop of M16 and M14: if the LN plate voltage rises due to external interference, the conduction degree of M16 increases, and the LN plate is pulled down to VREFN; if the LN plate voltage decreases, the conduction degree of M14 increases, and the HP plate is pulled up to VREFP, and the LN plate voltage is compensated through the capacitive coupling effect. In the set stage, the differential output signal PB / PX drives M13 and M17: when PB is at a high level, M13 is turned on, and the LN plate is pulled to VREFP; when PX is at a low level, M17 is turned on, and the HP plate is pulled to VREFN, realizing the differential driving of the capacitor plate.

[0051] Compared with the prior art, the traditional reset circuit cannot maintain the plate voltage after the RES signal is disabled, resulting in voltage drift in the touch detection stage. The PB / PX control circuit automatically compensates the change of the plate voltage after the RES is disabled through the positive feedback loop of M14-M16, without the need to continuously apply the reset signal. In addition, the traditional driving circuit needs to control the HP and LN plates separately, while the present scheme simultaneously drives the complementary plates through the differential output signal, reducing the number of switch tubes.

[0052] By the technical solution, the application can maintain the stability of the capacitor plate voltage in the touch detection stage, avoid voltage drift caused by reset noise and leakage current. The positive feedback reset holding circuit automatically compensates the plate voltage change after the RES fails, reducing the fluctuation of the touch signal baseline. The differential driving mode controls the HP and LN plates simultaneously through complementary signals, reducing the complexity and power consumption of the driving circuit.

[0053] The application further proposes that the NB / NX control circuit includes PMOS tube M18, PMOS tube M19, NMOS tube M20, NMOS tube M21 and NMOS tube M22, wherein: the gate of M18 is connected to the LP plate, the source receives the differential reference voltage VREFP, and the drain is connected to the HN plate; the gate of M19 is connected to the differential output NB, the source receives the differential reference voltage VREFP, and the drain is connected to the LP plate; the gate of M20 is connected to the differential output NX, the source receives the differential reference voltage VREFN, and the drain is connected to the HN plate; the gate of M21 is connected to the HN plate, the source receives the differential reference voltage VREFN, and the drain is connected to the LP plate; the gate of M22 is connected to the RES signal, the source receives the differential reference voltage VREFN, and the drain is connected to the gate of M18, the drain of M19 and the drain of M21 through the LP plate.

[0054] Among them, the differential reference voltage VREFP and VREFN refer to the positive and negative reference voltages for driving the capacitor plate, which can be realized by a high-precision bandgap reference source. By setting a stable voltage difference, the consistency of the driving signal amplitude is ensured.

[0055] The differential output NB and NX refer to the opposite driving signal pair generated by the latch result, which can be realized by a cross-coupled inverter. The charging and discharging direction of the plate is controlled through the complementary logic relationship.

[0056] The HN plate and the LP plate refer to the complementary plate nodes of the second capacitor array and the first capacitor array, which can be realized by a metal-insulator-metal structure capacitor. The symmetric driving path is formed by cross-connection.

[0057] The RES signal refers to the reset control signal, which can be generated by a global synchronous logic circuit. By activating the NMOS tube M22, the LP plate is forced to pull down to the VREFN level.

[0058] Specifically, as Figure 9The differential signal timing waveform of the set driving circuit is shown. In the set stage, when the RES signal is in the invalid state, the differential output NB and NX control the conduction state of M19 and M20 according to the latch result. When NB is high, M19 is turned on to charge LP plate to high level through VREFP, and M20 is turned off to keep HN plate in the original state; when NX is low, M20 is turned on to discharge HN plate to low level through VREFN. At this time, M18 and M21 form a positive feedback loop: the LP plate voltage controls the charging path of the HN plate through the M18 gate, and the HN plate voltage adjusts the discharge path of the LP plate through the M21 gate, thereby forming a self-sustaining mechanism of the plate voltage. In the reset stage, the RES signal activates M22, forcibly pulls down the LP plate to VREFN, and M21 is turned off due to the change of the HN plate voltage, realizing the fast reset of the capacitor array.

[0059] Compared with the prior art, the traditional NB / NX driving circuit directly drives the plate by using independent switching tubes, which causes the plate voltage to be easily affected by the leakage current after reset. The scheme introduces the positive feedback loop of M18-M21 in the driving path, so that the plate voltage is maintained stable by cross coupling in the set stage without relying on continuous external control signals. In addition, M19 and M20 are driven by differential signals in time-sharing mode, which avoids the risk of power short circuit caused by simultaneous conduction, and reduces the dynamic power consumption compared with the traditional single-ended driving structure.

[0060] Through the above technical scheme, the application solves the problem of plate voltage drift after reset of the traditional driving circuit, and ensures the voltage stability of the capacitor array in the touch detection stage by offsetting the influence of leakage current through the positive feedback loop. At the same time, the time-sharing differential driving strategy reduces the current surge caused by the simultaneous action of switching tubes, reduces the signal crosstalk risk in the high-speed refresh scene, and improves the signal-to-noise ratio of the embedded touch system.

[0061] The application further provides a display device, which includes display driving circuit system, capacitor array and display panel. The lower plate HP / LN of the capacitor array is driven by PB / PX signal, and the HN / LP is driven by NB / NX signal; the display panel receives the output of the capacitor array to drive the pixel unit.

[0062] Among them, the lower plate HP / LN of the capacitor array is driven by PB / PX signal, which means that the high plate HP and the low plate LN are controlled by differential output signals PB and PX for charging and discharging. Specifically, a driving circuit composed of PMOS and NMOS can be used to realize this, and the voltage state of different plates is controlled by complementary signals.

[0063] The lower plate HN / LP of the capacitor array driven by the NB / NX signal refers to that the high plate HN and the low plate LP are controlled by the charging and discharging of the differential output signals NB and NX. Specifically, a symmetric PMOS and NMOS combined driving circuit can be used to achieve this, forming a complementary signal pair to maintain the symmetry of the plate voltage.

[0064] The display panel receiving the output of the capacitor array to drive the pixel unit refers to that the differential voltage signal is transmitted to the pixel electrode of the display panel through the common nodes VP and VN of the capacitor array. Specifically, a row and column driving line in cooperation with a thin film transistor switch can be used to achieve this, converting the latched quantization result into a pixel voltage.

[0065] Specifically, in the display driving stage, the PB / PX signal and the NB / NX signal drive the HP / LN plate and the HN / LP plate of the capacitor array respectively, generate a differential voltage through the set driving circuit, and apply it to the common node of the capacitor array. When the reset signal RES is disabled, the positive feedback reset holding circuit maintains the voltage state of the lower plate, avoiding voltage drift caused by leakage current or noise. The common nodes VP and VN of the capacitor array transmit the differential voltage to the row and column driving lines of the display panel, and control the charging and discharging of the pixel unit through the thin film transistor switch, thereby realizing high refresh rate dynamic display.

[0066] Compared with the prior art, the lower plate of the capacitor array of the traditional display device relies on the continuous reset signal to maintain the voltage after reset, which is prone to voltage instability due to signal path delay or leakage current. However, the present scheme uses a positive feedback reset holding circuit to autonomously maintain the plate voltage after the reset signal is disabled, and uses separate PB / PX and NB / NX driving signals to control the complementary plates, reducing the mutual interference between signals and improving the stability of the pixel driving voltage. In addition, the latched output of the prior art needs to drive a complementary signal pair at the same time, resulting in increased load of the previous stage circuit. However, the present scheme splits the driving signal path, reducing the output load of the latch circuit.

[0067] Through the above technical scheme, the present application can maintain the stability of the lower plate voltage of the capacitor array in the embedded touch display scene, reduce the reset noise and voltage feedthrough effect, and ensure the signal baseline accuracy in the touch detection stage. At the same time, the separate driving signal path reduces the output load of the latch circuit, improves the signal transmission speed, and meets the needs of high refresh rate display. In addition, the self-sustaining mechanism of the positive feedback reset holding circuit avoids the energy consumption of the continuous reset signal, which helps to reduce the power consumption of the overall system.

[0068] The application further provides an in-cell touch panel device, comprising display driving circuit system and touch detection module; the display driving circuit system comprises dynamic latch unit, capacitor array and set driving circuit; the touch detection module comprises differential amplifier, which is used for detecting voltage changes of HP-LN polar plate of the first capacitor array and HN-LP polar plate of the second capacitor array, and identifying touch signal by comparing voltage difference.

[0069] The differential amplifier refers to a circuit capable of amplifying the difference between two input signals, which can be implemented by an operational amplifier or a comparator circuit, and is used for detecting the voltage difference between the HP-LN polar plate and the HN-LP polar plate, so as to offset common-mode noise and improve signal identification accuracy. The HP-LN polar plate refers to the high-position polar plate of the first capacitor array and the low-position polar plate of the second capacitor array, and the voltage changes of the two are detected to form a differential input signal, so as to eliminate the influence of external interference on a single polar plate. The HN-LP polar plate refers to the high-position polar plate of the second capacitor array and the low-position polar plate of the first capacitor array, and the voltage changes thereof are complementary to those of the HP-LN polar plate, so that the touch signal can be accurately extracted by comparing the difference between the two. The voltage difference comparison refers to comparing the voltage difference output by the differential amplifier with a reference threshold, which can be implemented by an analog-to-digital converter or a logic circuit, and is used for judging the touch position or the pressure intensity.

[0070] Specifically, in the touch detection stage, the display driving circuit system drives the lower polar plate of the capacitor array through the dynamic latch unit and the set driving circuit, so that the lower polar plate can maintain a stable voltage through the positive feedback reset holding circuit after the reset signal is disabled. The differential amplifier of the touch detection module is connected with the HP polar plate of the first capacitor array and the LN polar plate of the second capacitor array, and the HN polar plate of the second capacitor array and the LP polar plate of the first capacitor array, respectively, and detects the voltage difference between the two groups of polar plates in real time. When a touch operation occurs, the capacitance between the polar plates of the capacitor array changes due to the change of the touch position, the differential amplifier amplifies the voltage difference and transmits it to the comparison circuit, and the touch signal is identified by analyzing the difference.

[0071] Compared with the prior art, the traditional touch detection adopts a single-end detection method, which only monitors the voltage of a single polar plate and is easily affected by reset noise or environmental interference. In this scheme, the voltage changes of the complementary polar plates are collected simultaneously through differential detection, the common-mode noise is offset by using the differential signal, and the baseline drift caused by power fluctuation or temperature change is avoided. In addition, the positive feedback reset holding circuit and the differential amplifier work cooperatively, which can maintain the symmetry of the polar plate voltage after the reset signal is disabled, and further reduce the influence of the capacitance feedthrough effect.

[0072] By the technical scheme, the common-mode interference in the touch detection stage can be effectively inhibited, and the signal-to-noise ratio of the touch signal is improved. The differential detection mechanism reduces the misjudgment caused by reset noise or asymmetric plate voltage, and ensures the stability of the touch signal baseline. Meanwhile, through the cooperation of the dynamic latching unit and the set driving circuit, high refresh rate display is maintained while high-precision touch detection is realized, which is suitable for low-power scenarios of an embedded touch display integrated system.

[0073] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A display driving circuit system with an integrated dynamic latch unit, characterized in that: It includes a dynamic latch unit, a capacitor array and a set drive circuit; The dynamic latch unit includes: a control signal generating circuit for generating a latch control signal CLK and an input control signal SW based on an asynchronous clock signal CLKC and a shift state signal QX; A controllable input circuit, used for controlling the connection between the input signal and the latch circuit through a SW signal; Positive feedback latch circuit, used to amplify the input signal and latch the quantization result when CLK is at a low level; An output buffer for enhancing the driving capability of the latch result and generating a shift signal QOUT; Capacitor arrays, including: The first capacitor array is composed of a plurality of capacitor groups connected in parallel. Each capacitor group includes two capacitors connected in parallel, whose lower plates are a high-order plate HP and a low-order plate LP, and whose upper plates are connected to a common node VP. The second capacitor array is composed of a plurality of parallel capacitor groups, each capacitor group includes two parallel capacitors, the lower plates of which are a high plate HN and a low plate LN, and the upper plates are connected to a common node VN; The lower plate of each capacitor group is provided with a positive feedback reset and hold circuit, which is controlled by a reset signal RES and is used to maintain the plate voltage state after the reset signal RES fails. The set drive circuit includes: a PB / PX control circuit for driving the HP plate of the first capacitor array and the LN plate of the second capacitor array respectively through a differential output signal PB / PX; an NB / NX control circuit for respectively driving the HN plate of the second capacitor array and the LP plate of the first capacitor array via a differential output signal NB / NX; The capacitor array is connected to the set drive circuit through a positive feedback reset hold circuit, and is used to maintain the plate voltage state under the control of a reset signal RES, and drive the plate to charge and discharge through a differential output signal during the set phase.

2. The display driving circuit system with integrated dynamic latch unit according to claim 1, characterized in that: The control signal generating circuit includes a PMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3, a PMOS transistor M5 and a PMOS transistor M6, wherein: The gate of M1 is connected to the shift state signal QX, the source is connected to the power supply VDD, and the drain outputs the latch control signal CLK; The gate of M2 and the gate of M1 are connected to the shift state signal QX, the drain and the drain of M1 are connected to the CLK node, and the source is connected to the drain of M3; The gate of M3 is connected to the asynchronous clock signal CLKC, and the source is grounded; The gate of M5 is connected to the latch state node X, the source is connected to the power supply VDD, and the drain is connected to the input control signal SW; The gate of M6 is connected to the input control signal SW, the source is connected to the power supply VDD, and the drain is connected to the output buffer; The CLK signal is generated by the delay logic of M1-M3, and the input control signal SW is generated by M5-M6 and then delayed by the inverter and fed back to the controllable input circuit.

3. The display driving circuit system with integrated dynamic latch unit according to claim 2, characterized in that: The controllable input circuit includes a PMOS transistor M5, a PMOS transistor M6 and an NMOS transistor M9, wherein: The gate of M9 is connected to the latch state node X, the drain is fed back to the drain of M5 through the input control signal SW, and the source is grounded; When the input control signal SW is low, M6 is turned on and charges the source of M11 to the power supply VDD, and M9 is turned off to isolate the input signal; when the input control signal SW is high, M6 is turned off, M9 is turned on and passes the input signal to the positive feedback latch circuit.

4. The display driving circuit system with integrated dynamic latch unit according to claim 3, characterized in that: The positive feedback latch circuit includes a PMOS transistor M4, a PMOS transistor M7, an NMOS transistor M8 and an NMOS transistor M9, wherein: The gate of M4 is connected to the latch control signal CLK, the source is connected to the power supply VDD, and the drain is connected to the source of M7, serving as the tail current source of the positive feedback latch circuit; The gate of M7 is connected to the asynchronous clock signal CLKC, the source is connected to the drain of M4, and the drain is connected to the latch state node X; The gate of M8 is connected to the latch control signal CLK, the source is grounded, and the drain is connected to the drain of M7 and the drain of M9 through the latch state node X; The positive feedback latch circuit is configured to trigger a latching operation at a falling edge of CLK, and the CLK signal maintains an anti-phase relationship with the asynchronous clock CLKC.

5. The display driving circuit system with integrated dynamic latch unit according to claim 1, wherein: The output buffer includes an NMOS transistor M10, a PMOS transistor M11 and an NMOS transistor M12, wherein: The gate of M10 is connected to the input control signal SW, the drain outputs the shift signal QOUT, and the source is grounded; The gate of M11 is connected to the latch result signal QRES, the source is connected to the drain of M6, and the drain is connected to the shift signal QOUT; The gate of M12 is connected to the latch result signal QRES, the drain is connected to the shift signal QOUT, and the source is grounded; After the shift signal QOUT passes through the level conversion circuit, two pairs of differential output signals PB / PX and NB / NX are generated.

6. The display driving circuit system with integrated dynamic latch unit according to claim 1, characterized in that: The PB / PX control circuit includes a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, an NMOS transistor M16, and an NMOS transistor M17: The gate of M13 is connected to the differential output PB, the source receives the differential reference voltage VREFP, and the drain is connected to the LN plate; The gate of M14 is connected to the LN plate, the source receives the differential reference voltage VREFP, and the drain is connected to the HP plate; The gate of M15 is connected to the reset signal RES, the source receives the differential reference voltage VREFN, and the drain is connected to the LN plate; The gate of M16 is connected to the HP plate, the source receives the differential reference voltage VREFN, and the drain is connected to the LN plate; The gate of M17 is connected to the differential output PX, the source receives the differential reference voltage VREFN, and the drain is connected to the drain of M14 and the gate of M16 through the HP plate.

7. The display driving circuit system with integrated dynamic latch unit according to claim 6, characterized in that: The NB / NX control circuit includes a PMOS transistor M18, a PMOS transistor M19, an NMOS transistor M20, an NMOS transistor M21, and an NMOS transistor M22, wherein: The gate of M18 is connected to the LP plate, the source receives the differential reference voltage VREFP, and the drain is connected to the HN plate; The gate of M19 is connected to the differential output NB, the source receives the differential reference voltage VREFP, and the drain is connected to the LP plate; The gate of M20 is connected to the differential output NX, the source receives the differential reference voltage VREFN, and the drain is connected to the HN plate; The gate of M21 is connected to the HN plate, the source receives the differential reference voltage VREFN, and the drain is connected to the LP plate; The gate of M22 is connected to the RES signal, the source receives the differential reference voltage VREFN, and the drain is connected to the gate of M18, the drain of M19 and the drain of M21 through the LP plate.

8. A display device comprising: The display driving circuit system according to any one of claims 1 to 7; The capacitor array has its lower plates HP / LN driven by the PB / PX signal, and HN / LP driven by the NB / NX signal; The display panel receives the output of the capacitor array to drive the pixel units.

9. An in-cell touch panel device, comprising: The display driving circuit system according to any one of claims 1 to 7; The touch detection module includes a differential amplifier for detecting voltage changes of the HP-LN plates of the first capacitor array and the HN-LP plates of the second capacitor array, and identifying touch signals by comparing voltage differences.

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