Driving circuit and method of display panel, display panel and display equipment

Abstract

The invention discloses a driving circuit and method of a display panel, the display panel and display equipment, and relates to the technical field of display, the circuit comprises a picture detection module, and the picture detection module is set to detect the picture scene type of an input picture and determine a picture detection signal according to the picture scene type; the signal trigger end of the compensation trigger module is electrically connected with the first signal interface of the picture detection module, and the compensation trigger module is set to receive the picture detection signal sent by the picture detection module and generate a clock signal according to the picture detection signal as a level trigger signal of the heavy-load picture; the signal input end of the charging compensation module is electrically connected with the signal output end of the compensation trigger module, and the charging compensation module is set to carry out charging compensation according to the clock signal sent by the compensation trigger module. The invention aims to improve the surface uniformity of oversized screen picture display.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a driving circuit of a display panel, a method thereof, a display panel and a display device. BACKGROUND

[0002] With the rapid development of display panels towards ultra-large size, the factors such as too long horizontal data transmission distance of the panel and too large line impedance result in large RC (resistance-capacitance) load in the transmission process, and the phenomenon is more obvious in the middle part of the screen.

[0003] The prior art reduces the line resistance of the clock signal (CK) to reduce the RC load, thereby relieving the Gate delay (scan signal delay) problem caused by too large impedance, but this method cannot eliminate the color cast phenomenon when the line resistance is reduced to the limit of the panel line impedance, especially under the H-Line (one row of bright and one row of black) heavy load picture, the rising / falling edge of the CK waveform is delayed due to too large RC load in the middle part of the screen, the actual charging time deviates from the ideal time, and the color cast problem of bright black level and dark white level is caused, which seriously affects the surface uniformity of the ultra-large size screen picture display.

[0004] Therefore, how to improve the surface uniformity of the ultra-large size screen picture display is a technical problem to be solved at present. SUMMARY

[0005] The main purpose of the present application is to provide a driving circuit of a display panel, a method thereof, a display panel and a display device, which aims to improve the surface uniformity of the ultra-large size screen picture display.

[0006] To achieve the above-mentioned purpose, the present application provides a driving circuit of a display panel, which comprises:

[0007] a picture detection module, which is configured to detect the picture scene type of an input picture, and determine a picture detection signal according to the picture scene type;

[0008] a compensation trigger module, a signal trigger end of which is electrically connected with a first signal interface of the picture detection module, and the compensation trigger module is configured to receive the picture detection signal sent by the picture detection module, and generate a clock signal according to the level trigger signal of the heavy load picture according to the picture detection signal;

[0009] a charging compensation module, a signal input end of which is electrically connected with a signal output end of the compensation trigger module, and the charging compensation module is configured to perform charging compensation according to the clock signal sent by the compensation trigger module.

[0010] In an embodiment, the charging compensation module comprises a boost compensation unit;

[0011] The non-phase input end of the boost compensation unit is connected with the signal output end of the boost compensation unit.

[0012] The non-phase input end of the boost compensation unit is connected with the signal output end of the boost compensation unit.

[0013] In an embodiment, the driving circuit comprises a level conversion integrated chip, the charging compensation module comprises a gate voltage detection unit and a voltage compensation unit, and the compensation trigger module and the voltage compensation unit are integrated in the level conversion integrated chip.

[0014] The clock signal end of the gate voltage detection unit constitutes the signal input end of the charging compensation module and is electrically connected with the signal output end of the compensation trigger module.

[0015] The right voltage sampling end of the gate voltage detection unit is electrically connected with the right wire end of each gate wire, the left voltage sampling end of the gate voltage detection unit is electrically connected with the left wire end of each gate wire, and the detection output end of the gate voltage detection unit is electrically connected with the signal acquisition end of the picture detection module.

[0016] The second signal end of the picture detection module is electrically connected with the voltage compensation unit.

[0017] In an embodiment, the gate voltage detection unit is configured to, in response to the clock signal sent by the compensation trigger module, perform voltage acquisition for a preset detection number of gate wires line by line, acquire the left wire voltage, the middle wire voltage and the right wire voltage of each gate wire, determine the voltage detection average value according to the right wire voltage, the middle wire voltage and the left wire voltage of each gate wire, and transmit the clock signal carrying the voltage detection average value to the voltage compensation unit through the picture detection module.

[0018] The voltage compensation unit is configured to, after receiving the clock signal carrying the voltage detection average value, perform charging compensation on the clock signal according to the voltage detection average value.

[0019] In an embodiment, the compensation trigger module comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube and a sixth switch tube.

[0020] The gate end of the first switch tube, the gate end of the third switch tube and the first passage end of the fifth switch tube are respectively connected with a power supply end, the first passage end of the first switch tube is electrically connected with the first passage end of the third switch tube.

[0021] The first pass-through end of the first switch tube is electrically connected to a connection node of the first pass-through end of the third switch tube to form a signal output end of the compensation trigger module, and is electrically connected to a signal input end of the charging compensation module;

[0022] The second pass-through end of the first switch tube is electrically connected to the first pass-through end of the second switch tube, and the second pass-through end of the second switch tube is grounded;

[0023] The gate end of the second switch tube is electrically connected to a first signal interface of the picture detection module, a gate end of the fifth switch tube, and a gate end of the sixth switch tube, respectively, to form a signal trigger end of the compensation trigger module, the second pass-through end of the fifth switch tube is electrically connected to the first pass-through end of the sixth switch tube, and the second pass-through end of the sixth switch tube is grounded;

[0024] The gate end of the fourth switch tube is electrically connected to a connection node of the second pass-through end of the fifth switch tube and the first pass-through end of the sixth switch tube, the first pass-through end of the fourth switch tube is electrically connected to the second pass-through end of the third switch, and the second pass-through end of the fourth switch tube is grounded.

[0025] In addition, to achieve the above object, the application further provides a panel compensation method, which is applied to any one of the driving circuits and comprises the following steps:

[0026] After determining the picture scene type of the input picture, a picture detection signal is determined according to the picture scene type by controlling the picture detection module;

[0027] When the picture detection signal is a level trigger signal of a heavy load picture, a clock signal is generated according to the level trigger signal by controlling the compensation trigger module;

[0028] Charging compensation is performed according to the clock signal by controlling the charging compensation module.

[0029] In an embodiment, the charging compensation module comprises a boost compensation unit, and the step of controlling the charging compensation module to perform charging compensation according to the clock signal comprises the following steps:

[0030] A voltage gain multiple of the boost compensation unit is determined, and the clock voltage threshold of the clock signal is boosted according to the voltage gain multiple by controlling the charging compensation module;

[0031] The display panel during the heavy load picture is charged and compensated according to the boosted clock voltage threshold.

[0032] In an embodiment, the charging compensation module comprises a gate voltage detection unit and a voltage compensation unit, and the step of controlling the charging compensation module to perform charging compensation according to the clock signal comprises:

[0033] controlling the gate voltage detection unit to collect the right side trace voltage, the middle trace voltage and the left side trace voltage of each gate trace line row by row when the clock signal is collected, and determining a voltage detection average value according to the right side trace voltage, the middle trace voltage and the left side trace voltage of each gate trace line;

[0034] generating a clock signal carrying the voltage detection average value according to the clock signal and the voltage detection average value, and controlling the voltage compensation unit to perform charging compensation on the clock signal according to the voltage detection average value.

[0035] In addition, to achieve the above-mentioned purpose, the present application further provides a display panel, which comprises the driving circuit according to any one of the above-mentioned embodiments, and the driving circuit comprises a picture detection module, a compensation trigger module and a charging compensation module.

[0036] The display panel comprises a display area and a non-display area surrounding the periphery of the display area, and is fixedly provided with a plurality of parallelly arranged gate trace lines. The gate voltage detection unit in the charging compensation module is arranged on the side of the non-display area close to a circuit board. The picture detection module and a level conversion integrated chip are fixedly arranged on the circuit board. The compensation trigger module and the voltage compensation unit in the charging compensation module are integrally arranged in the level conversion integrated chip.

[0037] In addition, to achieve the above-mentioned purpose, the present application further provides a display device, which comprises the display panel according to the above-mentioned embodiments.

[0038] or a memory, a processor and a panel compensation program stored on the memory and executable on the processor, and the processor implements the steps of the panel compensation method according to any one of the above-mentioned embodiments when executing the panel compensation program.

[0039] The application applies the driving circuit of the display panel integrated with a picture detection module, a compensation triggering module and a charging compensation module to an ultra-large size display panel, can solve the display unevenness problem caused by excessively large line impedance from the root, and significantly improves the surface uniformity of the picture display of the ultra-large size screen. Specifically, the picture detection module can accurately identify the picture scene type caused by the RC load abnormality of the heavy load picture by detecting the input picture in real time. Next, the picture detection signal generated based on the picture scene type is transmitted to the signal triggering end of the compensation triggering module through the first signal interface of the picture detection module. At this time, the compensation triggering module generates the pre-corrected clock signal based on the picture detection signal as the level triggering signal of the heavy load picture, and sends the clock signal to the charging compensation module, so that the charging compensation module reconstructs the timing characteristics (such as the rising / falling edge slope) of the clock signal to compensate the signal delay caused by excessively large line impedance, ensures that the middle area of the ultra-large size screen can still obtain the consistent charging time as the edge area of the screen under the heavy load picture (i.e. H-Line heavy load picture), thereby eliminating the color deviation phenomenon of the black level brightness lifting and the white level brightness attenuation caused by the RC load difference, and further significantly improving the surface uniformity of the picture display of the ultra-large size screen. BRIEF DESCRIPTION OF DRAWINGS

[0040] The accompanying drawings, which are incorporated into and form a part of the specification, illustrate an embodiment consistent with the present application and, together with the description, serve to explain the principles of the application.

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, those skilled in the art can obtain other drawings according to these drawings without any creative effort.

[0042] Figure 1 is a structural block diagram of the present application simulating the gradually increasing RC load of the panel;

[0043] Figure 2 is a CK delay simulation waveform schematic diagram of the present application simulating the gradually increasing RC load of the panel;

[0044] Figure 3 is a structural block diagram of the first embodiment of the driving circuit of the display panel of the present application;

[0045] Figure 4 is a clock signal waveform compensation schematic diagram related to the embodiment of the present application;

[0046] Figure 5 is a boost compensation unit circuit schematic diagram related to the embodiment of the present application;

[0047] Figure 6is a driving circuit schematic diagram of a display panel related to the embodiment scheme of the present application;

[0048] Figure 7 is a compensation trigger module circuit schematic diagram related to the embodiment scheme of the present application;

[0049] Figure 8 is a structure schematic diagram of detecting 1 gate wire related to the embodiment scheme of the present application;

[0050] Figure 9 is a structure schematic diagram of detecting 2 gate wires related to the embodiment scheme of the present application;

[0051] Figure 10 is a structure schematic diagram of detecting N gate wires related to the embodiment scheme of the present application;

[0052] Figure 11 is a structure schematic diagram of a display device related to the embodiment scheme of the present application.

[0053] Explanation of reference signs:

[0054] 10, picture detection module; 20, compensation trigger module; 30, charging compensation module; OP1, operational amplifier; R1, first resistor; R2, second resistor; 31, gate voltage detection unit; 32, voltage compensation unit; 40, level conversion integrated chip; Q1, first switch tube; Q2, second switch tube; Q3, third switch tube; Q4, fourth switch tube; Q5, fifth switch tube; Q6, sixth switch tube.

[0055] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0057] It should be noted that if the present application embodiments involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), if the certain posture changes, the directional indications also change accordingly.

[0058] In addition, if the description of "first", "second" and the like is involved in the embodiments of the present application, the description of "first", "second" and the like is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can be explicitly or implicitly included at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, nor in the protection scope claimed by the present application.

[0059] The exemplary embodiments will be described in detail herein with reference to the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0060] With the continuous development of display technology, the size of the display screen of LCD (Liquid Crystal Display) is getting larger and larger, such as 94-inch and 100-inch screens have been mass-produced, but as the size increases, the charging time requirement for the panel of the super large size screen is more stringent. One important point is that the data signal has a large RC load in the transmission process due to the excessive size of the panel, the excessive length of the data transmission distance, the excessive impedance of the line, and the like, and the phenomenon is more obvious in the middle part of the screen, especially under the heavy load picture of H-Line (one row of bright and one row of black), the middle part of the screen will be wrong due to the Gate delay, resulting in the color cast phenomenon that the black level becomes lighter and the white level becomes darker.

[0061] Figure 1 The RC load gradually increases with the increase of the size of the analog panel in Figure 2 As shown in the CK delay simulation waveform of the RC load gradually increasing, the prior art reduces the bus line resistance of CK to reduce the panel RC load, thereby reducing the degree of Gate delay (scanning signal delay, i.e. the timing delay of scanning signal in the transmission process due to RC load). However, when the CK resistance value is reduced to only the panel line impedance, the color cast phenomenon cannot be eliminated.

[0062] To eliminate the color cast phenomenon of the display of the super large size screen and improve the uniformity of the display of the super large size screen, the present application provides a driving circuit of a display panel and a method thereof, a display panel and a display device.

[0063] The present application provides a driving circuit of a display panel, which refers to Figure 3As shown, Figure 3 is a structural block diagram of a first embodiment of a driving circuit of a display panel of the present application. The driving circuit of the display panel comprises:

[0064] A picture detection module 10 is arranged to detect a picture scene type of an input picture and determine a picture detection signal according to the picture scene type.

[0065] In the present embodiment, the input picture is intelligently recognized and classified by the picture detection module 10, precise judgment can be achieved according to the difference characteristics of the heavy load picture and the normal picture scene, and a different picture detection signal is output through the high and low level signals. For example, the picture detection module 10 automatically detects the input picture of the video source. If the picture scene type of the input picture is a heavy load picture, a high level is provided as a picture detection signal to activate the compensation trigger module 20 to enable the charging compensation module 30 to realize charging compensation for the heavy load picture. If the picture scene type of the input picture is a normal picture, a low level is provided as a picture detection signal to the compensation trigger module 20 to close the charging compensation function, avoiding excessive intervention to the normal picture scene, which not only guarantees the display uniformity, but also reduces the risk of panel power consumption and signal distortion.

[0066] It should be noted that the picture detection module 10 can be understood as a TCON IC (Timing Controller Integrated Circuit). The normal picture can be understood as a video picture other than the heavy load picture. The video source can be understood as a video input device such as a camera, a player, a computer, etc. The heavy load picture can be understood as a horizontal bright and dark alternating picture of H-Line (one bright line and one black line).

[0067] In a specific embodiment, after the picture detection module 10 receives the input picture from the video source, the pixel brightness values of the input picture are scanned line by line, and it is detected whether the brightness absolute difference between the pixel brightness value of each line and the pixel brightness value of the adjacent line is higher than a preset bright and dark alternating standard threshold value. If the brightness absolute difference of a plurality of consecutive lines (for example, 6 lines) is higher than the bright and dark alternating standard threshold value, it is determined that the input picture is a heavy load picture. If at least one of the brightness absolute differences of the plurality of consecutive lines does not exceed the bright and dark alternating standard threshold value, it is determined that the input picture is a normal picture.

[0068] A compensation trigger module 20 is electrically connected to a first signal interface of the picture detection module 10. The compensation trigger module 20 is arranged to receive the picture detection signal sent by the picture detection module 10, and generate a clock signal according to the picture detection signal as a level trigger signal for the heavy load picture.

[0069] In the embodiment, the signal trigger end of the compensation trigger module 20 is electrically connected with the first signal interface of the picture detection module 10. After the compensation trigger module 20 receives the picture detection signal sent by the picture detection module 10, the compensation trigger module 20 automatically generates a pre-corrected clock signal based on the picture detection signal as a level trigger signal representing a high level, so that the compensation trigger module 20 electrically connected with the charging compensation module 30 increases the rising / falling edge slope of the clock signal through voltage boosting, thereby offsetting the charging time deviation caused by the panel RC load and eliminating the color deviation phenomenon in the middle of the picture.

[0070] The charging compensation module 30, a signal input end of the charging compensation module 30 is electrically connected with a signal output end of the compensation trigger module 20, and the charging compensation module 30 is configured to perform charging compensation according to the clock signal sent by the compensation trigger module 20.

[0071] In the embodiment, the signal input end of the charging compensation module 30 is electrically connected with the signal output end of the compensation trigger module 20. The charging compensation module 30 performs voltage boosting on the clock signal to increase the rising / falling edge slope of the clock signal, thereby achieving waveform compensation of the signal waveform of the clock signal and forming a compensated waveform B20, so that the compensated charging time ti is consistent with the ideal charging time t0, thereby eliminating the color deviation phenomenon caused by the time sequence delay of the actual waveform B10. Figure 4 Figure 4

[0072] Further, in some possible embodiments, the charging compensation module 30 includes a voltage boosting compensation unit. A same-phase input end of the voltage boosting compensation unit constitutes the signal input end of the charging compensation module 30 and is electrically connected with the signal output end of the compensation trigger module 20. An opposite-phase input end of the voltage boosting compensation unit is connected with a signal output end of the voltage boosting compensation unit.

[0073] In the embodiment, the voltage boosting compensation unit provided in the application can include an operational amplifier OP1, a first resistor R1 and a second resistor R2, and the circuit structure is as shown in FIG. 4. Figure 5 When the same-phase input end of the operational amplifier is connected with the clock signal sent by the signal input end of the charging compensation module 30, the clock voltage threshold V_CK of the clock signal is subjected to voltage boosting according to a preset feedback voltage boosting algorithm, so that the charging time (and the compensated charging time) of the horizontal alternating bright black picture is consistent with the ideal charging time through the boosted clock voltage threshold Vout, thereby eliminating the time sequence delay of the time sequence signal caused by the RC load, effectively suppressing the color deviation phenomenon of the black level brightness rising and the white level brightness attenuation caused by the RC load difference, and further significantly improving the surface uniformity of the picture display of the super-large size screen.

[0074] ​​It should be noted that the preset feedback boost algorithm expression is Vout = [1 + (R1 / R2)] * V_CK, wherein R1 represents the resistance value of the first resistor R1, and R2 represents the resistance value of the second resistor R2, that is, the resistance value ratio of the first resistor R1 and the second resistor R2 determines the voltage gain multiple [1 + (R1 / R2)], and the resistance value ratio can be customized according to application requirements.

[0075] Further, in some possible embodiments, the driving circuit includes a level conversion integrated chip 40, the charging compensation module 30 includes a gate voltage detection unit 31 and a voltage compensation unit 32, and the compensation trigger module 20 and the voltage compensation unit 32 are integrated in the level conversion integrated chip 40; a clock signal end of the gate voltage detection unit 31 constitutes a signal input end of the charging compensation module 30 and is electrically connected with a signal output end of the compensation trigger module 20; a right voltage sampling end of the gate voltage detection unit 31 is electrically connected with a right wire end of each gate wire, a left voltage sampling end of the gate voltage detection unit 31 is electrically connected with a left wire end of each gate wire, and a detection output end of the gate voltage detection unit 31 is electrically connected with a signal acquisition end of the picture detection module 10; and a second signal end of the picture detection module 10 is electrically connected with the voltage compensation unit 32.

[0076] In the embodiment, the gate voltage detection unit 31 in the charging compensation module 30 is packaged in the display panel as shown in the following figure. Figure 6 The non-display area represented by the oblique line shadow part, and the compensation trigger module 20 and the voltage compensation unit 32 in the charging compensation module 30 are integrated in the level conversion integrated chip 40, to replace the design of the compensation trigger module 20 and the charging compensation module 30 as peripheral circuits as shown in the following figure. Figure 3 The design not only effectively reduces the cost of peripheral circuits, but also increases the versatility of the level conversion integrated chip 40.

[0077] It should be noted that the level conversion integrated chip 40 (Level Shift IC) can generate a clock signal output to the display panel. The level conversion integrated chip 40 and the picture detection module 10 (i.e., TCON IC) are assembled in the PCBA (Printed Circuit Board Assembly) as shown in the following figure, and Figure 6 The blank rectangle in the following figure represents an effective display area. Figure 6

[0078] ​Further, in some possible embodiments, the gate voltage detection unit 31 is configured to, in response to the clock signal sent by the compensation trigger module 20, perform voltage collection for each of the preset number of gate lines row by row, to obtain the left-side line voltage, the middle line voltage and the right-side line voltage of each of the gate lines, to determine the voltage detection average value according to the right-side line voltage, the middle line voltage and the left-side line voltage of each of the gate lines, and to transmit the clock signal carrying the voltage detection average value to the voltage compensation unit 32 via the picture detection module 10; and the voltage compensation unit 32 is configured to, after receiving the clock signal carrying the voltage detection average value, perform charge compensation on the clock signal according to the voltage detection average value.

[0079] In the present embodiment, referring to Figure 6 , through the electrical connection between the gate voltage detection unit 31 and the compensation trigger module 20, the compensation trigger module 20 outputs a clock signal to the voltage detection unit 31 in response to the level trigger signal during the heavy-load picture, and the voltage detection unit 31 starts a voltage detection period in response to the rising edge or the falling edge of the clock signal.

[0080] During the voltage detection period, the gate voltage detection unit 31 performs row-by-row scanning and voltage collection for the preset number of gate lines (for example, N gate lines evenly distributed on the display panel, or key lines with representative RC load characteristics based on historical data). Specifically, for each selected gate line, the voltage detection unit 31 synchronously collects the voltage values at three specific positions on the gate line through the built-in multiplexer and analog-to-digital converter circuit, one of which is the voltage at the left end of the gate line, defined as the left-side line voltage (i.e. VL1, VL2, VL3, VL4, … and VLn shown in Figure 6 ); the second one is the voltage near the geometric midpoint of the gate line, defined as the middle line voltage (i.e. V_m1, V_m2, V_m3, V_m4, … and V_mn shown in Figure 6 ); and the third one is the voltage at the right end of the gate line, defined as the right-side line voltage (i.e. Vr1, Vr2, Vr3, Vr4, … and Vrn shown in Figure 6 ).

[0081] After the preset number of gate lines are detected, the data processing chip of the gate voltage detection unit 31 processes the voltage data of each gate line. Specifically, for a single gate line i (i = 1, 2, 3, …, n), first, the voltage difference between the voltage of the left side line and the voltage of the middle line, i.e., the voltage difference (VLi-V_mi) between the voltage of the left side line VL i and the voltage of the middle line V_mi, and the voltage difference (Vri-V_mi) between the voltage of the right side line Vri and the voltage of the middle line V_mi, are calculated; next, the arithmetic mean of the calculated voltage difference (VLi-V_mi) and the voltage difference (Vri-V_mi) is taken as the line voltage difference average of the gate line i; then, the gate voltage detection unit 31 sends the data packet carrying the line voltage difference average to the picture detection module 10 through the serial or parallel communication interface, and the picture detection module 10 processes the line voltage difference average of all gate lines (i.e., the preset number of gate lines) to obtain an accurate voltage detection average excluding the process deviation of the gate line; then, the picture detection module 10 sends the clock signal carrying the voltage detection average to the voltage compensation unit 32 through the second signal terminal, so that the voltage compensation unit 32 processes the voltage detection average according to the preset feedback voltage boosting algorithm, thereby the voltage detection average after voltage boosting can be used to compensate the charging time deviation caused by the line impedance difference, so that the charging time (and the compensated charging time) of the horizontal alternating bright and dark picture is consistent with the ideal charging time, which not only effectively eliminates the local error that may be introduced by the traditional single-point detection, but also adapts to the RC load difference of different areas (especially the middle and edge of large-size panels), significantly improves the full-screen charging uniformity, and finally solves the display quality problems such as color cast and uneven brightness from the signal source, which is especially suitable for the uniformity optimization of super-large-size display panels under heavy load pictures.

[0082] It should be noted that the voltage compensation unit 32 is the same as the voltage boosting compensation unit, i.e., the circuit structure of the voltage compensation unit 32 can refer to Figure 5 .

[0083] In a specific embodiment, the starting voltage on the left side of the first Gate line (i.e., the voltage of the left line) is defined as VL1, the middle voltage (i.e., the voltage of the middle line) is defined as V_m1, and the starting voltage on the right side (i.e., the voltage of the right line) is defined as Vr1. The starting voltage on the left side of the second gate line is defined as VL2, the middle voltage is defined as V_m2, and the starting voltage on the right side is defined as Vr2. Since the length of the large-size panel line is too long, taking the first gate line as an example, the starting voltage on the left side VL1 is basically the same as the starting voltage on the right side Vr1. As the line moves towards the middle, the voltage will gradually decrease due to the length of the line, and will eventually decrease to the middle voltage V_m1. In this way, there will be a voltage difference between the two sides and the center. The generation of the voltage difference is the cause of the color deviation, and the color deviation can be eliminated by eliminating the voltage difference. Therefore, by detecting the three voltage data of a single gate line and performing calculations, the average line voltage difference can be obtained. The expression of the average line voltage difference is as follows:

[0084]

[0085] Calculating the voltage difference between the two ends and taking the average can accurately obtain the average voltage difference of the trace, significantly improving the accuracy of the overall voltage difference value of each gate trace. The voltage difference between the two ends refers to the voltage difference on the left (VL1-V_m1) and the voltage difference on the right (Vr1-V_m1).

[0086] Since the manufacturing process of each gate trace may fluctuate, the number of gate traces detected can be increased. For example, increasing the number of detected gate traces to 2 can improve data accuracy. The following algorithm can be used for calculation:

[0087]

[0088] By calculating the average voltage difference from both sides to the middle of a single gate line, and then adding the average voltage difference of the two lines and taking the average value, we can obtain a data that eliminates the influence of gate line process deviation.

[0089] If you need to further improve the accuracy of the data, you can Figure 6 Increase the number of gate lines to be detected, and average the voltage differences of all lines to obtain the voltage detection average. The specific algorithm is as follows:

[0090]

[0091] Wherein, n represents the preset detection number of the gate traces, the more the preset detection number, the more accurate the voltage detection average. Specifically, the trace voltage difference average of all the gate traces detected by the gate voltage detection unit 31 is transmitted to the picture detection module 10, so that the picture detection module 10 averages the trace voltage difference average of all the gate traces, obtains the clock signal carrying the voltage detection average, and then outputs the clock signal to the internal voltage compensation unit 32 to increase the proportion data (i.e. resistance ratio) of the voltage detection average, and then gives the level conversion integrated chip 40 for real-time adjustment, and finally outputs the clock signal waveform after gain (i.e. the clock signal waveform carrying the voltage detection average after voltage increase), so as to achieve the effect of the same charging time for the panels with different process effects, eliminate the influence of the inter-chip difference, and achieve the consistency of eliminating color cast.

[0092] Further, in some other possible embodiments, the compensation trigger module 20 includes a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a fifth switch tube Q5, and a sixth switch tube Q6; the gate end of the first switch tube Q1, the gate end of the third switch tube Q3, and the first path end of the fifth switch tube Q5 are respectively connected with a power supply end, and the first path end of the first switch tube Q1 is electrically connected with the first path end of the third switch tube Q3; the connection node of the first path end of the first switch tube Q1 and the first path end of the third switch tube Q3 constitutes a signal output end of the compensation trigger module 20, which is electrically connected with a signal input end of the charging compensation module 30; the second path end of the first switch tube Q1 is electrically connected with the first path end of the second switch tube Q2, and the second path end of the second switch tube Q2 is grounded; the gate end of the second switch tube Q2 constitutes a signal trigger end of the compensation trigger module 20, which is respectively electrically connected with a first signal interface of the picture detection module 10, the gate end of the fifth switch tube Q5, and the gate end of the sixth switch tube Q6; the second path end of the fifth switch tube Q5 is electrically connected with the first path end of the sixth switch tube Q6, and the second path end of the sixth switch tube Q6 is grounded; the gate end of the fourth switch tube Q4 is connected with the connection node of the second path end of the fifth switch tube Q5 and the first path end of the sixth switch tube Q6, the first path end of the fourth switch tube Q4 is electrically connected with the second path end of the third switch tube Q3, and the second path end of the fourth switch tube Q4 is grounded.

[0093] In this embodiment, the first switch transistor Q1, the second switch transistor Q2, the third switch transistor Q3, the fourth switch transistor Q4, and the sixth switch transistor Q6 in the compensation trigger module 20 are N-type MOS transistors, and the fifth switch transistor Q5 is a P-type MOS transistor. Due to the characteristics that N-type MOS transistors are turned on at a high level and P-type MOS transistors are turned on at a low level, a constant high level is input to the gate terminals of the first switch transistor Q1 and the third switch transistor Q3, so that the gate terminal of the second switch transistor Q2 is connected to the first signal interface (i.e., the first signal interface) of the image detection module 10. Figure 7 The source terminal of the second switch Q2 is connected to the clock signal, and the source terminal of the fourth switch Q4 is connected to a constant low level. The image detection module 10 automatically detects the scene type of the input video source to determine the corresponding image detection signal. In other words, the T-image detection module 10 sends a high-level signal to the first signal interface connected to the gate terminal of the second switch Q2 when it detects an H-Line image, and sends a low-level signal to the first signal interface when it detects a normal image.

[0094] Specifically, when the gate terminal of the second switch tube Q2 receives a high-level signal, the second switch tube Q2 circuit and the sixth switch tube Q6 in the compensation trigger module 20 will be turned on after receiving the high-level signal. The fifth switch tube Q5 is in a cut-off state when receiving the high-level signal. At this time, the drain terminal connected to the fifth switch tube Q5 and the sixth switch tube Q6 will generate a low-level signal. At this time, the fourth switch tube Q4 is in a cut-off state due to receiving the low-level signal, which ultimately makes the signal output terminal (i.e. Figure 7 OUT terminal shown) output Figure 7 The clock signal CK is shown. When the gate terminal of the second switch Q2 receives a low-level signal, the second switch Q2 circuit and the sixth switch Q6 in the compensation trigger module 20 are turned off due to the low-level signal, while the fifth switch Q5 is turned on due to the low-level signal. At this time, the drain terminal connected to the fifth switch Q5 and the sixth switch Q6 will generate a high-level signal. At this time, the fourth switch Q4 is turned on due to the high-level signal, pulling the signal CK down to the ground terminal, ultimately causing the signal output terminal of the compensation trigger module 20 to not output the signal CK. The compensation trigger module 20 thus outputs the clock signal CK when detecting an H-line image and does not output the clock signal CK when detecting a normal image. This not only compensates for the clock signal waveform of the overloaded image, but also avoids excessive interference with the normal image scene, ensuring display uniformity while reducing panel power consumption and the risk of signal distortion.

[0095] In summary, the display panel driving circuit integrated with the picture detection module 10, the compensation triggering module 20 and the charging compensation module 30 is applied to the super-large size display panel, which can solve the display unevenness problem caused by the excessively large line impedance from the root cause and significantly improve the surface uniformity of the super-large size screen picture display. Specifically, the picture detection module 10 can accurately identify the picture scene type with abnormal RC load caused by the heavy load picture by detecting the input picture in real time. Next, the picture detection signal generated based on the picture scene type is transmitted to the signal triggering end of the compensation triggering module 20 through the first signal interface of the picture detection module 10. At this time, the compensation triggering module 20 generates the pre-corrected clock signal based on the picture detection signal as the level triggering signal of the heavy load picture and sends it to the charging compensation module 30, so that the charging compensation module 30 reconstructs the timing characteristics (such as the rising / falling edge slope) of the clock signal to compensate for the signal delay caused by the excessively large line impedance, and ensures that the middle area of the super-large size screen can still obtain the consistent charging duration with the edge area of the screen under the heavy load picture (i.e. H-Line heavy load picture), thereby eliminating the color cast phenomenon of the black level brightness lifting and the white level brightness attenuation caused by the RC load difference, and further significantly improving the surface uniformity of the super-large size screen picture display.

[0096] Further, based on the first embodiment of the display panel driving circuit of the present application, the second embodiment of the panel compensation method of the present application is proposed.

[0097] The panel compensation method of the present application is applied to the driving circuit of any one of the display panels described above, and is executed by the display device applied to the driving circuit of the display panel. The panel compensation method of the present application includes the following implementation steps S10 to S30.

[0098] Step S10: After determining the picture scene type of the input picture, the picture detection module 10 determines the picture detection signal according to the picture scene type.

[0099] In this embodiment, the picture detection module 10 can intelligently identify and classify the input picture, accurately judge the difference between the heavy load picture and the normal picture scene, and output different picture detection signals through high and low level signals. For example, the picture detection module 10 automatically detects the input picture of the video source. If the picture scene type of the input picture is a heavy load picture, a high level is provided as a picture detection signal to activate the compensation triggering module 20 to enable the charging compensation module 30 to realize the charging compensation of the heavy load picture. If the picture scene type of the input picture is a normal picture, a low level is provided as a picture detection signal to the compensation triggering module 20 to turn off the charging compensation function, avoiding excessive intervention to the normal picture scene, which not only guarantees the display uniformity, but also reduces the risk of panel power consumption and signal distortion.

[0100] Step S20: When the picture detection signal is a level trigger signal of a heavy picture, controlling the compensation trigger module 20 to generate a clock signal according to the level trigger signal.

[0101] In the embodiment, through the electrical connection between the signal trigger end of the compensation trigger module 20 and the first signal interface of the picture detection module 10, after the picture detection module 10 sends the picture detection signal to the compensation trigger module 20, the compensation trigger module 20 automatically generates a pre-corrected clock signal based on the picture detection signal as a level trigger signal representing a high level, so that the compensation trigger module 20 electrically connected to the charging compensation module 30 increases the rising / falling edge slope of the clock signal through voltage boosting, thereby offsetting the charging time deviation caused by the panel RC load and eliminating the color deviation phenomenon in the middle of the picture.

[0102] Step S30: Controlling the charging compensation module 30 to perform charging compensation according to the clock signal.

[0103] In the embodiment, through the electrical connection between the signal input end of the charging compensation module 30 and the signal output end of the compensation trigger module 20, the charging compensation module 30 performs voltage boosting processing on the clock signal to raise the rising / falling edge slope of the clock signal, thereby achieving waveform compensation of the signal waveform of the clock signal, forming Figure 4 the compensated waveform B20, so that the compensated charging time ti is consistent with the ideal charging time t0, so as to eliminate the color deviation phenomenon caused by the timing delay of the actual waveform B10. Figure 4

[0104] Further, in other possible embodiments, the charging compensation module 30 includes a voltage boosting compensation unit, and the step S20 of controlling the charging compensation module 30 to perform charging compensation according to the clock signal can further include steps S201 to S202.

[0105] Step S201: Determining the voltage gain multiple of the voltage boosting compensation unit, and controlling the charging compensation module 30 to perform voltage boosting processing on the clock voltage threshold of the clock signal according to the voltage gain multiple.

[0106] In the embodiment, the charging compensation module 30 provided by the application includes a voltage boosting compensation unit, which can include an operational amplifier OP1, a first resistor R1 and a second resistor R2. Since the voltage gain multiple is [1+(R1 / R2)], i.e., the voltage gain multiple of the voltage boosting compensation unit can be accurately obtained by calculating the resistance ratio of the first resistor R1 and the second resistor R2; next, according to the product of the voltage gain multiple and the clock voltage threshold, the voltage boosted clock voltage threshold can be accurately obtained.

[0107] ​Step S202: performing charging compensation on the display panel during the heavy load picture according to the boosted clock voltage threshold.

[0108] In the embodiment, the charging time (and the compensated charging time) of the horizontal alternating bright black picture is made consistent with the ideal charging time by the boosted clock voltage threshold Vout, so as to eliminate the timing delay of the timing signal caused by the RC load, effectively suppress the color deviation phenomenon of the black level brightness rising and the white level brightness attenuating caused by the RC load difference, and further significantly improve the face uniformity of the super large size screen picture display.

[0109] Further, in some possible embodiments, the charging compensation module 30 includes a gate voltage detection unit 31 and a voltage compensation unit 32, and the step S20 of controlling the charging compensation module 30 to perform charging compensation according to the clock signal can further include steps A10 to A20.

[0110] Step A10: controlling the gate voltage detection unit 31 to collect the right side trace voltage, the middle trace voltage and the left side trace voltage of each gate trace line row by row when the clock signal is collected, and determining the voltage detection average value according to the right side trace voltage, the middle trace voltage and the left side trace voltage of each gate trace line.

[0111] In the embodiment, through the electrical connection between the gate voltage detection unit 31 and the compensation trigger module 20, the compensation trigger module 20 responds to the level trigger signal during the heavy load picture, and outputs the clock signal to the voltage detection unit 31. The voltage detection unit 31 starts a voltage detection period in response to the rising edge or the falling edge of the clock signal. During the voltage detection period, the gate voltage detection unit 31 performs row-by-row scanning and voltage collection operation on a corresponding number of gate trace lines according to a preset detection number set by the user. The preset detection number is a number of gate trace lines set by the user according to the actual application scenario (such as the panel size, the process fluctuation range or the real-time requirement), and can be specifically configured to detect 1, 2 or N (N≥3) gate trace lines, so that the gate voltage detection unit 31 can achieve the best balance between detection accuracy and processing efficiency to meet the optimization requirements in different application scenarios.

[0112] Specifically, for each selected gate trace line, the voltage detection unit 31 synchronously collects the voltage values at three specific positions on the gate trace line through the built-in multiplexer and analog-to-digital converter circuit. One is the voltage at the left end of the gate trace line, defined as the left side trace voltage (i.e. VL1, VL2, VL3, VL4, … and VLn as shown in the figure). Figure 6 The other is the voltage near the geometric midpoint of the gate trace line, defined as the middle trace voltage (i.e. VM1, VM2, VM3, VM4, … and VMn as shown in the figure). Figure 6V_m1, V_m2, V_m3, V_m4, …, and V_mn) shown in the figure; the third is the voltage at the starting point of the right end of the gate wire, defined as the right wire voltage (i.e. Figure 6 Vr1, Vr2, Vr3, Vr4, …, and Vrn) shown in the figure.

[0113] After completing the voltage collection on the preset number of gate wires, the data processing chip of the gate voltage detection unit 31 processes the voltage data of each gate wire. Specifically, for a single gate wire i (i = 1, 2, 3, …, n), first calculate the voltage difference between the left and right wire voltages and the middle wire voltage, i.e. the voltage difference (VLi-V_mi) between the left wire voltage VL i and the middle wire voltage V_mi, and the voltage difference (Vri-V_mi) between the right wire voltage Vri and the middle wire voltage V_mi; Next, the arithmetic mean between the calculated voltage difference (VLi-V_mi) and the voltage difference (Vri-V_mi) is taken as the wire pressure difference average of the gate wire i; Subsequently, the gate voltage detection unit 31 sends data packets carrying the wire pressure difference average to the picture detection module 10 through a serial or parallel communication interface, and processes the wire pressure difference average of all gate wires (i.e. the preset number of gate wires) through the picture detection module 10. The mean value processing can accurately obtain a voltage detection mean value excluding the process deviation of the gate wire; Subsequently, the clock signal carrying the voltage detection mean value is sent to the voltage compensation unit 32 through the second signal terminal of the picture detection module 10, so that the voltage compensation unit 32 can perform voltage boosting processing on the voltage detection mean value according to the preset feedback voltage boosting algorithm, so that the voltage detection mean value after voltage boosting can compensate for the charging time deviation caused by the wire impedance difference, so that the charging time (and the compensated charging time) of the horizontal alternating bright black picture is consistent with the ideal charging time. Not only effectively eliminates the local error that may be introduced by the traditional single-point detection, but also adapts to the RC load difference of different regions (especially the middle and edges of large-size panels), significantly improves the full-screen charging uniformity, and finally realizes the display quality problem of color deviation, brightness unevenness, etc. from the signal source, especially suitable for large-size display panel under heavy load picture.

[0114] It should be noted that if further improvement of data accuracy is required, the middle wire voltage V_mi of the gate wire i (i = 1, 2, 3, …, n) can be divided into voltage V_mri and voltage V_mLi, wherein the voltage V_mLi refers to the voltage value from the left end of the gate wire i to its geometric midpoint, and the voltage V_mri refers to the voltage value from the right end of the gate wire i to its geometric midpoint.

[0115] In a specific embodiment, when the preset detection number is 1, the gate voltage detection unit 31 only detects a single representative gate trace i (i=A) (e.g. Figure 8 Gate traces in the center area of ​​the panel shown, critical gate traces determined based on historical data, or Figure 8 The gate line at the farthest end of the driver chip represented by the black rectangle column shown in the figure) performs the above-mentioned voltage acquisition and line average processing process. The gate voltage detection unit 31 has the fastest detection speed when the preset detection number is 1, and the system resource usage is the lowest. It is suitable for scenes with extremely high real-time requirements and good panel uniformity (i.e., small-size display panel scenes, such as smartphones, smart watches, and portable device screens, etc.). For example, refer to Figure 8 When the gate voltage detection unit 31 locates the gate line i (i=A) according to the preset row scanning sequence, it synchronously collects four key voltage values ​​on the gate line i (i=A), namely, the voltage VLA at the left end starting point of the line, the voltage V_mLA at the midpoint of the left half of the line, the voltage V_mrA at the midpoint of the right half of the line, and the voltage VrA at the right end starting point of the line; then, the voltage difference (VLA-V_mLA) and the voltage difference (VrA-V_mrA) are calculated respectively; then, the two voltage difference values ​​are arithmetic averaged to output a more accurate line voltage difference average value [(VLA-V_mLA)+(VrA-V_mrA)] / 2 of the gate line i (i=A); and this line voltage difference average value [(VLA-V_mLA)+(VrA-V_mrA)] / 2 is used as the voltage detection average value of the gate line i (i=A).

[0116] In order to improve the detection accuracy, the data detection amount can be increased, so the number of gate lines to be detected can be increased, such as increasing the number of gate lines to be detected to N, where N is greater than or equal to 2 and is a natural number.

[0117] In a preferred embodiment, when the number of detection gate lines is preset to 2, refer to Figure 9 , due to being far away from the driver chip ( Figure 9The gate lines on the side far away from the driving chip usually have the longest transmission path and the largest RC load, and the voltage decay and signal delay phenomenon is most significant. The gate voltage detection unit 31 detects the voltage of the gate lines i (i = 1, 2) on the side far away from the driving chip, that is, the voltage detection of the gate voltage detection unit 31 with a preset detection number of 2 is applicable to the medium-sized display panel scenario (such as tablet computers, notebook computers, and vehicle-mounted display screens, etc.). For example, the gate voltage detection unit 31 collects four key voltage values (i.e. voltage VL1, voltage V_mL1, voltage V_mr1, and voltage Vr1) on the gate line i (i = 1) and four key voltage values (i.e. voltage VL2, voltage V_mL2, voltage V_mr2, and voltage Vr2) on the gate line i (i = 2) according to the preset row scanning; then, the voltage detection average of the gate lines i (i = 1, 2) is calculated according to the four key voltage values on the gate line i (i = 1) and the four key voltage values on the gate line i (i = 2).

[0118] In addition, it should be noted that the expression of the voltage detection average of the gate lines i (i = 1, 2) is:

[0119]

[0120] In a preferred embodiment, in order to further improve the detection accuracy, the number of gate line detections is further increased, and the detection number is set to N, and N is greater than 2. When the preset detection number is N (N = n), referring to Figure 10 Since the gate lines i (i = 1, 2) on the side far away from the driving chip Figure 10The gate lines on the side far from the driving chip generally have the longest transmission path and the largest RC load, and the voltage attenuation and signal delay phenomenon is most significant. That is, the N (N=n) gate lines farthest from the driving chip are selected as the preset number of gate lines for voltage detection, and the gate voltage detection unit 31 performs voltage detection on the gate lines i (i=1, 2, 3…n) far from the driving chip. That is, when the preset number of gate lines for voltage detection is N, the voltage detection of the gate voltage detection unit 31 is applicable to a display scenario in which there is a certain fluctuation in the process or the RC load difference of different regions of the panel is more obvious (that is, a large-size, high-resolution display panel such as a high-end television, a commercial large screen, and an e-sports display, etc.). For a large-size, medium-size, or high-resolution display panel, the voltage attenuation and signal delay are more significant in the middle and far ends, which causes more serious color cast. Therefore, multiple gate lines in the middle and far ends of the panel can be detected to obtain data. Of course, for the RC load imbalance, voltage drop, or signal attenuation imbalance caused by the panel process, the display panel also has a color cast problem. Since the color cast does not necessarily occur in the middle and far ends, it can occur anywhere on the panel. Therefore, the positions of the multiple detected gate lines can be set at all positions of the display panel, or the positions of the multiple detected gate lines can be set according to the positions where the color cast is more likely to occur. The present application is not limited in this regard.

[0121] Specifically, for a single gate line i (i=1, 2, 3, …, n), first, the voltage difference between the voltages of the left and right side lines and the voltage of the middle line is calculated, that is, the voltage difference (VLi-V_mi) between the left side line voltage VLi and the middle line voltage V_mi, and the voltage difference (Vri-V_mi) between the right side line voltage Vri and the middle line voltage V_mi. Next, the arithmetic mean of the calculated voltage difference (VLi-V_mi) and the voltage difference (Vri-V_mi) is taken as the average voltage difference of the gate line i. Then, the data packet carrying the average voltage difference of each line is sent to the picture detection module 10 through the serial or parallel communication interface by the gate voltage detection unit 31, and the average voltage difference of the N gate lines is processed by the picture detection module 10 to obtain an accurate voltage detection mean value excluding the process deviation of the gate line. Based on the above principles and processes, the display panel completes the voltage detection of multiple gate lines through the driving module and the control module.

[0122] In addition, it should be noted that the expression of the voltage detection mean value of the gate line i (i=1, 2, 3…n) is:

[0123]

[0124] Wherein, n represents a preset detection number, and the more the preset detection number is, the more accurate the voltage detection average is. Specifically, the line voltage difference average of the n gate lines detected by the gate voltage detection unit 31 is transmitted to the picture detection module 10, so that the picture detection module 10 averages the line voltage difference average of the n gate lines to obtain a clock signal carrying the voltage detection average and then output to the internal voltage compensation unit 32 to increase the proportion data (i.e. resistance ratio) of the voltage detection average, and then output to the level conversion integrated chip 40 for real-time adjustment. Finally, the clock signal waveform after gain (i.e. the clock signal waveform carrying the voltage detection average after voltage increase) is output, so as to achieve the effect that the panels with different process effects reach the same charging time, eliminate the influence of the difference between the chips, and achieve the consistency of eliminating color cast.

[0125] Step A20: generating a clock signal carrying the voltage detection average according to the clock signal and the voltage detection average, and controlling the voltage compensation unit 32 to charge compensate the clock signal according to the voltage detection average.

[0126] In this embodiment, the voltage compensation unit 32 integrated in the level conversion integrated chip 40 increases the voltage detection average according to the preset feedback voltage increase algorithm, so that the voltage detection average after voltage increase can compensate for the charging time deviation caused by the difference in line impedance, so that the charging time (and the charging time after compensation) under the horizontal alternating bright and dark picture is consistent with the ideal charging time. Not only can it effectively eliminate the local error that may be introduced by the traditional single-point detection, but also can adapt to the RC load difference of different areas (especially the middle and edge of large-size panels), significantly improve the full-screen charging uniformity, and finally realize the solution of color cast, brightness unevenness and other display quality problems from the signal source. It is especially suitable for large-size display panels under heavy load pictures.

[0127] In summary, the compensation trigger module 20 and the picture detection module 10 are electrically connected in the present application, which can effectively eliminate the color cast problem of the large-size H-Line picture, can detect the H-Line picture, and through the voltage compensation unit 32 electrically connected with the compensation trigger module 20 Figure 3 The voltage compensation unit shown in the figure compensates the clock signal output by the compensation trigger module 20 based on the H-Line picture, and exits the compensation when it is not an H-line picture (i.e. normal picture), so as to prevent over-compensation for normal pictures. The level conversion integrated chip 40 integrated with the compensation trigger module 20 and the voltage compensation unit 32 can also achieve the effect that the panels with different process effects reach the same charging time, eliminate the influence of the difference between the chips, and achieve the consistency of eliminating color cast.

[0128] In addition, the present application also provides a display panel, which comprises the driving circuit of any one of the above-mentioned embodiments, and the driving circuit comprises a picture detection module, a compensation trigger module and a charging compensation module.

[0129] The display panel includes a display area and a non-display area surrounding the periphery of the display area, the display panel is fixedly provided with a plurality of parallelly arranged gate lines, the non-display area is provided with a gate voltage detection unit in the charging compensation module close to one side of the circuit board, the circuit board is fixedly provided with the picture detection module and a level conversion integrated chip, the compensation trigger module and a voltage compensation unit in the charging compensation module are integrally arranged in the level conversion integrated chip.

[0130] In addition, the application further provides a display device. Figure 11 , Figure 11 is a structural schematic diagram of a display device related to the embodiment scheme of the application. The display device of the embodiment of the application can be a device for running a local panel compensation method.

[0131] As shown in Figure 11 , the display device of the embodiment of the application can include a display panel or a processor 1001, for example, a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to realize the connection and communication between the components. The user interface 1003 can include a display screen (Display) and an input unit such as a keyboard (Keyboard). The optional user interface 1003 can further include a standard wired interface and a wireless interface. The network interface 1004 can optionally include a standard wired interface and a wireless interface (such as a Wi-Fi interface).

[0132] The memory 1005 is arranged on the main body of the display device, and the memory 1005 stores a program. When the program is executed by the processor 1001, corresponding operations are realized. The memory 1005 is also used to store parameters for use by the display device. The memory 1005 can be a high-speed RAM memory or a stable memory (non-volatile memory) such as a disk memory. The memory 1005 can also be an independent storage device from the aforementioned processor 1001.

[0133] Those skilled in the art can understand that Figure 11 the structure of the display device shown in the above description does not constitute a limitation on the display device, and can include more or fewer components than those shown, or combine certain components, or different component arrangements.

[0134] As shown in Figure 11 , the memory 1005 as a storage medium can include an operating system, a network communication module, a user interface module, and a panel compensation program.

[0135] In Figure 11In the display device shown, the processor 1001 can be configured to invoke a panel compensation program stored in the memory 1005 and perform the steps of the panel compensation method as described above.

[0136] It should be noted that, in this document, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or system that includes the element.

[0137] The above-mentioned sequence numbers of the embodiments of the present application are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0138] From the above description of the embodiments, one skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software and necessary general hardware platforms, and of course, they can also be implemented by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium such as the above-mentioned ROM / RAM, magnetic disc, or optical disc, and includes a number of instructions for causing a display device (which can be a mobile phone, computer, server, or network device) to execute the methods described in the various embodiments of the present application.

[0139] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A driving circuit for a display panel, characterized in that: The driving circuit includes: a picture detection module, the picture detection module being configured to detect a picture scene type of an input picture and determine a picture detection signal according to the picture scene type; a compensation trigger module, wherein a signal trigger end of the compensation trigger module is electrically connected to the first signal interface of the picture detection module, and the compensation trigger module is configured to receive a picture detection signal sent by the picture detection module and generate a clock signal according to the picture detection signal being a level trigger signal for reloading the picture; A charging compensation module, wherein the signal input end of the charging compensation module is electrically connected to the signal output end of the compensation trigger module, and the charging compensation module is configured to perform charging compensation according to the clock signal sent by the compensation trigger module.

2. The driving circuit according to claim 1, wherein: The charging compensation module includes a boost compensation unit; The non-inverting input terminal of the boost compensation unit constitutes the signal input terminal of the charging compensation module and is electrically connected to the signal output terminal of the compensation trigger module; The out-of-phase input terminal of the boost compensation unit is connected to the signal output terminal of the boost compensation unit.

3. The driving circuit according to claim 1, wherein: The driving circuit includes a level conversion integrated chip, the charging compensation module includes a gate voltage detection unit and a voltage compensation unit, and the compensation trigger module and the voltage compensation unit are integrated into the level conversion integrated chip; The clock signal terminal of the gate voltage detection unit constitutes the signal input terminal of the charging compensation module and is electrically connected to the signal output terminal of the compensation trigger module; The right voltage sampling end of the gate voltage detection unit is electrically connected to the right wiring end of each gate wiring, the left voltage sampling end of the gate voltage detection unit is electrically connected to the left wiring end of each gate wiring, and the detection output end of the gate voltage detection unit is electrically connected to the signal acquisition end of the image detection module; The second signal terminal of the image detection module is electrically connected to the voltage compensation unit.

4. The driving circuit according to claim 3, wherein: The gate voltage detection unit is configured to respond to a clock signal sent by the compensation trigger module, collect voltages row by row for a preset number of gate lines, obtain a left line voltage, a middle line voltage, and a right line voltage for each gate line, determine a voltage detection average value based on the right line voltage, the middle line voltage, and the left line voltage of each gate line, and transmit a clock signal carrying the voltage detection average value to the voltage compensation unit via the image detection module; The voltage compensation unit is configured to perform charge compensation on the clock signal according to the voltage detection mean value after receiving the clock signal carrying the voltage detection mean value.

5. The driving circuit according to claim 1, wherein: The compensation trigger module includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube and a sixth switch tube; The gate terminal of the first switching tube, the gate terminal of the third switching tube, and the first path terminal of the fifth switching tube are respectively connected to the power supply terminal, and the first path terminal of the first switching tube is electrically connected to the first path terminal of the third switching tube; The connection node where the first path end of the first switch tube is electrically connected to the first path end of the third switch tube constitutes the signal output end of the compensation trigger module, and is electrically connected to the signal input end of the charging compensation module; The second passage end of the first switch tube is electrically connected to the first passage end of the second switch tube, and the second passage end of the second switch tube is grounded; The gate terminal of the second switch tube constitutes a signal trigger terminal of the compensation trigger module and is electrically connected to the first signal interface of the image detection module, the gate terminal of the fifth switch tube, and the gate terminal of the sixth switch tube respectively; the second path terminal of the fifth switch tube is electrically connected to the first path terminal of the sixth switch tube, and the second path terminal of the sixth switch tube is grounded; The gate end of the fourth switch tube intersects with the connection node where the second path end of the fifth switch tube is electrically connected to the first path end of the sixth switch tube, the first path end of the fourth switch tube is electrically connected to the second path end of the third switch, and the second path end of the fourth switch tube is grounded.

6. A panel compensation method, characterized in that: The panel compensation method is applied to the driving circuit according to any one of claims 1 to 5, and the panel compensation method includes: After determining the scene type of the input picture, controlling the picture detection module to determine a picture detection signal according to the scene type of the picture; When the image detection signal is a level trigger signal of a heavy image, controlling the compensation trigger module to generate a clock signal according to the level trigger signal; The charging compensation module is controlled to perform charging compensation according to the clock signal.

7. The panel compensation method according to claim 6, wherein: The charging compensation module includes a boost compensation unit, and the step of controlling the charging compensation module to perform charging compensation according to the clock signal includes: determining a voltage gain multiple of the boost compensation unit, and controlling the charging compensation module to perform a voltage boost process on a clock voltage threshold of the clock signal according to the voltage gain multiple; The display panel is charged and compensated according to the boosted clock voltage threshold when the image is reloaded.

8. The panel compensation method according to claim 6, wherein: The charging compensation module includes a gate voltage detection unit and a voltage compensation unit. The step of controlling the charging compensation module to perform charging compensation according to the clock signal includes: Controlling the gate voltage detection unit to collect the right line voltage, the middle line voltage, and the left line voltage of each gate line row by row when a clock signal is collected, and determining a voltage detection average value according to the right line voltage, the middle line voltage, and the left line voltage of each gate line; A clock signal carrying the voltage detection mean value is generated according to the clock signal and the voltage detection mean value, and the voltage compensation unit is controlled to perform charge compensation on the clock signal according to the voltage detection mean value.

9. A display panel, characterized in that: The display panel comprises the driving circuit according to any one of claims 1 to 5, wherein the driving circuit comprises a picture detection module, a compensation trigger module and a charging compensation module; The display panel includes a display area and a non-display area surrounding the display area. The display panel is fixedly provided with multiple parallel gate lines. A gate voltage detection unit in the charging compensation module is provided on the side of the non-display area close to the circuit board. The picture detection module and the level conversion integrated chip are fixedly arranged on the circuit board. The compensation trigger module and the voltage compensation unit in the charging compensation module are integrated in the level conversion integrated chip.

10. A display device, characterized in that: The display device comprises the display panel according to claim 9; or, A memory, a processor, and a panel compensation program stored in the memory and executable on the processor, wherein the processor implements the steps of the panel compensation method according to any one of claims 6 to 8 when executing the panel compensation program.

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