Memory circuit and memory
By adopting a parallel storage sub-block structure and a shared row decoder in the DRAM storage circuit, the problem of insufficient integration and capacity of the storage circuit without changing the external size is solved, and higher storage capacity and reading accuracy are achieved.
Patent Information
- Application Number
- CN202510957946.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2021-09-13
- Publication Date
- 2025-10-17
AI Technical Summary
It is difficult to increase the integration and capacity of existing DRAM storage circuits without changing the external size, and there are problems with reading accuracy.
A side-by-side storage sub-block structure is adopted, in which the middle storage sub-block shares a row decoder with the adjacent sub-block, and the high-order byte and the low-order byte share a row decoder. The switching circuit and control unit are used to ensure reading accuracy, simplify circuit connection and shorten RC delay.
The capacity and reading accuracy of the storage circuit are improved without increasing the number of storage segments, the circuit design is simplified, the RC delay caused by the wire resistance is shortened, and the overall performance of the storage circuit is improved.
Smart Images
Figure CN120808833A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to the field of semiconductor, and particularly relate to a storage circuit and a memory. BACKGROUND
[0002] DRAM (Dynamic Random Access Memory) as a high-speed large-capacity data storage carrier, is an essential part of most electronic systems. The smallest storage unit in DRAM is composed of a capacitor and a transistor, and the operation mechanism of DRAM is divided into read and write. When reading, the bit line (BL) is first charged to half of the operating voltage (VDD / 2), and then the transistor is turned on through the word line (WL), so that the capacitor and the bit line share the charge. If the internal storage value of the capacitor is 1, the voltage of the bit line will be raised to higher than half of the operating voltage by charge sharing, and if the internal storage value of the capacitor is 0, the voltage of the bit line will be pulled down to lower than half of the operating voltage. After obtaining the voltage of the bit line, it needs to be amplified by an amplifier to determine the internal storage value of the capacitor. When writing, the transistor is turned on through the word line. If 1 needs to be written, the bit line voltage is raised to the operating voltage to store the corresponding charge in the capacitor, and if 0 needs to be written, the bit line voltage is lowered to a low level to discharge the charge in the capacitor. SUMMARY
[0003] Embodiments of the present application provide a storage circuit and a memory, which at least have advantages of improving the integration and capacity of the storage circuit without changing the external size.
[0004] According to some embodiments of the present application, the embodiments of the present application provide a storage circuit, comprising: a plurality of storage blocks, each of the storage blocks comprising a first storage sub-block, a second storage sub-block and a third storage sub-block arranged in sequence, the second storage sub-block comprising a first storage part and a second storage part, the first storage sub-block and the first storage part being used for storing high bytes, the second storage part and the third storage sub-block being used for storing low bytes, and the block selection addresses of different storage parts arranged side by side being different in the arrangement direction of the storage sub-blocks.
[0005] In addition, the number of storage segments in the first storage sub-block is the same as the number of storage segments in the third storage sub-block, and the number of storage segments in the first storage part is the same as the number of storage segments in the second storage part.
[0006] In addition, the sum of the number of storage segments of the first storage part and the second storage part is equal to the number of storage segments of the first storage sub-block.
[0007] In addition, the memory segment storing the high-order byte and the memory segment storing the low-order byte include the same number of word lines.
[0008] In addition, the first memory sub-block includes a third memory portion and a fourth memory portion, the third memory sub-block includes a fifth memory portion and a sixth memory portion, the third memory portion, the first memory portion and the fifth memory portion are arranged side by side, the fourth memory portion, the second memory portion and the sixth memory portion are arranged side by side, the third memory portion and the first memory portion include the same number of word lines, and the second memory portion and the sixth memory portion include the same number of word lines.
[0009] In addition, the memory circuit includes a first row decoder and a second row decoder, the first row decoder is located between the third memory portion and the first memory portion, the second row decoder is located between the fourth memory portion and the second memory portion, the first row decoder is configured to activate the word lines of the third memory portion, and the second row decoder is configured to activate the word lines of the fourth memory portion and the second memory portion.
[0010] In addition, the memory circuit further includes a first switch circuit, a second switch circuit and a third switch circuit, the first switch circuit is connected in series between the first row decoder and the third memory portion, the second switch circuit is connected in series between the second row decoder and the fourth memory portion, the third switch circuit is connected in series between the second row decoder and the second memory portion, the first switch circuit and the second switch circuit are configured to receive a first flag signal and turn on, the third switch circuit is configured to receive a second flag signal and turn on, the first flag signal represents reading a high-order byte, and the second flag signal represents reading a low-order byte.
[0011] In addition, the memory circuit further includes a sense amplifier configured to amplify a read signal of a bit line to form a first amplified signal, the sense amplifier includes a first sense amplifier, a second sense amplifier, a third sense amplifier and a fourth sense amplifier, the first sense amplifier is configured to amplify a read signal of a bit line in the first memory portion, the second sense amplifier is configured to amplify a read signal of a bit line in the second memory portion, the third sense amplifier is configured to amplify a read signal of a bit line in the third memory portion, and the fourth sense amplifier is configured to amplify a read signal of a bit line in the fourth memory portion; a first control unit and a second control unit, the first control unit is located between the first sense amplifier and the third sense amplifier, the second control unit is located between the second sense amplifier and the fourth sense amplifier, the first control unit is configured to control the third sense amplifier, and the second control unit is configured to control the fourth sense amplifier and the second sense amplifier.
[0012] In addition, the storage circuit further comprises a fourth switch circuit, a fifth switch circuit and a sixth switch circuit, the fourth switch circuit is connected with the first control unit and the third sense amplifier, the fifth switch circuit is connected with the second control unit and the fourth sense amplifier, the sixth switch circuit is connected with the second control unit and the second sense amplifier, the fifth switch circuit and the sixth switch circuit are used for receiving a first flag signal and being turned on, the fourth switch circuit is used for receiving a second flag signal and being turned on, the first flag signal represents reading a high byte, and the second flag signal represents reading a low byte.
[0013] In addition, the first control unit and the second control unit are located between the first storage sub-block and the second storage sub-block.
[0014] In addition, the storage circuit further comprises a third row decoder and a fourth row decoder, the third row decoder is located between the first storage unit and the fifth storage unit, the fourth row decoder is located between the second storage unit and the sixth storage unit, the third row decoder is used for activating word lines in the first storage unit and the fifth storage unit, and the fourth row decoder is used for activating word lines in the sixth storage unit.
[0015] In addition, the storage circuit further comprises a local input / output line, a main amplifier and a global input / output line, the local input / output line is used for transmitting a read signal amplified by a sense amplifier, and is recorded as a first amplified signal, the main amplifier is used for receiving and amplifying the first amplified signal to obtain a second amplified signal, and the main amplifier is further used for transmitting the second amplified signal to the global input / output line.
[0016] In addition, the local input / output line comprises a first local input / output line and a third local input / output line, the first local input / output line is connected with the first storage sub-block, the third local input / output line is connected with the third storage sub-block, the global input / output line comprises a high-bit global input / output line and a low-bit global input / output line, and the storage circuit further comprises a seventh switch circuit and an eighth switch circuit, the seventh switch circuit is used for connecting the first local input / output line and the high-bit global input / output line, and is used for receiving a first flag signal and being turned on, the first flag signal represents reading a high byte, and the eighth switch circuit is used for connecting the third local input / output line and the low-bit global input / output line, and is used for receiving a second flag signal and being turned on, the second flag signal represents reading a low byte.
[0017] In addition, the local input / output line also includes a second local input / output line, which is connected to the second storage sub-block; and also includes: a selector, one end of which is connected to the second local input / output line, for receiving the first flag signal or the second flag signal, and if the first flag signal is received, the second local input / output line is connected to the high-order global input / output line; if the second flag signal is received, the second local input / output line is connected to the low-order global input / output line.
[0018] According to some embodiments of the present application, another aspect of the present application further provides a memory comprising the above-mentioned storage circuit.
[0019] The technical solution provided by the embodiments of the present application has at least the following advantages: In the above technical solution, three storage sub-blocks are set side by side, and the storage sub-block in the middle position can share the same row decoder with the adjacent storage sub-block, without introducing an additional row decoder, which is beneficial to increasing the capacity of the storage block with a smaller circuit area without increasing the number of storage segments in the storage sub-block; in addition, the second storage sub-block in the middle position is used to store high bytes and low bytes, and the storage sub-blocks on both sides are used to store high bytes or low bytes. In this way, the storage segment storing the high bytes and the storage segment storing the low bytes can share the same row decoder, avoiding the activation of the wrong word line by the shared row decoder, which is beneficial to improving the reading accuracy of the storage circuit; in addition, in the arrangement direction of the storage sub-blocks, the block selection addresses of different side-by-side storage parts are different, which is beneficial to further avoid the activation of the wrong word line by the shared row decoder. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] One or more embodiments are exemplarily described by the pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.
[0021] Figures 1 to 4 A schematic diagram of the structure of the storage circuit provided in an embodiment of the present application. DETAILED DESCRIPTION
[0022] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.
[0023] Figures 1 to 4 A schematic diagram of the structure of the storage circuit provided in an embodiment of the present application.
[0024] Reference Figures 1 to 2 The storage circuit includes a plurality of storage blocks 10, each of which includes a first storage sub-block 11, a second storage sub-block 12 and a third storage sub-block 13 arranged in sequence, the second storage sub-block 12 includes a first storage part 121 and a second storage part 122, the first storage sub-block 11 and the first storage part 121 are used to store high bytes, the second storage part 122 and the third storage sub-block 13 are used to store low bytes, and the block selection addresses of different storage parts arranged side by side are different in the arrangement direction of the storage sub-blocks.
[0025] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings.
[0026] Reference Figure 1 The storage circuit can include a plurality of storage blocks 10, and as the capacity of the storage circuit changes, the capacity, number and arrangement of the storage blocks 10 will also change accordingly. Taking the capacity of the storage circuit as 16G and the capacity of each storage block 10 as 1G as an example, the storage circuit includes 16 storage blocks 10 (BK0~BK15), and the arrangement of the storage blocks 10 is 4×4. In addition, each storage block has a corresponding row decoder (not shown) and a column decoder YDEC, the row decoder is used to receive a row address signal and activate a corresponding word line, and the column decoder is used to obtain a read signal of a bit line of a specific column address, which is amplified by a sense amplifier and then input into a local input / output line.
[0027] It should be noted that the storage circuit structure provided by the embodiments of the present application is not only suitable for capacities of 16G and below, but also suitable for capacities of 16G and above. Among them, the same peripheral circuit region 14 is shared by adjacent storage blocks 10, and the peripheral circuit region 14 can include a decoding circuit, the decoding circuit is connected to a word line driver, and the word line driver is used to drive the word line in the storage block 10. In the case of 4×4 arrangement, two peripheral circuit regions 14 are provided for each row; in addition, the peripheral circuit region 14 and the column decoder YEDC are located on different sides of the storage block 10.
[0028] In addition, the storage circuit also includes an intersection area circuit XP located between four adjacent storage blocks 10 (for example, BK0, BK1, BK4 and BK5). The intersection area circuit XP may be provided with structures such as a pull-up drive circuit, a local balancing circuit, an input-output balancing circuit, a pre-charging circuit and a balancing drive circuit. The pull-up drive circuit is used to provide an operating voltage for the first electrode line to activate the sense amplifier; the local balancing circuit is connected in series between the first electrode line and the second electrode line, and is used to connect or disconnect the first electrode line and the second electrode line. If the first electrode line and the second electrode line are connected, the sense amplifier cannot be activated; the input-output balancing circuit and the pre-charging circuit are connected in series between the bit line pair, the pre-charging circuit is used to raise the voltage of the bit line pair to half of the operating voltage, the input-output balancing circuit is used to share the charge of the bit line pair, and the balancing drive circuit is used to activate the input-output balancing circuit and the pre-charging circuit.
[0029] In some embodiments, the number of storage segments in the first storage sub-block 11 is the same as the number of storage segments in the third storage sub-block 13, and the number of storage segments in the first storage unit 121 is the same as the number of storage segments in the second storage unit 122. This helps ensure that the number of storage segments storing high-order bytes is equal to the number of storage segments storing low-order bytes, ensuring that the storage blocks can effectively store high-order bytes and low-order bytes of the same number of bits, avoiding redundancy in the storage segments storing high-order bytes or low-order bytes, and improving the utilization of the storage blocks.
[0030] by Figure 2 In the illustrated embodiment, the first storage sub-block 11 includes 32 storage segments (SEG0U to SEG31U corresponding to 1U to 32U), where "U" indicates that the storage segment stores high-order bytes. The third storage sub-block 13 also includes 32 storage segments (SEG16L to SEG47L corresponding to 17L to 48L), where "L" indicates that the storage segment stores low-order bytes. Correspondingly, the first storage unit 121 includes 16 storage segments (SEG0L to SEG15L corresponding to 1L to 16L), and the second storage unit 122 also includes 16 storage segments (SEG32U to SEG47U corresponding to 33U to 48U), where "U" indicates that the storage segment stores high-order bytes. It should be noted that as the capacity of the storage circuit and storage block changes, the number of storage segments contained in each storage sub-block will also change. For example, if the capacity of each storage block doubles, the number of storage segments contained in each storage sub-block will double.
[0031] Furthermore, if the number of high-order byte memory segments and low-order byte memory segments is the same, and if each memory segment contains the same number of word lines, then the high-order byte memory segment and the low-order byte memory segment contain the same number of word lines. It should be noted that the number of memory cells contained in a memory segment may vary in different memories. In some embodiments, the sum of the number of memory segments in the first memory unit 121 and the second memory unit 122 is equal to the number of memory segments in the first memory sub-block 11. In other words, the first memory sub-block 11, the second memory sub-block 12, and the third memory sub-block 13 have the same number of memory segments.
[0032] like Figure 2 As shown, the first storage sub-block 11, the second storage sub-block 12 and the third storage sub-block 13 each include 48 storage segments; in other embodiments, the sum of the number of storage segments in the first storage unit 121 and the second storage unit 122 can also be smaller than the number of storage segments in the first storage sub-block 11, so that all storage segments in the second storage sub-block 12 can also share a row decoder with the first storage sub-block 11 or the third storage sub-block 13.
[0033] In some embodiments, the logical starting address of the storage segment in the first storage sub-block 11, the starting logical address of the storage segment in the second storage sub-block 12, and the starting logical address of the third storage sub-block 13 are sequentially extended, wherein the starting logical address of the storage segment in the second storage unit 122 is later than the starting logical address of the storage segment in the first storage unit 121. Since the physical address of a storage unit in a storage segment = the starting address of the segment + the offset within the segment, the physical address of the storage unit in the second storage unit 122 is later than the physical address of the storage unit in the first storage unit 121. The physical addresses of the storage units in the first storage sub-block 11 and the second storage unit 122 are discontinuous. Correspondingly, the physical addresses of the storage units in the first storage unit 121 and the third storage sub-block 13 are discontinuous.
[0034] In some embodiments, the first storage sub-block 11 includes a third storage unit 111 and a fourth storage unit 112, the third storage sub-block 13 includes a fifth storage unit 131 and a sixth storage unit 132, the third storage unit 111, the first storage unit 121 and the fifth storage unit 131 are arranged side by side, wherein the fourth storage unit 112, the second storage unit 122 and the sixth storage unit 132 are arranged side by side, wherein the first storage unit 121 and the third storage unit 111 include the same number of word lines, and the second storage unit 122 and the sixth storage unit 132 include the same number of word lines, so that the first storage unit 121 and the second storage unit 122 share the same row decoder with the storage units in the adjacent storage sub-blocks.
[0035] Further, the number of word lines in the first storage unit 121 is equal to the number of word lines in the second storage unit 122, the number of word lines in the first storage unit 121, the third storage unit 111 and the fifth storage unit 131 is the same, and the number of word lines in the second storage unit 122, the fourth storage unit 112 and the sixth storage unit 132 is the same.
[0036] In some embodiments, with reference to Figure 3 , the storage circuit comprises: a first row decoder 21 and a second row decoder 22, the first row decoder 21 is located between the third storage unit 111 and the first storage unit 121, and the second row decoder 22 is located between the fourth storage unit 112 and the second storage unit 122, the first row decoder 21 is used to activate the word lines in the third storage unit 111 and the first storage unit 121, and the second row decoder 22 is used to activate the word lines in the fourth storage unit 112. Using the same row decoder to activate the word lines in different storage sub-blocks is conducive to saving circuit area and simplifying the storage circuit; in addition, arranging the shared row decoder between the corresponding two storage units is conducive to shortening the circuit connection distance, avoiding long RC delay caused by large wire resistance, and improving the reading speed of the storage circuit; at the same time, arranging the two storage units sharing the row decoder to store high bytes and low bytes respectively is conducive to avoiding activating the wrong word line after the row decoder receives the row address.
[0037] It should be noted that the logical address of the storage segment is composed of the most significant bit and the block selection address, and the most significant bit is the leftmost bit of the row address RA <n>, the block select address is the other bits of the row address RA <n-1:0>,refer to Figure 2 The most significant bit (MSB) of the storage segment storing the high-order byte is 0, and the most significant bit of the storage segment storing the low-order byte is 1. Different storage blocks storing bytes of the same type (high-order byte or low-order byte) have different block select addresses, such as SEG0~SEG47. Different storage blocks storing bytes of different types may have the same block select addresses, such as SEG0~SEG47.
[0038] In some embodiments, the storage circuit further includes: a first switch circuit 31, a second switch circuit 32, and a third switch circuit 33. The first switch circuit 31 connects the first row decoder 21 and the third storage unit 111, the second switch circuit 32 connects the second row decoder 22 and the fourth storage unit 112, and the third switch circuit 33 connects the first row decoder 21 and the first storage unit 121. The first switch circuit 31 and the second switch circuit 32 are configured to receive a first flag signal 41 and turn on, and the third switch circuit is configured to receive a second flag signal 42 and turn on. The first flag signal 41 indicates reading a high-order byte, and the second flag signal 42 indicates reading a low-order byte. Connecting the switch circuit in series between the row decoder and the storage unit to connect the row decoder and the storage unit storing the byte when reading the corresponding byte helps further prevent the row decoder from activating the wrong word line and improve the accuracy of data read by the storage circuit.
[0039] In some embodiments, the storage circuit further includes a third row decoder 23 and a fourth row decoder 24. The third row decoder 23 is located between the fifth storage section 131 and the first storage section 121, and the fourth row decoder 24 is located between the sixth storage section 132 and the second storage section 122. The third row decoder 23 is used to activate the word line of the fifth storage section 131, and the fourth row decoder 24 is used to activate the word lines of the second storage section 122 and the sixth storage section 132. The switch circuit connected in series between the third row decoder 23 and the fifth storage section 131 is turned on upon receiving the second flag signal 42, the switch circuit connected in series between the fourth row decoder 24 and the sixth storage section 132 is turned on upon receiving the second flag signal 42, and the switch circuit connected in series between the fourth row decoder 24 and the second storage section 122 is turned on upon receiving the first flag signal 41. Similar to the first row decoder 21 and its corresponding switch circuit, the provision of the fourth row decoder 24 facilitates circuit simplification and improves the read rate of the storage circuit. Furthermore, the first row decoder 21 and the fourth row decoder 24, which have similar connections and functions, are provided simultaneously.
[0040] Correspondingly, the storage circuit further comprises: a first sense amplifier 141, a second sense amplifier 142, a third sense amplifier 43, and a fourth sense amplifier 44, the first sense amplifier 141 is used for amplifying the readout signal of the bit line in the first storage unit 121, the second sense amplifier 142 is used for amplifying the readout signal of the bit line in the second storage unit 122, the third sense amplifier 43 is used for amplifying the readout signal of the bit line in the third storage unit 111, and the fourth sense amplifier 44 is used for amplifying the readout signal of the bit line in the fourth storage unit 112; a first control unit 51 and a second control unit 52, the first control unit 51 is located between the first sense amplifier 141 and the third sense amplifier 43, the second control unit 52 is located between the second sense amplifier 142 and the fourth sense amplifier 44, the first control unit 51 is used for controlling the first sense amplifier 141 and the third sense amplifier, and the second control unit 52 is used for controlling the fourth sense amplifier 44. Similar to the setting of the first row decoder 21, the first control unit 51 is set to be connected to and control two adjacent sense amplifiers, which is conducive to simplifying the circuit and shortening the RC delay; at the same time, the connection relationship between the first control unit 51 and the first row decoder 21 and the respective adjacent components is similar, which is conducive to simplifying the layout design of the storage circuit.
[0041] Among them, the first row decoder 21 and the first control unit 51 are located between the first storage unit 121 and the third storage unit 111 and the corresponding sense amplifiers, and the first control unit 51 and the second control unit 52 are located between the first storage sub-block 11 and the second storage sub-block 12.
[0042] In some embodiments, the storage circuit further comprises: a fourth switch circuit 34, a fifth switch circuit 35, and a sixth switch circuit 36, the fourth switch circuit 34 is connected to the first control unit 51 and the first sense amplifier 141, the fifth switch circuit 35 is connected to the first control unit 51 and the third sense amplifier 43, the sixth switch circuit 36 is connected to the second control unit 52 and the fourth sense amplifier 44, the fifth switch circuit 35 and the sixth switch circuit 36 are used for receiving the first flag signal 41 and being turned on, the fourth switch circuit 34 is used for receiving the second flag signal 42 and being turned on, the first flag signal 41 is used for indicating reading a high byte, and the second flag signal 42 indicates reading a low byte. As described above, by setting the switch circuit, the first control unit 51 is connected to the corresponding sense amplifier at the corresponding time, which is conducive to ensuring that the first control unit 51 is ready to control the corresponding sense amplifier, and then accurately amplifying the tiny readout signal on the corresponding bit line, and ensuring the accuracy of data reading of the storage circuit.
[0043] In some embodiments, the storage circuit further comprises a third row decoder 23 and a fourth row decoder 24, the third row decoder 23 is located between the first storage unit 121 and the fifth storage unit 131, and the fourth row decoder 24 is located between the second storage unit 122 and the sixth storage unit 132, the third row decoder 23 is used to activate the word line in the fifth storage unit 131, and the fourth row decoder 24 is used to activate the word line in the second storage unit 122 and the sixth storage unit 132.
[0044] Correspondingly, the storage circuit further comprises a fifth sense amplifier 45 and a sixth sense amplifier 46, the fifth sense amplifier 45 is used to amplify the readout signal of the bit line in the fifth storage unit 131, and the sixth sense amplifier 46 is used to amplify the readout signal of the bit line in the sixth storage unit 132; in addition, the storage circuit further comprises a third control unit 53 and a fourth control unit 54, the third control unit 53 is connected with the fifth sense amplifier 45 through a corresponding switch circuit, so as to adjust the fifth sense amplifier 45 when the storage circuit reads the low byte, and the fourth control unit 54 is connected with the second sense amplifier 142 and the sixth sense amplifier 46 through different switch circuits, so as to adjust the second sense amplifier 142 when reading the high byte and adjust the sixth sense amplifier 46 when reading the low byte.
[0045] In some embodiments, referring to Figure 4 , the storage circuit further comprises a local input and output line LIO, a main amplifier 60 and a global input and output line GIO, the local input and output line LIO is used to transmit the readout signal amplified by the sense amplifier, the main amplifier 60 is used to receive and amplify the readout signal output by the local input and output line LIO, and transmit the readout signal amplified again to the global input and output line GIO.
[0046] It can be understood that each local input and output line LIO corresponds to a bit line, the number of bit lines in the storage block 10 is the same as the number of columns of the storage array in the storage block 10, that is, the more the number of columns of the storage array, the more the number of bit lines in the storage block 10; similarly, the number of bit lines in each storage sub-block is the same as the number of columns of the storage array in the storage sub-block. In addition, each local input and output line LIO corresponds to a main amplifier 60, the main amplifier 60 is used to receive and amplify the readout signal output by the corresponding local input and output line LIO, and according to the type of byte stored by the storage sub-block, the main amplifier 60 is connected with the corresponding global input and output line GIO.
[0047] In multi-byte data, the bytes are divided into high bytes and low bytes, in order to ensure the accuracy of data reading, the high bytes are transmitted by the high global input / output line UGIO and the low bytes are transmitted by the low global input / output line LGIO. In some embodiments, the first storage sub-block 11, the second storage sub-block 12 and the third storage sub-block 13 each contain 128 bit lines, and the global input / output line GIO is used to transmit 16 bytes of data, of which the first 8 bytes are high bytes and the last 8 bytes are low bytes. Since each byte is 8 bits, the global input / output line GIO is used to transmit 128 bits of data.
[0048] In the embodiment, the local input / output line LIO includes the first local input / output line LIO1 and the third local input / output line LIO3, the first local input / output line LIO1 is connected with the first storage sub-block 11, and the third local input / output line LIO3 is connected with the third storage sub-block 13. The global input / output line GIO includes the high global input / output line UGIO and the low global input / output line LGIO. In addition, the storage circuit further includes: a seventh switch circuit 37, which is used to connect the first local input / output line LIO1 and the high global input / output line UGIO, and is used to receive the first flag signal 41 and turn on; and an eighth switch circuit 38, which is used to connect the third local input / output line LIO3 and the low global input / output line LGIO, and is used to receive the second flag signal 42 and turn on.
[0049] In addition, the local input / output line LIO further includes the second local input / output line LIO2, which is connected with the second storage sub-block 12. The storage circuit further includes: a selector 39, one end of which is connected with the second local input / output line LIO2, and is used to receive the first flag signal 41 or the second flag signal 42. If the first flag signal 41 is received, the second local input / output line LIO2 is connected with the high global input / output line UGIO. If the second flag signal 42 is received, the second local input / output line LIO2 is connected with the low global input / output line LGIO.
[0050] In some embodiments, a main input / output line and a cross-point region circuit XP are further connected in series between the local input / output line LIO and the main amplifier 60. After being amplified by the sense amplifier and activated by the column selection signal, the readout signal of the bit line is sequentially transmitted to the local input / output line LIO, the cross-point region circuit, the main input / output line, and the main amplifier 60. After the main amplifier 60 performs a second amplification on the readout signal of the bit line, the readout signal is transmitted to the data segment sub through a receiving amplifier, a multiplexer, and an output buffer. The receiving amplifier is activated by a corresponding start signal to amplify the tiny signal generated on the global input / output line. The multiplexer is a parallel-serial conversion circuit that sequentially transmits the multiple pieces of stored information read from the memory array to the output buffer. The output order is controlled by a corresponding group of data output start signals.
[0051] Correspondingly, in the write operation, the data signal to be stored is input from the data terminal and transmitted to the input buffer together with the data input start signal. The data in the input buffer is transmitted to the word line driver through the demultiplexer, the global write driver, and the global input / output line GIO. Correspondingly, the demultiplexer is a circuit that serially-parallelly converts the data information input in time sequence. The correspondence between the input data signal and the global input / output line GIO is controlled by the data input start signal, so as to be consistent with the output order in the read operation.
[0052] Specifically, the selector 39 can include a first switch 391 and a second switch 392. One end of each of the first switch 391 and the second switch 392 is connected with the main amplifier 60, for receiving the readout signal amplified again. The other end of the first switch 391 is connected with the high-bit global input / output line UGIO, for receiving the first flag 41 and being turned on. The other end of the second switch 392 is connected with the low-bit input / output line LGIO, for receiving the flag signal 42 and being turned on.
[0053] In the embodiment, three storage sub-blocks are arranged side by side. The storage sub-block in the middle position can share the same row decoder with the adjacent storage sub-blocks, without introducing additional row decoders, which is beneficial to increasing the capacity of the storage block with a smaller circuit area without increasing the number of storage segments in the storage sub-block. In addition, the second storage sub-block in the middle position is used to store high-bit bytes and low-bit bytes, and the storage sub-blocks on both sides are used to store high-bit bytes or low-bit bytes. In this way, the storage segments for storing high-bit bytes and the storage segments for storing low-bit bytes can share the same row decoder, which avoids the activation of the shared row decoder on the wrong word line, and is beneficial to improving the reading accuracy of the storage circuit.
[0054] The embodiment of the present application further provides a memory comprising the memory circuit.
[0055] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be limited by the scope defined in the claims. < / n>
Claims
1. A storage circuit, characterized in that: include: A plurality of storage blocks, each of the storage blocks includes a first storage sub-block, a second storage sub-block and a third storage sub-block arranged in sequence, the second storage sub-block includes a first storage part and a second storage part; the first storage sub-block, the first storage part, the second storage part and the third storage sub-block each include a plurality of storage segments, the logical addresses of the storage segments consist of a most significant bit and a block selection address; the most significant bits of the logical addresses of the storage segments of the first storage sub-block and the first storage part are the same, and the most significant bits of the logical addresses of the storage segments of the second storage part and the third storage sub-block are the same; in the arrangement direction of the storage sub-blocks, the block selection addresses of the storage segments in different side-by-side storage sub-blocks are different.
2. The storage circuit according to claim 1, wherein: The number of storage segments in the first storage sub-block is the same as the number of storage segments in the third storage sub-block, and the number of storage segments in the first storage part is the same as the number of storage segments in the second storage part.
3. The storage circuit according to claim 2, wherein: The sum of the number of storage segments of the first storage part and the second storage part is equal to the number of storage segments of the first storage sub-block.
4. The storage circuit according to claim 2, wherein: The memory segments of the first memory sub-block and the first memory unit include the same number of word lines as the memory segments of the second memory unit and the third memory sub-block.
5. The storage circuit according to claim 1, wherein: The first storage sub-block includes a third storage unit and a fourth storage unit, the third storage sub-block includes a fifth storage unit and a sixth storage unit, the third storage unit, the first storage unit and the fifth storage unit are arranged side by side, the fourth storage unit, the second storage unit and the sixth storage unit are arranged side by side, the third storage unit and the first storage unit include the same number of word lines, and the second storage unit and the sixth storage unit include the same number of word lines.
6. The storage circuit according to claim 5, wherein: include: A first row decoder and a second row decoder, wherein the first row decoder is located between the third storage unit and the first storage unit, and the second row decoder is located between the fourth storage unit and the second storage unit, the first row decoder is used to activate the word line of the third storage unit, and the second row decoder is used to activate the word lines of the fourth storage unit and the second storage unit.
7. The storage circuit according to claim 6, wherein: Also includes: A first switch circuit, a second switch circuit and a third switch circuit, the first switch circuit is connected in series between the first row decoder and the third storage unit, the second switch circuit is connected in series between the second row decoder and the fourth storage unit, the third switch circuit is connected in series between the second row decoder and the second storage unit, the first switch circuit and the second switch circuit are used to receive a first flag signal and be turned on, the third switch circuit is used to receive a second flag signal and be turned on, the first flag signal represents reading data in the first storage sub-block and the first storage unit, and the second flag signal represents reading data in the second storage unit and the third storage sub-block.
8. The storage circuit according to claim 5, wherein: Also includes: a sense amplifier configured to amplify a read signal of a bit line to form a first amplified signal, the sense amplifier comprising a first sense amplifier, a second sense amplifier, a third sense amplifier, and a fourth sense amplifier, the first sense amplifier configured to amplify a read signal of a bit line in the first storage section, the second sense amplifier configured to amplify a read signal of a bit line in the second storage section, the third sense amplifier configured to amplify a read signal of a bit line in the third storage section, and the fourth sense amplifier configured to amplify a read signal of a bit line in the fourth storage section; a first control unit and a second control unit, wherein the first control unit is located between the first sense amplifier and the third sense amplifier, and the second control unit is located between the second sense amplifier and the fourth sense amplifier, the first control unit is used to control the third sense amplifier, and the second control unit is used to control the fourth sense amplifier and the second sense amplifier.
9. The storage circuit according to claim 8, wherein: Also includes: a fourth switch circuit, a fifth switch circuit, and a sixth switch circuit, wherein the fourth switch circuit connects the first control unit and the third sense amplifier, the fifth switch circuit connects the second control unit and the fourth sense amplifier, and the sixth switch circuit connects the second control unit and the second sense amplifier. The fifth switch circuit and the sixth switch circuit are configured to receive a first flag signal and be turned on, and the fourth switch circuit is configured to receive a second flag signal and be turned on. The first flag signal indicates reading data from the first storage sub-block and the first storage unit, and the second flag signal indicates reading data from the second storage unit and the third storage sub-block.
10. The storage circuit according to claim 8, wherein: The first control unit and the second control unit are both located between the first storage sub-block and the second storage sub-block.
11. The storage circuit according to claim 5, wherein: include: a third row decoder and a fourth row decoder, the third row decoder is located between the first storage unit and the fifth storage unit, the fourth row decoder is located between the second storage unit and the sixth storage unit, the third row decoder is used to activate the word lines in the first storage unit and the fifth storage unit, and the fourth row decoder is used to activate the word lines in the sixth storage unit.
12. The storage circuit according to claim 1, wherein: Also includes: Local input / output lines, a main amplifier, and a global input / output line. The local input / output line is used to transmit the readout signal amplified by the sense amplifier, which is recorded as a first amplified signal. The main amplifier is used to receive and amplify the first amplified signal to obtain a second amplified signal. The main amplifier is also used to transmit the second amplified signal to the global input / output line.
13. The storage circuit according to claim 12, wherein: The local input / output lines include a first local input / output line and a third local input / output line, the first local input / output line is connected to the first storage sub-block, the third local input / output line is connected to the third storage sub-block, and the global input / output lines include a high-order global input / output line and a low-order global input / output line; and further include: a seventh switch circuit, configured to connect the first local input / output line and the high-order global input / output line, and to receive a first flag signal and be turned on, wherein the first flag signal indicates reading data from the first storage sub-block and the first storage unit; An eighth switch circuit is configured to connect the third local input / output line and the low-order global input / output line, and to receive a second flag signal and be turned on, wherein the second flag signal indicates reading data from the second storage unit and the third storage sub-block.
14. The storage circuit according to claim 13, wherein: The local input / output line further includes a second local input / output line, the second local input / output line being connected to the second storage sub-block; and further includes: A selector, one end of which is connected to the second local input / output line, and is used to receive the first flag signal or the second flag signal. If the first flag signal is received, the second local input / output line is connected to the high-order global input / output line; if the second flag signal is received, the second local input / output line is connected to the low-order global input / output line.
15. A memory, characterized in that: The storage circuit comprises the storage circuit according to any one of claims 1 to 14.