Spinning logic device and logic operation method

Abstract

The invention discloses a spin logic device and a logic operation method, and relates to the technical field of spin electronics, the spin logic device comprises a spin orbit moment channel layer, n magnetic tunnel junctions grown on the spin orbit moment channel layer and a peripheral control circuit, the peripheral control circuit applies control current and control voltage to the magnetic tunnel junctions, the method is used for regulating and controlling the magnetization direction of the magnetic tunnel junction. By utilizing the synergistic effect of a spin orbit moment technology and a voltage regulation magnetic anisotropy technology, the spin logic device realizes 16 kinds of logic operations of Boolean logic, an adder, a subtracter and a multiplier; wherein before logical operation, the initial resistance state of each magnetic tunnel junction is read to serve as logical input; during logical operation, different control currents and control voltages are applied to the magnetic tunnel junctions for regulation and control according to the type of the logical operation; and after the logic operation is finished, logic output is stored in a specified magnetic tunnel junction in situ in a resistance state form.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of spin electronics, and can also be used in the fields of memory-compute integration and non-volatile memory computing technology, and in particular relates to a spin logic device and a logic operation method. BACKGROUND

[0002] In recent years, the rapid development of information industries such as big data, cloud computing, the Internet of Things and artificial intelligence has brought about a large amount of data, and higher requirements have been put forward for the storage capacity and read-write speed of the memory in the computer system. However, as the size of semiconductor devices continues to shrink, quantum tunneling effects are increasingly evident in nanoscale transistor devices, leading to increasing leakage current and static power consumption. Magnetic random access memory (MRAM) based on spintronic devices has the advantages of non-volatility, low power consumption, radiation resistance, and unlimited high-speed read-write, and is expected to become a key technology to overcome the power bottleneck in the post-Moore era, and has attracted widespread attention from academia and industry.

[0003] Traditional computing systems use the von Neumann architecture of separation of storage and computation, and the speed of the storage unit is seriously lagging behind the logic unit, bringing about the problems of "power wall" and "memory wall", and it is difficult to meet the urgent demand for high-speed operation in high-computing scenarios. Memory-compute integration technology has emerged as the times require, aiming to break this dilemma. However, existing non-volatile Boolean logic and memory-compute integration technologies are difficult to achieve low-power, efficient and comprehensive Boolean logic operations and addition, subtraction and multiplication functions in the same structure, and have problems such as low integration, complex operation and poor scalability, which seriously restrict the performance improvement and actual use of the device.

[0004] This section is intended to provide background or context to the embodiments of the application recited in the claims. The description herein does not constitute admission that the prior art is prior art. SUMMARY

[0005] To solve at least one of the technical problems mentioned in the background section, the present application provides a spin logic device and a logic operation method, which is based on the magnetic tunnel junction structure of magnetic random access memory, and utilizes the synergistic effect of spin-orbit torque technology and voltage-controlled magnetic anisotropy technology to achieve an efficient, low-power, high-integration logic operation and memory integration solution.

[0006] In a first aspect, the present application provides a spin logic device, comprising a spin-orbit torque channel layer, n magnetic tunnel junctions grown on the spin-orbit torque channel layer, and a peripheral control circuit, wherein:

[0007] The peripheral control circuit applies a control current and a control voltage to the magnetic tunnel junction, the control current generates a spin-orbit torque effect in the spin-orbit torque channel layer, and the control voltage generates a voltage-regulated magnetic anisotropy effect in the magnetic tunnel junction, which is used to regulate the magnetization direction of the magnetic tunnel junction, so that the spin logic device realizes the logic operation of 16 kinds of Boolean logic, adder, subtractor and multiplier.

[0008] Before the logic operation, the initial resistance state of each magnetic tunnel junction is read as a logic input; during the logic operation, different control currents and voltages are applied to each magnetic tunnel junction according to the type of logic operation; after the logic operation, the logic output is stored in the specified magnetic tunnel junction in the form of resistance state.

[0009] In some optional modes of the embodiment, when the resistance state of the magnetic tunnel junction is in a low resistance state, the control voltage satisfies a first preset voltage threshold and the control current satisfies a first preset current threshold, the resistance state of the magnetic tunnel junction can be flipped from the low resistance state to a high resistance state based on the lowering effect of the control voltage on the potential barrier; when the control voltage satisfies a second preset voltage threshold and the control current satisfies the first preset current threshold, the resistance state of the magnetic tunnel junction cannot be flipped from the low resistance state to the high resistance state.

[0010] When the resistance state of the magnetic tunnel junction is in a high resistance state, the control voltage satisfies a first preset voltage threshold and the control current satisfies a second preset current threshold, the resistance state of the magnetic tunnel junction can be flipped from the high resistance state to a low resistance state based on the lowering effect of the control voltage on the potential barrier; when the control voltage satisfies a second preset voltage threshold and the control current satisfies the second preset current threshold, the resistance state of the magnetic tunnel junction cannot be flipped from the high resistance state to the low resistance state.

[0011] In some optional modes of the embodiment, when n=2, the spin logic device includes a first magnetic tunnel junction and a second magnetic tunnel junction grown on the spin-orbit torque channel layer, the initial resistance state of the first magnetic tunnel junction is defined as p, and the initial resistance state of the second magnetic tunnel junction is defined as q, and the p and q are used as two logic input variables of the logic operation; the peripheral control circuit is used to perform one-step write operation or two-step write operation on the first magnetic tunnel junction and the second magnetic tunnel junction by applying a first control voltage V G1 to the first magnetic tunnel junction, a second control voltage V G2 to the second magnetic tunnel junction, and a control current I.

[0012] The one-step write operation is used for the spin logic device to implement TRUE logic operation, FALSE logic operation, COPY p logic operation, COPY q logic operation, NOT p logic operation, NOT q logic operation, AND logic operation, OR logic operation, NIMP logic operation, RIMP logic operation, XNOR logic operation, XOR logic operation, IMP logic operation, RNIMP logic operation, and half-subtractor operation.

[0013] The two-step write operation is used for the spin logic device to implement NOR logic operation, NAND logic operation, and half-adder operation.

[0014] In some optional modes of the embodiment, when n=3, the spin logic device comprises a first magnetic tunnel junction, a second magnetic tunnel junction, and a third magnetic tunnel junction grown on the spin-orbit torque channel layer, the initial resistance state of the first magnetic tunnel junction is defined as p, the initial resistance state of the second magnetic tunnel junction is defined as q, and the initial resistance state of the third magnetic tunnel junction is defined as x, and the p, q, and x are three logic input variables of a logic operation.

[0015] The peripheral control circuit is configured to perform a three-step write operation or a five-step write operation on the first magnetic tunnel junction, the second magnetic tunnel junction, and the third magnetic tunnel junction by applying a first control voltage V G1 to the first magnetic tunnel junction, a second control voltage V G2 to the second magnetic tunnel junction, a third control voltage V G3 to the third magnetic tunnel junction, and a control current I.

[0016] The three-step write operation is used for the spin logic device to implement full-subtractor operation, and the five-step write operation is used for the spin logic device to implement full-adder operation.

[0017] In some optional modes of the embodiment, when n=4, the spin logic device comprises a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction, and a fourth magnetic tunnel junction grown on the spin-orbit torque channel layer, the initial resistance state of the first magnetic tunnel junction is defined as p, the initial resistance state of the second magnetic tunnel junction is defined as q, the initial resistance state of the third magnetic tunnel junction is defined as x, and the initial resistance state of the fourth magnetic tunnel junction is defined as y, and the p, q, x, and y are four logic input variables of a logic operation.

[0018] The peripheral control circuit is configured to perform a three-step write operation or a five-step write operation on the first magnetic tunnel junction, the second magnetic tunnel junction, the third magnetic tunnel junction, and the fourth magnetic tunnel junction by applying a first control voltage V G1 to the first magnetic tunnel junction, a second control voltage V G2 to the second magnetic tunnel junction, a third control voltage V G3, a fourth control voltage V G4 and a control current I to perform a six-step write operation on the first magnetic tunnel junction, the second magnetic tunnel junction, the third magnetic tunnel junction and the fourth magnetic tunnel junction.

[0019] The six-step write operation is used to implement a multiplier operation by the spin logic device.

[0020] In some optional manners of the embodiment, the one-step write operation includes:

[0021] Let the V G1 = 1, V G2 = 0, I = 1, after the logic operation ends, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a TRUE logic operation.

[0022] Let the V G1 = 1, V G2 = 0, I = 0, after the logic operation ends, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a FALSE logic operation.

[0023] Let the V G1 = 0, V G2 = 0, I = 0, after the logic operation ends, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a COPY p logic operation.

[0024] Let the V G1 = 1, V G2 = 0, I = q, after the logic operation ends, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a COPY q logic operation.

[0025] Let the V G1 = 1, V G2 = 0, after the logic operation ends, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a NOT p logic operation.

[0026] Let the V G1 = 1, V G2 = 0, after the logic operation ends, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a NOT q logic operation.

[0027] Let the V G1 = p, V G2= 0, I = q, after the logic operation, the logic output is stored in the first magnetic tunnel junction in the form of resistance state, the spin logic device realizes AND logic operation;

[0028] Let the V V G2 = 0, I = q, after the logic operation, the logic output is stored in the first magnetic tunnel junction in the form of resistance state, the spin logic device realizes OR logic operation;

[0029] Let the V G1 = p, V G2 = 0, after the logic operation, the logic output is stored in the first magnetic tunnel junction in the form of resistance state, the spin logic device realizes NIMP logic operation;

[0030] Let the V V G2 = 0, after the logic operation, the logic output is stored in the first magnetic tunnel junction in the form of resistance state, the spin logic device realizes RIMP logic operation;

[0031] Let the V V G2 = 0, after the logic operation, the logic output is stored in the first magnetic tunnel junction in the form of resistance state, the spin logic device realizes XNOR logic operation;

[0032] Let the V G1 = q, V G2 = 0, after the logic operation, the logic output is stored in the first magnetic tunnel junction in the form of resistance state, the spin logic device realizes XOR logic operation;

[0033] Let the V G1 = 0, I = 1, after the logic operation, the logic output is stored in the second magnetic tunnel junction in the form of resistance state, the spin logic device realizes IMP logic operation;

[0034] Let the V G1 = 0, V G2 = p, after the logic operation, the logic output is stored in the second magnetic tunnel junction in the form of resistance state, the spin logic device realizes RNIMP logic operation;

[0035] Let the V G1 = q, V G2 = p, After the logic operation is completed, the difference of the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the borrow of the logic output is stored in the second magnetic tunnel junction in the form of a resistance state. The spin logic device implements a half-subtractor operation.

[0036] In some optional aspects of this embodiment, the two-step write operation includes a first-step write sub-operation and a second-step write sub-operation, wherein:

[0037] The first step of writing sub-operation includes setting the V G1 =0, After the first step of writing sub-operation is completed, the second step of writing sub-operation includes setting the V G1 =0, V G2 =p, After the logic operation is completed, the logic output is stored in the second magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a NOR logic operation;

[0038] The first step of writing sub-operation includes setting the V G1 =0, V G2 =p, After the first step of writing sub-operation is completed, the second step of writing sub-operation includes setting the V G1 =0, After the logic operation is completed, the logic output is stored in the second magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a NAND logic operation;

[0039] The first step of writing sub-operation includes setting the V G1 =q,V G2 =0, After the first step of writing sub-operation is completed, the second step of writing sub-operation includes setting the V G1 =0, V G2 =q, I=p; after the logic operation is completed, the sum of the logic outputs is stored in the first magnetic tunnel junction in the form of a resistance state, and the carry of the logic output is stored in the second magnetic tunnel junction in the form of a resistance state, and the spin logic device realizes a half adder operation.

[0040] In some optional aspects of this embodiment, the three-step write operation includes a first write sub-operation, a second write sub-operation, and a third write sub-operation, wherein:

[0041] The first step of writing sub-operation includes setting the V G1 =q,V G2 =p, V G3 =0, After the first step of writing sub-operation is completed, the second step of writing sub-operation includes setting the VG1 = x, V G2 = 0, V G3 = p1, After the second write sub-operation is executed, the third write sub-operation includes setting the V G1 = 0, V G2 = 0, I = q2, after the logical operation is completed, the difference of the logical output is stored in the first magnetic tunnel junction in the form of a resistance state, and the borrow bit of the logical output is stored in the third magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a full subtractor operation;

[0042] wherein the p1 is a resistance state of the first magnetic tunnel junction after the first write sub-operation; the x2 is a resistance state of the third magnetic tunnel junction after the second write sub-operation; and the q2 is a resistance state of the second magnetic tunnel junction after the second write sub-operation.

[0043] In some optional modes of the embodiment, the five write operations include a first write sub-operation, a second write sub-operation, a third write sub-operation, a fourth write sub-operation, and a fifth write sub-operation, wherein:

[0044] The first write sub-operation includes setting the V G1 = 0, V G2 = 0, V G3 = x, I = q; after the first write sub-operation is executed, the second write sub-operation includes setting the V G1 = 0, V G2 = x, V G3 = 0, After the second write sub-operation is executed, the third write sub-operation includes setting the V G1 = 0, V G2 = q2, V G3 = 0, I = p; after the third write sub-operation is executed, the fourth write sub-operation includes setting the V G1 = q2, V G2 = 0, V G3 = 0, After the fourth write sub-operation is executed, the fifth write sub-operation includes setting the V G1 = 0, V G2 = 0, I = q3, after the logical operation is completed, the sum of the logical output is stored in the first magnetic tunnel junction in the form of a resistance state, and the carry bit of the logical output is stored in the third magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a full adder operation;

[0045] Wherein, the q2 is the resistance state of the second magnetic tunnel junction after the second step write sub-operation; the x1 is the resistance state of the third magnetic tunnel junction after the first step write sub-operation; the q3 is the resistance state of the second magnetic tunnel junction after the third step write sub-operation.

[0046] In some alternative manners of the embodiment, the six-step write operation comprises a first step write sub-operation, a second step write sub-operation, a third step write sub-operation, a fourth step write sub-operation, a fifth step write operation and a sixth step write sub-operation, wherein:

[0047] The first step write sub-operation comprises setting the V G1 = 1, V G2 = 1, V G3 = 1, V G4 = 1, I = 0; after the first step write sub-operation is executed, the second step write sub-operation comprises setting the V G1 = y, V G2 = x, V G3 = 0, V G4 = 0, I = p; after the second step write sub-operation is executed, the third step write sub-operation comprises setting the V G1 = 0, V G2 = 0, V G3 = x, V G4 = y, I = q, after the third step write sub-operation is executed, the fourth step write sub-operation comprises setting the V G1 = 0, V G2 = 0, V G3 = p2, V G4 = 0, After the fourth step write sub-operation is executed, the fifth step write sub-operation comprises setting the V G1 = p2, V G2 = 0, V G3 = 0, V G4 = 0, I = x3, after the fifth step write sub-operation is executed, the sixth step write sub-operation comprises setting the V G1 = 0, V G2 = p5, V G3 = 0, V G4 = 0, The spin logic device implements a multiplier operation;

[0048] Wherein, the p2 is the resistance state of the first magnetic tunnel junction after the second step write sub-operation; the x3 is the resistance state of the third magnetic tunnel junction after the third step write sub-operation; the q2 is the resistance state of the second magnetic tunnel junction after the second step write sub-operation; the p5 is the resistance state of the first magnetic tunnel junction after the fifth step write sub-operation.

[0049] In a second aspect, the embodiment of the present application provides a logic operation method of the spin logic device, comprising:

[0050] Before the logic operation, the initial resistance states of the magnetic tunnel junctions are read as logic inputs;

[0051] During the logic operation, different control currents and control voltages are applied to the magnetic tunnel junctions according to the type of the logic operation;

[0052] After the logic operation, the logic output is stored in the designated magnetic tunnel junction in the form of the resistance state.

[0053] The spin logic device and the logic operation method provided by the embodiment of the present application are based on the magnetic tunnel junction structure of the magnetic random access memory, and the synergistic effect of the spin-orbit torque technology and the voltage control magnetic anisotropy technology can realize 16 kinds of Boolean logic operations, as well as the functions of the adder, the subtracter and the multiplier. The logic input and the logic output are stored in the magnetic tunnel junction in the form of the resistance state, the logic operation and the data storage are integrated, and the advantages of non-volatility, low power consumption, programmability, multi-function and scalability are achieved. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor. In the drawings:

[0055] Figure 1 It is one of the structure schematic diagrams of the spin logic device in the embodiment of the present application;

[0056] Figure 2 It is the second structure schematic diagram of the spin logic device in the embodiment of the present application;

[0057] Figure 3 It is the spin-orbit torque flipping curve under different V G voltages in the embodiment of the present application;

[0058] Figure 4Spin-in logic input and output schematic diagram in the embodiment of the present application;

[0059] Figure 5 Spin logic device structure schematic diagram three in the embodiment of the present application;

[0060] Figure 6 Spin logic device structure schematic diagram four in the embodiment of the present application;

[0061] Figure 7 2bit MTJ and 3bit MTJ corresponding implementation function schematic diagram respectively;

[0062] Figure 8 Spin logic device structure schematic diagram five in the embodiment of the present application;

[0063] Figure 9 4bit MTJ corresponding implementation function schematic diagram;

[0064] Figure 10 Spin logic device-based logic operation method flowchart in the embodiment of the present application. DETAILED DESCRIPTION

[0065] To make the purpose, technical scheme and advantages of the embodiment of the present application more clear and explicit, the embodiment of the present application is further described in detail below in combination with the drawings. Herein, the illustrative embodiment of the present application and its description are used to explain the present application, but not as a limitation of the present application.

[0066] The third generation spin-orbit torque magnetic random access memory (Spin-Orbit Torque MRAM: SOT-MRAM) realizes the separation of read and write paths, greatly improves the performance of the device such as breakdown voltage and service life. By applying a transverse current in the strip-shaped heavy metal layer below the ferromagnetic layer, a perpendicular spin current can be generated, which makes the magnetization of the ferromagnetic layer flip through the spin-orbit torque effect. At this time, the write current does not pass through the magnetic tunnel junction, avoiding the breakdown of the magnetic tunnel junction; the read current path is separated from the write current path, avoiding read-write interference, which is conducive to the separate optimization of read and write performance; the spin-orbit torque effect does not have intrinsic relaxation delay in the process of magnetic moment flip, and has a faster data write speed. Therefore, the spin-orbit torque magnetic random access memory is more suitable for cache and other high-speed write and high-reliability storage application scenarios than the spin transfer torque magnetic random access memory. However, for magnetic tunnel junctions with perpendicular magnetic anisotropy, an in-plane external magnetic field is usually needed to assist the flip, which greatly increases the write power consumption and circuit complexity. The anti-ferromagnetic / ferromagnetic / oxide film structure is expected to realize deterministic magnetization flip without external magnetic field, which is an important research direction in the field of spin electronics in recent years.

[0067] Applying a voltage across a magnetic tunnel junction can effectively control the perpendicular magnetic anisotropy, that is, a voltage control of magnetic anisotropy (VCMA) effect. By using the voltage control of magnetic anisotropy effect to reduce the energy barrier during data writing, and by using the spin-orbit torque effect to realize deterministic magnetization flipping, high-speed and low-power data writing can be realized, which has broad application prospects. This writing method uses a VCMA voltage to selectively write multiple magnetic tunnel junctions (MTJs), so that each MTJ is no longer a three-terminal device, multiple MTJs share two drive transistors, which is conducive to improving the storage density, and the VCMA voltage reduces the energy barrier that needs to be overcome during the writing operation, thereby reducing the critical flipping current. Meanwhile, the spin-orbit torque current generates a spin-orbit torque to realize deterministic flipping of the magnetic moment, thereby effectively reducing the data writing error probability.

[0068] The existing non-volatile Boolean logic and storage-computing integrated technology has many problems. Specifically, in terms of memory devices, multi-resistance states (phase change memory cells) have high power consumption, slow speed and poor thermal stability; resistance variable devices have low durability, difficulty in controlling resistance precision and temperature sensitivity; spin gate logic devices based on STT effect have limited service life; in terms of power consumption, the separation of memory and computing units causes data to be frequently transmitted between the two, resulting in increased system power consumption and complicated operation process; in terms of integration, the existing technology is difficult to realize low-power, high-efficiency and comprehensive Boolean logic operation, adder and multiplier functions in the same structure, resulting in low integration and limiting the further improvement of device performance and integration; in terms of operation steps, the existing technology requires many devices and complicated operations, has poor expandability, and affects the stability and convenience of the device.

[0069] Therefore, as shown in the accompanying drawings, Figure 1 the embodiment of the present application provides a spin logic device, which comprises a spin-orbit torque channel layer (SOT channel layer), n magnetic tunnel junctions (MTJ1, MTJ2, MTJ3, …, MTJn) grown on the SOT channel layer, and a peripheral control circuit, wherein n is a natural number greater than 1.

[0070] The peripheral control circuit applies a control current and a control voltage to the magnetic tunnel junctions. The control current generates a spin-orbit torque effect in the spin-orbit torque channel layer, and the control voltage generates a voltage control of magnetic anisotropy effect in the magnetic tunnel junctions, which is used to control the magnetization direction of the magnetic tunnel junctions, so that the spin logic device realizes 16 kinds of Boolean logic, adder, subtracter and multiplier logic operations.

[0071] Wherein, before the logic operation, the initial resistance state of each magnetic tunnel junction is read as the logic input; during the logic operation, different control currents and control voltages are applied to the magnetic tunnel junction according to the type of logic operation; after the logic operation, the logic output is stored in the designated magnetic tunnel junction in the form of resistance state, that is, the current resistance state of the designated tunnel junction after being regulated is taken as the logic output.

[0072] In the present application, as shown in Figure 1 each MTJ top connects the source of a transistor; the drain of the transistor is connected to the VCMA control voltage V Gn or the read voltage V read when reading the resistance state of the MTJ; the gate of the transistor is connected to the bit line; for example, the top of the first magnetic tunnel junction MTJ1 connects the source of the transistor M1; the drain of the transistor M1 is connected to the first control voltage V G1 or the read voltage V read when reading the resistance state of the MTJ; the gate of the transistor M1 is connected to the bit line; the top of the second magnetic tunnel junction MTJ2 connects the source of the transistor M2; the drain of the transistor M2 is connected to the second control voltage V G2 or the read voltage V read when reading the resistance state of the MTJ; the gate of the transistor M2 is connected to the bit line; the top of the third magnetic tunnel junction MTJ3 connects the source of the transistor M3; the drain of the transistor M3 is connected to the third control voltage V G3 or the read voltage V read when reading the resistance state of the MTJ; the gate of the transistor M3 is connected to the bit line; the top of the nth magnetic tunnel junction MTJn connects the source of the transistor M n ; the drain of the transistor M n is connected to the nth control voltage V Gn or the read voltage V read when reading the resistance state of the MTJ; the gate of the transistor M n is connected to the bit line.

[0073] The SOT channel layer is connected to the transistor M L and the transistor M R at both ends; wherein the source of the transistor M L connects the SOT channel layer, the drain of the transistor M L is connected to the control current I or GND, and the gate of the transistor M L is connected to the word line; the source of the transistor M R connects the SOT channel layer, the drain of the transistor M R is connected to GND or the gate of the transistor M R is connected to the word line. Among them, denotes the negative of the control current I, for example when the control current I is -2.5 mA, is 2.5 mA.

[0074] It should be noted that when I = +2.5 mA (corresponding to logic 1), the drain of transistor M L is connected to the control current I, and the drain of transistor M R is connected to GND; when I = -2.5 mA (corresponding to logic 0), the drain of transistor M L is connected to GND, and the drain of transistor M R is connected to

[0075] It should be understood that the above-mentioned transistors M1, transistors M2, transistors M3, …, transistors M n , transistors M L , transistors M R , word lines, and bit lines, etc. constitute the peripheral control circuit of the present application.

[0076] Referring to Figure 1 , a schematic diagram of a device structure of the present application is shown, and the basic structure is to grow a plurality of MTJs on a spin-orbit torque channel layer, and the spin-orbit torque channel layer is a channel layer capable of generating spin-orbit torque, which is composed of heavy metal film, anti-ferromagnetic film, topological insulator, two-dimensional material, semi-metal film, or oxide film, etc.

[0077] As shown in Figure 2 , each magnetic tunnel junction includes a free layer, a barrier layer, and a reference layer which are sequentially stacked, wherein the free layer and the reference layer are ferromagnetic layers, the free layer and the reference layer are sandwiched by the barrier layer, and the reference layer can further include an anti-ferromagnetic layer and a top heavy metal layer; the free layer and the reference layer can have perpendicular magnetic anisotropy or in-plane magnetic anisotropy. Under perpendicular magnetic anisotropy, the magnetization direction is perpendicular to the film plane; when in-plane magnetic anisotropy, the magnetization direction is parallel to the film plane.

[0078] In the present application, the resistance state of the MTJ is determined by the relative direction of the reference layer and the free layer. When the reference layer and the free layer are arranged in parallel, the MTJ is in a low resistance state, and the logic state corresponding to the magnetic tunnel junction is defined as low level "0"; when the reference layer and the free layer are anti-parallel, the MTJ is in a high resistance state, and the logic state corresponding to the magnetic tunnel junction is defined as high level "1".

[0079] In one specific example, when the material of the spin-orbit torque channel layer is an anti-ferromagnetic film, as shown in Figure 2 , an in-plane exchange bias field is formed at the interface between the anti-ferromagnetic layer and the free layer, so that the device can be written without magnetic field, i.e. field-free flipping is achieved.

[0080] It should be noted that the above-mentioned method of achieving field-free reversal of the perpendicular magnetic anisotropy moment is to utilize the exchange bias field of the antiferromagnetic / ferromagnetic interface, but the content protected by the patent described in this application includes other methods of achieving field-free reversal, such as using a hard mask to generate in-plane stray fields, introducing out-of-plane spin polarization currents, constructing lateral structural asymmetry, adopting interlayer exchange coupling mechanisms, applying low-symmetry material systems, combining materials with opposite spin Hall angles, and utilizing new materials such as topological insulators or Weyl semimetals.

[0081] In this application, the spin-orbit torque effect is generated by applying a current I of a specific direction and magnitude to the spin-orbit torque channel layer; at the same time, a suitable voltage V is applied to the top of the MTJ. G , the voltage-controlled magnetic anisotropy (VCMA) effect is used to control the magnetic anisotropy energy barrier of the ferromagnetic layer.

[0082] In this application, the synergistic effect of spin-orbit torque technology and voltage-controlled magnetic anisotropy technology can be used to effectively change the magnetization direction of the ferromagnetic layer. Specifically, under the joint action of SOT current and VCMA voltage, the magnetization direction of the ferromagnetic layer can be switched between two stable states, corresponding to the precise flipping of the logic state from "0" to "1" or "1" to "0", thereby successfully completing basic logic operations. The resistance value of MTJ is used to characterize the data state. The logic input is the resistance state of the device. After the logic operation is completed, the logic output is also stored in the device in the form of a resistance state, thereby realizing the integration of logic operation and data storage.

[0083] In this application, logic operations are implemented collaboratively based on spin-orbit moment technology and voltage-controlled magnetic anisotropy technology. By setting the thresholds for the VCMA control voltage and the SOT control current, the flipping of the magnetic tunnel junction resistance state is controlled. Specifically, the VCMA voltage can lower the potential barrier, thereby reducing the critical current density required for the magnetic tunnel junction resistance state flipping. As a result, the threshold current required to flip the magnetic tunnel junction resistance state differs when the VCMA voltage is applied and when it is not.

[0084] Thus, in some optional aspects of this embodiment, when the resistance state of the magnetic tunnel junction is a low resistance state, the control voltage satisfies a first preset voltage threshold (for example, 0.6V) and the control current satisfies a first preset current threshold (for example, 2.5mA), based on the effect of the control voltage on lowering the potential barrier, the resistance state of the magnetic tunnel junction can be flipped from the low resistance state to the high resistance state; when the control voltage satisfies a second preset voltage threshold (for example, 0V) and the control current satisfies a first preset current threshold (for example, 2.5mA), the resistance state of the magnetic tunnel junction cannot be flipped from the low resistance state to the high resistance state;

[0085] When the resistance state of the magnetic tunnel junction is high resistance, the control voltage satisfies a first preset voltage threshold (for example, 0.6V) and the control current satisfies a second preset current threshold (for example, -2.5mA), the resistance state of the magnetic tunnel junction can be flipped from high resistance to low resistance based on the lowering effect of the control voltage on the potential barrier; when the control voltage satisfies the second preset voltage threshold (for example, 0V) and the control current satisfies the second preset current threshold (for example, -2.5mA), the resistance state of the magnetic tunnel junction cannot be flipped from high resistance to low resistance.

[0086] Specifically, in an embodiment of the present application, referring to Figure 3 , it is shown that the spin orbit torque (SOT) control voltage and current threshold values for different V G oltage and spin orbit torque (SOT) current. When the initial resistance state is low resistance (R L ), when V G is 0.6V and SOT current I is 2.5mA, the MTJ can be flipped to high resistance, when V G is 0V and SOT current I is 2.5mA, the MTJ cannot be flipped to high resistance; when the initial resistance is high resistance (R H ), when V G is 0.6V and SOT current I is -2.5mA, the MTJ can be flipped from high resistance to low resistance, when V G is 0V and SOT current I is -2.5mA, the MTJ cannot be flipped from high resistance to low resistance.

[0087] It should be noted that the threshold values of the VCMA voltage and the SOT control current described above are exemplary and do not constitute an improper limitation on the present application.

[0088] Referring to Figure 4 , the present application realizes spin-in-memory logic, which realizes 16 kinds of Boolean logic based on a 2-bit memory, the logic input is the resistance state R MTJ1 of MTJ1 and the resistance state R MTJ2 of MTJ2, and the logic output is also saved in the form of MTJ1 resistance state or MTJ2 resistance state.

[0089] Table 1 is a comparison of logic parameters and experimental parameters defined by the present application, wherein p, q, x, y are the initial resistance states of MTJ1, MTJ2, MTJ3, and MTJ4, respectively, p1, q1, x1, y1 are the resistance states of MTJ1, MTJ2, MTJ3, and MTJ4 after the end of step one, and so on. n , q n , x n , y nResistive states of MTJ1, MTJ2, MTJ3, MTJ4 after step n respectively. Resistive state is defined as logic "0" when it is low resistive state, and defined as logic "1" when it is high resistive state; V G represents VCMA voltage applied on MTJ, VCMA voltage is defined as logic "0" when it is 0V, i.e. V G =0, and defined as logic "1" when it is 0.6V, i.e. V G =1; I represents SOT current, SOT current is defined as logic "0" when it is -2.5mA, i.e. I=0, and defined as logic "1" when it is +2.5mA, i.e. I=1.

[0090] It should be noted that the threshold setting of VCMA control voltage and SOT control current described above is exemplary, and does not constitute improper limitation on the present application.

[0091] Table 1

[0092]

[0093] In some optional manners of the embodiment, as shown in Figure 5 when n=2, the spin logic device includes a first magnetic tunnel junction MTJ1 and a second magnetic tunnel junction MTJ2 grown on the spin orbit torque channel layer, an initial resistive state of the first magnetic tunnel junction is defined as p, and an initial resistive state of the second magnetic tunnel junction is defined as q, the p and q are two logic input variables for logic operation; the peripheral control circuit is configured to perform one-step write operation or two-step write operation on the first magnetic tunnel junction and the second magnetic tunnel junction by applying a first control voltage V G1 to the first magnetic tunnel junction, applying a second control voltage V G2 to the second magnetic tunnel junction, and controlling current I, wherein:

[0094] the one-step write operation is used for the spin logic device to realize TRUE logic operation, FALSE logic operation, COPY p logic operation, COPY q logic operation, NOT p logic operation, NOT q logic operation, AND logic operation, OR logic operation, NIMP logic operation, RIMP logic operation, XNOR logic operation, IMP logic operation, RNIMP logic operation, and half subtractor operation; and the two-step write operation is used for the spin logic device to realize NOR logic operation, NAND logic operation, and half adder operation.

[0095] Table 2

[0096]

[0097]

[0098] Table 2 is a schematic diagram of 16 steps for implementing full Boolean logic in an embodiment of the present invention. The oblique lower box in Table 2 indicates that step 2 of the logic operation is not performed. In some optional embodiments of this embodiment, as shown in Table 2, the one-step write operation includes:

[0099] Let the V G1 =1, V G2 =0, I=1, after the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device realizes a TRUE logic operation;

[0100] Let the V G1 =1, V G2 =0, I=0, after the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a FALSE logic operation;

[0101] Let the V G1 =0, V G2 =0, I=0, after the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements the COPY p logic operation;

[0102] Let the V G1 =1, V G2 =0, I=q, after the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements the COPY q logic operation;

[0103] Let the V G1 =1, V G2 =0, After the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a NOT p logic operation;

[0104] Let the V G1 =1, V G2 =0, After the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a NOT q logic operation;

[0105] Let the V G1 =p, V G2 =0, I=q, after the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device realizes an AND logic operation;

[0106] Let the VG2 =0, I=q, after the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements an OR logic operation;

[0107] Let the V G1 =p, V G2 =0, After the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements the NIMP logic operation;

[0108] Let the V G2 =0, After the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements the RIMP logic operation;

[0109] Let the V G2 =0, After the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements an XNOR logic operation;

[0110] Let the V G1 =q,V G2 =0, After the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements an XOR logic operation;

[0111] Let the V G1 =0, I=1, after the logic operation is completed, the logic output is stored in the second magnetic tunnel junction in the form of a resistance state, and the spin logic device implements an IMP logic operation;

[0112] Let the V G1 =0, V G2 =p, After the logic operation is completed, the logic output is stored in the second magnetic tunnel junction in the form of a resistance state, and the spin logic device implements the RNIMP logic operation;

[0113] Let the V G1 =q,V G2 =p, After the logic operation is completed, the difference of the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the borrow of the logic output is stored in the second magnetic tunnel junction in the form of a resistance state. The spin logic device implements a half-subtractor operation (see Table 3).

[0114] The following is the above VG1 , V G2 and the value of I is described as follows, wherein:

[0115] V G1 = 1, indicating that the logic value of the first control voltage is "1", i.e. the applied first control voltage needs to satisfy the first preset voltage threshold (e.g. 0.6V); V G1 = 0 indicates that the logic value of the first control voltage is "0", i.e. the applied first control voltage needs to satisfy the second preset voltage threshold (e.g. 0V); V G1 = p indicates that the logic value of the first control voltage is equal to the logic value corresponding to the initial resistance state of the first magnetic tunnel junction (e.g. when the initial resistance state of the first magnetic tunnel junction is a low resistance state, p = 0, then V G1 = 0, i.e. the applied first control voltage needs to satisfy the second preset voltage threshold; when the initial resistance state of the first magnetic tunnel junction is a high resistance state, p = 1, then V G1 = 1, i.e. the applied first control voltage needs to satisfy the first preset voltage threshold); V G1 = q indicates that the logic value of the first control voltage is equal to the logic value corresponding to the initial resistance state of the second magnetic tunnel junction (e.g. when the initial resistance state of the second magnetic tunnel junction is a low resistance state, i.e. q = 0, then V G1 = 0, i.e. the applied first control voltage needs to satisfy the second preset voltage threshold; when the initial resistance state of the second magnetic tunnel junction is a high resistance state, i.e. q = 1, then V G1 = 1, i.e. the applied first control voltage needs to satisfy the first preset voltage threshold).

[0116] V G2 = 1, indicating that the logic value of the second control voltage is "1", i.e. the applied second control voltage needs to satisfy the first preset voltage threshold (e.g. 0.6V); V G2 = 0 indicates that the logic value of the second control voltage is "0", i.e. the applied second control voltage needs to satisfy the second preset voltage threshold (e.g. 0V); V G2 = p indicates that the logic value of the second control voltage is equal to the logic value corresponding to the initial resistance state of the first magnetic tunnel junction (e.g. when the initial resistance state of the first magnetic tunnel junction is a low resistance state, p = 0, then V G2 = 0, i.e. the applied second control voltage needs to satisfy the second preset voltage threshold; when the initial resistance state of the first magnetic tunnel junction is a high resistance state, p = 1, then V G2 = 1, i.e. the applied second control voltage needs to satisfy the first preset voltage threshold); V G2 = q indicates that the logic value of the second control voltage is equal to the logic value corresponding to the initial resistance state of the second magnetic tunnel junction (e.g. when the initial resistance state of the second magnetic tunnel junction is a low resistance state, i.e. q = 0, then V G2= 0, i.e. the second control voltage applied should satisfy the second preset voltage threshold; when the initial resistance state of the second magnetic tunnel junction is high resistance state, i.e. q = 1, then V G2 = 1, i.e. the second control voltage applied should satisfy the first preset voltage threshold.

[0117] I = 1, indicating that the logic value of the control current is "1", i.e. the control current applied should satisfy the first preset current threshold (2.5 mA); I = 0, indicating that the logic value of the control current is "0", i.e. the control current applied should satisfy the second preset current threshold (-2.5 mA); I = p, indicating that the logic value of the control current is equal to the logic value corresponding to the initial resistance state of the first magnetic tunnel junction (for example, when the initial resistance state of the first magnetic tunnel junction is low resistance state, p = 0, then I = 0, i.e. the control current applied should satisfy the second preset current threshold; when the initial resistance state of the first magnetic tunnel junction is high resistance state, p = 1, then I = 1, i.e. the control current applied should satisfy the first preset voltage threshold); I = q, indicating that the logic value of the control current is equal to the logic value corresponding to the initial resistance state of the second magnetic tunnel junction (for example, when the initial resistance state of the second magnetic tunnel junction is low resistance state, i.e. q = 0, then I = 0, i.e. the control current applied should satisfy the second preset current threshold; when the initial resistance state of the second magnetic tunnel junction is high resistance state, i.e. q = 1, then I = 1, i.e. the control current applied should satisfy the first preset current threshold).

[0118] In addition, represents logical NOT operation, for example, represents taking the inverse of the logic variable p, i.e. if p is logic 1, then is logic 0; if p is logic 0, then is logic 1.

[0119] Referring to Table 2, the operation steps of implementing 16 kinds of full Boolean logic based on 2-bit memory are shown. Among them, logical NOR and NAND need two-step operation, and the remaining 14 kinds of logic can be implemented in one step operation without initialization. The logic outputs of IMP, RNIMP, NOR and NAND are stored in MTJ2 in the form of resistance state, and the logic outputs of the remaining logic are stored in MTJ1 in the form of resistance state.

[0120] Taking the implementation of AND logic operation of the spin logic device as an example, the initial resistance state of MTJ1 is p, the initial resistance state of MTJ2 is q, and the operation step is one-step write operation, i.e. the V G1 = p, V G2 = 0, I = q can implement the logic AND operation. Specifically, when the input logic value combination (p, q) is (0, 0), (0, 1), (1, 0) and (1, 1) respectively, the corresponding control voltage and control current (V G1 ,V G2,I) are (0,0,0), (0,0,1), (1,0,0) and (1,0,1), among which, when (V G1 ,V G2 ,I) is (0,0,0), (0,0,1) and (1,0,0), the resistance state of MTJ1 does not flip and remains at logic 0; when (V G1 ,V G2 ,I) is (1,0,1), the resistance state of MTJ1 flips to logic 1. Therefore, after the spin logic device performs AND logic operation, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state. The current resistance states of MTJ1 are 0, 0, 0 and 1, which fully complies with the logic AND operation rules.

[0121] In some optional aspects of this embodiment, the two-step write operation includes a first-step write sub-operation and a second-step write sub-operation, wherein:

[0122] The first step of writing sub-operation includes setting the V G1 =0, After the first step of writing sub-operation is completed, the second step of writing sub-operation includes setting the V G1 =0, V G2 =p, After the logic operation is completed, the logic output is stored in the second magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a NOR logic operation;

[0123] The first step of writing sub-operation includes setting the V G1 =0, V G2 =p, After the first step of writing sub-operation is completed, the second step of writing sub-operation includes setting the V G1 =0, After the logic operation is completed, the logic output is stored in the second magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a NAND logic operation.

[0124] The above V G1 、V G2 As for the value of I, please refer to the above description, which will not be described in detail in this application.

[0125] Table 3

[0126]

[0127] Table 3 is a schematic diagram of the implementation steps of the half adder, full adder, half subtractor, full subtractor and multiplier in the embodiment of the present invention; Referring to Table 3, the first step of writing sub-operation includes setting the V G1 =q,V G2=0, After the first step of writing sub-operation is completed, the second step of writing sub-operation includes setting the V G1 =0, V G2 =q, I=p; after the logic operation is completed, the sum of the logic outputs is stored in the first magnetic tunnel junction in a resistive state, and the carry of the logic output is stored in the second magnetic tunnel junction in a resistive state. The spin logic device implements a half adder operation. The truth tables of the half adder and the half subtractor are shown in Table 4 and are not described in detail in this application.

[0128] Table 4

[0129]

[0130] In some optional embodiments of this embodiment, such as Figure 6 As shown, when n=3, the spin logic device includes a first magnetic tunnel junction MTJ1, a second magnetic tunnel junction MTJ2 and a third magnetic tunnel junction MTJ3 grown on the spin-orbit moment channel layer, and the initial resistance state of the first magnetic tunnel junction is defined as p, the initial resistance state of the second magnetic tunnel junction is defined as q, and the initial resistance state of the third magnetic tunnel junction is defined as x, and the p, q and x are used as three logic input variables of the logic operation; the peripheral control circuit is used to apply a first control voltage V to the first magnetic tunnel junction G1 , applying a second control voltage V to the second magnetic tunnel junction G2 , applying a third control voltage V to the third magnetic tunnel junction G3 And control the current I to perform a three-step write operation or a five-step write operation on the first magnetic tunnel junction, the second magnetic tunnel junction and the third magnetic tunnel junction, wherein the three-step write operation is used for the spin logic device to implement a full subtractor operation; the five-step write operation is used for the spin logic device to implement a full adder operation.

[0131] In some optional aspects of this embodiment, the three-step write operation includes a first write sub-operation, a second write sub-operation, and a third write sub-operation, wherein:

[0132] As shown in Table 3, the first step of writing sub-operation includes setting the V G1 =q,V G2 =p, V G3 =0, After the first step of writing sub-operation is completed, the second step of writing sub-operation includes setting the V G1 =x,V G2 =0, V G3 =p1, After the second step of writing sub-operation is completed, the third step of writing sub-operation includes setting the VG1 =0, V G2 =0, I=q2, after the logic operation is completed, if Figure 7 As shown, the difference of the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the borrow of the logic output is stored in the third magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a full subtractor operation;

[0133] Among them, p1 is the resistance state of the first magnetic tunnel junction after the first step write sub-operation; x2 is the resistance state of the third magnetic tunnel junction after the second step write sub-operation; q2 is the resistance state of the second magnetic tunnel junction after the second step write sub-operation.

[0134] The above V G1 、V G2 、V G3 The values ​​of I are similar to those described above and will not be repeated here. The following describes the value types not involved, where:

[0135] V G1 = x, indicating that the logic value of the first control voltage is equal to the logic value corresponding to the initial resistance state of the third magnetic tunnel junction (for example, when the initial resistance state of the third magnetic tunnel junction is a low resistance state, that is, x = 0, then V G1 =0, that is, the first control voltage applied must meet the second preset voltage threshold; when the initial resistance state of the third magnetic tunnel junction is high resistance, that is, x=1, then V G1 =1, that is, the applied first control voltage must meet the first preset voltage threshold).

[0136] V G3 =1, indicating that the logic value of the third control voltage is "1", that is, the applied third control voltage must meet the first preset voltage threshold (for example, 0.6V); V G3 =0 indicates that the logic value of the third control voltage is "0", that is, the applied third control voltage must meet the second preset voltage threshold (for example, 0V); V G3 =p indicates that the logic value of the third control voltage is equal to the logic value corresponding to the initial resistance state of the first magnetic tunnel junction (for example, when the initial resistance state of the first magnetic tunnel junction is a low resistance state, p=0, then V G3 =0, that is, the applied third control voltage must meet the second preset voltage threshold; when the initial resistance state of the first magnetic tunnel junction is high resistance, p=1, then V G3 =1, that is, the applied third control voltage must meet the first preset voltage threshold); V G3 =q means that the logic value of the first control voltage is equal to the logic value corresponding to the initial resistance state of the second magnetic tunnel junction (for example, when the initial resistance state of the second magnetic tunnel junction is a low resistance state, that is, q=0, then VG3 = 0, i.e. the third control voltage to be applied has to satisfy the second preset voltage threshold; when the initial resistance state of the second magnetic tunnel junction is high resistance state, i.e. q = 1, then V G3 = 1, i.e. the third control voltage to be applied has to satisfy the first preset voltage threshold); V G3 = x, indicating that the logic value of the third control voltage is equal to the logic value corresponding to the initial resistance state of the third magnetic tunnel junction; V G3 = pi, indicating that the logic value of the third control voltage is equal to the logic value corresponding to the resistance state of the first magnetic tunnel junction after the first step write sub-operation; V G3 = x2, indicating that the logic value of the third control voltage is equal to the logic value corresponding to the resistance state of the third magnetic tunnel junction after the second step write sub-operation; = x2, indicating that the logic value of the third control voltage is equal to the logic value corresponding to the resistance state of the third magnetic tunnel junction after the second step write sub-operation.

[0137] I = pi, indicating that the logic value of the control current is equal to the logic value corresponding to the resistance state of the first magnetic tunnel junction after the first step write sub-operation; I = pi, indicating that the logic value of the control current is equal to the logic value corresponding to the resistance state of the first magnetic tunnel junction after the first step write sub-operation;

[0138] In some alternatives of the embodiment, the five-step write operation includes a first step write sub-operation, a second step write sub-operation, a third step write sub-operation, a fourth step write sub-operation and a fifth step write sub-operation, wherein:

[0139] As shown in Table 3, the first step write sub-operation includes setting the V G1 = 0, V G2 = 0, V G3 = x, I = q; after the first step write sub-operation is performed, the second step write sub-operation includes setting the V G1 = 0, V G2 = x, V G3 = 0, After the second step write sub-operation is performed, the third step write sub-operation includes setting the V G1 = 0, V G2 = q2, V G3 = 0, I = p, after the third step write sub-operation is performed, the fourth step write sub-operation includes setting the V G1 = q2, V G2 = 0, V G3 = 0, After the fourth step write sub-operation is performed, the fifth step write sub-operation includes setting the VG1 =0, V G2 =0, I=q3, such as Figure 7 As shown, after the logic operation is completed, the sum of the logic outputs is stored in the first magnetic tunnel junction in the form of a resistance state, and the carry of the logic output is stored in the third magnetic tunnel junction in the form of a resistance state, and the spin logic device realizes a full adder operation;

[0140] Wherein, q2 is the resistance state of the second magnetic tunnel junction after the second-step write sub-operation; x1 is the resistance state of the third magnetic tunnel junction after the first-step write sub-operation; q3 is the resistance state of the second magnetic tunnel junction after the third-step write sub-operation; I=q3 indicates that the logic value of the control current is equal to the logic value corresponding to the resistance state of the second magnetic tunnel junction after the third-step write sub-operation; V G3 =x1, indicating that the logic value of the third control voltage is equal to the logic value corresponding to the resistance state of the third magnetic tunnel junction after the first write sub-operation; The logic value of the third control voltage is equal to the inverse value of the logic value corresponding to the resistance state of the third magnetic tunnel junction after the first write sub-operation; V G1 =q2 indicates that the logic value of the first control voltage is equal to the logic value corresponding to the resistance state of the second magnetic tunnel junction after the second step write sub-operation; V G2 =q2 indicates that the logic value of the second control voltage is equal to the logic value corresponding to the resistance state of the second magnetic tunnel junction after the second writing sub-operation.

[0141] In some optional embodiments of this embodiment, such as Figure 8 As shown, when n=4, the spin logic device includes a first magnetic tunnel junction MTJ1, a second magnetic tunnel junction MTJ2, a third magnetic tunnel junction MTJ3 and a fourth magnetic tunnel junction MTJ4 grown on the spin-orbit moment channel layer, and the initial resistance state of the first magnetic tunnel junction is defined as p, the initial resistance state of the second magnetic tunnel junction is defined as q, the initial resistance state of the third magnetic tunnel junction is defined as x, and the initial resistance state of the fourth magnetic tunnel junction is defined as y, and the p, q, x and y are used as four logic input variables of the logic operation; the peripheral control circuit is used to apply a first control voltage V to the first magnetic tunnel junction G1 , applying a second control voltage V to the second magnetic tunnel junction G2 , applying a third control voltage V to the third magnetic tunnel junction G3 , applying a fourth control voltage V to the fourth magnetic tunnel junction G4 And controlling the current I to perform a six-step write operation on the first magnetic tunnel junction, the second magnetic tunnel junction, the third magnetic tunnel junction and the fourth magnetic tunnel junction, wherein the six-step write operation is used for the spin logic device to implement a multiplier operation.

[0142] In some alternatives of the embodiment, the six-step write operation includes a first-step write sub-operation, a second-step write sub-operation, a third-step write sub-operation, a fourth-step write sub-operation, a fifth-step write sub-operation and a sixth-step write sub-operation, wherein:

[0143] As shown in Table 3, the first-step write sub-operation includes setting the V G1 = 1, V G2 = 1, V G3 = 1, V G4 = 1, I = 0; after the first-step write sub-operation is executed, the second-step write sub-operation includes setting the V G1 = y, V G2 = x, V G3 = 0, V G4 = 0, I = p; after the second-step write sub-operation is executed, the third-step write sub-operation includes setting the V G1 = 0, V G2 = 0, V G3 = x, V G4 = y, I = q, after the third-step write sub-operation is executed, the fourth-step write sub-operation includes setting the V G1 = 0, V G2 = 0, V G3 = p2, V G4 = 0, after the fourth-step write sub-operation is executed, the fifth-step write sub-operation includes setting the V G1 = p2, V G2 = 0, V G3 = 0, V G4 = 0, I = x3, after the fifth-step write sub-operation is executed, the sixth-step write sub-operation includes setting the V G1 = 0, V G2 = p5, V G3 = 0, V G4 = 0, The spin logic device implements a multiplier operation;

[0144] wherein the p2 is a resistance state of the first magnetic tunnel junction after the second-step write sub-operation; the x3 is a resistance state of the third magnetic tunnel junction after the third-step write sub-operation; the q2 is a resistance state of the second magnetic tunnel junction after the second-step write sub-operation; the p5 is a resistance state of the first magnetic tunnel junction after the fifth-step write sub-operation;

[0145] wherein V G1 = y indicates that a logic value of the first control voltage is equal to a logic value corresponding to an initial resistance state of the fourth magnetic tunnel junction, V G4=0, indicating that the logic value of the fourth control voltage is 0, that is, the applied fourth control voltage must meet the second preset voltage threshold; V G4 =1, indicating that the logic value of the fourth control voltage is 1, that is, the applied fourth control voltage must meet the first preset voltage threshold; V G4 =y, indicating that the logic value of the fourth control voltage is equal to the logic value corresponding to the initial resistance state of the fourth magnetic tunnel junction. The description of other values ​​is similar to the above, and this application will not repeat them here.

[0146] In addition, as shown in Table 5, it is a schematic table of the MTJ storage values ​​after the half adder, half subtractor, full adder, and full subtractor are executed according to the steps shown in Table 3 (i.e., the resistance state of each MTJ after each step). Taking the half adder as an example, step 1 (the first step of writing the sub-operation) is actually performing an XOR operation on MTJ1, and step 2 (the second step of writing the sub-operation) is actually performing an AND operation on MTJ2. In addition, p1 is the resistance state of MTJ1 after step 1, and q2 is the resistance state of MTJ2 after step 2. Referring to Table 5, in the full subtractor, p1 = p XOR q; q2 = p RNIMP q. The interpretation of the remaining storage values ​​is similar and will not be described in detail in this application.

[0147] like Figure 9 As shown, the 4-bit MTJ realizes the function of a 2-bit multiplier, A1A0*B1B0=Y3Y2Y1Y0. Before the logic operation, MTJ1, MTJ2, MTJ3 and MTJ4 store A1 (i.e. p), A0 (i.e. q), B1 (i.e. x) and B0 (i.e. y). It should be noted that after the logic operation is completed, MTJ1, MTJ2, MTJ3 and MTJ4 store Y3, Y2, Y1 and Y0 respectively.

[0148] Table 5

[0149]

[0150] Table 6

[0151]

[0152] Taking the multiplier as an example, as shown in Table 6, it is a schematic table of the storage values ​​of each MTJ after the multiplier is executed according to each step shown in Table 3 (that is, the resistance state of each MTJ after each step); wherein, the logic input is (p, q, x, y), the five-step operation (V G1 ,V G2 ,V G3 ,V G4 ,I) are (1,1,1,1,0), (y,x,0,0,p), (0,0,x,y,q), (p2,0,0,0,x3) and After that, MTJ1, MTJ2, MTJ3 and MTJ4 store Y3, Y2, Y1 and Y0 respectively, that is, the multiplication operation is completed; after the logic operation is completed, MTJ1, MTJ2, MTJ3 and MTJ4 store Y3, Y2, Y1 and Y0 respectively. Wherein, Y3=A1B0A0B1, Y2=A1B0A0B1XOR A1B1, Y1=A0B1 XOR A1B0, Y0=A0B0.

[0153] The application proposes an innovative storage and calculation integrated architecture based on a spintronic device, which combines spin-orbit torque-magnetic random access memory (SOT-MRAM) and voltage-controlled magnetic anisotropy (VCMA) technology, fundamentally solves the problems of high power consumption, high integration difficulty and complex operation of current in-memory computing technology, and realizes comprehensive Boolean logic operation, adder and multiplier functions under different bit positions, further improving device performance and integration.

[0154] The core of the application is a logic design for in-memory computing suitable for magnetic storage devices. The device manufactures a plurality of magnetic tunnel junctions (MTJs) on a spin-orbit torque channel layer, each MTJ serving as a storage unit. The MTJ is composed of two ferromagnetic layers sandwiching a very thin insulating layer. The magnetization direction of the ferromagnetic layer is precisely controlled to intuitively represent the logic state. When the magnetization directions of the upper and lower ferromagnetic layers are parallel, it is set to logic "0" state; when they are anti-parallel, it corresponds to logic "1" state. The logic input is presented in the form of resistance state, and the logic output is also saved in the form of resistance state inside the device, thereby realizing true storage and calculation integration. During data writing, the spin-orbit torque effect and the voltage-controlled magnetic anisotropy effect are combined to greatly reduce the writing power consumption. In a plurality of MTJ arrays, the VCMA technology realizes efficient selection of specific units.

[0155] Among them, in terms of logic operation, the application comprehensively covers functions from basic Boolean logic to complex arithmetic operation: 16 kinds of full Boolean logic operations are realized in 2bit MTJ, and half adder and half subtracter functions are supported, providing a complete solution for basic logic operation; full adder and full subtracter functions are further realized in 3bit MTJ, meeting the needs of higher level arithmetic operation; in 4bit MTJ, multiplier function is realized, expanding the computing capacity of the device. This design not only covers comprehensive functions from simple logic to complex calculation, but also fully utilizes the comprehensive advantages of spin in-memory logic and VCMA technology, significantly improving the device performance and integration, and providing a comprehensive innovative solution for the development of next-generation magnetic storage devices.

[0156] The embodiment of the present application also provides a logic operation method based on a spin logic device, as described in the following embodiment. Since the principle of solving problems of the logic operation method is similar to that of the spin logic device, implementation of the logic operation method can refer to implementation of the spin logic device, and repeated parts will not be described herein.

[0157] Specifically, as shown in the figure, Figure 10 the logic operation method comprises:

[0158] Step 10, reading initial resistance states of each magnetic tunnel junction as logic inputs before logic operation;

[0159] Step 20, during logic operation, applying different control currents and voltages to each magnetic tunnel junction according to a type of logic operation;

[0160] Step 30, after logic operation, storing logic outputs in the form of resistance states in designated magnetic tunnel junctions in situ.

[0161] The peripheral control circuit applies control currents and voltages to each magnetic tunnel junction to change resistance states of each magnetic tunnel junction, wherein the resistance states of each magnetic tunnel junction are used to define logic states corresponding to the magnetic tunnel junction.

[0162] In some optional manners of the embodiment, when n=2, the peripheral control circuit applies a first control voltage V G1 to the first magnetic tunnel junction, a second control voltage V G2 to the second magnetic tunnel junction, and a control current I to perform one-step write operation or two-step write operation on the first magnetic tunnel junction and the second magnetic tunnel junction, wherein:

[0163] The one-step write operation is used for the spin logic device to implement TRUE logic operation, FALSE logic operation, COPY p logic operation, COPY q logic operation, NOT p logic operation, NOT q logic operation, AND logic operation, OR logic operation, NIMP logic operation, RIMP logic operation, XNOR logic operation, IMP logic operation, RNIMP logic operation, and half subtractor operation; and the two-step write operation is used for the spin logic device to implement NOR logic operation, NAND logic operation, and half adder operation.

[0164] When n=3, the peripheral control circuit applies a first control voltage V G1 to the first magnetic tunnel junction, a second control voltage V G2 to the second magnetic tunnel junction, and a third control voltage V G3 to the third magnetic tunnel junction.and control current I to perform a three-step write operation or a five-step write operation on the first magnetic tunnel junction, the second magnetic tunnel junction and the third magnetic tunnel junction, wherein the three-step write operation is used for the spin logic device to implement a full subtracter operation; and the five-step write operation is used for the spin logic device to implement a full adder operation.

[0165] When n = 4, the peripheral control circuit applies a first control voltage V G1 to the first magnetic tunnel junction, a second control voltage V G2 to the second magnetic tunnel junction, a third control voltage V G3 to the third magnetic tunnel junction, a fourth control voltage V G4 to the fourth magnetic tunnel junction, and controls current I to perform a six-step write operation on the first magnetic tunnel junction, the second magnetic tunnel junction, the third magnetic tunnel junction and the fourth magnetic tunnel junction, wherein the six-step write operation is used for the spin logic device to implement a multiplier operation.

[0166] Since the principle of solving problems of the logic operation method is similar to the above spin logic device, the implementation of the method can be referred to the implementation of the aforementioned spin logic device, which will not be described here.

[0167] It can be understood that the above examples are only examples listed for better understanding the technical solutions of the embodiments of the present application, and are not the only limitation of the embodiments of the present application.

[0168] It should be noted that in the description of the present application, the terms "upper", "lower" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0169] It should also be noted that in the description of the present application, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitation, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0170] In the embodiments of the present application, the singular form "a", "an" and "the" include the plural form, should be broadly understood as "one" or "a kind of", and not limited to the meaning of "one"; in addition, the term "said" should be understood to include both singular and plural forms, unless the context clearly indicates otherwise. In addition, the term "according to" should be understood as "at least partially according to", and the term "based on" should be understood as "at least partially based on", unless the context clearly indicates otherwise.

[0171] It should be understood that the steps shown above can be reordered, added or deleted. For example, the steps described in the present disclosure can be executed in parallel, sequentially or in different order, as long as the desired results of the technical solutions of the present disclosure can be achieved, which is not limited herein.

[0172] The above specific embodiments do not constitute a limitation on the protection scope of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

[0173] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application, and it should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A spin logic device, characterized in that: The device comprises a spin-orbit moment channel layer, n magnetic tunnel junctions grown on the spin-orbit moment channel layer, and a peripheral control circuit, wherein: The peripheral control circuit applies a control current and a control voltage to the magnetic tunnel junction, wherein the control current generates a spin-orbit moment effect in the spin-orbit moment channel layer, and the control voltage generates a voltage-controlled magnetic anisotropy effect in the magnetic tunnel junction, which is used to control the magnetization direction of the magnetic tunnel junction, so that the spin logic device implements 16 types of Boolean logic, adder, subtractor and multiplier logic operations; Before the logic operation, the initial resistance state of each magnetic tunnel junction is read as the logic input; during the logic operation, different control currents and voltages are applied to each magnetic tunnel junction for regulation according to the type of logic operation; after the logic operation is completed, the logic output is stored in situ in the specified magnetic tunnel junction in the form of a resistance state.

2. The spin logic device according to claim 1, wherein When the resistance state of the magnetic tunnel junction is a low resistance state, the control voltage satisfies a first preset voltage threshold and the control current satisfies a first preset current threshold, based on the effect of the control voltage on lowering the potential barrier, the resistance state of the magnetic tunnel junction can be flipped from the low resistance state to the high resistance state; when the control voltage satisfies a second preset voltage threshold and the control current satisfies a first preset current threshold, the resistance state of the magnetic tunnel junction cannot be flipped from the low resistance state to the high resistance state; When the resistance state of the magnetic tunnel junction is a high resistance state, the control voltage satisfies a first preset voltage threshold and the control current satisfies a second preset current threshold, based on the effect of the control voltage on lowering the potential barrier, the resistance state of the magnetic tunnel junction can be flipped from a high resistance state to a low resistance state; when the control voltage satisfies a second preset voltage threshold and the control current satisfies a second preset current threshold, the resistance state of the magnetic tunnel junction cannot be flipped from a high resistance state to a low resistance state.

3. The spin logic device according to claim 1, wherein: When n=2, the spin logic device includes a first magnetic tunnel junction and a second magnetic tunnel junction grown on the spin-orbit moment channel layer, wherein the initial resistance state of the first magnetic tunnel junction is defined as p, and the initial resistance state of the second magnetic tunnel junction is defined as q, and the p and q are used as two logical input variables of the logic operation; the peripheral control circuit is used to apply a first control voltage V to the first magnetic tunnel junction G1 , applying a second control voltage V to the second magnetic tunnel junction G2 and controlling the current I to perform a one-step write operation or a two-step write operation on the first magnetic tunnel junction and the second magnetic tunnel junction, wherein: The one-step write operation is used for the spin logic device to implement a TRUE logic operation, a FALSE logic operation, a COPY p logic operation, a COPY q logic operation, a NOT p logic operation, a NOT q logic operation, an AND logic operation, an OR logic operation, a NIMP logic operation, a RIMP logic operation, an XNOR logic operation, an XOR logic operation, an IMP logic operation, a RNIMP logic operation, and a half-subtractor operation; The two-step write operation is used for the spin logic device to implement NOR logic operation, NAND logic operation and half adder operation.

4. The spin logic device according to claim 1, wherein When n=3, the spin logic device includes a first magnetic tunnel junction, a second magnetic tunnel junction, and a third magnetic tunnel junction grown in the spin-orbit moment channel layer, wherein the initial resistance state of the first magnetic tunnel junction is defined as p, the initial resistance state of the second magnetic tunnel junction is defined as q, and the initial resistance state of the third magnetic tunnel junction is defined as x, and the p, q, and x are used as three logic input variables of a logic operation; The peripheral control circuit is configured to apply a first control voltage V to the first magnetic tunnel junction G1 , applying a second control voltage V to the second magnetic tunnel junction G2 , applying a third control voltage V to the third magnetic tunnel junction G3 and controlling the current I to perform a three-step write operation or a five-step write operation on the first magnetic tunnel junction, the second magnetic tunnel junction, and the third magnetic tunnel junction; The three-step write operation is used for the spin logic device to implement a full subtractor operation; and the five-step write operation is used for the spin logic device to implement a full adder operation.

5. The spin logic device according to claim 1, wherein When n=4, the spin logic device includes a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction, and a fourth magnetic tunnel junction grown on the spin-orbit moment channel layer, wherein the initial resistance state of the first magnetic tunnel junction is defined as p, the initial resistance state of the second magnetic tunnel junction is defined as q, the initial resistance state of the third magnetic tunnel junction is defined as x, and the initial resistance state of the fourth magnetic tunnel junction is defined as y, and the p, q, x, and y are used as four logic input variables of a logic operation; The peripheral control circuit is configured to apply a first control voltage V to the first magnetic tunnel junction G1 , applying a second control voltage V to the second magnetic tunnel junction G2 , applying a third control voltage V to the third magnetic tunnel junction G3 , applying a fourth control voltage V to the fourth magnetic tunnel junction G4 and controlling the current I to perform a six-step write operation on the first magnetic tunnel junction, the second magnetic tunnel junction, the third magnetic tunnel junction, and the fourth magnetic tunnel junction; The six-step write operation is used for the spin logic device to implement a multiplier operation.

6. The spin logic device according to claim 3, wherein: The one-step write operation includes: Let the V G1 =1, V G2 =0, I=1, after the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device realizes a TRUE logic operation; Let the V G1 =1, V G2 =0, I=0, after the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a FALSE logic operation; Let the V G1 =0, V G2 =0, I=0, after the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements the COPY p logic operation; Let the V G1 =1, V G2 =0, I=q, after the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements the COPY q logic operation; Let the V G1 =1, V G2 =0, After the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a NOT p logic operation; Let the V G1 =1, V G2 =0, After the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a NOT q logic operation; Let the V G1 =p, V G2 =0, I=q, after the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device realizes an AND logic operation; Let the V G2 =0, I=q, after the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements an OR logic operation; Let the V G1 =p, V G2 =0, After the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements the NIMP logic operation; Let the V G2 =0, After the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements the RIMP logic operation; Let the V G2 =0, After the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements an XNOR logic operation; Let the V G1 =q,V G2 =0, After the logic operation is completed, the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the spin logic device implements an XOR logic operation; Let the V G1 =0, I=1, after the logic operation is completed, the logic output is stored in the second magnetic tunnel junction in the form of a resistance state, and the spin logic device implements an IMP logic operation; Let the V G1 =0, V G2 =p, After the logic operation is completed, the logic output is stored in the second magnetic tunnel junction in the form of a resistance state, and the spin logic device implements the RNIMP logic operation; Let the V G1 =q,V G2 =p, After the logic operation is completed, the difference of the logic output is stored in the first magnetic tunnel junction in the form of a resistance state, and the borrow of the logic output is stored in the second magnetic tunnel junction in the form of a resistance state. The spin logic device implements a half-subtractor operation.

7. The spin logic device according to claim 3, wherein: The two-step write operation includes a first-step write sub-operation and a second-step write sub-operation, wherein: The first step of writing sub-operation includes setting the V G1 =0, After the first step of writing sub-operation is completed, the second step of writing sub-operation includes setting the V G1 =0, V G2 =p, After the logic operation is completed, the logic output is stored in the second magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a NOR logic operation; The first step of writing sub-operation includes setting the V G1 =0, V G2 =p, After the first step of writing sub-operation is completed, the second step of writing sub-operation includes setting the V G1 =0, After the logic operation is completed, the logic output is stored in the second magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a NAND logic operation; The first step of writing sub-operation includes setting the V G1 =q,V G2 =0, After the first step of writing sub-operation is completed, the second step of writing sub-operation includes setting the V G1 =0, V G2 =q, I=p; after the logic operation is completed, the sum of the logic outputs is stored in the first magnetic tunnel junction in the form of a resistance state, and the carry of the logic output is stored in the second magnetic tunnel junction in the form of a resistance state, and the spin logic device realizes a half adder operation.

8. The spin logic device according to claim 4, wherein: The three-step write operation includes a first write sub-operation, a second write sub-operation, and a third write sub-operation, wherein: The first step of writing sub-operation includes setting the V G1 =q,V G2 =p, V G3 =0, After the first step of writing sub-operation is completed, the second step of writing sub-operation includes setting the V G1 =x,V G2 =0, V G3 =p1, After the second step of writing sub-operation is completed, the third step of writing sub-operation includes setting the V G1 =0, V G2 =0, I=q2, after the logic operation is completed, the difference of the logic output is stored in the first magnetic tunnel junction in the form of a resistive state, and the borrow of the logic output is stored in the third magnetic tunnel junction in the form of a resistive state, and the spin logic device implements a full subtractor operation; Wherein, p1 is the resistance state of the first magnetic tunnel junction after the first write sub-operation; x2 is the resistance state of the third magnetic tunnel junction after the second write sub-operation; q2 is the resistance state of the second magnetic tunnel junction after the second write sub-operation; The five-step write operation includes a first write sub-operation, a second write sub-operation, a third write sub-operation, a fourth write sub-operation, and a fifth write sub-operation, wherein: The first step of writing sub-operation includes setting the V G1 =0, V G2 =0, V G3 = x, I = q; after executing the first step of writing sub-operation, the second step of writing sub-operation includes setting the V G1 =0, V G2 =x,V G3 =0, After the second step of writing sub-operation is completed, the third step of writing sub-operation includes setting the V G1 =0, V G2 =q2, V G3 = 0, I = p, after the third step of writing sub-operation is completed, the fourth step of writing sub-operation includes setting the V G1 =q2, V G2 =0, V G3 =0, After the fourth step of writing sub-operation is completed, the fifth step of writing sub-operation includes setting the V G1 =0, V G2 =0, I=q3, after the logic operation is completed, the sum of the logic outputs is stored in the first magnetic tunnel junction in the form of a resistance state, and the carry of the logic output is stored in the third magnetic tunnel junction in the form of a resistance state, and the spin logic device implements a full adder operation; Among them, q2 is the resistance state of the second magnetic tunnel junction after the second-step write sub-operation; x1 is the resistance state of the third magnetic tunnel junction after the first-step write sub-operation; and q3 is the resistance state of the second magnetic tunnel junction after the third-step write sub-operation.

9. The spin logic device according to claim 5, wherein: The six-step write operation includes a first write sub-operation, a second write sub-operation, a third write sub-operation, a fourth write sub-operation, a fifth write operation, and a sixth write sub-operation, wherein: The first step of writing sub-operation includes setting the V G1 =1, V G2 =1, V G3 =1, V G4 =1, I=0; after executing the first step of writing sub-operation, the second step of writing sub-operation includes setting the V G1 =y,V G2 =x,V G3 =0, V G4 = 0, I = p; after the second step of writing sub-operation is performed, the third step of writing sub-operation includes setting the V G1 =0, V G2 =0, V G3 =x,V G4 =y, I=q, after executing the third step of writing sub-operation, the fourth step of writing sub-operation includes setting the V G1 =0, V G2 =0, V G3 =p2,V G4 =0, After the fourth step of writing sub-operation is completed, the fifth step of writing sub-operation includes setting the V G1 =p2,V G2 =0, V G3 =0, V G4 =0, I=x3, after executing the fifth step of writing sub-operation, the sixth step of writing sub-operation includes setting the V G1 =0, V G2 =p5, V G3 =0, V G4 =0, The spin logic device implements a multiplier operation; Among them, p2 is the resistance state of the first magnetic tunnel junction after the second-step write sub-operation; x3 is the resistance state of the third magnetic tunnel junction after the third-step write sub-operation; q2 is the resistance state of the second magnetic tunnel junction after the second-step write sub-operation; p5 is the resistance state of the first magnetic tunnel junction after the fifth-step write sub-operation.

10. A logic operation method based on the spin logic device according to any one of claims 1 to 9, characterized in that: include: Before the logic operation, reading the initial resistance state of each magnetic tunnel junction as a logic input; During a logic operation, different control currents and control voltages are applied to each magnetic tunnel junction for regulation according to the type of the logic operation; After the logic operation is completed, the logic output is stored in situ in the specified magnetic tunnel junction in the form of a resistance state.

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