Arithmetic circuit, nonvolatile memory, and method for controlling arithmetic circuit

Abstract

The present invention reduces power consumption in an arithmetic circuit that uses a magnetoresistance effect element.　This arithmetic circuit comprises an arithmetic element and a control circuit. The arithmetic element includes a magnetoresistance effect element the magnetization direction of which is reversed by a voltage controlled magnetic anisotropy (VCMA) effect. The control circuit performs input processing for sequentially inputting, to the arithmetic element, a plurality of bits to be computed in a predetermined logical operation, and after the input processing, output processing for causing the arithmetic element to output one-bit output data indicating the result of the logical operation.

Description

Arithmetic circuit, nonvolatile memory, and method for controlling arithmetic circuit

[0001] The present technology relates to an arithmetic circuit, and more particularly to an arithmetic circuit that performs logical operations, a nonvolatile memory, and a control method for the arithmetic circuit.

[0002] Conventionally, magnetoresistive effect elements such as MTJ (Magnetic Tunnel Junction) elements have been used in nonvolatile memories and the like. For example, a two-input arithmetic circuit using a toggle MRAM (Magnetoresistive RAM) MTJ element, which is flipped using a magnetic field induced by a current, has been proposed (see, for example, Patent Document 1). In this arithmetic circuit, two input lines are connected to one MTJ element, and control is performed to either pass a current in a predetermined direction through one input line or stop the current, and to pass a current in a direction opposite to the predetermined direction through the other input line or stop the current. By these controls, the resistance state of the MTJ element is flipped when a current flows through only one of the two input lines.

[0003] Japanese Patent Application Laid-Open No. 2007-22854

[0004] In the above-mentioned conventional technology, the exclusive OR operation is realized by controlling the currents of the two input lines. However, the above-mentioned operation circuit has a problem in that it consumes a large amount of power because it uses a magnetic field induced by the current.

[0005] This technology was developed in light of these circumstances, and aims to reduce power consumption in arithmetic circuits that use magnetoresistive elements.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an arithmetic circuit including an arithmetic element including a magnetoresistive effect element whose magnetization direction is reversed by the VCMA (Voltage Controlled Magnetic Anisotropy) effect, and a control circuit that performs an input process of sequentially inputting a plurality of bits to be operated on by a predetermined logical operation to the arithmetic element, and an output process of causing the arithmetic element to output one-bit output data indicating the result of the logical operation after the input process, and a control method thereof, which has the effect of reducing power consumption.

[0007] In this first aspect, the logical operation may include an exclusive OR operation, thereby providing an effect that the exclusive OR is operated with low power consumption.

[0008] In this first aspect, the logical operation may include a logical product operation, thereby providing an effect that the logical product is operated with low power consumption.

[0009] In this first aspect, the logical operation may include a logical sum operation, thereby providing an effect that the logical sum is calculated with low power consumption.

[0010] In addition, in the first aspect, the device may further comprise a bias voltage generating circuit that generates a bias voltage under the control of the control circuit, thereby providing the effect of reversing the magnetization direction of the magnetoresistive element by the bias voltage.

[0011] In this first aspect, the bias voltage may include an initialization voltage, and the bias voltage generation circuit may perform, before the input process, a read process of reading out a bit held in the magnetoresistive element, and an initialization process of applying the initialization voltage if the read bit has a specific logical value and not applying the initialization voltage if the read bit does not have the specific logical value, thereby achieving the effect of initializing the magnetoresistive element with low power consumption.

[0012] In addition, in this first aspect, the bias voltage may include first and second bias voltages, and the computing element may include the magnetoresistive element and a selection transistor connected in series between a first input node to which the first bias voltage is input and a second input node to which the second bias voltage is input, thereby achieving an computing element with three inputs.

[0013] In addition, in this first aspect, the computing element may include the magnetoresistive element and a selection transistor connected in series between an input node to which the bias voltage is input and a ground node, thereby achieving an effect of realizing a two-input computing element.

[0014] In this first aspect, the selection transistor may be an n-channel metal oxide semiconductor (nMOS) transistor, and the magnetoresistive element may be inserted between the nMOS transistor and the input node, thereby achieving a two-input arithmetic element.

[0015] In this first aspect, the selection transistor may be a p-channel MOS (p-channel MOS) transistor, and the magnetoresistive element may be inserted between the pMOS transistor and the ground node, thereby achieving an operation element with two inputs.

[0016] In addition, in this first aspect, the arithmetic element may include first and second arithmetic elements, the first arithmetic element having a first logic gate, the second arithmetic element having a second logic gate, and the first and second arithmetic elements may share an output circuit that outputs the output data to the control circuit and a selector that selects either the output circuit or the first or second logic gate and connects it to the output circuit, thereby providing an effect of reducing the circuit scale and circuit area.

[0017] In the first aspect, the magnetoresistive element may include a pinned layer, a free layer, and a tunnel barrier layer, thereby providing the effect of reversing the magnetization direction of the free layer due to the VCMA effect.

[0018] In the first aspect, the magnetoresistive element may include a pair of a free layer and a tunnel barrier layer whose magnetization is exchange-coupled with the pinned layer, thereby providing an effect of facilitating input processing.

[0019] A second aspect of the present technology is a nonvolatile memory including a memory cell array in which a predetermined number of memory cells are arranged, each memory cell including a magnetoresistive element whose magnetization direction is reversed by the VCMA effect, and a control circuit that performs an input process of inputting a plurality of bits to be operated on by a predetermined logical operation into the memory cells in sequence, and an output process of outputting one bit of output data indicating the result of the logical operation from the memory cells after the input process, thereby reducing the power consumption of the nonvolatile memory.

[0020] In addition, in the second aspect, an error correction circuit may be further provided that detects and corrects errors in the data using the output data, thereby improving error resistance.

[0021] 1 is a block diagram showing an example configuration of an arithmetic circuit in a first embodiment of the present technology; FIG. 2 is an example perspective view of a logic gate in the first embodiment of the present technology; FIG. 3 is a cross-sectional view showing an example configuration of a magnetoresistive effect element in the first embodiment of the present technology; FIG. 4 is a diagram showing an example relationship between perpendicular magnetic anisotropy and voltage of a magnetoresistive effect element in the first embodiment of the present technology; FIG. 5 is a graph showing an example relationship between resistance value and gate voltage of a select transistor in the first embodiment of the present technology; FIG. 6 is a diagram for explaining initialization processing in the first embodiment of the present technology; FIG. 7 is a diagram for explaining input processing in the first embodiment of the present technology; FIG. 8 is a diagram for explaining output processing in the first embodiment of the present technology; FIG. 9 is a timing chart showing an example operation of the arithmetic circuit in the first embodiment of the present technology, and a circuit diagram of the arithmetic circuit; FIG. 10 is a circuit diagram showing an example configuration of an arithmetic element in a comparative example; FIG. 11 is a flowchart showing an example operation of the arithmetic circuit in the first embodiment of the present technology; FIG. 10 is a circuit diagram showing a configuration example of an arithmetic element according to a second embodiment of the present technology. FIG. 11 is a cross-sectional view showing a configuration example of a magnetoresistive effect element according to the second embodiment of the present technology. FIG. 12 is a cross-sectional view showing a configuration example of a magnetoresistive effect element according to a modified example of the second embodiment of the present technology. FIG. 13 is a diagram for explaining input processing according to a third embodiment of the present technology. FIG. 14 is a graph showing an example of the relationship between the resistance value and gate voltage of a selection transistor according to the third embodiment of the present technology. FIG. 15 is a diagram showing respective voltage divisions of the magnetoresistive effect element and the selection transistor according to the third embodiment of the present technology. FIG. 16 is a circuit diagram showing a configuration example of an arithmetic element according to a fourth embodiment of the present technology. FIG. 17 is a diagram for explaining input processing according to the fourth embodiment of the present technology. FIG. 18 is a circuit diagram showing a configuration example of an arithmetic element according to a fifth embodiment of the present technology. FIG. 19 is a diagram for explaining input processing according to the fifth embodiment of the present technology. FIG. 19 is a block diagram showing a configuration example of an arithmetic circuit according to a sixth embodiment of the present technology.Fig. 10 is a circuit diagram showing a configuration example of a calculation block according to a sixth embodiment of the present technology. Fig. 11 is a block diagram showing a configuration example of a nonvolatile memory according to a seventh embodiment of the present technology. Fig. 12 is a circuit diagram showing a configuration example of a memory cell array according to the seventh embodiment of the present technology. Fig. 13 is a block diagram showing a configuration example of a nonvolatile memory according to an eighth embodiment of the present technology. Fig. 14 is a block diagram showing a configuration example of a memory block according to the eighth embodiment of the present technology.

[0022] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example of performing a logical operation on an arithmetic element including a magnetoresistive effect element) 2. Second embodiment (an example of performing a logical operation on an arithmetic element including a magnetoresistive effect element arranged on the ground side) 3. Third embodiment (an example of performing a logical OR operation on an arithmetic element including a magnetoresistive effect element) 4. Fourth embodiment (an example of performing a logical AND operation on an arithmetic element including a magnetoresistive effect element) 5. Fifth embodiment (an example of performing a logical OR operation on a three-input arithmetic element including a magnetoresistive effect element) 6. Sixth embodiment (an example of performing a logical operation on a plurality of arithmetic elements each including a magnetoresistive effect element) 7. Seventh embodiment (an example of performing a logical operation on a memory cell including a magnetoresistive effect element) 8. Eighth embodiment (an example of performing a logical operation on a memory cell including a magnetoresistive effect element and correcting an error using output data)

[0023] 1. First Embodiment [Configuration Example of Arithmetic Circuit] Fig. 1 is a block diagram showing a configuration example of an arithmetic circuit 100 according to an embodiment of the present technology. The arithmetic circuit 100 is a circuit that performs a predetermined logical operation and is used, for example, in a communication device or a non-volatile memory. The arithmetic circuit 100 includes a control circuit 110, a bias voltage generation circuit 120, and a predetermined number of arithmetic elements 200. Each arithmetic element 200 also includes a logic gate 205 including a magnetoresistive effect element 210 and a selection transistor 220, and an output circuit 230. When two or more arithmetic elements 200 are arranged, the arithmetic elements 200 are arranged, for example, in a two-dimensional lattice pattern.

[0024] The control circuit 110 controls the bias voltage generation circuit 120 and the arithmetic element 200. Input data IN, which is the target of a predetermined logical operation, and commands instructing initialization and logical operation are input to this control circuit 110. The initialization is executed immediately before the logical operation.

[0025] The control circuit 110 controls the bias voltage generation circuit 120 with a control signal in accordance with the initialization command, and executes initialization processing to initialize the operation element 200. Furthermore, the control circuit 110 supplies input data IN and a control signal to the bias voltage generation circuit 120 in accordance with a logical operation command, and executes input processing to input the input data IN to the operation element 200.

[0026] The logical operation may be, for example, an exclusive OR. The input data IN has a data size of N bits (N is an integer equal to or greater than 2), and these bits are input one bit at a time.

[0027] After the input process, the control circuit 110 controls the bias voltage generating circuit 120 using a control signal, and executes an output process in which the processing element 200 outputs output data OUT indicating the result of the logical operation.

[0028] The bias voltage generation circuit 120 generates a gate voltage Vg and a bias voltage Vb in accordance with a control signal from the control circuit 110 and supplies them to the logic gate 205. The bias voltage generation circuit 120 supplies the bias voltage Vb over a pulse period. This voltage causes the magnetization vector of the free layer in the magnetoresistive element 210 to precess around the horizontal direction of the external magnetic field, and application of the bias voltage is stopped when the magnetization vector reverses during this precession.

[0029] In logic gate 205, magnetoresistive element 210 and selection transistor 220 are connected in series between input node 201, to which bias voltage Vb is input, and a ground node. Furthermore, selection transistor 220 is, for example, an nMOS transistor, and a gate voltage Vg is applied to its gate.

[0030] The magnetoresistive element 210 is an element whose magnetization direction is reversed by the VCMA effect. The resistance value of the magnetoresistive element 210 changes depending on the magnetization direction. For example, an MTJ element is used as the magnetoresistive element 210. An MTJ element whose magnetization direction is reversed by the VCMA effect is called a VC (Voltage-Controlled)-MTJ.

[0031] The output circuit 230 detects whether the voltage at the connection node between the magnetoresistive element 210 and the selection transistor 220 is equal to or lower than a predetermined reference voltage V ｒｅｆ The output circuit 230 outputs 1-bit data indicating whether the input voltage is higher than the reference voltage as output data OUT to the control circuit 110. The output circuit 230 may be, for example, an inverter made up of an nMOS transistor and a pMOS transistor.

[0032] 2 is an example of a perspective view of a logic gate 205 according to the first embodiment of the present technology. When two or more processing elements 200 are arranged in a two-dimensional lattice, the axis parallel to the row direction is the X axis, and the axis parallel to the column direction is the Y axis. The axis perpendicular to the X axis and the Y axis is the Z axis.

[0033] The selection transistor 220 includes a gate 221, a source 222, and a drain 223. One of the ends of the magnetoresistive element 210 is connected to a bias voltage generating circuit 120 (not shown) via a signal line 218 wired in the Z-axis direction. The other of the ends of the magnetoresistive element 210 is connected to the drain 223 via a signal line 219 wired in the Z-axis direction.

[0034] 3 is a cross-sectional view showing an example of the configuration of the magnetoresistive effect element 210 according to the first embodiment of the present technology. The magnetoresistive effect element 210 includes a pinned layer 211, a tunnel barrier layer 212, a free layer 213, and a magnetic granting layer 214. With the side connected to the bias voltage generating circuit 120 facing upward, the pinned layer 211, the tunnel barrier layer 212, the free layer 213, and the magnetic granting layer 214 are stacked in this order from top to bottom.

[0035] The pinned layer 211 is a layer that has magnetic anisotropy and an invariable magnetization direction. The magnetization direction of the pinned layer 211 is, for example, an upward direction. However, the magnetization direction may also be a downward direction.

[0036] The tunnel barrier layer 212 is a nonmagnetic layer. The free layer 213 has magnetic anisotropy and its magnetization direction is reversed by the VCMA effect. The magnetic donor layer 214 applies a magnetic field to the free layer 213 in a plane direction perpendicular to the free layer 213.

[0037] Furthermore, when the magnetization directions of the pinned layer 211 and the free layer 213 are different, the magnetoresistive element 210 is in a high-resistance state where the resistance value is higher than a predetermined value, and when the magnetization directions of the pinned layer 211 and the free layer 213 are the same, the magnetoresistive element 210 is in a low-resistance state where the resistance value is lower than a predetermined value. This magnetization direction can be changed by applying a predetermined bias voltage Vb to the magnetoresistive element 210. For example, the low-resistance state and the high-resistance state of the magnetoresistive element 210 can be associated with logical values ​​"0" and "1," respectively, to store one bit of data.

[0038] 4 is a diagram showing an example of the relationship between the perpendicular magnetic anisotropy and voltage of the magnetoresistive effect element 210 according to the first embodiment of the present technology. The vertical axis in the diagram represents the perpendicular magnetic anisotropy of the magnetoresistive effect element 210, and the horizontal axis represents the voltage applied to the magnetoresistive effect element 210. The voltage is applied so that the potential on the pinned layer 211 side of the magnetoresistive effect element 210 is higher than that on the magnetic grant layer 214 side.

[0039] As shown in the figure, the higher the voltage, the lower the perpendicular magnetic anisotropy. Note that when a voltage is applied so that the potential on the pinned layer 211 side is lower, the higher the voltage, the higher the magnetic anisotropy. This phenomenon in which the perpendicular magnetic anisotropy changes with voltage is called the VCMA effect.

[0040] V ｓｗ When a voltage lower than V is applied, the magnetoresistive element 210 has anisotropy in the perpendicular direction and maintains this state. ｓｗ When a voltage of V is applied over a pulse period, the anisotropy of the magnetoresistive element 210 disappears and the magnetization direction is reversed.ｓｗ When a voltage higher than V is applied, the magnetoresistive element 210 has anisotropy in the in-plane direction, and this state is maintained. ｓｗ The value of depends on the VCMA effect and is, for example, about 1 volt (V).

[0041] FIG. 5 shows the resistance value R of the selection transistor 220 according to the first embodiment of the present technology. ＴＲ 1 is a graph showing an example of the relationship between the resistance R and the gate voltage Vg. ＴＲ The horizontal axis in the figure represents the gate voltage Vg.

[0042] The gate voltage Vg when the selection transistor 220 is turned on is V ｏｎ The gate voltage Vg is V ｏｎ When ＴＲ is the resistance value R of the magnetoresistive element 210 ＭＴＪ is a very small value compared to

[0043] In addition, the lower the gate voltage Vg, the lower the resistance value R ＴＲ The gate voltage Vg becomes higher than V ｏｎ Resistance value R when Vg (→ L) is lower ＴＲ R ＴＲ (→L). The timing of applying Vg(→L) will be described later.

[0044] 6 is a diagram for explaining the initialization process according to the first embodiment of the present technology. In the figure, "a" indicates the resistance state of the magnetoresistive effect element 210, the bias voltage Vb, and the gate voltage Vg during the initialization process. "L" in "a" in the figure indicates a low resistance state, and "H" indicates a high resistance state. This also applies to Figures 7 and subsequent figures. In Figure 6, "b" indicates the respective voltage divisions of the magnetoresistive effect element 210 and the selection transistor 220.

[0045] When the magnetoresistive element 210 is initialized to a low resistance state, the magnetization direction of the magnetoresistive element 210 is reversed by application of a bias voltage Vb if the magnetoresistive element 210 is in a high resistance state, and is not reversed if the magnetoresistive element 210 is in a low resistance state. In order for the magnetoresistive element 210 to reverse only in the high resistance state, as illustrated in b in the same figure, the divided voltage of the magnetoresistive element 210 is V ｓｗ The combination of bias voltage and gate voltage that satisfies this condition is found.

[0046] Since the magnetoresistive element 210 and the selection transistor 220 are connected in series, the following equation holds: Vb=V ＭＴＪ +V ＴＲ ...Equation 1 V in the above equation ＭＴＪ is the voltage division of the magnetoresistive element 210, and V ＴＲ is the voltage divider of the select transistor 220.

[0047] The current I flowing through the magnetoresistive element 210 and the selection transistor 220 is expressed by the following formula: I=Vb / (R ＭＴＪ +R ＴＲ ) ...Equation 2 R in the above equation ＭＴＪ is the resistance value of the magnetoresistive element 210, and R ＴＲ is the resistance value of the selection transistor 220.

[0048] When the magnetoresistive element 210 is in a high resistance state, V ＭＴＪ V ｓｗ The current I when this occurs, that is, the current required for reversal, is I ｓｗ Then, I ｓｗ is expressed by the following formula: ｓｗ =V ｓｗ / R ＭＴＪ (H) ...Equation 3 In the above equation, R ＭＴＪ (H) is the resistance value of the magnetoresistive element 210 in the high resistance state.

[0049] I ｓｗ R required to obtain ＴＲ R ＴＲ(→L), the following equation is obtained from equations 2 and 3: ｓｗ =V ｓｗ / R ＭＴＪ (H) =Vb / (R ＭＴＪ (H) + R ＴＲ (→L)) ...Formula 4

[0050] By transforming Equation 4, the following equation is obtained: ＴＲ (→L)=(Vb / V ｓｗ -1) R ＭＴＪ (H) ...Formula 5

[0051] For example, R ＴＲ (→L) to R ＭＴＪ If the value is set to be the same as (H), then from Equation 5, the bias voltage is set to 2×V ｓｗ This 2 × V ｓｗ is the initialization voltage V ｉｎｉｔ The initialization voltage V ｉｎｉｔ When the magnetoresistive element 210 is in a high resistance state, the magnetization direction of the element is reversed by the application of the voltage V .

[0052] On the other hand, if the magnetoresistive element 210 is in a low resistance state, the initialization voltage V ｉｎｉｔ When V is applied ＭＴＪ is expressed by the following formula: ＭＴＪ =R ＭＴＪ (L) x I ｓｗ ...Equation 6 In the above equation, R ＭＴＪ (L) is the resistance value of the magnetoresistive element 210 in the low resistance state, and R ＭＴＪ (H) is a lower value.

[0053] Substituting the right side of Equation 3 into Equation 6, the following equation is obtained: V ＭＴＪ = (R ＭＴＪ (L) / R ＭＴＪ (H))V ｓｗ ...Formula 7

[0054] R ＭＴＪ (L) is R ＭＴＪ Since the voltage is lower than (H), the right side of Equation 7 is V ｓｗ Therefore, the magnetoresistive element 210 does not reverse and maintains its state.

[0055] As shown in a and b in the figure, at the time of initialization, the bias voltage generating circuit 120 converts the bias voltage Vb into the initialization voltage V ｉｎｉｔ and the gate voltage Vg is set to R ＴＲ (→L). As a result, the magnetoresistive element 210 is inverted in the high resistance state, and the magnetoresistive element 210 is not inverted in the low resistance state. As a result, the magnetoresistive element 210 is initialized to the low resistance state. The control circuit 110 can also initialize the magnetoresistive element 210 to the high resistance state.

[0056] 7 is a diagram for explaining input processing according to the first embodiment of the present technology. In the figure, a indicates the resistance state of the magnetoresistive element 210, the bias voltage Vb, the gate voltage Vg, and the output data OUT during the input processing. In the figure, b indicates a truth table of the computing element 200.

[0057] The control circuit 110 receives the n-th (n is an integer from 1 to N) bit of the N-bit input data, and controls the bias voltage generating circuit 120 according to the logical value of that bit.

[0058] As shown in the example of a in the figure, when the nth bit of the logical value "0" is input, the bias voltage generation circuit 120 sets the bias voltage Vb to 0 volts (V) (i.e., does not apply the bias voltage Vb). At this time, the value of the gate voltage Vg is arbitrary.

[0059] On the other hand, when the n-th bit of the logical value "1" is input, the bias voltage generating circuit 120 generates the bias voltage Vb as V ｓｗ is applied, and the gate voltage Vg is V ｏｎ is applied.

[0060] When Vb is 0 volts (V), that is, when the bias voltage Vb is not applied, the magnetoresistive element 210 does not invert. As a result, when the magnetoresistive element 210 is in a low resistance state (L), output data OUT of 0 volts (V) is read out, and when the magnetoresistive element 210 is in a high resistance state (H), V ＤＤ The output data OUT is read out.

[0061] On the other hand, V ｓｗ When the power supply voltage V is applied, the magnetoresistive element 210 is inverted. ＤＤ If the magnetoresistive element 210 is in a high resistance state (H), output data OUT of 0 (V) is read out.

[0062] When the output data OUT is read (in other words, output), the bias voltage Vb and the gate voltage Vg are controlled to values ​​different from those at the time of input.

[0063] A logical value of “0” is assigned to the low resistance state (L) of the magnetoresistive effect element 210, 0 volts (V) of Vb, and 0 volts (V) of OUT, and a logical value of “0” is assigned to the high resistance state (H) of the magnetoresistive effect element 210, and ｓｗ And, OUT V ＤＤ A logic value of "1" can be assigned to each of the low resistance state (L) and the high resistance state (H). In this case, 0 volts (V) and V ｓｗ , 0 volts (V) and V ＤＤ The assignment of each logical value can also be reversed.

[0064] Furthermore, if the resistance state of the magnetoresistive element 210 is input A, the bias voltage Vb is input B, and the output data OUT is output, then as illustrated in b in the figure, when only one of the inputs A and B has a logical value of 1, the output will have a logical value of 1. This output corresponds to the exclusive OR of the inputs A and B.

[0065] As shown in a and b in the figure, when inputting, the bias voltage generating circuit 120 sets the bias voltage Vb to 0 volts (V) or V ｓｗ and set the gate voltage Vg to V ｏｎ This executes an exclusive OR operation. Note that a NON-EXCLUSIVE OR operation can also be realized by reversing the logic assigned to only one of the input side (i.e., input A and input B) and the output side.

[0066] 8 is a diagram for explaining the output process according to the first embodiment of the present technology. In the figure, a indicates the resistance state of the magnetoresistive element 210, the bias voltage Vb, and the gate voltage Vg during the output process. In the figure, b indicates the respective voltage divisions of the magnetoresistive element 210 and the selection transistor 220.

[0067] As shown in FIG. 1A, the bias voltage generating circuit 120 generates the bias voltage Vb by dividing the bias voltage Vb by the initialization voltage V ｉｎｉｔ Lower read voltage V ｒｅａｄ The gate voltage Vg is set to Vg (→L) as in the initialization.

[0068] As shown in FIG. 1B, the read voltage V ｒｅａｄ By applying V, the voltage division of the magnetoresistive element 210 becomes V in both the high resistance state and the low resistance state. ｓｗ Therefore, the magnetization direction of the magnetoresistive element 210 is not reversed.

[0069] The reference voltage V of the output circuit 230 ｒｅｆ is set to a value between the divided voltage of the magnetoresistive effect element 210 in the high resistance state and the divided voltage of the magnetoresistive effect element 210 in the low resistance state. As a result, the output circuit 230 outputs output data OUT having a value according to the resistance value of the magnetoresistive effect element 210.

[0070] 9 is a timing chart showing an example of the operation of the arithmetic circuit 100 according to the first embodiment of the present technology, and a circuit diagram of the arithmetic element 200. In the figure, "a" is a timing chart showing an example of the operation of the arithmetic circuit 100, and "b" in the figure is a circuit diagram of the arithmetic element 200.

[0071] As shown in FIG. 11A, for example, it is assumed that a bit string of "111001010" is input to the arithmetic circuit 100 as input data IN.

[0072] The control circuit 110 in the arithmetic circuit 100 performs an initialization process to initialize the magnetoresistive element 210 to a low resistance state (L) corresponding to the logical value "0." "Init" in the figure indicates the initialization process.

[0073] Then, the control circuit 110 controls the bias voltage generation circuit 120 to input the first bit of the logical value "1" to the arithmetic element 200. The bias voltage generation circuit 120, under the control of the control circuit 110, ｓｗ The application of this bias voltage causes the magnetoresistive element 210 (MTJ element or the like) to invert and assume a high resistance state (H) corresponding to the logical value "1."

[0074] Next, the control circuit 110 sequentially inputs the second and third bits of logic value "1." The magnetoresistive element 210 is inverted with each input and goes into a high resistance state (H).

[0075] Then, the control circuit 110 controls the bias voltage generation circuit 120 to input the fourth bit with a logical value of "0" to the arithmetic element 200. The bias voltage generation circuit 120 sets the bias voltage to 0 volts (V) (in other words, does not apply it) according to the control of the control circuit 110. Because no bias voltage is applied, the magnetoresistive effect element 210 does not invert and maintains the high resistance state (H).

[0076] The control circuit 110 inputs the fifth bit and onwards in the same manner, and after inputting the last bit, it reads (in other words, outputs) the output data OUT. "Read" in the figure a indicates a read process. In the figure, output data with a logical value of "1" is read. This output data OUT corresponds to the exclusive OR of "111001010".

[0077] When the arithmetic circuit 100 is applied to a nonvolatile memory or a communication device, the output data OUT can be added to the input data as parity. This parity indicates whether the number of "1"s in the bit string "111001010" is odd or not, and can be used for error detection and correction in the nonvolatile memory or the communication device.

[0078] In addition to error detection and correction, the above-described calculations can also be used for pseudo-random number generation processing (such as the Xorshift method) in various information processing devices.

[0079] As shown in FIG. 1B, the logic gate 205 in the computing element 200 functions as a two-input XOR (exclusive OR) gate. Data held in the magnetoresistive element 210 in the logic gate 205 is fed back as input A of the two inputs. Input B of the two inputs is data input by the control circuit 110 via the bias voltage generation circuit 120. The control circuit 110 inputs each bit in the input data in order as input B, thereby reading out the exclusive OR of those bits.

[0080] In the circuit shown in FIG. 1B, the logic gate 205 includes one transistor, and the output circuit 230 (such as an inverter) includes two transistors. Therefore, the calculation element 200 that calculates an exclusive OR can be realized using three transistors.

[0081] Here, a comparative example is assumed in which an arithmetic element that achieves the same function as in b in the figure using only transistors, without using the magnetoresistive effect element 210, is used.

[0082] 10 is a circuit diagram showing an example of the configuration of an arithmetic element in the comparative example. For example, the arithmetic element in the comparative example includes a two-input XOR gate 280 and a flip-flop 270. The flip-flop 270 holds the bit output by the XOR gate 280 and feeds it back to the XOR gate 280 as input A. The XOR gate 280 receives its own input A and an external input B.

[0083] The XOR gate 280 also includes nMOS transistors 281 to 288. The nMOS transistors 281 to 284 are connected in series between the power supply voltage Vdd and the reference voltage Vss. The inverted value xA of input A is input to the gate of the nMOS transistor 281, and input B is input to the gate of the nMOS transistor 282. The input A is input to the gate of the nMOS transistor 283, and input B is input to the gate of the nMOS transistor 284.

[0084] Furthermore, nMOS transistors 285 to 288 are connected in series between the power supply voltage Vdd and the reference voltage Vss. Input A is input to the gate of nMOS transistor 285, and the inverted value xB of input B is input to the gate of nMOS transistor 286. The inverted value xA is input to the gate of nMOS transistor 287, and the inverted value xB is input to the gate of nMOS transistor 288.

[0085] The connection node of nMOS transistors 282 and 283 is connected to the connection node of nMOS transistors 286 and 287, and the voltages at these nodes are output as output data indicating the results of the operation.

[0086] As shown in the figure, the comparative example requires a flip-flop 270 to feed back the output to one of the two inputs, and this flip-flop 270 can be realized using, for example, eight transistors. The number of transistors in the XOR gate 280 is also eight. Therefore, the number of transistors in the arithmetic element of the comparative example is 16.

[0087] In contrast to this, when the magnetoresistive effect element 210 is used, the arithmetic element 200 can be realized with three transistors as described above. Therefore, the circuit scale and mounting area can be reduced compared to the comparative example.

[0088] Furthermore, the toggle MRAM described in Patent Document 1 consumes a large amount of power because it uses a magnetic field induced by a current to perform reversal. Furthermore, Patent Document 1 requires two input lines to be connected to one magnetoresistive element.

[0089] In contrast, in the computing element 200, the magnetoresistive effect element 210 is inverted by the VCMA effect, so that power consumption can be reduced compared to Patent Document 1. Furthermore, as illustrated in Fig. 2, only one signal line (signal line 218 in the figure) is required to be connected to the input side of the magnetoresistive effect element 210, so that the number of wirings can be reduced compared to Patent Document 1.

[0090] It is also possible to provide a plurality of arithmetic elements 200 in the arithmetic circuit 100. The control circuit 110 can then input the same input data to the plurality of arithmetic elements 200, and determine the final output data by majority vote of the outputs of the arithmetic elements 200. This can improve error resistance.

[0091] 11 is a flowchart showing an example of the operation of the arithmetic circuit 100 according to the first embodiment of the present technology. This operation is started when an initialization command is input to the arithmetic circuit 100, for example.

[0092] The control circuit 110 in the arithmetic circuit 100 initializes the magnetoresistive element 210 and sets n to an initial value (step S901). Then, when a logical operation command and input data are input, the control circuit 110 inputs the n-th bit of the input data (step S902) and determines whether input of all bits has been completed (step S903).

[0093] If input of all bits has not been completed (step S903: No), the control circuit 110 increments n (step S905) and repeats step S902 and subsequent steps.

[0094] On the other hand, if input of all bits is complete (step S903: Yes), the control circuit 110 outputs the output data (step S904) and ends the operation for the calculation.

[0095] As described above, according to the first embodiment of the present technology, bits in input data are input in order to the computing element 200 including the magnetoresistive effect element 210 whose magnetization direction is reversed by the VCMA effect, so that it is possible to reduce power consumption compared to Patent Document 1. Also, it is possible to reduce the number of wirings compared to Patent Document 1.

[0096] [First Modification] In the first embodiment described above, the bias voltage generating circuit 120 generates the initialization voltage V ｉｎｉｔHowever, it is preferable to reduce the power consumption during initialization. The arithmetic circuit 100 in the first modification of the first embodiment applies the initialization voltage V only when the bit held in the magnetoresistive element 210 is a specific logical value. ｉｎｉｔ This embodiment differs from the first embodiment in that a voltage of

[0097] 12 is a block diagram showing an example configuration of a computing element 200 according to a first modified example of the first embodiment of the present technology. The computing element 200 according to the first modified example of the first embodiment differs from the first embodiment in that it further includes a switch 240.

[0098] The switch 240 selects either the output terminal of the output circuit 230 or the bias voltage generating circuit 120 in accordance with a control signal SW from the control circuit 110 and connects it to the magnetoresistive element 210 .

[0099] 13 is a diagram for explaining the initialization process in the first modification of the first embodiment of the present technology, in which a portion a in the figure is a timing chart showing an example of the operation of the arithmetic circuit 100, and b in the figure shows the resistance state of the magnetoresistive effect element 210, the bias voltage Vb, and the gate voltage Vg during the initialization process.

[0100] As illustrated in FIG. 10A, in the first modification of the first embodiment, the control circuit 110 performs a read process to read out bits held in the magnetoresistive element 210 before the initialization process.

[0101] Then, as shown in b in the figure, when the read bit is a logical value "0" (L at b in the figure), the bias voltage generation circuit 120 sets the bias voltage Vb to 0 volts (V) (i.e., does not apply it). Since the bias voltage Vb is not applied, the magnetoresistive element 210 does not invert and maintains the low resistance state (L). The value of the gate voltage Vg at this time is arbitrary.

[0102] On the other hand, if the read bit is a logical value "1" (H of b in the figure), the bias voltage generating circuit 120 sets the bias voltage Vb to the initialization voltage V ｉｎｉｔand the gate voltage Vg is set to Vg (→L).

[0103] When no bias voltage is applied, the control circuit 110 controls the switch 240 illustrated in FIG. 12 to connect the magnetoresistive element 210 to the output circuit 230. ｉｎｉｔ When applying a bias voltage, the magnetoresistive element 210 is connected to the bias voltage generating circuit 120 .

[0104] It is also possible to eliminate the need for the switch 240 and have the control circuit 110 control only the bias voltage and gate voltage.

[0105] As illustrated in FIG. 13b, only when the read bit is a specific logic value (such as "1") that needs to be inverted, the bias voltage generating circuit 120 generates the initialization voltage V ｉｎｉｔ Therefore, even in the case of a logical value that does not require inversion (such as "0"), the initialization voltage V ｉｎｉｔ In comparison with the first embodiment in which a voltage is applied, the power consumption can be reduced.

[0106] As described above, according to the first modification of the first embodiment of the present technology, only when the read bit has a specific logical value, the bias voltage generation circuit 120 generates the initialization voltage V ｉｎｉｔ Therefore, power consumption can be reduced compared to the first embodiment.

[0107] [Second Modification] In the first embodiment described above, the bias voltage generation circuit 120 applies a bias voltage to the arithmetic element 200, and stops applying the voltage when the magnetization vector of the free layer reverses during precession of the vector. However, in the first embodiment, the pulse width of the applied voltage needs to be precisely controlled to improve the probability of successful reversal, which makes input processing difficult. The arithmetic circuit 100 in this first modification of the first embodiment differs from the first embodiment in that two free layers whose magnetizations are exchange-coupled are arranged within the magnetoresistive element 210, thereby facilitating input processing.

[0108] 14 is a cross-sectional view showing a configuration example of a magnetoresistive effect element 210 according to a second modification of the first embodiment of the present technology. The magnetoresistive effect element 210 according to the second modification of the first embodiment differs from the first embodiment in that it further includes an exchange coupling layer 215 and a free layer 216 in addition to a pinned layer 211, a tunnel barrier layer 212, a free layer 213, and a magnetic granting layer 214. For example, the pinned layer 211, the tunnel barrier layer 212, the free layer 213, the exchange coupling layer 215, the free layer 216, and the magnetic granting layer 214 are stacked in this order from top to bottom.

[0109] The magnetization of free layer 213 is exchange-coupled with free layer 216. In other words, free layers 213 and 216 are ferromagnetically coupled or antiferromagnetically coupled. In the case of ferromagnetic coupling, the magnetization directions of free layers 213 and 216 are the same, and in the case of antiferromagnetic coupling, the magnetization directions of free layers 213 and 216 are opposite to each other. Furthermore, free layer 213 has the VCMA effect, while free layer 216 does not. Note that free layers 213 and 216 are an example of a pair of free layers as defined in the claims.

[0110] When reversing the magnetization vector in the input process, for example, when the magnetization vector of the free layer 213 starts precessing due to application of a bias voltage, the exchange-coupled free layer 216 also starts precessing accordingly. Then, the bias voltage generating circuit 120 stops applying the voltage at the timing when the magnetization vector is reversed.

[0111] In the first embodiment, which has only the free layer 213, if the timing at which the application of the bias voltage is stopped is shifted from the timing at which the magnetization vector reverses, the vector may reverse again. In contrast, in the configuration illustrated in the figure, the exchange-coupled free layer 216 suppresses the reversal of the free layer 213. This eliminates the need for precise control of the pulse width, making input processing easier.

[0112] Since the free layers 213 and 216 are exchange-coupled, the magnetization directions of the free layers 213 and 216 cannot be reversed individually, and therefore each of the free layers 213 and 216 records one bit.

[0113] As described above, according to the second modification of the first embodiment of the present technology, since the exchange-coupled free layers 213 and 216 are provided, precise control of the pulse width is not required, and input processing becomes easier.

[0114] 2. Second Embodiment In the first embodiment described above, the selection transistor 220 is inserted on the ground side, but this is not limiting. The arithmetic circuit 100 in this second embodiment differs from the first embodiment in that a magnetoresistive effect element 210 is inserted on the ground side.

[0115] 15 is a circuit diagram showing a configuration example of a computing element 200 according to a second embodiment of the present technology. The computing element 200 according to the second embodiment differs from the first embodiment in that it includes a selection transistor 225 instead of the selection transistor 220. A pMOS transistor is used as the selection transistor 225.

[0116] The selection transistor 225 is inserted between the input node 201 and the magnetoresistive element 210. The magnetoresistive element 210 is inserted between the selection transistor 225 and the ground node.

[0117] In addition, since the selection transistor 225 is a pMOS transistor, when it is turned on, it is set to a low level V ｏｎ is applied.

[0118] 16 is a cross-sectional view showing a configuration example of a magnetoresistive effect element according to a modification of the second embodiment of the present technology, in which a magnetic grant layer 214, a free layer 213, a tunnel barrier layer 212, and a pinned layer 211 are stacked in this order from top to bottom, with the side connected to the ground node being the upper side.

[0119] It should be noted that the first modified example of the first embodiment can be applied to the second embodiment.

[0120] As described above, according to the second embodiment of the present technology, it is possible to reduce power consumption in the computing element 200 in which the magnetoresistive effect element 210 is inserted on the ground side.

[0121] [Modification] A second modification of the first embodiment, in which two free layers whose magnetizations are exchange-coupled are provided, can be applied to the second embodiment described above. The arithmetic circuit 100 in this modification of the second embodiment differs from the second embodiment in that two free layers whose magnetizations are exchange-coupled are provided in the magnetoresistive element 210, thereby facilitating input processing.

[0122] 17 is a cross-sectional view showing a configuration example of a magnetoresistive effect element 210 according to a modification of the second embodiment of the present technology. The magnetoresistive effect element 210 according to the modification of the second embodiment differs from the first embodiment in that it further includes an exchange coupling layer 215 and a free layer 216 in addition to the pinned layer 211, the tunnel barrier layer 212, the free layer 213, and the magnetic granting layer 214. For example, with the direction toward the ground node taken as the upward direction, the magnetic granting layer 214, the free layer 216, the exchange coupling layer 215, the free layer 213, the tunnel barrier layer 212, and the pinned layer 211 are stacked in this order from top to bottom.

[0123] In the configuration shown in the figure, the exchange-coupled free layer 216 suppresses re-inversion of the free layer 213. This eliminates the need for precise control of the pulse width, making input processing easier.

[0124] As described above, according to the modification of the second embodiment of the present technology, since the exchange-coupled free layers 213 and 216 are provided, precise control of the pulse width is not required, and input processing becomes easier.

[0125] 3. Third Embodiment In the first embodiment described above, the arithmetic circuit 100 calculates an exclusive OR, but it can also perform logical operations other than the exclusive OR. The arithmetic circuit 100 in this third embodiment differs from the first embodiment in that it calculates a logical OR.

[0126] 18 is a diagram for explaining input processing according to the third embodiment of the present technology. In the figure, a indicates the resistance state of the magnetoresistive element 210, the bias voltage Vb, the gate voltage Vg, and the output data OUT during the input processing. In the figure, b indicates the truth table of the computing element 200.

[0127] As illustrated in FIG. 11A, when a logical value "0" is input as input B, the bias voltage generating circuit 120 sets the bias voltage Vb to 0 volts (V) (i.e., does not apply it).

[0128] To realize the logical OR operation, the magnetization direction of the magnetoresistive element 210 is reversed when the magnetoresistive element 210 is in a low resistance state (L) by applying a bias voltage Vb corresponding to the logical value "1", and the magnetization direction is prevented from being reversed when the magnetoresistive element 210 is in a high resistance state (H). In order for the magnetoresistive element 210 to reverse only when it is in a low resistance state, the divided voltage of the magnetoresistive element 210 is V ｓｗ The combination of bias voltage and gate voltage that satisfies this condition is found.

[0129] Since the magnetoresistive element 210 and the selection transistor 220 are connected in series, the above-mentioned formula 1 holds.

[0130] The current I flowing through the magnetoresistive element 210 and the selection transistor 220 is expressed by the above-mentioned formula 2.

[0131] When the magnetoresistive element 210 is in a low resistance state, V ＭＴＪ V ｓｗ The current I when this occurs, that is, the current required for reversal, is I ｓｗ Then, I ｓｗ is expressed by the following formula: ｓｗ =V ｓｗ / R ＭＴＪ (L) ...Equation 8 In the above equation, R ＭＴＪ (L) is the resistance value of the magnetoresistive element 210 in the low resistance state.

[0132] I ｓｗ R required to obtain ＴＲ R ＴＲ (→H), the following equation is obtained from equations 2 and 8: ｓｗ =V ｓｗ / R ＭＴＪ (L) =Vb / (R ＭＴＪ (L) + R ＴＲ (→H)) ...Formula 9

[0133] By transforming Equation 9, the following equation is obtained: ＴＲ (→H)=(Vb / V ｓｗ -1) R ＭＴＪ (L)...Formula 10

[0134] For example, R ＴＲ (→H) to R ＭＴＪ If the value is set to be approximately the same as (L), then, from Equation 10, the bias voltage is set to 2×V ｓｗ This 2 × V ｓｗ V ＯＲ Let's say. V ＯＲ When the magnetoresistive element 210 is in a low resistance state, the magnetization direction of the element is reversed by the application of the voltage V .

[0135] On the other hand, if the magnetoresistive element 210 is in a high resistance state, V ＯＲ When V is applied ＭＴＪ is expressed by the following formula: ＭＴＪ =R ＭＴＪ (H) x I ｓｗ ...Formula 11

[0136] Substituting the right side of Equation 8 into Equation 11, the following equation is obtained: V ＭＴＪ = (R ＭＴＪ (H) / R ＭＴＪ (L))V ｓｗ ...Formula 12

[0137] R ＭＴＪ (L) is R ＭＴＪ (H), so the right side of Equation 12 is V ｓｗ Therefore, the magnetoresistive element 210 does not reverse and maintains its state.

[0138] As shown in the example of a in the figure, when the n-th bit of the logical value "0" is input, the bias voltage generating circuit 120 does not apply the bias voltage Vb.

[0139] On the other hand, when the n-th bit of the logical value "1" is input, the bias voltage generating circuit 120 sets the bias voltage Vb to V ＯＲ The gate voltage is R ＴＲ (→H) is Vg(→H).

[0140] The assignment of the logic values ​​of the resistance states and the output data OUT is the same as in the first embodiment, and the logic value “0” is assigned to 0 volts (V) of Vb, and the logic value “0” is assigned to V ＯＲ is assigned a logical value of "1".

[0141] In this case, as shown in FIG. 1B, when at least one of inputs A and B has a logical value of 1, the output has a logical value of 1. This output corresponds to the logical sum of inputs A and B.

[0142] FIG. 19 is a graph showing the resistance value R of the selection transistor 220 according to the third embodiment of the present technology. ＴＲ 1 is a graph showing an example of the relationship between the resistance R and the gate voltage Vg. ＴＲ The horizontal axis in the figure represents the gate voltage Vg. ｏｎ A gate voltage Vg(→H) which is lower and higher than Vg(→L) is applied.

[0143] FIG. 20 is a diagram showing the voltage division of the magnetoresistive element 210 and the selection transistor 220 according to the third embodiment of the present technology.

[0144] As described above, when a logic value "1" is input as input B, the bias voltage generating circuit 120 generates a bias voltage V ＯＲ and the gate voltage is set to Vg (→H). As a result, when the magnetoresistive element 210 is in a high resistance state, the divided voltage of the magnetoresistive element 210 is V ｓｗ When the magnetoresistive element 210 is in a low resistance state, the voltage division of the magnetoresistive element 210 is higher than V ｓｗ and the magnetization direction is reversed.

[0145] The first and second modifications of the first embodiment, and the second embodiment and its modifications can be applied to the third embodiment.

[0146] Furthermore, the only difference between the first and third embodiments is the control of the bias voltage generation circuit 120, and since the circuit configuration is the same, the control circuit 110 can switch between executing an exclusive OR operation and a logical OR operation.

[0147] As described above, according to the third embodiment of the present technology, when the logical value “1” is input, the bias voltage generation circuit 120 sets the bias voltage Vb and the gate voltage Vg to V ＯＲ and Vg(→H), a logical OR operation can be realized.

[0148] 4. Fourth Embodiment In the first embodiment described above, the arithmetic circuit 100 calculates an exclusive OR, but it is also possible to perform logical operations other than the exclusive OR. The arithmetic circuit 100 in this fourth embodiment differs from the first embodiment in that it calculates a logical AND.

[0149] 21 is a circuit diagram showing a configuration example of a computing element 200 according to a fourth embodiment of the present technology. The computing element 200 according to the fourth embodiment differs from the first embodiment in that it further includes an inverter 250.

[0150] An input terminal of the inverter 250 is connected to the bias voltage generation circuit 120, and an output terminal of the inverter 250 is connected to the magnetoresistive element 210. When the bias voltage generation circuit 120 sets the bias voltage Vb to 0 volts (V), the inverter 250 applies the bias voltage to the magnetoresistive element 210. When the bias voltage generation circuit 120 applies the bias voltage Vb, the inverter 250 sets the voltage to the magnetoresistive element 210 to 0 volts (V).

[0151] 22 is a diagram for explaining input processing according to the fourth embodiment of the present technology. In the figure, a indicates the resistance state of the magnetoresistive element 210, the bias voltage Vb, the gate voltage Vg, and the output data OUT during the input processing. In the figure, b indicates the truth table of the computing element 200.

[0152] As shown in the example of a in the figure, when a logical value "0" is input as input B, the bias voltage generating circuit 120 sets the bias voltage Vb to 0 volts (V) (i.e., does not apply it). At this time, the inverter 250 applies the bias voltage V ＡＮＤ is applied to the magnetoresistive element 210.

[0153] To realize the logical product operation, the application of a bias voltage Vb corresponding to the logical value "0" reverses the magnetization direction of the magnetoresistive element 210 if it is in a high resistance state (H), and prevents it from reversing if it is in a low resistance state (L).

[0154] For example, by setting the bias voltage and gate voltage to the same values ​​as those at the time of initialization, the magnetoresistive element 210 can be inverted only in the resistive state (H). For example, the inverter 250 applies a bias voltage of the same value as that at the time of initialization to V ＡＮＤ The bias voltage generating circuit 120 supplies the gate voltage as Vg (→L).

[0155] On the other hand, when the n-th bit of the logical value "1" is input as the input B, the bias voltage generating circuit 120 generates V ｓｗ The inverter 250 applies a bias voltage of 0 volts (V) (i.e., does not apply any bias voltage). The value of the gate voltage Vg at this time is arbitrary.

[0156] By the above control, when both inputs A and B have the logical value "1", the output has the logical value "1", as shown in FIG.

[0157] The first and second modifications of the first embodiment, and the second embodiment and its modifications can be applied to the fourth embodiment.

[0158] Furthermore, in the fourth embodiment, the logic assignment of input B can be reversed to eliminate the inverter 250. In this case, the circuit configuration will be similar to that of the first and second embodiments, and the control circuit 110 can switch between executing an exclusive OR operation, a logical OR operation, and a logical AND operation.

[0159] As described above, according to the fourth embodiment of the present technology, an inverter 250 is added, and when a logical value “0” is input, the bias voltage generation circuit 120 sets the gate voltage Vg to Vg (→L), thereby realizing a logical product operation.

[0160] 5. Fifth Embodiment In the first embodiment described above, the arithmetic circuit 100 executes an exclusive OR operation on two inputs, but is not limited to this configuration. The arithmetic circuit 100 in this fifth embodiment differs from the first embodiment in that it executes an exclusive OR operation on three inputs.

[0161] 23 is a circuit diagram showing a configuration example of a computing element 200 according to the fifth embodiment of the present technology. In the computing element 200 according to the fifth embodiment, a magnetoresistive effect element 210 and a selection transistor 220 are inserted in series between input nodes 201 and 202. The bias voltage generation circuit 120 inputs a bias voltage Vb to the input node 201 and a bias voltage Vc to the input node 202.

[0162] 24 is a diagram for explaining input processing according to the fifth embodiment of the present technology. In the figure, a indicates the resistance value R of the magnetoresistive effect element 210 during input processing. ＭＴＪ , bias voltage Vb, bias voltage Vc, and output data OUT. In the figure, "b" indicates the truth table of the arithmetic element 200.

[0163] As illustrated in FIG. 1A, when the bias voltages Vb and Vc are both 0 volts (V), the magnetization direction of the magnetoresistive element 210 is not reversed. Therefore, when the magnetoresistive element 210 is in a low resistance state (L), output data OUT of 0 volts (V) is output, and when the magnetoresistive element 210 is in a high resistance state (H), V ＤＤ The output data OUT is output.

[0164] In addition, the bias voltage Vb is V ｓｗ When the bias voltage Vc is 0 volts (V), the magnetization direction of the magnetoresistive element 210 is reversed. Therefore, if the magnetoresistive element 210 is in a low resistance state (L), V ＤＤ If the magnetoresistive element 210 is in a high resistance state (H), output data OUT of 0 volts (V) is output.

[0165] Also, the bias voltage Vb is 0 volts (V), and the bias voltage Vc is −V ｓｗ, the magnetization direction of the magnetoresistive element 210 is reversed. Therefore, if the magnetoresistive element 210 is in the low resistance state (L), V ＤＤ If the magnetoresistive element 210 is in a high resistance state (H), output data OUT of 0 volts (V) is output.

[0166] In addition, the bias voltage Vb is V ｓｗ And the bias voltage Vc is -V ｓｗ In this case, the magnetization direction of the magnetoresistive element 210 is not reversed. Therefore, if the magnetoresistive element 210 is in a low resistance state (L), output data OUT of 0 volts (V) is output, and if the magnetoresistive element 210 is in a high resistance state (H), V ＤＤ The output data OUT is output.

[0167] As shown in FIG. 1B, when the resistance state of the magnetoresistive element 210 is input A and the bias voltages Vb and Vc are input B and input C, respectively, an exclusive OR of three inputs can be realized.

[0168] For example, the control circuit 110 sets the bias voltage Vc to 0 volts (V) and inputs the first bit of the input data as input B. Then, the control circuit 110 inputs the second and third bits as input B and input C. From the fourth bit onwards, the data is input two bits at a time.

[0169] The fifth embodiment can be applied to the first and second modifications of the first embodiment, the second embodiment and its modifications, the third embodiment, and the fourth embodiment.

[0170] Thus, according to the fifth embodiment of the present technology, the magnetoresistive effect element 210 and the selection transistor 220 are connected in series between the input nodes 201 and 202 to which the bias voltages Vb and Vc are input, thereby realizing a three-input exclusive OR operation.

[0171] 6. Sixth Embodiment In the first embodiment described above, the logic gate 205 and the output circuit 230 are arranged in the processing element 200, but it is preferable to reduce the circuit size when arranging a plurality of processing elements 200. The processing circuit 100 in this sixth embodiment differs from the first embodiment in that a single output circuit 230 is shared by a plurality of processing elements 200.

[0172] 25 is a block diagram showing a configuration example of an arithmetic circuit 100 according to a sixth embodiment of the present technology. The arithmetic circuit 100 according to the sixth embodiment differs from the first embodiment in that a plurality of arithmetic elements, such as arithmetic elements 200-1 and 200-2, are arranged in an arithmetic block 206. Each of these arithmetic elements includes a logic gate, and shares a selector 260 and an output circuit 230. The arithmetic elements 200-1 and 200-2 are examples of the first and second arithmetic elements set forth in the claims.

[0173] Furthermore, the processing element 200-1 includes a logic gate 205-1, and the processing element 200-2 includes a logic gate 205-2. The logic gates 205-1 and 205-2 are examples of the first and second logic gates set forth in the claims.

[0174] The selector 260 selects one of a plurality of logic gates such as the logic gates 205 - 1 and 205 - 2 in accordance with a selection signal SEL from the control circuit 110 and connects it to the output circuit 230 .

[0175] 26 is a circuit diagram showing an example configuration of the operation block 206 according to the sixth embodiment of the present technology. Each of the logic gates, such as the logic gates 205-1 and 205-2, includes a magnetoresistive element 210 and a selection transistor 220 connected in series. A connection node between the magnetoresistive element 210 and the selection transistor 220 is connected to a selector 260.

[0176] The bias voltage generating circuit 120 applies a bias voltage to each of the logic gates individually. For example, a bias voltage Vb1 is applied to the logic gate 205-1, and a bias voltage Vb2 is applied to the logic gate 205-2.

[0177] As illustrated in Figures 25 and 26, by multiple arithmetic elements sharing a selector 260 and an output circuit 230, the circuit size and circuit area of ​​the arithmetic circuit 100 can be reduced compared to when an output circuit 230 is provided for each arithmetic element.

[0178] It should be noted that the first to fifth embodiments and their respective modifications can be applied to the sixth embodiment.

[0179] As described above, according to the sixth embodiment of the present technology, multiple arithmetic elements share the selector 260 and the output circuit 230, and therefore the circuit size and circuit area can be reduced compared to when an output circuit 230 is provided for each arithmetic element.

[0180] 7. Seventh Embodiment In the first embodiment described above, the arithmetic circuit 100 executes an exclusive OR operation, but it is also possible to apply this arithmetic circuit 100 to a nonvolatile memory. The seventh embodiment differs from the first embodiment in that the nonvolatile memory executes an exclusive OR operation.

[0181] 27 is a block diagram showing a configuration example of a nonvolatile memory 300 according to the seventh embodiment of the present technology. The nonvolatile memory 300 includes an input / output interface 310, a control circuit 110, a bit line address decoder 320, a bias voltage generation circuit 120, and a bit line control circuit 330. The nonvolatile memory 300 further includes a word line address decoder 340, a word line control circuit 350, a memory cell array 360, and a sense amplifier 370.

[0182] The input / output interface 310 exchanges commands, addresses, data, and the like with a host system.

[0183] The control circuit 110 in the seventh embodiment controls the bias voltage generating circuit 120 and the like in response to commands, and causes them to execute predetermined logical operations.

[0184] The bias voltage generating circuit 120 in the seventh embodiment generates a bias voltage under the control of the control circuit 110 and supplies it to the memory cell array 360 via the bit line control circuit 330 .

[0185] In the memory cell array 360, a plurality of memory cells (not shown) are arranged in a two-dimensional lattice pattern. Each memory cell includes a magnetoresistive element. The structure of the memory cells will be described in detail later. In addition, in the memory cell array 360, bit lines and source lines are wired for each column, and word lines are wired for each row.

[0186] The bit line address decoder 320 selects the bit line and source line to be accessed by decoding the address received by the input / output interface 310 .

[0187] The bit line control circuit 330 outputs a pulse signal of a bias voltage to the selected bit line and source line.

[0188] The word line address decoder 340 selects a word line to be accessed by decoding an address received by the input / output interface 310 .

[0189] The word line control circuit 350 outputs a gate voltage signal to a selected word line.

[0190] The sense amplifier 370 reads data from the memory cell to be accessed. The read data is output to the control circuit 110.

[0191] 28 is a circuit diagram showing an example of a configuration of a memory cell array 360 according to the seventh embodiment of the present technology. A plurality of memory cells 207 are arranged in a two-dimensional lattice in the memory cell array 360. In the memory cell array 360, a bit line BL and a source line SL are wired for each column of the memory cells 207, and a word line WL is wired for each row of the memory cells 207.

[0192] Each of the memory cells 207 includes a magnetoresistive element 210 and a select transistor 220. The magnetoresistive element 210 and the select transistor 220 are connected in series between a bit line BL and a source line SL. A word line WL is connected to the gate of the select transistor 220.

[0193] As described above, the magnetization direction of the magnetoresistive element 210 is reversed by the VCMA effect. A nonvolatile memory 300 in which such magnetoresistive elements 210 are arranged is called a VC-MRAM.

[0194] 27 and 28, the circuit configured by the memory cell 207 and the sense amplifier 370 is similar to that of the arithmetic element 200 in the first embodiment. The control circuit 110 can cause the memory cell 207 to execute a logical operation by the same control as in the first embodiment.

[0195] The command to the nonvolatile memory 300 includes, for example, an initialization command and an XOR command. In accordance with the initialization command, the control circuit 110 performs the initialization process described with reference to Fig. 6. For example, the magnetoresistive element 210 is initialized to a low resistance state.

[0196] The host or the like transmits an XOR command together with the input data to be operated on. In response to this XOR command, the control circuit 110 performs the input processing described with reference to Fig. 7 and the output processing described with reference to Fig. 8. This executes an exclusive OR operation on the input data.

[0197] Furthermore, the host or the like can also send a high resistance command in addition to the initialization command and the XOR command. When this high resistance command is executed, only that command is sent, and no data is transferred. In accordance with the high resistance command, the control circuit 110 performs the same control as when input B with a logic value of "1" is input in a and b of FIG. 18. That is, the bias voltage and gate voltage are V ＯＲ and Vg (→H). The high resistance command does not require data transfer, so the time required to input the command can be reduced accordingly.

[0198] In addition to the initialization command and the XOR command, the host or the like can also send an inversion command. When this inversion command is executed, only the command is sent, and no data is transferred. In accordance with the inversion command, the control circuit 110 performs the same control as when input B with a logic value of "1" is input in a and b of FIG. 7. That is, the bias voltage and gate voltage are V ｓｗ and V оｎ is controlled by.

[0199] The magnetoresistive element 210 can also be initialized to a high resistance state by an initialization command. In this case, the host or the like can transmit a low resistance command in addition to the initialization command and the XOR command. The control circuit 110 performs the same control as that described with reference to FIG. 6 in accordance with the low resistance command.

[0200] Furthermore, the first to sixth embodiments and their respective modifications can be applied to the seventh embodiment.

[0201] When applying the third embodiment in which a logical sum is calculated, the host or the like can send an OR command. The control circuit 110 calculates the logical sum in accordance with the command using control similar to that of the third embodiment. When applying the fourth embodiment in which a logical product is calculated, the host or the like can send an AND command. The control circuit 110 calculates the logical product in accordance with the command using control similar to that of the fourth embodiment.

[0202] In this way, according to the seventh embodiment of the present technology, bits in the input data are input in order to the memory cells 207 including the magnetoresistive effect elements 210, so that logical operations can be performed in the nonvolatile memory 300.

[0203] 8. Eighth Embodiment In the seventh embodiment described above, the nonvolatile memory 300 calculates an exclusive OR, but the calculation result can be used for error detection and correction. The nonvolatile memory 300 in this eighth embodiment differs from the seventh embodiment in that the calculation result of the exclusive OR is used for error detection and correction.

[0204] 29 is a block diagram showing an example configuration of a nonvolatile memory 300 according to an eighth embodiment of the present technology. The nonvolatile memory 300 according to the eighth embodiment includes an input / output interface 310, an error correction circuit 380, and a predetermined number of memory blocks 390.

[0205] 30 is a block diagram showing an example configuration of a memory block 390 according to the eighth embodiment of the present technology. The memory block 390 includes a control circuit 110, a bit line address decoder 320, a bias voltage generation circuit 120, and a bit line control circuit 330. The memory block 390 further includes a word line address decoder 340, a word line control circuit 350, a memory cell array 360, and a sense amplifier 370.

[0206] 29 detects and corrects errors in read data. When this error correction circuit 380 receives data to be written from the input / output interface 310, it encodes the data and supplies it as write data to the memory block 390. When the error correction circuit 380 receives read data from the memory block 390, it detects and corrects (in other words, decodes) errors in the read data and supplies it to the input / output interface 310.

[0207] The error correction circuit 380 can use the above-mentioned exclusive OR operation for encoding and decoding. The error correction circuit 380 inputs input data to be operated on to a memory block 390. The control circuit 110 in the memory block 390 causes the memory cells 207 to operate the exclusive OR using control similar to that in the first embodiment, reads output data indicating the operation result, and supplies it to the error correction circuit 380. The error correction circuit 380 performs syndrome calculations using the output data to detect and correct errors.

[0208] The host or the like can send an error check command, and in response to the error check command, the error correction circuit 380 detects errors in the read data using an exclusive OR operation.

[0209] The host or the like can also send a refresh command. In response to the refresh command, the error correction circuit 380 detects an error in the read data using an exclusive OR operation. If the error is correctable, the error correction circuit 380 identifies the location of the error and supplies the address of the memory cell 207 holding the erroneous bit and an inversion command to the memory block 390. In response to the inversion command, the control circuit 110 performs the same control as when input B with a logic value of "1" is input in a and b of FIG. 7. That is, the bias voltage and gate voltage are V ｓｗ and V оｎ This inverts the bit in which the error occurred, and the error is corrected.

[0210] The VC-MTJ has high compatibility with logic processes and can be easily integrated with general logic circuits. Arithmetic circuits including the VC-MTJ are applicable not only to the error correction function of VC-MRAM but also to general error correction circuits. For example, XOR operations are frequently used in the encoding process and syndrome calculation of LDPC (Low-Density Parity-Check) codes used in mobile communications, etc. Furthermore, the XOR operation is also used in the encoding kernel of polar codes.

[0211] Furthermore, the first to sixth embodiments and their respective modifications can be applied to the eighth embodiment.

[0212] Thus, according to the eighth embodiment of the present technology, the error correction circuit 380 uses the result of the exclusive OR calculation to detect and correct errors in the read data, thereby improving the error resistance of the non-volatile memory 300.

[0213] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0214] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0215] The present technology may also be configured as follows: (1) An arithmetic circuit comprising: an arithmetic element including a magnetoresistive effect element whose magnetization direction is reversed by the VCMA effect; and a control circuit that performs an input process of sequentially inputting a plurality of bits to be operated on by a predetermined logical operation to the arithmetic element, and an output process of causing the arithmetic element to output one-bit output data indicating a result of the logical operation after the input process. (2) The arithmetic circuit according to (1), wherein the logical operation includes an exclusive OR operation. (3) The arithmetic circuit according to (1) or (2), wherein the logical operation includes a logical AND operation. (4) The arithmetic circuit according to any of (1) to (3), wherein the logical operation includes a logical OR operation. (5) The arithmetic circuit according to any of (1) to (4), further comprising a bias voltage generation circuit that generates a bias voltage according to control of the control circuit. (6) The arithmetic circuit according to (5), wherein the bias voltage includes an initialization voltage, and the bias voltage generation circuit performs, before the input process, a read process of reading a bit held in the magnetoresistive element and an initialization process of applying the initialization voltage if the read bit has a specific logical value and not applying the initialization voltage if the read bit does not have the specific logical value. (7) The arithmetic circuit according to (5) or (6), wherein the bias voltage includes first and second bias voltages, and the arithmetic element includes the magnetoresistive element and a selection transistor connected in series between a first input node to which the first bias voltage is input and a second input node to which the second bias voltage is input. (8) The arithmetic circuit according to (5) or (6), wherein the arithmetic element includes the magnetoresistive element and a selection transistor connected in series between an input node to which the bias voltage is input and a ground node. (9) The arithmetic circuit according to (8), wherein the selection transistor is an nMOS transistor, and the magnetoresistive element is inserted between the nMOS transistor and the input node. (10) The arithmetic circuit according to (7), wherein the selection transistor is a pMOS transistor, and the magnetoresistive element is inserted between the pMOS transistor and the ground node.(11) The arithmetic circuit according to any of (1) to (10), wherein the arithmetic elements include first and second arithmetic elements, the first arithmetic element having a first logic gate, the second arithmetic element having a second logic gate, and the first and second arithmetic elements share an output circuit that outputs the output data to the control circuit and a selector that selects the output circuit and either the first or second logic gate and connects it to the output circuit. (12) The arithmetic circuit according to any of (1) to (11), wherein the magnetoresistive effect element includes a pinned layer, a free layer, and a tunnel barrier layer. (13) The arithmetic circuit according to any of (1) to (12), wherein the magnetoresistive effect element includes a pair of a free layer and a tunnel barrier layer whose magnetization is exchange-coupled with the pinned layer. (14) A nonvolatile memory comprising: a memory cell array in which a predetermined number of memory cells are arranged, each memory cell including a magnetoresistive element whose magnetization direction is reversed by the VCMA effect; and a control circuit that performs an input process of sequentially inputting a plurality of bits to be operated on by a predetermined logical operation into the memory cells, and an output process of causing the memory cells to output one-bit output data indicating the result of the logical operation after the input process. (15) The nonvolatile memory according to (14), further comprising an error correction circuit that detects and corrects data errors using the output data. (16) A control method for an arithmetic circuit comprising: an input procedure of sequentially inputting a plurality of bits to be operated on by a predetermined logical operation into an arithmetic element including a magnetoresistive element whose magnetization direction is reversed by the VCMA effect, and an output procedure of causing the arithmetic element to output one-bit output data indicating the result of the logical operation after the input process.

[0216] 100 arithmetic circuit 110 control circuit 120 bias voltage generation circuit 200, 200-1, 200-2 arithmetic element 205, 205-1, 205-2 logic gate 206 arithmetic block 207 memory cell 210 magnetoresistance effect element 211 pin layer 212 tunnel barrier layer 213, 216 free layer 214 magnetic imparting layer 215 exchange coupling layer 220, 225 selection transistor 221 gate 222 source 223 drain 230 output circuit 240 switch 250 inverter 260 selector 270 flip-flop 280 XOR (exclusive OR) gate 281 to 288 nMOS transistor 300 nonvolatile memory 310 input / output interface 320 bit line address decoder 330 bit line control circuit 340 Word line address decoder 350 Word line control circuit 360 Memory cell array 370 Sense amplifier 380 Error correction circuit 390 Memory block

Claims

1. An arithmetic circuit comprising: an arithmetic element including a magnetoresistive element whose magnetization direction is reversed by the VCMA (Voltage Controlled Magnetic Anisotropy) effect; and a control circuit that performs an input process in which multiple bits to be operated on by a predetermined logical operation are input to the arithmetic element in order, and an output process in which, after the input process, the arithmetic element outputs one bit of output data indicating the result of the logical operation.

2. The arithmetic circuit according to claim 1, wherein the logical operation includes an exclusive OR operation.

3. The arithmetic circuit according to claim 1, wherein the logical operation includes a logical AND operation.

4. The arithmetic circuit according to claim 1, wherein the logical operation includes a logical sum operation.

5. The arithmetic circuit according to claim 1, further comprising a bias voltage generating circuit for generating a bias voltage under the control of said control circuit.

6. The arithmetic circuit according to claim 5, wherein the bias voltage includes an initialization voltage, and the bias voltage generation circuit performs, before the input process, a read process of reading out a bit held in the magnetoresistive element, and an initialization process of applying the initialization voltage if the read bit has a specific logical value, and not applying the initialization voltage if the read bit does not have the specific logical value.

7. The arithmetic circuit according to claim 5, wherein the bias voltage includes a first and a second bias voltage, and the arithmetic element comprises the magnetoresistive element and a selection transistor connected in series between a first input node to which the first bias voltage is input and a second input node to which the second bias voltage is input.

8. The arithmetic circuit according to claim 5, wherein the arithmetic element comprises the magnetoresistive element and a selection transistor connected in series between an input node to which the bias voltage is input and a ground node.

9. The arithmetic circuit according to claim 8, wherein the selection transistor is an nMOS (n-channel Metal Oxide Semiconductor) transistor, and the magnetoresistive element is inserted between the nMOS transistor and the input node.

10. The arithmetic circuit according to claim 8, wherein the selection transistor is a pMOS (p-channel MOS) transistor, and the magnetoresistive element is inserted between the pMOS transistor and the ground node.

11. The arithmetic circuit according to claim 1, wherein the arithmetic elements include first and second arithmetic elements, the first arithmetic element having a first logic gate, the second arithmetic element having a second logic gate, and the first and second arithmetic elements share an output circuit that outputs the output data to the control circuit and a selector that selects either the output circuit or the first or second logic gate and connects it to the output circuit.

12. The arithmetic circuit according to claim 1, wherein the magnetoresistive element includes a pinned layer, a free layer, and a tunnel barrier layer.

13. The arithmetic circuit according to claim 1, wherein the magnetoresistive element includes a pair of a free layer and a tunnel barrier layer whose magnetization is exchange-coupled with a pinned layer.

14. A non-volatile memory comprising: a memory cell array in which a predetermined number of memory cells are arranged, each containing a magnetoresistive element whose magnetization direction is reversed by the VCMA effect; and a control circuit that performs an input process in which multiple bits that are the subject of a predetermined logical operation are input to said memory cells in order, and an output process in which, after said input process, said memory cells are output with one bit of output data indicating the result of said logical operation.

15. The nonvolatile memory according to claim 14, further comprising an error correction circuit that uses the output data to detect and correct data errors.

16. A control method for an arithmetic circuit comprising: an input procedure for sequentially inputting a plurality of bits to be operated on by a predetermined logical operation into an arithmetic element including a magnetoresistive element whose magnetization direction is reversed by the VCMA effect; and an output procedure for causing the arithmetic element to output one bit of output data indicating the result of the logical operation after the input processing.

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