Operation method of memory, memory and memory system

Abstract

The embodiment of the invention provides an operation method of a memory, the memory and a memory system. The memory comprises a memory cell array composed of a plurality of memory blocks, and each memory block at least comprises a plurality of memory strings and a plurality of word lines coupled with the memory strings; the operation method comprises the following steps: applying an erasing voltage to a to-be-erased memory block in a first time period; in a second time period after the first time period, conducting a top selection tube and a bottom selection tube of each memory string in the memory block to be erased, so that charges in a channel of each erased memory string are released from two ends of the memory string; and performing an erase verification operation on the storage block.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese application No. 2022108899778, filed on July 27, 2022, entitled “Memory operating method, memory and memory system,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to, but not limited to, a memory operating method, a memory, and a memory system. Background Art

[0004] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. The gate of a flash memory cell has a structure consisting of a tunnel insulator layer, a floating gate electrode, a dielectric layer, and a control gate. Because non-volatile solid-state memory can retain data even after power is removed, a specialized erase operation is required to delete data. This erase operation involves applying a voltage between the gate and substrate of the flash memory cell, releasing the charge stored in the floating gate electrode. This, in turn, changes the threshold voltage of the memory cell, thereby erasing the data.

[0005] However, after performing an erase operation on a memory cell, the charge remaining in the channel often interferes with subsequent reading and writing of data. Therefore, how to clean up the charge remaining after erasure is an important operation for memory control. Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a memory operating method, a memory, and a memory system.

[0007] In a first aspect, an embodiment of the present disclosure provides a method for operating a memory, wherein the memory includes a memory cell array composed of a plurality of memory blocks, each of the memory blocks including at least a plurality of memory strings and a plurality of word lines coupled to the memory strings; the method comprising:

[0008] Applying an erase voltage to a memory block to be erased during a first period of time;

[0009] In a second time period after the first time period, turning on the top selection tube and the bottom selection tube of each memory string in the memory block to be erased, so that the charges in the channel of each memory string after erasure are released from both ends of the memory string;

[0010] An erase verification operation is performed on the memory block.

[0011] In some embodiments, the turning on, during the second time period after the first time period, the top select transistor and the bottom select transistor of each memory string in the memory block to be erased, comprises:

[0012] applying a first turn-on voltage to a top select gate line in the memory block; wherein the top select gate line is connected to the control electrode of the top select transistor;

[0013] applying a second turn-on voltage to a bottom select gate line in the memory block; wherein the bottom select gate line is connected to the control electrode of the bottom select transistor

[0014] synchronously applying, during the second time period, a first gate-on voltage to a first gate switch connected to the top select gate line and a second gate switch connected to the bottom select gate line, so that the first turn-on voltage is applied to the top select transistor and the second turn-on voltage is applied to the bottom select transistor.

[0015] In some embodiments, the first turn-on voltage is equal to the second turn-on voltage.

[0016] In some embodiments, the method further comprises:

[0017] applying, during a first time period, a second gate-on voltage to the first gate switch and the second gate switch; the second gate-on voltage is less than the first gate-on voltage.

[0018] In some embodiments, the method further comprises:

[0019] turning on, during the second time period, a discharge path in a page buffer to which a bit line corresponding to the memory string is coupled.

[0020] In some embodiments, the turning on, during the second time period, a discharge path in a page buffer to which a bit line corresponding to the memory string is coupled, comprises:

[0021] applying a third turn-on voltage to a control switch in the discharge path in the page buffer to which the bit line is coupled.

[0022] In some embodiments, the method further comprises:

[0023] applying, during the second time period, an off voltage to a control switch between the bit line and a sensing node in the page buffer, so as to disconnect a pre-charge path and a path between latches in the page buffer.

[0024] In some embodiments, the applying, during a first time period, an erase voltage to the memory block to be erased, comprises:

[0025] applying, during the first time period, a ground voltage to each word line of the memory block to be erased;

[0026] Meanwhile, the erase voltage is applied to each bit line or source line of the storage block to be erased.

[0027] In some embodiments, the method further comprises:

[0028] During the second time period, the erase voltage applied to each bit line or source line is switched to a ground voltage.

[0029] In some embodiments, the performing the erase verification operation on the storage block comprises:

[0030] applying an erase verification voltage to a selected word line on the storage block; wherein the selected word line is any word line on the storage block;

[0031] applying an open voltage to an unselected word line on the storage block; wherein the open voltage is greater than or equal to a maximum threshold voltage of a storage cell; and the erase verification voltage is less than the open voltage;

[0032] reading the storage cell corresponding to the selected word line to obtain a verification result of the erase verification operation.

[0033] In a second aspect, the embodiments of the present disclosure provide a memory, comprising:

[0034] a peripheral circuit and a storage cell array composed of a plurality of storage blocks;

[0035] The peripheral circuit is configured to at least perform the operation method of any of the above embodiments.

[0036] In a third aspect, the embodiments of the present disclosure provide a memory system, comprising:

[0037] a memory and a controller;

[0038] The memory comprises at least a peripheral circuit and a storage cell array composed of a plurality of storage blocks; and the peripheral circuit is configured to at least perform the operation method of any of the above embodiments.

[0039] The operation method of the memory provided by the embodiments of the present disclosure uses the method of simultaneously opening the top selection tube and the bottom selection tube to solve the problem of channel charge residue during the storage block erase process, so that the channel charge can be discharged from both ends of the channel, thereby reducing the channel charge residue after erasing, and further reducing the problem of subsequent read errors caused by the channel charge to raise the channel potential. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 a structural schematic diagram of an exemplary system provided by the embodiments of the present disclosure;

[0041] Figure 2 A structural diagram of a memory card according to an embodiment of the present disclosure;

[0042] Figure 3 A structural diagram of a solid state drive (SSD) according to an embodiment of the present disclosure;

[0043] Figure 4 A structural diagram of a memory including an array of memory cells and a peripheral circuit according to an embodiment of the present disclosure;

[0044] Figure 5 A structural diagram of a memory according to an embodiment of the present disclosure;

[0045] Figure 6 A diagram of a page buffer in a peripheral circuit of a memory according to an embodiment of the present disclosure;

[0046] Figure 7 A diagram of a memory string in a memory according to an embodiment of the present disclosure;

[0047] Figure 8 A diagram of a word line and a common word line in a memory according to an embodiment of the present disclosure;

[0048] Figure 9 A diagram of a top select gate and a bottom select gate controlling release of channel charge in a memory string in a memory according to an embodiment of the present disclosure;

[0049] Figure 10 A waveform diagram of an erase operation of a memory according to an embodiment of the present disclosure;

[0050] Figure 11 A flowchart of a method of operating a memory according to an embodiment of the present disclosure;

[0051] Figure 12 A waveform diagram of an erase operation in a method of operating a memory according to an embodiment of the present disclosure;

[0052] Figure 13 A diagram of a control switch state of a page buffer in a method of operating a memory according to an embodiment of the present disclosure;

[0053] Figure 14 A diagram of a memory cell state distribution in a memory according to an embodiment of the present disclosure;

[0054] Figure 15 A structural diagram of a memory according to an embodiment of the present disclosure;

[0055] Figure 16A structural schematic diagram of a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] For the purpose of facilitating the understanding of the present disclosure, the present disclosure will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terminology used in the description of the present disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0058] As shown in FIG. 1, Figure 1 The exemplary system 10 can include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory 34 therein; and the host 20 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device.

[0059] In embodiments of the present disclosure, the host 20 can be configured to send data to or receive data from the storage system 30. Here, the storage system 30 can include a controller 32 and one or more memories 34. Among others, the memory 34 can include, but is not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc.

[0060] On the other hand, the controller 32 can be coupled to the memory 34 and the host 20 and configured to control the memory 34. Exemplarily, the controller can be designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile telephones, etc. In some embodiments, the controller can also be designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc. and enterprise storage arrays. Further, the controller can manage data in the memory and communicate with the host. The controller can be configured to control memory read, erase, and program operations, etc.; also configured to manage various functions regarding data stored in or to be stored in the memory, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc.; also configured to handle error correction codes (ECC) regarding data read from or written to the memory. In addition, the controller can also perform any other suitable functions, such as formatting the memory, or communicating with external devices (e.g., a host) according to a specific communication protocol, etc. Figure 1For example, the controller can communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini-interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0061] In the embodiments of the present disclosure, the controller and one or more memories can be integrated into various types of storage devices, for example, included in the same package (for example, a universal flash storage (UFS) package or an eMMC package). That is, the storage system can be implemented and packaged into different types of terminal electronic products. Figure 2 As shown, the controller 32 and the single memory 34 may be integrated into a memory card 40. The memory card 40 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 40 may also include a computer that connects the memory card 40 to a host (e.g., Figure 1 The memory card connector 42 is coupled to the host 20 in the embodiment. Figure 3 In another embodiment shown in FIG, the controller 32 and the plurality of memories 34 may be integrated into the SSD 50. The SSD 50 may also include a computer that interfaces the SSD 50 with a host (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 50 is greater than the storage capacity and / or operating speed of the memory card 40.

[0062] It should be noted that the memory involved in the embodiments of the present disclosure may be a semiconductor memory, which is a solid-state electronic device for storing data information manufactured using semiconductor integrated circuit technology. For example, Figure 4 Schematic diagram of an optional memory 60 in the embodiment of the present disclosure. The memory 60 may be Figures 1 to 3 The memory 34 in the Figure 4As shown, the memory 60 can be comprised of a memory cell array 62 and peripheral circuitry 64 coupled to the memory cell array 62, among other things. Here, the memory cell array can be a NAND flash memory cell array in which memory cells are provided in an array of NAND memory strings 66, each of which extends vertically over a substrate (not shown). In some embodiments, each NAND memory string 66 can include a plurality of memory cells coupled in series and stacked vertically. Each memory cell can hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within the memory cell region. Additionally, each memory cell in the memory cell array 62 described above can be a floating gate type of memory cell that includes a floating gate transistor, or a charge trap type of memory cell that includes a charge trapping transistor.

[0063] In embodiments of the present disclosure, the memory cells described above can be single level cells (SLC) that have two possible storage states and thus can store one bit of data. For example, a first storage state "0" can correspond to a first voltage range, and a second storage state "1" can correspond to a second voltage range. In other embodiments, each memory cell is a multi level cell (MLC) that is capable of storing more than a single bit of data in more than four memory states. For example, a MLC can store two bits per cell, three bits per cell (also referred to as a triple level cell (TLC)), or four bits per cell (also referred to as a quad level cell (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. Illustratively, if each MLC stores two bits of data, the MLC can be programmed to take on one of three possible program levels by writing one of three possible nominal storage values to the memory cell from an erased state. A fourth nominal storage value can be used for the erased state.

[0064] In embodiments of the present disclosure, the peripheral circuitry described above can be coupled to the array of memory cells by bit lines (BLs), word lines (WLs), source lines, source select gates (SSGs), and drain select gates (DSGs). Here, the peripheral circuitry can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of the array of memory cells by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell via the bit lines, word lines, source lines, SSGs, and DSGs. In addition, the peripheral circuitry can also include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. Illustratively, as shown in Figure 5 FIG. 7. The peripheral circuitry 70 includes page buffers / sense amplifiers 71, column decoders / bit line drivers 72, row decoders / word line drivers 73, voltage generators 74, control logic 75, registers 76, an interface 77, and a data bus 78. It should be understood that the peripheral circuitry 70 described above can be the same as the peripheral circuitry 64 in Figure 4 FIG. 6, and in other embodiments, the peripheral circuitry 70 can also include additional peripheral circuitry not shown in Figure 4 FIG. 6.

[0065] As shown in Figure 6 FIG. 9, a page buffer 90 is shown in an embodiment of the present disclosure. The page buffer 90 can be coupled to the array of memory cells 80 via bit lines BL. Each page buffer includes a register set 91 connected by a bit line bias switch VBL BIAS to ground by a discharge switch VBL DISCH . In addition, at least one sense node can be included in the page buffer between the register set and the word line. As shown in Figure 6 FIG. 9, the page buffer 90 includes a sense node SO and a sense node SO2, and a select transistor VSO BLK is included between the two sense nodes. In addition, the page buffer can also include a bit line switch V PASS between the bit line for controlling whether the entire page buffer is connected to the bit line.

[0066] In embodiments of the present disclosure, the array of memory cells can be formed as shown in Figure 7The shown memory strings 700 are formed by connecting a plurality of memory cell stacks by a channel 720 perpendicular to a substrate 710. A word line 730 is perpendicular to the channel and can surround the channel for use as a gate electrode of the memory cell. The storage structure 740 between the gate electrode of the memory cell and the channel includes at least a tunneling layer 741, a storage layer 742 (charge trapping layer), and a blocking layer 743. The storage structure can generally be a tunneling layer including silicon oxide, a storage layer including silicon nitride, and a blocking layer including silicon oxide, i.e., an ONO structure.

[0067] Each memory cell can be in an erased state or a programmed state, and the programmed state can have a plurality of states. The erased state is used to indicate an original state of the memory cell without programming, or a state without storing data, and can also be understood as storing data "0"; the programmed state is used to indicate a state of storing different data. For example, for the memory cell of the above-mentioned SLC, it can store 1-bit data, so only one erased state is needed to represent data "0", and one programmed state is needed to represent data "1". For the memory cell of the above-mentioned MLC, it can store 2-bit data, so one erased state is needed to represent data "00", and three programmed states are needed to represent data "01", "10", and "11".

[0068] The above-mentioned erased state and programmed state are essentially embodied by the threshold voltage of the memory cell. Since the memory cell with the ONO structure can achieve charge trapping, by applying a voltage between the gate electrode and the channel, the tunneling effect can be used to make the charge pass through the tunneling layer to the storage layer, i.e., the charge trapping layer, so that the charge is trapped in the storage layer. The change in the amount of charge in the storage layer will cause the threshold voltage of the memory cell to change. Therefore, if data is to be stored in the memory cell, the corresponding charge can be injected into the storage layer to achieve it. Here, the process of injecting charge can be referred to as "programming", i.e., adjusting the state of the memory cell from the erased state to different programmed states by programming.

[0069] Correspondingly, if the data in the memory cell is to be erased, i.e., to be restored from the programmed state to the erased state, the opposite process of programming needs to be used, i.e., applying an opposite voltage between the gate electrode and the channel, using the tunneling effect to make the charge trapped in the storage layer pass through the tunneling layer back to the channel, thereby releasing the charge in the storage layer and making the threshold voltage of the memory cell return to the range of the erased state.

[0070] In embodiments of the present disclosure, the memory cell array of the memory described above can be composed of a plurality of memory blocks, each memory block having a source, and the channel bottom of each memory string in the memory block can be connected to the SL of the source through a doped region in the substrate, and the top of the memory string is connected to the BL. The memory block is the smallest unit of the erase operation. When erasing, a high voltage can be applied to the SL or the BL, and at the same time, the channel of the memory string is maintained in a non-conductive state, for example, a 0V voltage is applied to the word line of each memory cell on the memory string. At this time, the high voltage of the BL or the SL is coupled to the channel, which raises the voltage of the channel, so that the electric charges stored in the memory layer tunnel into the channel, thereby achieving erasing.

[0071] In some embodiments, after applying the erase voltage, a verification process can be used to confirm whether the erasing is successful. The principle of the verification process is similar to that of the read operation, for example, a verification voltage of the erased state is applied to the WL (which can be referred to as the selected word line, Sel Blk WL) corresponding to the memory cell to be verified, and a pass voltage Vpass is applied to the other WL (unselected word line), and then read through the BL. If the voltage is read, that is, the memory cell is turned on, it means that the threshold voltage of the memory cell is less than the verification voltage, that is, the memory cell has been successfully erased. If the voltage is not read, that is, the memory cell is not turned on, it means that the threshold voltage of the memory cell is greater than the verification voltage, that is, the memory cell has not been successfully erased.

[0072] However, it can be understood that, since the electric charges in the memory layer return to the channel after erasing, and the channel is essentially not conductive, these electric charges will affect the subsequent read or other operations. Therefore, the electric charges in the channel need to be discharged after erasing to ensure that they do not affect subsequent operations.

[0073] For the above verification process, since there are residual electric charges in the channel, the channel discharges at the beginning of the verification. At this time, the current generated by the discharge will have a coupling effect on the selected word line, causing the voltage of the selected word line to be pulled down, and even to a negative voltage. Since the word lines of the memory block are also coupled to a common word line (LWL, Local Word Line), as shown in Figure 8 Pulling down the selected word line SEL_WL will cause the voltage of the unselected word line UNSEL_WL to leak, thereby causing the threshold voltage to shift after the verification ends, and errors will occur in subsequent read operations.

[0074] In some embodiments, the Bottom Select Gate (BSG) of the memory string can be opened to make the channel partially conductive. As shown in Figure 9As shown, by lifting the voltage of SD Vg (String Driver Gate), the voltage of BSG is lifted after erasing. Here SD Vg is a switch used to control whether the string selection line of each storage string in the storage block applies a voltage. When SD Vg is opened, the voltage signals applied on the BSG line and the TSG line are loaded on the control electrode of BSG and the control electrode of TSG. As shown Figure 10 As shown, SD Vg is maintained at 6V in the preparation stage and the erasing stage, and the erasing voltage Vers is applied to BL or SL in the erasing stage, so that the voltage of BSG and TSG is coupled from low voltage vss to high voltage. When the erasing voltage is applied, the voltage of BSG and TSG falls back to about 3V in the recovery stage. At this time, the voltage of SD Vg is lifted to 15V, so that TSG and BSG are gated, and since the voltage of TSG is about 0V at this time, the voltage of BSG is about 15V, so that BSG is opened to achieve the purpose of discharging, and TSG is maintained in the off state. Figure 9 As shown, 6V voltage is applied to BSG, and 0V voltage is applied to TSG, so that BSG is reopened to achieve the purpose of discharging, and TSG is maintained in the off state.

[0075] Since BSG is located at the bottom of the storage string, the channel discharging is performed by opening one end of BSG, so that the electric charge can quickly flow to the substrate, so as to perform subsequent erasing verification operation.

[0076] However, as the number of memory layers increases, it may be difficult to meet the discharging requirement after erasing only by opening BSG, a longer discharging time is required, and there is still a risk of residual charge causing the above-mentioned abnormality after erasing verification.

[0077] Therefore, as shown Figure 11 The embodiment of the present disclosure provides an operation method of a memory, the memory comprising a storage unit array composed of a plurality of storage blocks, each storage block comprising at least a plurality of storage strings and a plurality of word lines coupled with the storage strings; comprising:

[0078] Step S101, applying an erasing voltage to a storage block to be erased in a first time period;

[0079] Step S102, in a second time period after the first time period, turning on the top selection tube and the bottom selection tube of each storage string in the storage block to be erased, so that the electric charge in the channel of each storage string after erasing is discharged from both ends of the storage string.

[0080] Step S103, performing an erasing verification operation on the storage block.

[0081] In the embodiment of the present disclosure, after applying an erasing voltage to the storage block, the top selection tube and the bottom selection tube are opened at the same time, so that the electric charge in the channel is discharged from both ends of the channel, thereby accelerating the discharging speed and further reducing the residual charge, so that the discharging is more sufficient.

[0082] In some embodiments, the step S101 of applying an erase voltage to the storage block to be erased comprises:

[0083] applying the erase voltage to the source of the storage block to be erased while floating the bit lines connected to the corresponding storage strings; or applying the erase voltage to the bit lines of the storage block to be erased while floating the source; or applying the erase voltage to both the source and the bit lines of the storage block.

[0084] In the erase process, the erase voltage is applied to the source, i.e. a high voltage is applied to the SL, at this time the BL can be floated, so that the channel of the entire storage string is not turned on, but is coupled to a high level under the action of the high voltage of the SL, thereby generating a voltage difference between the gate (word line) of each storage cell. Similarly, the erase voltage can also be applied to the bit line, i.e. a high voltage is applied to the BL, while the source SL is floated, so that the channel is coupled to a high level, thereby achieving the erase of the storage block. In addition, the erase voltage can also be applied to the BL and SL at the same time, and the potential of the channel is raised to a high level as a whole, thereby achieving the erase of the storage block.

[0085] It can be understood that the erase voltage applied to the storage block to be erased can be a high voltage applied to the BL or the SL. In this process, the floated channel is coupled to a high level, and the TSG and the BSG can be coupled from a low level state to a high level state. Other WLs can be grounded or provided with a low voltage. The holes in the P+ (P-type heavily doped) polysilicon enter the channel under the action of the electric field, and then enter the storage layer based on the electric field generated by the voltage difference between the WL and the channel, and neutralize the electrons in the storage layer, thereby achieving the effect of erasing.

[0086] After the process is completed, the erase voltage is stopped, so that the holes stop continuing to enter the storage layer. At this time, there are a large number of residual holes in the channel.

[0087] Therefore, by the step S102, the top select transistor and the bottom select transistor of the storage string are opened, so that the residual charge is released.

[0088] In some embodiments, the step S102 of opening the top select transistor and the bottom select transistor of each storage string in the storage block in the second time period after the first time period comprises:

[0089] applying a first opening voltage to the top select gate line in the storage block; wherein the top select gate line is connected to the control electrode of the top select transistor;

[0090] applying a second opening voltage to the bottom select gate line in the storage block; wherein the bottom select gate line is connected to the control electrode of the bottom select transistor;

[0091] In the second period, a gate voltage is applied to the first gate switch connected to the top select gate line and the second gate switch connected to the bottom select gate line to apply the first turn-on voltage to the top select transistor and the second turn-on voltage to the bottom select transistor.

[0092] The memory block is composed of a multi-layer stack structure, in which conductive layers and insulating layers are alternately stacked and distributed in a plane perpendicular to the direction of the memory string channel. Each conductive layer can be used as a word line of a memory cell to control the memory cell of the ONO structure located on the side wall of the channel. The conductive layer at the top of the stack structure is the top select gate line TSG, and the conductive layer at the bottom of the stack structure is the bottom select gate line BSG, as shown in Figure 9

[0093] In some embodiments, the first turn-on voltage V1 and the second turn-on voltage V2 can be applied to the top select gate line TSG and the bottom select gate line BSG, respectively, in the second period, so that the select transistors at both ends of the channel are turned on.

[0094] In addition, the TSG and the BSG can be connected to the gate switches, respectively. That is, the first gate switch SD_Vg1 is connected to the TSG for gating the TSG, and the second gate switch SD_Vg2 is connected to the BSG for gating the BSG.

[0095] In this way, the voltages applied to the TSG and the BSG can not be changed, but the time of applying the voltages to the transistors at both ends of the channel can be controlled by the gate switches, so as to control the on-off of the channel.

[0096] In some embodiments, the first turn-on voltage is equal to the second turn-on voltage. Providing equal turn-on voltages to the top select gate line and the bottom select gate line can make the top select transistor and the bottom select transistor have the same turn-on degree, facilitating the release of charges from the channel. In addition, the TSG and the BSG can be connected to the same gate switch SD. After the end of the application of the above-mentioned erase voltage, the first turn-on voltage can be applied to the top select gate line and the second turn-on voltage can be applied to the bottom select gate line by turning on the gate switch SD. Since the top select gate line is connected to the control electrode of the TSG and the bottom select gate line is connected to the control electrode of the BSG, the first turn-on voltage and the second turn-on voltage can be applied to the TSG and the BSG synchronously, thereby turning on the TSG and the BSG and releasing the channel charges.

[0097] It should be noted that the first period can be in the erase phase as shown in Figure 12 The second period can be in the recovery phase after the erase phase.

[0098] In some embodiments, the method further comprises: ​

[0099] In a first period, a second gate voltage is applied to the first gate switch and the second gate switch, and the second gate voltage is lower than the first gate voltage.

[0100] For example, Figure 12 As shown, during the erase phase, the gate switch SD connected to TSG and BSG can provide a lower second gate voltage, such as ground or 6 V. Since the channel potential is high during the erase phase, TSG and BSG are actually in a disconnected state.

[0101] Switching to the second period, such as Figure 12 During the recovery phase, the gate voltage of the gate switch SD can be increased to the first gate voltage, for example, 15 V. At this time, BSG and TSG are turned on synchronously, so that both ends of the channel are in a conductive state, thereby facilitating the release of channel charges from both ends.

[0102] In some embodiments, the method further comprises:

[0103] In a second period, a discharge path in the page buffer coupled to the bit line corresponding to the memory string is opened.

[0104] In some embodiments, opening a discharge path in a page buffer coupled to a bit line corresponding to the memory string includes:

[0105] A third turn-on voltage is applied to a control switch in a discharge path in a page buffer coupled to the bit line.

[0106] In some embodiments, the method further comprises:

[0107] During the second period, a cutoff voltage is applied to a control switch between the bit line and a sensing node in the page buffer to disconnect a precharge path and a path between latches in the page buffer.

[0108] It is understood that the above-mentioned memory string is connected to the bit line BL, and the bit line is connected to the bit line BL through the following example. Figure 6 The page buffer shown is connected to other modules of the peripheral circuit. Since the bit line is not directly grounded, when the channel charge is released by opening the TSG, a path from the bit line BL to the ground Gnd must also be provided.

[0109] For example, Figure 13 As shown, in the embodiment of the present disclosure, the control switch between BL and the sensing nodes SO and SO2 of the page buffer 90 can be closed, and the discharge switch of the discharge path can be opened. Specifically, the bit line bias switch VBL BIAS and switch VSO BLK Applying a cutoff voltage opens the path, and the bit line switch V PASS , and discharge switch VBLDISCH and bit line switch V PASS An on voltage (i.e., the third on voltage described above) is applied to turn on the discharge path. In this way, the residual charge in the channel can be discharged to the discharge path through the bit line, so as to achieve the purpose of quickly discharging the charge.

[0110] It should be further noted that the above erasing operation, i.e., the step of applying an erasing voltage to the storage block to be erased in the first period, can specifically include:

[0111] In the first period, each word line of the storage block to be erased is applied with a ground voltage;

[0112] Meanwhile, each bit line or source line of the storage block to be erased is applied with the erasing voltage.

[0113] In the second period, the erasing voltage applied on each bit line or source line is switched to a ground voltage.

[0114] In some embodiments, the step S103 of performing an erasing verification operation on the storage block includes:

[0115] An erasing verification voltage is applied to a selected word line on the storage block; wherein the selected word line is any word line on the storage block;

[0116] An on voltage is applied to an unselected word line on the storage block; wherein the on voltage is greater than or equal to the maximum threshold voltage of the storage unit; the erasing verification voltage is less than the on voltage;

[0117] The storage unit corresponding to the selected word line is read to obtain a verification result of the erasing verification operation.

[0118] The above verification process can be implemented for different word lines in turn, similar to the reading process. An erasing verification voltage is applied to a selected word line on the storage block, and an on voltage is applied to other word lines. The process of reading the storage unit corresponding to the selected word line specifically includes: applying a voltage on the bit line, and through the sensing node connected by the bit line, it can be detected whether the channel is turned on. If the channel is turned on, it means that the above erasing verification voltage is greater than the threshold voltage of the storage unit coupled to the selected word line, i.e., the storage unit is successfully erased. If the channel is not turned on, it means that the above erasing verification voltage is less than the threshold voltage of the storage unit, i.e., the erasing of the storage unit fails.

[0119] It can be understood that, as shown in Figure 14 the above erasing verification voltage V vf0 is defined based on the target threshold voltage Vth after erasing. That is, the threshold voltage Vth of the storage unit successfully erased should be less than the erasing verification voltage V vf0, the threshold voltage Vth of the storage unit is greater than the erase verification voltage V vf0 , so that the storage unit cannot be turned on; only after successful erasing, the threshold voltage Vth of the storage unit is less than the erase verification voltage V vf0 . That is, if the successful erasing indicates that the storage unit has entered the erased state E0, and the maximum threshold voltage is V1, the set erase verification voltage V vf0 should be greater than or equal to V1.

[0120] As shown in Figure 15 , the embodiment of the present disclosure further provides a memory 100, comprising:

[0121] a peripheral circuit 110 and a storage unit array 120 composed of a plurality of storage blocks;

[0122] The peripheral circuit 110 is at least configured to perform the operation method described in any of the above embodiments. That is, the operation method provided by any of the above embodiments can be applied to the memory 100.

[0123] As shown in Figure 16 , the embodiment of the present disclosure further provides a memory system 200, comprising:

[0124] a memory 210 and a controller 220;

[0125] The memory 210 at least includes a peripheral circuit and a storage unit array composed of a plurality of storage blocks; the peripheral circuit is at least configured to perform the operation method described in any of the above embodiments. The memory 210 can also be the memory 100 shown in the above embodiments. Figure 12 .

[0126] The features disclosed in the several method or device embodiments of the present disclosure can be combined arbitrarily without conflict, to obtain new method embodiments or device embodiments.

[0127] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for operating a memory, characterized in that: The memory includes a memory cell array including a plurality of memory blocks, each of the memory blocks including a memory string and a bit line and a source line coupled to the memory string; the method includes: applying an erase voltage to the bit line or the source line during a first period; In a second period after the first period, turning on a first selection transistor of the memory string; wherein the first selection transistor is located between the bit line and a plurality of memory cells of the memory string, or the first selection transistor is located between the source line and the plurality of memory cells; and After the second period, an erase verification operation is performed on the memory block.

2. The operating method according to claim 1, characterized in that: The first selection tube and the second selection tube of the storage string are turned on in a second time period after the first time period; wherein the first selection tube is located between the bit line and the multiple storage cells of the storage string, and the second selection tube is located between the source line and the multiple storage cells; or, the first selection tube is located between the source line and the multiple storage cells of the storage string, and the second selection tube is located between the bit line and the multiple storage cells.

3. The operating method according to claim 2, characterized in that: include: Applying a first turn-on voltage to a first selection gate line to turn on the first selection transistor; wherein the first selection gate line is coupled to the first selection transistor; Applying a second turn-on voltage to a second selection gate line to turn on a second selection transistor of the memory string; wherein the second selection gate line is coupled to the second selection transistor; and During the second period, a first selection voltage is synchronously applied to a first selection switch connected to the first selection gate line and a second selection switch connected to the second selection gate line, so that the first turn-on voltage is applied to the first selection tube and the second turn-on voltage is applied to the second selection tube.

4. The operating method according to claim 3, characterized in that: The first turn-on voltage is equal to the second turn-on voltage.

5. The operating method according to claim 3, characterized in that: The method further comprises: While the erase voltage is applied to the bit line or the source line, a second gate voltage is applied to the first gate switch, and a third gate voltage is applied to the second gate switch.

6. The operating method according to claim 5, characterized in that: During the first period, the first selection gate line and the second selection gate line are floated.

7. The operating method according to claim 5, characterized in that: The second gate voltage is lower than the first gate voltage.

8. The operating method according to claim 5, characterized in that: The method further comprises: After the erase voltage is applied to the bit line or the source line, the bit line or the source line is discharged to a first voltage, and the first selection gate line is discharged to a second voltage; and After the first selection gate line is discharged to a second voltage, turning on the first selection transistor; The second voltage is greater than the first voltage, and the second voltage is less than the second selection voltage.

9. The operating method according to claim 8, characterized in that: The method further comprises: Before the first selection transistor is turned on in the second period, the first selection gate line is maintained discharged to the second voltage in the third period.

10. The operating method according to claim 8, characterized in that: The method further comprises: Before the bit line or the source line is discharged to the first voltage, the first selection gate line is maintained discharged to the second voltage within a third period.

11. The operating method according to claim 1, characterized in that: The method further comprises: In the second period, a third turn-on voltage is applied to a control switch in a discharge path in the page buffer coupled to the bit line, so as to turn on the discharge path in the page buffer coupled to the bit line.

12. The operating method according to claim 11, characterized in that: The method further comprises: During the second period, a cutoff voltage is applied to a control switch between the bit line and a sensing node in the page buffer, thereby disconnecting a precharge path in the page buffer and a path between latches.

13. The operating method according to claim 1, characterized in that: The applying an erase voltage to the bit line or the source line storage block within the first time period includes: During the first period, a ground voltage is applied to a plurality of word lines coupled to the memory cells; The erase voltage is applied to the bit line and the source line at the same time.

14. The operating method according to any one of claims 1 to 13, characterized in that: The performing an erase verification operation on the storage block includes: Applying an erase verification voltage to a selected word line on the memory block; wherein the selected word line is any word line on the memory block; Applying a turn-on voltage to unselected word lines on the memory block; wherein the turn-on voltage is greater than or equal to the maximum threshold voltage of the memory cell; and the erase verification voltage is less than the turn-on voltage; The memory cell corresponding to the selected word line is read to obtain a verification result of the erase verification operation.

15. A memory, characterized in that: The memory includes: A peripheral circuit and a memory cell array comprising a plurality of memory blocks, wherein the peripheral circuit is coupled to the memory cell array; Wherein, the peripheral circuit is at least configured as follows: applying an erase voltage to the bit line or the source line during a first period; In a second period after the first period, turning on a first selection transistor of the memory string; wherein the first selection transistor is located between the bit line and a plurality of memory cells of the memory string, or the first selection transistor is located between the source line and the plurality of memory cells; and After the second period, an erase verification operation is performed on the memory block.

16. The memory according to claim 15, wherein: The peripheral circuit is further configured to: turn on the first selection tube and the second selection tube of the storage string in a second time period after the first time period; wherein the first selection tube is located between the bit line and the multiple storage cells of the storage string, and the second selection tube is located between the source line and the multiple storage cells; or, the first selection tube is located between the source line and the multiple storage cells of the storage string, and the second selection tube is located between the bit line and the multiple storage cells.

17. The memory according to claim 16, wherein: The peripheral circuit is further configured to: Applying a first turn-on voltage to a first selection gate line to turn on the first selection transistor; wherein the first selection gate line is coupled to the first selection transistor; Applying a second turn-on voltage to a second selection gate line to turn on a second selection transistor of the memory string; wherein the second selection gate line is coupled to the second selection transistor; and During the second period, a first selection voltage is synchronously applied to a first selection switch connected to the first selection gate line and a second selection switch connected to the second selection gate line, so that the first turn-on voltage is applied to the first selection tube and the second turn-on voltage is applied to the second selection tube.

18. The memory according to claim 17, wherein: The first turn-on voltage is equal to the second turn-on voltage.

19. The memory according to claim 17, wherein: The peripheral circuit is further configured to: While the erase voltage is applied to the bit line or the source line, a second gate voltage is applied to the first gate switch, and a third gate voltage is applied to the second gate switch.

20. The memory according to claim 19, wherein The peripheral circuit is further configured to float the first selection gate line and the second selection gate line during the first time period.

21. The memory according to claim 19, wherein The second gate voltage is lower than the first gate voltage.

22. The memory according to claim 19, wherein: The peripheral circuit is further configured to: After the erase voltage is applied to the bit line or the source line, the bit line or the source line is discharged to a first voltage, and the first selection gate line is discharged to a second voltage; as well as After the first selection gate line is discharged to a second voltage, turning on the first selection transistor; The second voltage is greater than the first voltage, and the second voltage is less than the second selection voltage.

23. The memory according to claim 22, wherein: The peripheral circuit is further configured to: Before the first selection transistor is turned on in the second period, the first selection gate line is maintained discharged to the second voltage in the third period.

24. The memory according to claim 22, wherein: The peripheral circuit is further configured to: Before the bit line or the source line is discharged to the first voltage, the first selection gate line is maintained discharged to the second voltage within a third period.

25. The memory according to claim 15, wherein: The peripheral circuit is further configured to: In the second period, applying a third turn-on voltage to a control switch in a discharge path in the page buffer coupled to the bit line to turn on the discharge path in the page buffer coupled to the bit line; as well as During the second period, a cutoff voltage is applied to a control switch between the bit line and a sensing node in the page buffer, thereby disconnecting a precharge path in the page buffer and a path between latches.

26. The memory according to claim 15, wherein: The peripheral circuit is further configured to: During the first period, a ground voltage is applied to a plurality of word lines coupled to the memory cells; and The erase voltage is applied to the bit line and the source line at the same time.

27. The memory according to any one of claims 15 to 26, characterized in that: The peripheral circuit is further configured to: Applying an erase verification voltage to a selected word line on the memory block; wherein the selected word line is any word line on the memory block; Applying a turn-on voltage to unselected word lines on the memory block; wherein the turn-on voltage is greater than or equal to the maximum threshold voltage of the memory cell; and the erase verification voltage is less than the turn-on voltage; and The memory cell corresponding to the selected word line is read to obtain a verification result of the erase verification operation.

28. A memory system, characterized in that: The memory system comprises: One or more memories according to any one of claims 15 to 27, and a controller coupled to and controlling the memory.

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