Method of operating non-volatile memory, corresponding device and computer program product

Abstract

The present disclosure relates to a method of operating a non-volatile memory, a corresponding device and a computer program product. A method of operating a non-volatile memory (NVM) device in response to a fault in a memory sub-segment in an addressable memory segment of the NVM device, the NVM device comprising a backup memory segment, the backup memory segment comprising a backup memory sub-segment, the spare memory sub-segments are configured to replace respective failed memory sub-segments in the addressable memory segments. The method includes comparing addresses of memory sub-segments of an addressable memory segment as access candidates with a set of faulty memory sub-segment addresses, the set including addresses of faulty memory sub-segments coupled with a mask, the mask indicating an associated fault type; and replacing a memory sub-section of the addressable memory section as an access candidate with a spare memory sub-section of the spare memory sections, where the address comparison indicates a match through the identification of the compared address or a match through the identification of the compared address to which a mask is applied, the mask indicating an associated failure type.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102024000007324, filed on April 3, 2024, which is hereby incorporated herein by reference. Technical Field

[0003] This specification relates to the technical field of data storage.

[0004] One or more embodiments may be applied to computer storage technology, such as non-volatile memory (NVM).

[0005] For example, one or more embodiments may be applied to non-volatile phase-change memory currently referred to as PCM NVM or ePCM NVM. Background Art

[0006] Non-volatile memory (NVM) plays a key role in the field of digital storage, providing persistent data storage even in the absence of power.

[0007] In fact, the evolution of NVM technology has played an important role in shaping the power and efficiency of most electronic devices, ranging from computers and smartphones to embedded systems and data centers.

[0008] For example, phase change memory (referred to as PCM) is a computer memory technology and is typically a non-volatile random access memory technology that can also be embedded in integrated circuit (IC) semiconductor devices.

[0009] PCM operates bit by bit using an electric current that flows through a heated material called a phase change material (such as chalcogenide glass), thereby melting and quenching the phase change material, rendering it amorphous, or maintaining the phase change material within its crystallization temperature range, thereby switching it to a crystalline state. The amorphous state is associated with a low logic level for 1 bit of information, while the crystalline state is associated with a high logic level for the 1 bit of information.

[0010] Other examples of the nonvolatile memory may be ROM (Read Only Memory), flash memory, F-RAM (Ferroelectric Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeFET memory, RRAM memory, and the like.

[0011] NVM memory can be susceptible to failed cells (either arising during the manufacturing process or due to wear and tear during the life of the memory), potentially resulting in unreliable or erroneous data storage.

[0012] To solve such problems, NVM memories usually contain some redundancy, e.g. spare rows and / or columns for replacing faulty rows and / or columns, with the aim of maintaining the overall functionality of the memory device, that is, managing and mitigating possible defects or faults in the memory cells.

[0013] Therefore, such a redundancy approach can be used in NVMs in order to repair malfunctioning or faulty cells, replacing them with spare cells added in addition to the main array cells, and only in case such malfunctioning or faulty cells are detected.

[0014] Depending on the type of defect to be repaired, different types of redundancy approaches can be considered, e.g. row, column, sector or other redundancy.

[0015] For example, the case of a short between two adjacent columns can be repaired by replacing the two “bad” columns with a pair of spare columns, that is, with a pair of redundant columns.

[0016] Figure 1 A typical redundancy architecture 10 is illustrated, comprising an additional sense amplifier 104 red (that is, a redundant sense amplifier).

[0017] Figure 1 The architecture 10 of Figure 1 comprises a redundancy logic 100 configured to receive an address bus ADDR related to a memory section to be written / read, and a redundancy configuration bus indicating a bad memory section to be replaced with a spare memory section.

[0018] Such a redundancy configuration bus can be obtained from a plurality of redundancy registers RR, including for example a first redundancy register RR a , a second redundancy register RR b ,..., and a last redundancy register RR z .

[0019] The redundancy logic 100 is further configured to drive a plurality of multiplexers (collectively 102) via one or more selection commands in order to select either a main memory cell or a spare memory cell, the plurality of multiplexers including for example a first multiplexer 1021, a second multiplexer 1022, a third multiplexer 1023,..., and an Nth multiplexer 102 N .

[0020] The plurality of multiplexers 102 can be coupled to a plurality of sense amplifiers (collectively 104), such a plurality of sense amplifiers 104 including main sense amplifiers, e.g. a first sense amplifier 1041, a second sense amplifier 1042, a third sense amplifier 1043,..., and an Nth sense amplifier 104 Nand a redundant sense amplifier 104 red .

[0021] Each multiplexer of the plurality of multiplexers 102 can be coupled to a respective main sense amplifier 104 via a first terminal 1-N and to a redundant sense amplifier 104 via a second terminal red Such multiplexers are configured to select the main sense amplifier output signal SO 1-N (indicative of the selected main column) or the redundant sense amplifier output signal SO red (indicative of the selected spare column) at the second terminal based on a respective selection command sent from the redundancy logic 100 to the multiplexer.

[0022] Each multiplexer of the plurality of multiplexers 102 can be further configured to provide a respective data output signal DO 1-N (that is, the main sense amplifier output signal SO 1-N or the redundant sense amplifier output signal SO red ) as output based on the received respective selection command, such data output signal DO 1-N indicating the selected column (main column or spare column).

[0023] The main sense amplifiers 104 1-N may be coupled between respective main column selectors (collectively 106 1-N ) and respective multiplexers 102 and can be configured to provide respective main sense amplifier output signals SO 1-N indicative of the selected main column to the respective coupled multiplexers 102.

[0024] Each of the main column selectors 106 1-N may be configured to select a main column among a plurality of main columns included in a respective main column array AC 1-N and to provide a signal indicative of the selected main column to the respective coupled main sense amplifier 104 1-N .

[0025] Similarly, the redundant sense amplifiers 104 red may be coupled between a redundant column selector 106 red and respective multiplexers 102 and can be configured to provide redundant sense amplifier output signals SO red indicative of the selected spare column to the coupled multiplexers 102.

[0026] The redundant column selector 106 red may be configured to select a spare column among a plurality of spare columns included in a respective spare column array AC redselecting a spare column among a plurality of spare columns comprised in the spare column array AC red .

[0027] Thus, the spare column array AC red comprised spare columns can be addressed in parallel to the main columns comprised in one of the main column arrays AC 1-N and via the redundancy column selector 106 red . red The selected spare column can be read by the redundancy sense amplifier 104 1-N .

[0028] Thus, if a main column comprised in one of the main column arrays AC red is bad, the redundancy logic 100 is configured to replace the output of the main sense amplifier 104 red coupled to the bad main column (that is, the main sense amplifier output signal SO 1-N ) with the output of the redundancy sense amplifier 104 1-N via one or more selection commands.

[0029] Additionally, information related to the bad column can be stored in a redundancy register RR, such a redundancy register RR being configured to store information related to the address of the bad column and the number of the main sense amplifier 104 1-N comprising such bad column.

[0030] Note that Figure 1 the structure 10 can comprise more than one redundancy sense amplifier 104 red and more than one redundancy column selector 106 red together with a respective spare column array AC red .

[0031] In this case, if there is more than one redundancy sense amplifier 104 red , each multiplexer of the plurality of multiplexers 102 can be configured to receive at its input terminals each output SO red provided by the redundancy sense amplifiers of the more than one redundancy sense amplifier 104 red .

[0032] Note that in this case, the output SO i of the main sense amplifier comprising the bad column (with i ranging from 1 to N) is replaced by the output SO red of one of the redundancy sense amplifiers 104 red (that is, the redundancy sense amplifier used to repair such bad column).

[0033] Note that the redundant sense amplifier 104 red It can be considered that the main sense amplifier 104 1-N The same architecture is used to implement .

[0034] In addition, such redundant sense amplifier 104 red Can be coupled to the AC array with spare columns red Related redundant column selector 106 red The spare column array contains the same number of columns as the main column array AC 1-N One of the columns includes a number of spare columns that are equal to the number of main columns.

[0035] Figure 2 Pictured Figure 1 Example bad master column replacement in a typical redundant architecture 10.

[0036] Note that in the drawings of this application, bad main columns and corresponding bad signals are indicated by gray and black dashed lines, while spare columns for replacing such bad main columns and corresponding spare signals are indicated by white and black dashed lines.

[0037] Figure 2 A single bad main column replacement is illustrated, wherein the bad main column to be replaced is the third main column included in the second main column array AC2.

[0038] Therefore, such a bad main column is replaced by the spare column array AC red The third spare column included in is replaced.

[0039] Note that the bad main column to be replaced can also be any other main column, or another main column array AC 1-N The main columns included are, in fact, Figure 2 The scenarios reported in are only illustrative scenarios.

[0040] In this case, the spare column considered to replace the bad main column is the column in the position corresponding to the bad main column considered.

[0041] Therefore, one of the redundant registers RR can be configured to store the data corresponding to the bad primary column (that is, Figure 2 The address of the third main column in the exemplary scenario and the main sense amplifier 104 including such a bad main column 1-N (That is, in Figure 2 In the exemplary scenario of FIG. 1 , information related to the number of the second main sense amplifier 1042 is provided.

[0042] Figure 3 A typical redundant architecture 20 is shown, which includes a plurality of memory sectors (collectively referred to by reference numeral SE) and additional sense amplifiers 104.red (ie, redundant sense amplifiers), for example, the plurality of memory sectors include a first memory sector SE a , second memory sector SE b , the third memory sector SE c , ..., and the last memory sector SE i .

[0043] Note that reference has been made Figure 1 Description Figure 3 The parts, elements and / or components illustrated in the drawings are represented by the same reference numerals used previously in the drawings. Therefore, the description of such previously described parts, elements and / or components will not be repeated below in order not to overload this specification.

[0044] exist Figure 3 In the structure 20, the main sense amplifier 104 1-N Each of these can be coupled between:

[0045] A plurality of main column selectors including a first main column selector 106 1-N,a , second main column selector 106 1-N,b , third main column selector 106 1-N,c , ..., and finally a main column selector 106 1-N,i , wherein each of the plurality of main column selectors is included in a different memory sector, and

[0046] A corresponding multiplexer 102 is provided.

[0047] Such a main sense amplifier 104 1-N Each of the multiplexers 102 may be further configured to provide a corresponding main sense amplifier output signal SO to a corresponding coupled multiplexer 102. 1-N , the main sense amplifier output signal indicates a main column selected among a plurality of main columns included in the main column array.

[0048] The main column array may be selected from a plurality of main column arrays (including the first column array AC) associated with different main column selectors and corresponding different sectors. 1-N,a 、Second row array AC 1-N,b 、The third row array AC 1-N,c , ..., and the last column array AC 1-N,i ) is selected.

[0049] Therefore, the main column selector 106 1-N,a-i Each of the may be configured to be included in the corresponding main column array AC 1-N,a-iselecting a main column among the plurality of main columns and providing a signal indicative of the selected main column to a correspondingly coupled main sense amplifier 104 1-N .

[0050] Similarly, a redundant sense amplifier 104 red may be coupled between:

[0051] a plurality of redundant column selectors, collectively denoted by reference numeral 106 reda-redi refers to, including a first redundant column selector 106 reda , a second redundant column selector 106 redb , a third redundant column selector 106 redc , a last redundant column selector 106 redi wherein each redundant column selector of the plurality of redundant column selectors 106 reda-redi is included in a different memory sector, and

[0052] a corresponding multiplexer 102.

[0053] Such a redundant sense amplifier 104 red may be configured to provide a redundant sense amplifier output signal SO red to the coupled multiplexer 102, the redundant sense amplifier output signal being indicative of a selected spare column among a plurality of spare columns included in a spare column array.

[0054] The spare column array can be selected from a plurality of spare column arrays AC red,a-i including a first column array AC red,a , a second column array AC red,b , a third column array AC red,c , a last column array AC red,i .

[0055] Hence, each redundant column selector of the plurality of redundant column selectors 106 reda-redi may be configured to select a spare column among a plurality of spare columns included in a corresponding spare column array AC red,a-i and to provide a signal indicative of the selected spare column to the coupled redundant sense amplifier 104 red .

[0056] Note that a spare column included in one of the spare column arrays AC red,a-i may be addressed in parallel to a main column included in one of the main column arrays AC 1-N,a-i and the selected spare column can be read via the redundant sense amplifier 104 red .

[0057] Thus, if a main column included in one of the main column arrays AC 1-N,a-i is bad and is to be replaced, the redundancy logic 100 is configured to replace, via one or more selection commands, the output of the redundant sense amplifier 104 red (that is, the redundant sense amplifier output signal SO red ) for the output of the main sense amplifier 104 1-N coupled to the bad main column (that is, the main sense amplifier output signal SO 1-N associated with the bad main column).

[0058] In addition, information associated with the bad column can be stored in a redundancy register RR, such a redundancy register RR being configured to store information associated with the address of the bad column, with the number of the main sense amplifier 104 1-N including such bad column, and with the address of the sector including such bad column.

[0059] Note that, Figure 3 the structure 20 of the main column array AC red may include more than one redundant sense amplifier 104 reda-redi and more than one (or more) redundant column selector 106 red,a-i along with a corresponding spare column array AC red,a-i .

[0060] In this case, if there is more than one redundant sense amplifier 104 red , each multiplexer of the plurality of multiplexers 102 can be configured to receive, at its input terminal, each output SO red provided by a redundant sense amplifier of the more than one redundant sense amplifier 104 red .

[0061] Note that, in this case, the output SO i of the main sense amplifier including the bad column (where i ranges from 1 to N) is replaced by the output SO red of one of the redundant sense amplifiers 104 red (that is, the redundant sense amplifier used to repair such bad column).

[0062] Note that the redundant sense amplifier 104 red may be implemented considering the same architecture of the main sense amplifier 104 1-N .

[0063] In addition, such plurality of redundant column selectors 106 reda-redi may be associated with a corresponding spare column array AC red,a-i containing a number of columns equal to the number of columns of the main column array AC 1-N,a-iOne of the columns includes a number of spare columns that are equal to the number of main columns.

[0064] Figures 4 to 7 Pictured Figure 3 Example bad master column replacement in a typical redundant architecture.

[0065] Figure 4 The figure shows a single bad main column replacement, where the bad main column to be replaced is the second main column array AC of the third sector. 2,c The third main column included.

[0066] Therefore, such a bad main column is replaced by the spare column array AC of the third sector. red,c The third spare column included in is replaced.

[0067] Note that the bad main column to be replaced may also be any other main column, and may also be another main column array AC in a different sector. 1-N,a-i The main columns included are, in fact, Figure 4 The scenarios reported in are only illustrative scenarios.

[0068] In this case, the spare column considered for replacing the bad main column is a column included in the same sector as the bad main column and placed in a position corresponding to the bad main column considered.

[0069] Therefore, one of the redundant registers RR may be configured to store information related to:

[0070] Bad primary column (that is, Figure 4 The address of the third main column in the exemplary scenario of

[0071] The main sense amplifier 104 including such a bad main column 1-N (That is, in Figure 4 , and

[0072] Such bad main column sectors (that is, in Figure 4 In the exemplary scenario, the third sector is called SE c )’s address.

[0073] Figure 5 The figure shows several bad main columns being replaced, wherein the several bad main columns to be replaced include the second main column array AC of the third sector. 2,c The first main column and the second main column are included.

[0074] For example, in the event of a short circuit between two columns, several bad columns may appear.

[0075] Therefore, such several bad main columns are replaced by several spare columns (that is, the spare column array AC of the third sector).red,c The first spare column and the second spare column included in are replaced).

[0076] Note that the bad main columns to be replaced may also be any other main columns, and may also be other main column arrays AC in different sectors. 1-N,a-i In fact, the main columns included in Figure 5 The scenarios reported in are only illustrative scenarios.

[0077] In this case, the several spare columns considered for replacing the several bad main columns are columns included in the same sector as the several bad main columns and placed in positions corresponding to the several bad main columns considered.

[0078] Therefore, one of the redundant registers RR may be configured to store information related to:

[0079] Several bad master columns (that is, Figure 5 In the exemplary scenario of , the addresses of the first main column and the second main column are

[0080] The main sense amplifier 104 including several bad main columns 1-N (That is, in Figure 5 , and

[0081] Such a few bad main column sectors (that is, in Figure 5 In the exemplary scenario, the third sector is called SE c )’s address.

[0082] Figure 6 A single bad main column replacement is illustrated for each of the sectors, such that the single bad main column to be replaced is placed at the same position in each sector.

[0083] For example, in Figure 6 In the exemplary scenario of FIG. 1 , in each sector, the single bad main column to be replaced corresponds to the main column array AC included in the second main column array AC. 2,a-i The third main column in .

[0084] Therefore, in each sector, such a single bad main column is replaced by the corresponding spare column array AC. red,a-i The third spare column included in is replaced.

[0085] Note that in each sector, the position of a single bad main column to be replaced can also be any other position, or in another main column array AC. 1-N,a-i In fact, the position Figure 6 The scenarios reported in are only illustrative scenarios.

[0086] In this case, the spare column considered for replacing the single bad main column in each sector is a column placed in a position corresponding to the single bad main column considered.

[0087] Therefore, one of the redundant registers RR may be configured to store information related to:

[0088] A single bad primary column (that is, Figure 6 The address of the third main column in the exemplary scenario of

[0089] The main sense amplifier 104 including such a single bad main column 1-N (That is, in Figure 6 In the exemplary scenario of FIG, the number of the second main sense amplifier 1042 is shown.

[0090] Note that such redundant registers do not include sector addresses.

[0091] Figure 7 Figure 1 shows a bad main column array AC 1-N,a-i Replacement, wherein the bad main column array to be replaced is the second main column array AC of the third sector 2,c .

[0092] Therefore, such a bad main column array AC 2,c The spare column array AC of the third sector red,c replace.

[0093] Note that the bad main column array to be replaced can also be any other main column array AC possibly in a different sector. 1-N,a-i In fact, Figure 7 The scenarios reported in are only illustrative scenarios.

[0094] In this case, the spare column array considered for replacing the bad main column array is an array included in the same sector as the bad main column array.

[0095] Therefore, one of the redundant registers RR may be configured to store information related to:

[0096] The main sense amplifier 104 coupled to such a bad main column array 1-N (That is, in Figure 7 , and

[0097] Such bad main column array sectors (that is, in Figure 7 In the exemplary scenario, the third sector is called SE c )’s address.

[0098] Note that such redundant registers do not include bad main column addresses.

[0099] Note that other scenarios can also be considered, for example:

[0100] Replacing a bad main column array AC in each of the sectors 1-N,a-i Such bad main column array AC to be replaced 1-N,a-i Placed in the same position in each sector;

[0101] Replacing groups of four, eight or other number of adjacent bad main columns included in the same sector;

[0102] Replacing groups of two, four, eight or other number of adjacent bad main columns included in more than one sector;

[0103] Replacing a single bad bit in any of the main columns;

[0104] Replacing several bad bits in any several adjacent main columns or in any several adjacent main rows;

[0105] Replacing a part of any of the main columns; or

[0106] Similar replacements.

[0107] Note that each of such replacements has a different content of the redundant registers RR based on the address to be considered for identifying the part to be replaced (a column in only one sector, a single bit, a group of columns, etc.).

[0108] The known technical solution has a fixed and hard-coded content of the redundant registers RR.

[0109] Therefore, if the structures 10 and 20 and the corresponding redundant registers RR are designed to replace a given part of the array (for example, a column), each of the redundant registers RR can only replace the same kind of part, that is, designed to replace the given part.

[0110] For example, if the given part that can be replaced is a column, each of the redundant registers RR can be used to replace a column.

[0111] In this case, in the event of a short circuit between two adjacent columns, two redundant registers are used to replace the two columns.

[0112] In this case, in the event of a short circuit between four adjacent columns (that is, a column group), four redundant registers are used to replace such columns.

[0113] In general, the number of available redundant registers RR limits the number of faults that can be repaired.

[0114] It is noted that, if the kind of redundancy to be applied, that is, the given part considered to be replaced, does not fit the kind of defect present on silicon, the failed or faulty cell related to such defect is considered lost and unusable.

[0115] Therefore, a technical solution that helps to prevent the loss of failed or faulty cells in a non-volatile memory, NVM, allowing to replace them with spare cells in order to increase the endurance of such NVM would be beneficial. SUMMARY

[0116] It is an aim of one or more embodiments to help provide such a technical solution.

[0117] According to one or more embodiments, the aim is achieved via a method of operating a non-volatile memory having the features set out in the accompanying claims.

[0118] One or more embodiments relate to related devices.

[0119] One or more embodiments relate to related computer program products, loadable in at least one processing circuitry (e.g. a computer) and comprising software code for performing the steps of the method when the product is run on the at least one processing circuitry.

[0120] As used herein, a reference to such a computer program product is understood to refer equally to a computer-readable medium containing instructions for controlling a processing system so as to coordinate the implementation of the method according to one or more embodiments.

[0121] The claims are an integral part of the technical teaching provided in the embodiments.

[0122] The technical solution as described herein comprises a method of operating a non-volatile memory, NVM, device in response to a fault in at least one memory sub- section of an addressable memory section of the NVM device.

[0123] The NVM device further comprises a spare memory section comprising spare memory sub-sections configured to replace respective faulty memory sub-sections in the addressable memory section of the NVM device.

[0124] The method according to the technical solution described herein comprises:

[0125] comparing an address of a memory sub-section of the addressable memory section of the NVM device as access candidate with a set of faulty memory sub-section addresses, the set comprising at least one address of a faulty memory sub-section coupled with a mask, the mask indicating a related fault type; and

[0126] replacing a memory sub-section of the addressable memory section with a spare memory sub-section of a spare memory section in the spare memory section as a candidate for access, where such a comparison of addresses indicates a match of the identity of the compared addresses or a match of the identity of the compared addresses imposed with address masking by utilizing such a mask, where the mask indicates a related fault type.

[0127] The technical solutions as described herein help to prevent loss of failing or faulty cells in a non-volatile memory NVM, allowing to replace them with spare cells in order to increase the endurance of such a memory. BRIEF DESCRIPTION OF DRAWINGS

[0128] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings.

[0129] In the foregoing Figures 1 to 7 ;

[0130] Figure 8 illustrating a redundancy architecture comprising redundant sense amplifiers according to embodiments of the present specification;

[0131] Figure 9 and Figure 10 illustrating an exemplary bad main column replacement in a redundancy architecture of Figure 8 according to embodiments of the present specification;

[0132] Figure 11 illustrating another redundancy architecture comprising redundant sense amplifiers according to embodiments of the present specification;

[0133] Figure 12 illustrating an exemplary replacement in a redundancy architecture of Figure 11 according to embodiments of the present specification;

[0134] Figure 13 illustrating a redundancy architecture combining the architectures of Figure 8 and Figure 11 according to embodiments of the present specification; and

[0135] Figure 14 illustrating exemplary implementations of redundancy logic in a redundancy architecture of any of Figures 8 to 13 according to embodiments of the present specification, as well as extended redundancy registers and (global) redundancy mode registers.

[0136] Corresponding numerals and symbols in different figures generally refer to corresponding parts unless context dictates otherwise.

[0137] The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the embodiments.

[0138] The edges of the features drawn in the figures do not necessarily indicate limits of the features. DETAILED DESCRIPTION

[0139] In the following description, one or more specific details are described to provide an example embodiment of the disclosure. One or more embodiments can be obtained without one or more of the specific details, or with other methods, components, materials, and so forth. Other embodiments can have different configurations, components, and methods, and can be used in various applications.

[0140] Reference throughout this specification to "an embodiment" or "one embodiment" means that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" in various places in this specification do not necessarily refer to the same embodiment.

[0141] Furthermore, the particular configurations, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0142] The headings / reference herein are provided merely for convenience and thus do not define the limits of the protection or the scope of the embodiments.

[0143] For simplicity and illustrative purposes, the principles of the present disclosure are described by referring mainly to exemplary embodiments thereof. In the description, same reference numerals can be used to denote constituent elements having similar functions in different exemplary embodiments wherein the functions between constituent elements are similar. Unless otherwise defined, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The following description with reference to the accompanying drawings is provided to assist in understanding the principles of the present disclosure.

[0144] As described above, the technical solution as disclosed herein aims to help prevent loss of failed or faulty cells in a non-volatile memory NVM, allowing them to be replaced with spare cells in order to increase the endurance of such memory.

[0145] The technical solution as described herein includes a plurality of extended redundancy registers ERR comprising bits for addressing the non-volatile memory, and configured to address, via such bits, bad parts of the non-volatile memory to be replaced by spare parts.

[0146] The technical solution as described herein also includes:

[0147] a "per-die" redundancy mode register (also referred to as a global redundancy mode register) GRMR configured to include information related to the kind of redundancy to be applied on the die in order to implement the "per-die" approach, thereby allowing to decide per die, based on the defects of such die (that is, the kind of failure), the kind of redundancy (that is, the part that can be replaced) to be applied on the die in order to recover from such defects; and / or

[0148] a plurality of redundancy mode registers RMR, for example including a redundancy mode register RMR for each of the extension redundancy registers ERR, configured to include information related to the kind of redundancy to be applied on the part of the non-volatile memory addressed by the respective extension redundancy register in order to implement the "per-register" approach, thereby allowing to independently decide how to use each of the extension redundancy registers ERR, determining the kind of redundancy for each of the extension redundancy registers ERR based on the defects of the part of the non-volatile memory addressed by the respective extension redundancy register (that is, the kind of failure).

[0149] It is noted that even if the following description and the drawings related to the present technical solution refer to a redundancy architecture including a plurality of memory sectors (univocally denoted with the reference SE), the technical solution as described herein can be applied to a redundancy architecture including a single memory sector, for example the plurality of memory sectors including a first memory sector SE a , a second memory sector SE b , a third memory sector SE c ,..., and a last memory sector SE i .

[0150] The technical solution as described herein relates to a method of operating a non-volatile memory NVM device in response to a failure (for example, one or more failed or faulty units of the memory device having a related kind of failure), for example the related kind of failure being a column, a few columns, a bit, a few adjacent bits on the same column, an array, a portion of a column, etc. of at least one memory sub-sector in an addressable memory sector of the NVM device, for example indicated with the reference AC 1-N,a-i .

[0151] The NVM device further includes a spare memory sector, for example a memory sector indicated with the reference AC red,a-i , the spare memory sector including a spare memory sub-sector configured to replace a respective faulty memory sub-sector of the addressable memory sector AC red of the NVM device, for example via a redundancy sense amplifier 104 1-N and a plurality of multiplexers 102 1-N,a-i .

[0152] The method described herein comprises:

[0153] addressing memory segment AC of the NVM device 1-N,a-i the address of the memory subsegment (e.g. received via the address bus ADDR) as access candidate (e.g. to be read / written) is compared with a set of faulty memory subsegment addresses (e.g. one or more addresses included in a respective one of a plurality of extended redundancy registers ERR), the set comprising at least one address of a faulty memory subsegment coupled with a mask indicating a related fault type, e.g. one or more masks related to a kind of redundancy to be applied included in a plurality of redundancy mode registers RMR and / or a global redundancy mode register GRMR; and

[0154] for example, via the redundancy sense amplifier 104 red and the plurality of multiplexers 102 1-N with a spare memory subsegment of a spare memory segment AC red,a-i replaces the memory subsegment of the addressing memory segment AC 1-N,a-i addressed via the address bus ADDR as access candidate, such address comparison indicating a match by the identity of the compared address or by the identity of the compared address being applied with an address mask by means of a mask indicating a related fault type.

[0155] Note that such method can comprise storing the faulty memory addresses of the set of faulty memory subsegment addresses in a respective one of a plurality of (extended) redundancy registers ERR.

[0156] For example, Figure 8 Fig. illustrates a redundancy architecture 30 comprising a redundancy sense amplifier 104 red and implementing a "per-die" approach, according to an embodiment of the present specification.

[0157] Figure 8 The architecture 30 of Fig. comprises a redundancy logic 100 configured to receive:

[0158] an address bus ADDR related to a memory segment to be written / read, e.g. comprising an address of the memory segment to be written / read,

[0159] a "per-die" redundancy mode bus indicating a kind of redundancy to be applied on the die, and

[0160] an extended redundancy configuration bus indicating a bad memory segment to be replaced by a spare memory segment.

[0161] Such a "per-die" redundancy mode bus can be fetched from a "per-die" redundancy mode register (also referred to as a global redundancy mode register) GRMR configured to include information related to the kind of redundancy to be applied on the die, for example an address mask to mask a portion of the bits of the address bus ADDR in order to uniquely identify the kind of redundancy to be applied.

[0162] For example, if the column address is masked, the redundancy is applied to each column of the sector connected to the same sense amplifier.

[0163] For example, if the sector address is masked, the redundancy is applied to the same column in each sector.

[0164] Generally, the "per-die" redundancy mode register GRMR considered in the "per-die" approach or the plurality of redundancy mode registers RMR considered in the "per-register" approach can contain the same number of bits as the address bus ADDR.

[0165] In this case, each bit of the considered redundancy mode register (GRMR or RMR) can be used to mask or not mask the corresponding bit of the address bus ADDR based on its content.

[0166] Note that if an address bit is masked, it is not considered in the comparison operation (described below) between the address bus ADDR and the content of the considered extended redundancy register ERR.

[0167] Note that even if the following description focuses on redundancy mode registers RMR or GRMR having a number of bits equal to the number of bits of the address bus ADDR, different implementations having different numbers of bits can be considered.

[0168] For example, other possible implementations can be configured to not apply a one-to-one association between the bits of the address bus ADDR and the mask bits included in the redundancy mode register (RMR or GRMR).

[0169] For example, redundancy mode registers having fewer bits than the address bus ADDR can be considered.

[0170] In this case, each bit of the redundancy mode register can mask a group of bits of the address bus ADDR.

[0171] For example, a single bit of the considered redundancy mode register can mask the sector address (that is, all the bits of the address bus ADDR able to select a sector), another bit can mask the column address (that is, all the bits of the address bus ADDR able to select a column), or several address bits (for example, so that only even / odd bits can be selected), etc.

[0172] Note that any other combination of the previous cases can also be considered.

[0173] In summary, generally, the number of bits of the redundancy mode register RMR or GRMR is equal to or less than the number of bits of the address bus ADDR, and thus each bit of the considered redundancy mode register can mask one or more bits of the address.

[0174] The extended redundancy configuration bus can be obtained from a plurality of extended redundancy registers ERR comprising, for example, a first extended redundancy register ERR a , a second extended redundancy register ERR b ,..., and a last extended redundancy register ERR z .

[0175] Each extended redundancy register ERR of the plurality of extended redundancy registers ERR can:

[0176] comprise bits for addressing a non-volatile memory (e.g. the whole non-volatile memory or a part thereof (e.g. if the kind of redundancy can be applied on a part of the non-volatile memory)), and

[0177] be configured to address, via such bits, a bad part of the non-volatile memory to be replaced by a spare part.

[0178] The redundancy logic 100 is further configured to drive, via one or more selection commands, a plurality of multiplexers (collectively referred to as 102) in order to select a main memory cell or a spare memory cell, the plurality of multiplexers comprising, for example, a first multiplexer 1021, a second multiplexer 1022, a third multiplexer 1023,..., and an Nth multiplexer 102 N .

[0179] Note that such one or more selection commands can be generated based on the content of both the global redundancy mode register GRMR and the plurality of extended redundancy registers ERR.

[0180] Thus, the redundancy logic 100 can be configured to:

[0181] compare the received address bus ADDR with the bad memory section indicated by the extended redundancy configuration bus, that is to say, with the address of the bad memory section; and

[0182] if the address comparison indicates that the received address bus ADDR matches at least one address of the bad memory section by identification of the compared address to which a masking operation is applied based on the kind of redundancy to be applied on the die, that is to say, based on the type of fault affecting the addressed bad memory section, replace the memory section addressed by the address bus ADDR with a spare memory section.

[0183] For example, such a comparison operation can comprise:

[0184] comparing the received address bus ADDR with the bad memory segments indicated by the extended redundancy configuration bus in order to obtain one or more comparison signals, e.g. one or more comparison addresses obtained by comparing the address comprised in the received address bus ADDR with the addresses comprised in the extended redundancy register ERR related to the bad memory segments;

[0185] decoding the content of the global redundancy mode register GRMR in order to obtain information about the kind of redundancy to be applied on the die; and

[0186] determining, based on the comparison signals and the information about the kind of redundancy to be applied on the die, whether the memory segment addressed by the address bus ADDR is related to one of the bad memory segments to be replaced, e.g. by masking the comparison addresses with an address mask comprised in the global redundancy mode register GRMR.

[0187] For example, such a replacement operation can comprise, if the memory segment addressed by the address bus ADDR is related to one of the bad memory segments to be replaced, replacing one of the bad memory segments related to the address bus ADDR with a spare memory segment, e.g. by generating and applying one or more selection commands to the plurality of multiplexers 102, the one or more selection commands indicating one of such multiplexers 102 (related to the bad memory segment addressed in the address bus ADDR) to select the output of the redundancy sense amplifier 104 red .

[0188] The plurality of multiplexers 102 can be coupled to a plurality of sense amplifiers (collectively referred to as 104), such plurality of sense amplifiers 104 comprising main sense amplifiers, e.g. a first sense amplifier 1041, a second sense amplifier 1042, a third sense amplifier 1043, …, and an Nth sense amplifier 104 N and a redundancy sense amplifier 104 red .

[0189] Each multiplexer of the plurality of multiplexers 102 can be coupled via a first terminal to a respective main sense amplifier 104 1-N and via a second terminal to a redundancy sense amplifier 104 red such multiplexer being configured to select, based on a respective selection command sent from the redundancy logic 100 to the multiplexer, either a main sense amplifier output signal SO 1-N (indicative of the selected main column) at the first terminal or a redundancy sense amplifier output signal SO red(Indicates the selected spare column).

[0190] For example, if the redundancy logic 100 indicates via a corresponding select command that the redundant sense amplifier 104 is selected red The output of the redundant sense amplifier at the second terminal is selected, and the output signal SO red Otherwise, the main sense amplifier output signal SO is selected 1-N .

[0191] Each multiplexer in the plurality of multiplexers 102 may be further configured to provide a corresponding data output signal DO based on a corresponding selected command received. 1-N (That is, the main sense amplifier output signal SO 1-N or redundant sense amplifier output signal SO red ) as output, such data output signal DO 1-N Indicates the selected rank (primary or spare).

[0192] Main sense amplifier 104 1-N Each of these can be coupled between:

[0193] At least one main column selector 106 (e.g., Figure 8 The exemplary structure 30 illustrates a plurality of main column selectors 106 1-N,a-i , but a single main column selector 106 may also be considered 1-N );and

[0194] A corresponding multiplexer 102 is provided.

[0195] For example, if Figure 8 There are multiple main column selectors 106 as shown in the figure 1-N,a-i , such a plurality of main column selectors may include a first main column selector 106 1-N,a , second main column selector 106 1-N,b , third main column selector 106 1-N,c , ..., and finally a main column selector 106 1-N,i , and each of the plurality of main column selectors is included in a different memory sector.

[0196] Such a main sense amplifier 104 1-N Each of the master columns may also be configured to output a corresponding master sense amplifier signal SO indicating the selected master column. 1-N Provided to the corresponding coupled multiplexer 102.

[0197] For example, if there is a single master column selector 106 1-N , then the selected master column is selected from the master column selected by the single master column selector 1061-N selected among a plurality of main columns in a selected main column array.

[0198] For example, if as illustrated in Figure 8 there are a plurality of main column selectors 106 1-N,a-i , then such selected main column is selected among a plurality of main columns included in a main column array, such main column array being selected among a plurality of main column arrays (including the first column array AC 1-N,a , the second column array AC 1-N,b , the third column array AC 1-N,c ,..., and the last column array AC 1-N,i ) associated with different main column selectors and corresponding different sectors.

[0199] Hence, each of the main column selectors 106 (single main column selector 106 1-N or a plurality of main column selectors 106 1-N,a-i ) can be configured to select a main column among a plurality of main columns included in a corresponding main column array (single main column array AC 1-N or a plurality of main column arrays AC 1-N,a-i ) and to provide a signal indicative of the selected main column to a corresponding coupled main sense amplifier 104 1-N .

[0200] Similarly, a redundant sense amplifier 104 red may be coupled between:

[0201] at least one redundant column selector 106 red (e.g., a plurality of redundant column selectors 106 reda-redi are illustrated in the exemplary structure 30 of Figure 8 , but a single redundant column selector 106 red is also contemplated); and

[0202] a corresponding multiplexer 102.

[0203] For example, if as illustrated in Figure 8 there are a plurality of redundant column selectors 106 reda-redi , then such plurality of redundant column selectors can include a first redundant column selector 106 reda , a second redundant column selector 106 redb , a third redundant column selector 106 redc ,..., and a last redundant column selector 106 redi , and each of the plurality of redundant column selectors is included in a different memory sector.

[0204] The redundant sense amplifier 104 redmay also be configured to select a redundant column from among a plurality of redundant columns included in a respective array of redundant columns (a single array of redundant columns AC red to the coupled multiplexer 102.

[0205] For example, if there is a single redundant column selector 106 red then such a selected redundant column is selected from among a plurality of redundant columns included in an array of redundant columns AC red selected via the single redundant column selector 106 red .

[0206] For example, if as Figure 8 illustrated in Fig. 1 there are multiple redundant column selectors 106 reda-redi then such a selected redundant column is selected from among a plurality of redundant columns included in an array of redundant columns AC red,a-i selected from among a plurality of arrays of redundant columns AC red,a , AC red,b , AC red,c ,..., and a last array of redundant columns AC red,i associated with different redundant column selectors and respective different sectors.

[0207] Thus, each of the redundant column selectors 106 red (single redundant column selector 106 red or multiple redundant column selectors 106 red,a-i ) can be configured to select a redundant column from among a plurality of redundant columns included in a respective array of redundant columns (a single array of redundant columns AC red or a plurality of arrays of redundant columns AC red,a-i ) and to provide a signal indicative of the selected redundant column to the coupled main sense amplifier 104 red .

[0208] Note that the redundant columns included in the single array of redundant columns AC red or the plurality of arrays of redundant columns AC red,a-i may be addressable in parallel with the main columns included in the single array of main columns AC 1-N or the plurality of arrays of main columns AC 1-N,a-i , respectively.

[0209] The redundant column selected via the single redundant column selector 106 red or the multiple redundant column selectors 106 red,a-i may then be read by the redundant sense amplifier 104 red .

[0210] Thus, if the array of main columns AC 1-N or AC1-N,a-i the redundant sense amplifier 104 red outputs (that is, the redundant sense amplifier output signals SO red ) via one or more select commands to replace the output of the main sense amplifier 104 1-N coupled to the bad main column (that is, the main sense amplifier output signal SO 1-N associated with the bad main column).

[0211] Note that the structure 30 of the memory array 100 Figure 8 may include more than one redundant sense amplifier 104 red and more than one redundant column selector 106 red along with a corresponding spare column array AC red , or more than one redundant column selector 106 reda-redi along with a corresponding plurality of spare column arrays AC red,a-i .

[0212] Also, in this case, if there is more than one redundant sense amplifier 104 red , each multiplexer of the plurality of multiplexers 102 can be configured to receive at its input terminal each output SO red provided by one of the more than one redundant sense amplifier 104 red .

[0213] Also, note that in this case, the output SO i of the main sense amplifier including the bad column (where i ranges from 1 to N) is replaced by the output SO red of one of the redundant sense amplifiers 104 red (that is, the redundant sense amplifier used to repair such a bad column).

[0214] Note that the redundant sense amplifier 104 red may be implemented considering the same architecture of the main sense amplifier 104 1-N .

[0215] In addition, the redundant column selector 106 red or 106 reda-redi may be associated with a corresponding spare column array AC red or AC red,a-i containing a number of spare columns equal to the number of main columns included in one of the main column arrays AC 1-N or AC 1-N,a-i .

[0216] Thus, the method described herein can comprise storing in the memory (global) redundancy mode register GRMR such a mask indicating the relevant failure type, that is to say, the information related to the kind of redundancy to be applied, which is the failure type of the addressable memory segment AC 1-N,a-i , that is to say, the failure type related to the kind of redundancy to be applied on the die.

[0217] Figure 9 and Figure 10 Fig. 1 illustrates an exemplary bad main column replacement in the redundancy architecture 30 according to an embodiment of the present description. Figure 8

[0218] Figure 9 Fig. 2 illustrates a "per-die" method selecting an exemplary "per-column" replacement as the kind of redundancy to be applied on the die, that is to say, the part that can be replaced.

[0219] Thus, in this case, the global redundancy mode register GRMR is configured to comprise information indicating "per-column" redundancy as the kind of redundancy to be applied on the die, for example, an address mask masking the segment of the memory address comprising the row address, so that when using the "per-column" kind of redundancy in the "per-die" method, the row address is not considered in the comparison operation between the address bus ADDR and the content of the considered extended redundancy register ERR.

[0220] Thus, based on the content of the global redundancy mode register GRMR indicating "per-column" redundancy, the redundancy logic 100 is configured to generate one or more selection commands based only on a part of the address bits comprised in the extended redundancy register ERR and in the address bus ADDR, that is to say, based only on the address bits addressing the column and the sector, discarding the address bits related to the row.

[0221] Indeed, for example, the determination operation performed by the redundancy logic 100 can mask the comparison address obtained by comparing the address bits comprised in the extended redundancy register ERR with the address bits comprised in the address bus ADDR with the address mask comprised in the global redundancy mode register GRMR, thus masking the address bits related to the memory row.

[0222] For example, in the case of Figure 9 , the bad main column to be replaced is a single bad main column corresponding to:

[0223] a second main column comprised in the first main column array AC 1,i of the i-th sector;

[0224] a last main column comprised in the third main column array AC 3,i of the i-th sector;​

[0225] The third main column is included in the second main column array AC of the second sector 2,b in; and

[0226] The first main column is included in the third main column array AC of the first sector 3,a middle.

[0227] Therefore, in Figure 9 In the exemplary scenario of FIG. 5 , a plurality of extended redundancy registers ERR may be configured to address such a bad main column to be replaced.

[0228] Using the above configuration, such a single bad primary rank can be replaced with a corresponding spare rank corresponding to:

[0229] The second spare column is included in the spare column array AC of the i-th sector. red,i middle;

[0230] The last spare column, which is included in the spare column array AC of the i-th sector red,i middle;

[0231] The third spare column is included in the spare column array AC of the second sector. red,b in; and

[0232] The first spare column is included in the spare column array AC of the first sector red,a middle.

[0233] Note that the bad primary column considered may also be a set of any other primary columns, which may also include other primary arrays AC with different numbers of columns or possibly in different sectors. 1-N,a-i The columns included in Figure 9 The scenarios reported in are only illustrative scenarios.

[0234] In this case, the corresponding spare column considered for replacing such a bad main column is a column included in the same sector as the corresponding bad main column and placed in a position corresponding to such a corresponding bad main column.

[0235] Note that in Figure 9 In the structure 30, the bad main column in the different main arrays located at the same position but in the same sector (for example, the first main column array AC included in the i-th sector) 1,i The first main column and the second main column array AC included in the i-th sector 2,i The first main column in the ith sector) cannot be replaced by the corresponding spare space because the two bad main columns are to be replaced by the same spare column (for example, the spare column array AC included in the i-th sector in the previous example). red,i The first spare column in is replaced.

[0236] Note that the previous problem can be solved by considering more than one redundant sense amplifier 104 red and more than one redundant column selector 106 reda-redi along with a respective plurality of spare column arrays AC red,a-i .

[0237] Figure 10 A "per-die" approach is illustrated, which selects an exemplary "few columns" replacement as the kind of redundancy to be applied on the die (that is, the part that can be replaced).

[0238] Thus, in this case, the global redundancy mode register GRMR is configured to include information indicating "few columns" redundancy as the kind of redundancy to be applied on the die, for example an address mask masking a segment of the memory address containing the row address and the less significant bits of the column address, so that when using the "few columns" kind of redundancy in a "per-die" approach, the row address and the less significant bits of the column address are not considered in the comparison operation between the address bus ADDR and the content of the considered extended redundancy register ERR.

[0239] Thus, based on the content of the global redundancy mode register GRMR indicating "few columns" redundancy, the redundancy logic 100 is configured to generate the one or more selection commands based only on a part of the address bits included in the extended redundancy register ERR and in the address bus ADDR (that is, based only on the address bits addressing a few columns and sectors), discarding the address bits related to the row and the less significant bits of the column address.

[0240] Indeed, for example, the determination operation performed by the redundancy logic 100 can mask the comparison address obtained by comparing the address bits included in the extended redundancy register ERR with the address bits included in the address bus ADDR with the address mask included in the global redundancy mode register GRMR, thus masking the address bits related to the memory row and the less significant bits of the column address.

[0241] For example, in Figure 10 the few bad main columns to be replaced correspond to:

[0242] the first main column and the second main column, which are included in the first main column array AC 1,i in the i-th sector;

[0243] the penultimate main column and the last main column, which are included in the third main column array AC 3,i in the i-th sector;

[0244] the third main column and the fourth main column, which are included in the second main column array AC 2,b in the second sector; and

[0245] a first main column and a second main column comprised in a third main column array AC 3,a of the first sector.

[0246] Therefore, in the exemplary scenario of Figure 10 , the plurality of extended redundancy registers ERR can be configured to address such few bad main columns to be replaced.

[0247] Using the above configuration, such few bad main columns can be replaced respectively with corresponding few spare columns corresponding to:

[0248] a first spare column and a second spare column comprised in a spare column array AC red,i of the i-th sector;

[0249] a penultimate spare column and a last spare column comprised in a spare column array AC red,i of the i-th sector;

[0250] a third spare column and a fourth spare column comprised in a spare column array AC red,b of the second sector; and

[0251] a first spare column and a second spare column comprised in a spare column array AC red,a of the first sector.

[0252] Note that the few bad main columns under consideration can also be any other set of few bad main columns comprising a different number of few bad main columns or possibly few bad main columns comprised in other main arrays AC 1-N,a-i in different sectors, in fact, Figure 10 the scenario reported in the foregoing is just an exemplary scenario.

[0253] In this case, the corresponding few spare columns under consideration for replacing such few bad main columns are columns comprised in the same sector as the corresponding few bad main columns and collocated in positions corresponding to such corresponding few bad main columns.

[0254] Note that in the structure 30 of Figure 10 , few bad main columns located in the same position but in different main arrays AC 1,i of the same sector (e.g. a first main column and a second main column comprised in a first main column array AC 2,i of the i-th sector and a first main column and a second main column comprised in a second main column array AC red,i of the i-th sector) can not be replaced by corresponding few spare columns, as such few bad main columns are to be replaced by the same few spare columns (e.g. a first spare column and a second spare column comprised in a spare column array AC red,i of the i-th sector in the previous example).

[0255] Likewise, note that the previous problem can be solved by considering more than one redundant sense amplifier 104 red and more than one redundant column selector 106 reda-redi along with a respective plurality of spare column arrays AC red,a-i .

[0256] Figure 11 Fig. illustrates a redundant architecture 40 comprising redundant sense amplifiers 104 red and implementing a "per register" approach, according to embodiments of the present specification.

[0257] Figure 11 The architecture 40 of Fig. comprises a redundancy logic 100 configured to receive:

[0258] an address bus ADDR related to the memory section to be written / read, e.g. comprising the address of the memory section to be written / read, and

[0259] an extended redundancy configuration bus indicating the bad memory section to be replaced by a spare memory section.

[0260] Such an extended redundancy configuration bus can be fetched from a plurality of extended redundancy registers ERR comprising, e.g., a first extended redundancy register ERR a , a second extended redundancy register ERR b ,..., and a last extended redundancy register ERR z .

[0261] Each extended redundancy register of the plurality of extended redundancy registers ERR can:

[0262] comprise bits for addressing the non-volatile memory, e.g. the whole non-volatile memory or a portion thereof (e.g. if the kind of redundancy can be applied on a portion of the non-volatile memory), and

[0263] be configured to address, via such bits, the bad portion of the non-volatile memory to be replaced by a spare portion.

[0264] The redundancy logic 100 can be further configured to receive a "per register" redundancy mode bus indicating, for each extended redundancy register of the plurality of extended redundancy registers ERR, the kind of redundancy to be applied to the portion of the non-volatile memory addressed by the considered extended redundancy register.

[0265] Such a "per register" redundancy mode bus can be fetched from a plurality of redundancy mode registers RMR comprising, e.g., a first redundancy mode register RMRa , a second redundancy mode register RMR b ,..., and a last redundancy mode register RMR z .

[0266] Each of such redundancy mode registers RMR is associated with a respective extended redundancy register, and is configured to include information about the kind of redundancy to be applied to the part of the non-volatile memory addressed by such respective extended redundancy register.

[0267] In general, the number of registers in the plurality of redundancy mode registers RMR can be equal to or less than the number of extended redundancy registers ERR.

[0268] If the number of registers in the plurality of redundancy mode registers RMR is equal to the number of extended redundancy registers ERR, there is a one-to-one association between the redundancy mode registers RMR and the extended redundancy registers ERR.

[0269] If the number of registers in the plurality of redundancy mode registers RMR is less than the number of extended redundancy registers ERR, each redundancy mode register RMR can be associated with a group of extended redundancy registers ERR.

[0270] In this case, the selection of the kind of redundancy to be applied is done for a group of extended redundancy registers ERR.

[0271] For example, each of such redundancy mode registers RMR can include an address mask for masking the bits of the address bus ADDR that are not considered in the comparison operation between such address bus ADDR and the content of the considered extended redundancy register ERR when using the considered "per register" kind of redundancy associated with such respective extended redundancy register.

[0272] Hence, it is noted that there can be a redundancy mode register RMR for each extended redundancy register ERR, and thus, the number of registers in the plurality of redundancy mode registers RMR can be equal to the number of registers in the plurality of extended redundancy registers ERR.

[0273] Alternatively, the number of registers in the plurality of redundancy mode registers RMR can be less than the number of extended redundancy registers ERR, and thus, in this case, one or more of the plurality of redundancy mode registers RMR can be associated with a group of extended redundancy registers ERR, that is, with more than one extended redundancy register ERR.

[0274] The redundancy logic 100 is further configured to drive the plurality of multiplexers 102 via one or more selection commands, as Figure 8one or more selection commands are generated based on the contents of both the plurality of redundancy mode registers RMR and the plurality of extended redundancy registers ERR.

[0275] Thus, the redundancy logic 100 can be configured to:

[0276] compare the received address bus ADDR with the bad memory section indicated by the extended redundancy configuration bus, that is, with the address of the bad memory section; and

[0277] if the address comparison indicates that the received address bus ADDR matches at least one address of the bad memory section by identification of the compared address to which a masking operation is applied based on the kind of redundancy to be applied on the addressed part of the non-volatile memory, that is, based on the type of fault affecting the addressed bad memory section, replace the memory section addressed by the address bus ADDR with the spare memory section.

[0278] For example, such a comparison operation can comprise:

[0279] compare the received address bus ADDR with the bad memory section indicated by the extended redundancy configuration bus in order to obtain one or more comparison buses, for example, one or more comparison addresses obtained by comparing the address comprised in the received address bus ADDR with the addresses comprised in the extended redundancy registers ERR related to the bad memory section;

[0280] decode the contents of the plurality of redundancy mode registers RMR in order to obtain information on the kind of redundancy to be applied to the part of the non-volatile memory addressed by the extended redundancy registers ERR; and

[0281] determine whether the memory section addressed by the address bus ADDR is related to one of the bad memory sections to be replaced based on the comparison bus(es) and the information on the kind of redundancy to be applied to the part of the non-volatile memory addressed by such extended redundancy registers ERR, for example, by masking the comparison address with the respective address mask comprised in the plurality of redundancy mode registers RMR.

[0282] For example, such a replacement operation may include, if the memory segment addressed by the address bus ADDR is associated with one of the bad memory segments to be replaced, replacing one of the bad memory segments associated with the address bus ADDR with a spare memory segment, for example, by generating and applying one or more select commands to a plurality of multiplexers 102, the one or more select commands instructing one of such multiplexers 102 (the one associated with the bad memory segment addressed in the address bus ADDR) to select the redundant sense amplifier 104. red Output.

[0283] Notice, Figure 11 The diagram in the figure has been referenced Figure 8 The parts, elements and / or components described are represented by the same reference numerals used previously in this figure. Therefore, the description of such previously described parts, elements and / or components will not be repeated below in order not to overload this specification sheet.

[0284] Also note that reference has been made to Figure 8 The observations and conclusions described can also be applied to Figure 11 40, therefore, the description of such previously described observations and conclusions will not be repeated below so as not to overburden this specification.

[0285] Thus, the methods described herein may include:

[0286] The corresponding redundant mode register RMR is coupled (see Figures 11 to 13 ) to the (extended) redundant registers in the multiple (extended) redundant registers ERR, and

[0287] storing a respective mask indicating the relevant fault type (that is to say information about the kind of redundancy to be applied to the portion of the non-volatile memory addressed by the coupled (extended) redundancy register) in a respective redundancy mode register RMR;

[0288] The fault memory address and the mask coupled thereto and indicating the relevant fault type are respectively stored in the redundancy register ERR and in the corresponding redundancy mode register RMR coupled thereto.

[0289] Note that such methods described herein may include:

[0290] coupling a set of (extended) redundant registers (that is, a set comprising more than one extended redundant register) of the plurality of (extended) redundant registers ERR to the same respective redundant mode register RMR;

[0291] wherein the faulty memory address stored in the (extended) redundancy register ERR comprised in such a set is coupled to the mask indicating the related fault type stored in the same corresponding redundancy mode register RMR.

[0292] Further, it is noted that the corresponding mask indicating the related fault type can comprise at least one first mask indicating a first related fault type and at least one second mask indicating a second related fault type, wherein the first mask and the second mask are stored in a first redundancy mode register (e.g. the first redundancy mode register RMR a ) and in a second redundancy mode register (e.g. the second redundancy mode register RMR b ), the first mask and the second mask being identical or different therebetween.

[0293] For example, if the first related fault type and the second related fault type indicate the same fault type, the first mask can be identical to the second mask.

[0294] For example, if the first related fault type and the second related fault type indicate different fault types, the first mask can be different from the second mask.

[0295] Figure 12 Fig. illustrates an exemplary substitution via the “per register” approach in the redundancy architecture 40 of Figure 11 Fig. 1, according to an embodiment of the present description.

[0296] As previously described, the “per register” approach allows to apply different kinds of redundancy independently for each one of the extended redundancy registers ERR, thus selecting the array portion to be substituted with the redundancy portion.

[0297] The plurality of extended redundancy registers ERR can be configured to address a bad primary section of memory to be substituted.

[0298] With regard to the redundancy mode register RMR, for example, in the exemplary scenario of Figure 12 Fig. 1:

[0299] The first redundancy mode register RMR a related to the first extended redundancy register ERR a may comprise information indicating the “per column” redundancy as the kind of redundancy to be applied (e.g. an address mask for masking the section of the memory address containing the row address), so that when using the “per column” kind of redundancy of the first redundancy mode register RMR a the row address bits are not considered in the comparison operation between the address bus ADDR and the content of the extended redundancy register ERR;

[0300] The second redundancy mode register RMR a related to the second extended redundancy register ERRb A second redundancy mode register RMR related b may comprise information indicating "few columns" redundancy as the kind of redundancy to be applied (e.g. an address mask to mask a section of the memory address containing the row address and the less significant bits of the column address) so that when using the "few columns" kind of redundancy of the second redundancy mode register RMR, the row address bits and the less significant bits of the column address are not considered in the comparison operation between the address bus ADDR and the content of the extended redundancy register ERR. b

[0301] A third redundancy mode register related to a third extended redundancy register can comprise information indicating "by array" redundancy (i.e. including all columns in the same column array of a given sector) as the kind of redundancy to be applied (e.g. an address mask to mask a section of the memory address containing the row address and the column address bits) so that when using the "by array" kind of redundancy of the third redundancy mode register, the row address bits and the column address bits are not considered in the comparison operation between the address bus ADDR and the content of the extended redundancy register ERR;

[0302] A fourth redundancy mode register related to a fourth extended redundancy register can comprise information indicating "by bit" redundancy (i.e. related to a single bit) as the kind of redundancy to be applied (e.g. an address mask not masking any bit of the memory address) so that when using the "by bit" kind of redundancy of the fourth redundancy mode register, each bit of the memory is addressable to be replaced with a spare bit;

[0303] A fifth redundancy mode register related to a fifth extended redundancy register can comprise information indicating "by part of column" redundancy as the kind of redundancy to be applied (e.g. an address mask to mask a section of the memory address different from the section used to address the considered part of column and section) so that when using the "by part of column" kind of redundancy of the fifth redundancy mode register, a part of the row address bits are not considered in the comparison operation between the address bus ADDR and the content of the extended redundancy register ERR; and

[0304] A sixth redundancy mode register related to a sixth extended redundancy register can comprise information indicating "few adjacent bits on the same column" (e.g. considering few adjacent bits) redundancy as the kind of redundancy to be applied (e.g. an address mask to mask only the row address less significant bits of the memory address) so that when using the "few adjacent bits on the same column" kind of redundancy of the sixth redundancy mode register, each few bits of the memory are addressable to be replaced with a spare few bits.

[0305] Thus, in Figure 12 ​In an exemplary scenario of the type where the Redundancy Mode Register RMR indicates the content of the corresponding redundancy category based on the Redundancy Logic 100 being configured to generate one or more selection commands based on only a portion of the address bits included in the Extension Redundancy Register ERR and in the Address Bus ADDR, that is:

[0306] If a first Redundancy Mode Register RMR is considered a then the one or more selection commands are generated based on only the address bits addressing the columns and the sectors, discarding the address bits related to the rows;

[0307] If a second Redundancy Mode Register RMR is considered b then the one or more selection commands are generated based on only the address bits addressing a few columns and the sectors, discarding the address bits related to the rows and the lower significant bits of the column addresses;

[0308] If a third Redundancy Mode Register is considered then the one or more selection commands are generated based on only the address bits addressing the sectors, discarding the address bits related to the rows and the columns;

[0309] If a fourth Redundancy Mode Register is considered then the one or more selection commands are generated based on all the address bits;

[0310] If a fifth Redundancy Mode Register is considered then the one or more selection commands are generated based on only the address bits addressing a portion of the columns and the sectors, discarding the other bits of the address; and

[0311] If a sixth Redundancy Mode Register is considered then the one or more selection commands are generated based on all the address bits except the lower significant bits of the row address of the address.

[0312] In fact, for example, the determination operation performed by the Redundancy Logic 100 can mask the comparison address obtained by comparing the address bits included in the Extension Redundancy Register ERR with the address bits included in the Address Bus ADDR with the address mask included in the Redundancy Mode Register considered as described above.

[0313] For example, in an exemplary scenario of the type where the Redundancy Mode Register RMR indicates the content of the corresponding redundancy category based on the Redundancy Logic 100 being configured to generate one or more selection commands based on only a portion of the address bits included in the Extension Redundancy Register ERR and in the Address Bus ADDR, that is: Figure 12 In this exemplary scenario, the one or more selection commands are generated so as to:

[0314] based on the information included in a first Redundancy Mode Register RMR a (that is, the information related to the address of the bad main column) and a first Extension Redundancy Register ERR a replacing the last main column included in the third main column array AC red,i of the i-th sector with the last spare column included in the spare column array AC 3,i of the i-th sector;

[0315] based on the information included in the second redundancy mode register RMR b (and that is, information related to the addresses of several bad main columns) and the second extended redundancy register ERR b based on the information included in the first spare column and in the second spare column included in the array of spare columns AC red,i of the i-th sector, replace the first main column and the second main column included in the array of first main columns AC 1,i of the i-th sector;

[0316] based on the information included in the third redundancy mode register (that is, "array by array" redundancy) and in the third extended redundancy register (that is, information related to the address of a bad main array), replace the array of third main columns AC red,c of the third sector with the array of spare columns AC 3,c of the third sector;

[0317] based on the information included in the fourth redundancy mode register (that is, "bit by bit" redundancy) and in the fourth extended redundancy register (that is, information related to the address of a bad single main bit), replace the single main bit included in the third main column of the second main array AC red,b of the second sector with a single spare bit included in the third spare column of the spare array AC 2,b of the second sector;

[0318] based on the information included in the fifth redundancy mode register (that is, "part of a column" redundancy) and in the fifth extended redundancy register (that is, information related to the address of a bad part of a main column), replace the part of the last main column included in the array of first main columns AC red,a of the first sector with a part of the last spare column included in the array of spare columns AC 1,a of the first sector; and

[0319] based on the information included in the sixth redundancy mode register (that is, "several adjacent bits on the same column" redundancy) and in the sixth extended redundancy register (that is, information related to the address of several adjacent main bits), replace the several adjacent main bits included in the second main column of the second main array AC red,a of the first sector with several adjacent spare bits included in the second spare column of the spare array AC 2,a of the first sector.

[0320] Note that other kinds of redundancy in different numbers can also be considered, which can be replaced by the corresponding part (that is, the part in the same position in the same sector) in the spare memory section.

[0321] Thus, bad memory sections located in the same position but in different main arrays of the same sector cannot be replaced by the corresponding spare memory sections, since both bad memory sections are to be replaced by the same spare memory section.

[0322] Also, it is noted that the previous problem can be solved by considering more than one redundant sense amplifier 104 red and more than one (plural) redundant column selector 106 reda-redi along with a corresponding plurality of spare column arrays AC red,a-i .

[0323] Figure 13 The architecture 30 of the combination Figure 8 of the architecture 40 of the redundancy architecture 50 according to an embodiment of the present specification, thus implementing both the "per-die" approach and the "per-register" approach. Figure 11

[0324] Figure 13 The architecture 50 comprises the redundancy logic 100 configured to receive:

[0325] an address bus ADDR related to the memory section to be written / read, for example comprising the address of the memory section to be written / read,

[0326] a "per-die" redundancy mode bus indicating the kind of redundancy that can be applied on the die, and

[0327] an extended redundancy configuration bus indicating the bad memory section to be replaced by the spare memory section.

[0328] Such "per-die" redundancy mode bus can be fetched from a "per-die" redundancy mode register (also referred to as global redundancy mode register) GRMR configured to comprise information related to the kind of redundancy that can be applied on the die, for example bits to be masked from the address bus ADDR so as to allow an address mask of the desired kind of redundancy (that is, the considered "per-die" kind of redundancy) to be applied to the die.

[0329] The extended redundancy configuration bus can be fetched from a plurality of extended redundancy registers ERR comprising, for example, a first extended redundancy register ERR a , a second extended redundancy register ERR b ,..., and a last extended redundancy register ERR z .

[0330] Each extended redundancy register ERR of the plurality of extended redundancy registers ERR can:

[0331] ​including bits for addressing a non-volatile memory (e.g. the whole non-volatile memory or a part thereof (e.g. if the kind of redundancy can be applied on a part of the non-volatile memory)) and

[0332] configured to address, via such bits, a bad part of the non-volatile memory to be replaced by a spare part.

[0333] The redundancy logic 100 can be further configured to receive a "per register" redundancy mode bus indicating, for each of a plurality of extended redundancy registers ERR, the kind of redundancy to be applied to the part of the non-volatile memory addressed by the considered extended redundancy register.

[0334] Such a "per register" redundancy mode bus can be fetched from a plurality of redundancy mode registers RMR including, for example, a first redundancy mode register RMR a , a second redundancy mode register RMR b ,..., and a last redundancy mode register RMR z .

[0335] Each of such redundancy mode registers RMR is related to a respective extended redundancy register and is configured to include information about the kind of redundancy to be applied to the part of the non-volatile memory addressed by such respective extended redundancy register.

[0336] Thus, for example, each of such redundancy mode registers RMR can include an address mask for masking, when using the considered "per register" kind of redundancy related to such respective extended redundancy register, bits of the address bus ADDR not considered in the comparison operation between the address bus ADDR and the content of the extended redundancy register ERR.

[0337] Thus, it is noted that there is one redundancy mode register RMR for each extended redundancy register ERR, and thus, the number of registers in the plurality of redundancy mode registers RMR is equal to the number of registers in the plurality of extended redundancy registers ERR.

[0338] Alternatively, as previously described, the number of registers in the plurality of redundancy mode registers RMR can be less than the number of extended redundancy registers ERR, and thus, in this case, one or more of the plurality of redundancy mode registers RMR can be associated with a group of extended redundancy registers ERR, that is, with more than one extended redundancy register ERR.

[0339] The redundancy logic 100 is further configured to drive the plurality of multiplexers 102 (as illustrated inFigure 8 The one or more selection commands are generated based on:

[0340] a plurality of redundancy mode registers RMR or a global redundancy mode register GRMR (depending on the method to be used), and

[0341] a plurality of extended redundancy registers ERR.

[0342] Thus, the redundancy logic 100 can be configured to:

[0343] compare the received address bus ADDR with the bad memory section indicated by the extended redundancy configuration bus, that is, with the addresses of the bad memory section; and

[0344] if the comparison of the addresses indicates that the received address bus ADDR matches at least one address of the bad memory section by the identification of the compared addresses to which a masking operation is applied based on the kind of redundancy to be applied, that is, based on the type of fault affecting the addressed bad memory section, replace the memory section addressed by the address bus ADDR with the spare memory section.

[0345] For example, such a comparison operation can comprise:

[0346] comparing the received address bus ADDR with the bad memory section indicated by the extended redundancy configuration bus in order to obtain one or more comparison buses, for example, one or more comparison addresses obtained by comparing the addresses comprised in the received address bus ADDR with the addresses related to the bad memory section comprised in the extended redundancy registers ERR;

[0347] For example, an indication related to the method to be used, that is, the "per-die" method or the "per-register" method, is received via a binary control signal;

[0348] if the "per-die" method is to be used, for example, if the received binary control signal indicates that the "per-die" method is to be used, the contents of the global redundancy mode register GRMR are decoded in order to obtain information about the kind of redundancy, that is, the kind of redundancy signal, to be applied on the die;

[0349] if the "per-register" method is to be used, for example, if the received binary control signal indicates that the "per-register" method is to be used, the contents of the plurality of redundancy mode registers RMR are decoded in order to obtain information about the kind of redundancy, that is, the kind of redundancy signal, to be applied to the part of the non-volatile memory addressed by the extended redundancy registers ERR; and

[0350] Based on the kind of comparison bus and redundancy signal, it is determined whether the memory segment addressed by the address bus ADDR is associated with one of the bad memory segments to be replaced, for example by: if the "per die" method is considered, then the comparison address is masked with the corresponding address mask included in the global redundancy mode register GRMR, or if the "per register" method is considered, then the comparison address is masked with the corresponding address mask included in the plurality of redundancy mode registers RMR.

[0351] For example, such a replacement operation may include, if the memory segment addressed by the address bus ADDR is associated with one of the bad memory segments to be replaced, replacing one of the bad memory segments associated with the address bus ADDR with a spare memory segment, for example, by generating and applying one or more select commands to a plurality of multiplexers 102, the one or more select commands instructing one of such multiplexers 102 (the one associated with the bad memory segment addressed in the address bus ADDR) to select the redundant sense amplifier 104. red Output.

[0352] Pay attention again, Figure 13 The diagram in the figure has been referenced Figure 8 The parts, elements and / or components described are represented by the same reference numerals used previously in this figure. Therefore, the description of such previously described parts, elements and / or components will not be repeated below in order not to overload this specification.

[0353] Also note that reference has been made to Figure 8 The observations and conclusions described can also be applied to Figure 13 Structure 50, therefore, the description of such previously described observations and conclusions will not be repeated below so as not to overburden this specification.

[0354] Thus, the methods described herein may include:

[0355] reading a mask indicating the relevant fault type based on a received read control signal having, for example, one of a first value and a second value indicating a method to be used (that is, a “per die” method or a “per register” method), wherein the comparing comprises:

[0356] applying the mask stored in the redundant mode register RMR to the compared addresses taking into account a "per register" approach in response to the received control signal having the first value; or

[0357] In response to the received control signal having the second value the mask stored in the memory (global) redundancy mode register GRMR is thus applied to the compared addresses taking into account a “per die” approach.

[0358] Figure 14 The diagram shows an embodiment according to the present specification. Figures 8 to 13 The exemplary implementation 60 of the redundancy logic 100 and the extended redundancy register ERR and the redundancy mode register RMR and / or the global redundancy mode register GRMR included in any of the redundancy architectures 30 , 40 or 50 of .

[0359] Note that the number of bits and the division of registers reported below are described by way of example only, and therefore such details are not to be considered as limiting the scope of protection of the present application.

[0360] For example, the extended redundant register ERR may include:

[0361] The set of address bits, e.g. Figure 14 In the exemplary implementation 60 of , it includes 15 bits, divided into column address bits CA (e.g., 4 bits), row address bits RA (e.g., 8 bits), and sector address bits SA (e.g., 3 bits);

[0362] The main sense amplifier bit SO is set, for example, in Figure 14 The exemplary implementation 60 includes 8 bits for the sense amplifier 104 to be redundant. red addressing the alternate primary sense amplifier 104 (eg, via multiple primary sense amplifiers); and

[0363] The protection bit, for example, stores a high logic level (ie, "1") if the extended redundant register is used, or stores a low logic level (ie, "0") if the extended redundant register is not used.

[0364] For example, the redundant mode register RMR (if considering Figures 11 to 13 ) and the global redundant mode register GRMR (if considered Figures 8 to 10 and Figure 13 ) may include a set of address bits, for example, the set of address bits includes the same number of bits and the same division as the extended redundant register ERR.

[0365] Therefore, the address bit set of the redundant mode register RMR and the global redundant mode register GRMR can be divided into column address bits CM, row address bits RM and sector address bits SM, for example, the number of bits included is equal to the number of bits of the corresponding segment of the address bit set included in the extended redundant register ERR.

[0366] Alternatively, as previously described, a redundancy mode register having fewer bits than the address bus ADDR and the extended redundancy register ERR (that is, a "per-tube" redundancy mode register GRMR or a register of a plurality of redundancy mode registers RMR) can be considered.

[0367] As previously described, in this case, the bits included in the redundancy mode register RMR or GRMR can mask more than one bit of the address bus ADDR.

[0368] Thus, for example, each of the redundancy mode register RMR (if considered Figures 11 to 13 ) and the global redundancy mode register GRMR (if considered Figures 8 to 10 and Figure 13 ) can include a set of address bits, for example, including a number of bits less than the number of bits of the extended redundancy register ERR and a partitioning that can be the same or different from the partitioning of the extended redundancy register ERR.

[0369] Thus, the set of address bits of the redundancy mode register RMR and of the global redundancy mode register GRMR can be partitioned into column address bits CM, row address bits RM, and / or sector address bits SM, for example, including a number of bits equal to or less than the number of bits of the corresponding section of the set of address bits included in the extended redundancy register ERR.

[0370] Note that Figure 14 the exemplary implementation 60 illustrated in , the set of address bits of the redundancy mode register RMR and of the global redundancy mode register GRMR can include a number of bits equal to the number of bits of the extended redundancy register ERR and the same partitioning.

[0371] Figure 14 Note that the number of bits of each section of bits of the redundancy mode register RMR and of the global redundancy mode register GRMR can be changed to obtain the implementation considering different numbers of bits as described above by modifying

[0372] Figure 14 The exemplary implementation 60 illustrated in Figure 14 is considered a global redundancy mode register GRMR, "per-tube", or if such register illustrated in Figure 14 is considered a redundancy mode register RMR, "per-register", to determine whether the currently addressed main memory section is to be replaced by a backup memory section.

[0373] Note that such exemplary implementation 60 can be included, for example, in the redundancy logic 100.

[0374] Further, note that such exemplary implementation 60 can exist more than once and typically in a redundancy logic 100, e.g. once per extended redundancy register ERR.

[0375] Note that such exemplary implementation 60 is described below only by way of example, and therefore such details are not to be considered limiting the scope of protection of the present application.

[0376] Figure 14 An XOR gate XNOR<14:0> is illustrated, which is configured to receive at its input terminals an address bus ADDR (e.g. the address bus comprises a number of bits equal to the number of bits of the set of address bits comprised in the extended redundancy register ERR and the same partitioning ADDR<14:0>), and an extended redundancy configuration bus A<14:0> (which is indicative of the set of address bits comprised in the considered extended redundancy register ERR).

[0377] The XOR gate XNOR<14:0> is configured to compare the received buses bit by bit by applying an XOR operation, and to output a comparison bus COMP<14:0> comprising bits set to a high logic level in case of equality of the compared bits and bits set to a low logic level in case of difference of the compared bits.

[0378] Therefore, the method described herein can comprise, in the comparison operation:

[0379] checking whether the received address ADDR and a faulty memory address A, e.g. stored in the extended redundancy register ERR, of the set of faulty memory sub-section addresses are equal bit by bit, e.g. via an XOR gate, and

[0380] obtaining a comparison address, e.g. comprised in the comparison bus COMP, comprising bits set to one of a high logic level and a low logic level (e.g. the high logic level corresponding to equal bits) and bits set to the other logic level (e.g. the low logic level corresponding to different bits).

[0381] receiving the comparison bus COMP<14:0> at one terminal of an OR gate OR<14:0>, such OR gate OR<14:0> being further configured to receive at the other terminal a redundancy mode bus M<14:0>:

[0382] if Figure 14 The register illustrated in the middle can be considered a global redundancy mode register GRMR, then M<14:0> can be a "per-die" redundancy mode bus indicative of the kind of redundancy that can be applied on the die; or

[0383] ifFigure 14 Such a register, whose value is illustrated in the figure, is considered to be a redundancy mode register RMR, then a "per register" redundancy mode bus, which indicates the kind of redundancy that can be imposed on the memory segment addressed by such a corresponding extended redundancy register ERR, can be applied on the memory segment addressed by such a corresponding extended redundancy register.

[0384] Such a redundancy mode bus M<14:0> can be an address mask, comprising bits set to low logic level corresponding to bits to be considered, that is to say, relevant bits, and bits set to high logic level corresponding to bits not to be considered, that is to say, to be masked.

[0385] For example, if a "per bit" redundancy is considered, all the single bits of the set of address bits are relevant, that is to say, to be considered.

[0386] Thus, the redundancy mode bus M<14:0> can be an address mask comprising bits set to low logic level.

[0387] In this case, in the exemplary implementation 60 of Figure 14 In this case, in the exemplary implementation 60 of

[0388] For example, if a "per column" redundancy is considered, the bits addressing the columns and the sectors are relevant, that is to say, the bits to be considered are the column address bits CA and the sector address bits SA.

[0389] Thus, the redundancy mode bus M<14:0> can be an address mask comprising bits set to low logic level corresponding to the column address bits CA and the sector address bits SA, and bits set to high logic level corresponding to the row address bits RA.

[0390] In this case, in the exemplary implementation 60 of Figure 14 In this case, in the exemplary implementation 60 of

[0391] For example, if a "few columns" redundancy is considered, the bits addressing the columns and the sectors are relevant, that is to say, the bits to be considered are the column address bits CA and the sector address bits SA, except the lower significant bits of the column address.

[0392] Thus, the redundancy mode bus M<14:0> can be an address mask comprising bits set to low logic level corresponding to the column address bits CA and the sector address bits SA, except the lower significant bits, and bits set to high logic level corresponding to the row address bits RA and the lower significant bits of the column address bits CA. Thus, the redundancy mode bus M<14:0> can be an address mask comprising bits set to low logic level corresponding to the column address bits CA and the sector address bits SA, except the lower significant bits, and bits set to high logic level corresponding to the row address bits RA and the lower significant bits of the column address bits CA.

[0393] In this case, in the exemplary implementation 60 of the redundancy mode bus M<14:0> can be equal to 0x0FF1, masking the lower significant bits of the row address bits RA and of the column address bits CA, considering the hexadecimal notation. Figure 14

[0394] For example, if considering the "by array" redundancy, the bits relevant for addressing the sector are the ones to be considered, that is, the bits to be considered are the sector address bits SA.

[0395] Therefore, the redundancy mode bus M<14:0> can be an address mask, comprising bits set to low logic level corresponding to the sector address bits SA, and bits set to high logic level corresponding to the column address bits CA and to the row address bits RA.

[0396] In this case, in the exemplary implementation 60 of the redundancy mode bus M<14:0> can be equal to 0x0FF1, masking the lower significant bits of the row address bits RA and of the column address bits CA, considering the hexadecimal notation. Figure 14

[0397] Note that other types of redundancy can be considered, in addition to the ones described herein, simply by setting the desired bits to high logic level and setting the relevant bits to be considered to low logic level.

[0398] The OR gate OR<14:0> is configured to apply a bitwise OR operation to the comparison bus COMP<14:0> and to the redundancy mode bus M<14:0>, and to output the masked comparison bus COMP_MASK<14:0>, comprising bits set to high logic level (where the corresponding bits of the address bus ADDR and of the extended redundancy configuration bus A<14:0> are equal or masked), and bits set to low logic level (where the corresponding bits of the address bus ADDR and of the extended redundancy configuration bus A<14:0> are different and not masked).

[0399] The masked comparison bus COMP_MASK<14:0> is provided to the AND gate AND 0-14 which is configured to apply an AND operation to the bits of the received masked comparison bus COMP_MASK<14:0>, and to set the output signal Red_Act to high logic level if all the bits comprised in the masked comparison bus COMP_MASK<14:0> are set to high logic level.

[0400] The output signal Red_Act is a signal indicating whether the main memory section addressed by the address bus ADDR is to be replaced by the backup memory section.

[0401] ​​If the output signal Red_Act is set to a high logic level, the redundant sense amplifier 104 is enabled. red and corresponding redundant column selector 106 red One of the main memory banks addressed by the address bus ADDR is replaced by the corresponding spare memory bank.

[0402] Otherwise, if the output signal Red_Act is set to a low logic level, the main memory segment addressed by the address bus ADDR is not replaced by the corresponding spare memory segment, and thus, the redundant sense amplifier 104 red and corresponding redundant column selector 106 red is disabled.

[0403] Note that if the main memory bank addressed by the address bus ADDR is replaced by the corresponding spare memory bank, the redundant sense amplifier 104 will red Information on the address (that is, number) of the replaced master sense amplifier 104 is contained in the master sense amplifier bit SO of the extended redundant register ERR in question.

[0404] In fact, the master sense amplifier bit SO contains a number, for example in binary, which indicates which of the master sense amplifiers 104 is to be replaced by the redundant sense amplifier 104. red replace.

[0405] Thus, the methods described herein may be included in such a comparison operation:

[0406] masking a comparison address, for example, included in a comparison bus COMP, with a corresponding mask indicating a fault type, for example included in a redundant mode bus M, thereby obtaining a masked comparison address, for example included in a masked comparison bus COMP_MASK, wherein the masking operation regards a mask coupled to the fault memory address for obtaining the comparison address to be masked as the corresponding mask to be used;

[0407] Checks whether at least one bit of the masked comparison address COMP_MASK is set to a logic level corresponding to an equal bit, e.g. Figure 14 , is set to a high logic level; and

[0408] If a bit of at least one masked comparison address COMP_MASK is set to a logic level corresponding to an equal bit (e.g., a high logic level), a match between the received address ADDR and the fault memory address A used to obtain such at least one masked comparison address COMP_MASK is indicated by, for example, setting the output signal Red_Act to a high logic level.

[0409] Note that such masking operation can comprise setting the bits of the comparison address COMP to be masked to the logic level corresponding to the equal bits, that is to say, to the high logic level.

[0410] Thus, the method as described herein can comprise in the substitution operation:

[0411] reading a spare memory sub-sector in the spare memory sector AC red,a-i via a sense amplifier (e.g. the redundant sense amplifier 104 red ) configured to perform a read operation in the spare memory sector AC red,a-i , thereby obtaining a read signal (e.g. the redundant sense amplifier output signal SO red ), the spare memory sub-sector being configured to substitute a memory sub-sector of the addressable memory sector AC 1-N,a-i addressed via the address bus ADDR as a candidate for access, wherein the comparison operation is indicative of a match between the received address comprised in the address bus ADDR and the faulty memory address A comprised in the extended redundancy register ERR, for example via the output signal Red_Act being set to the high logic level; and

[0412] selecting the read signal SO red via a multiplexer (e.g. the multiplexer in the plurality of multiplexers 102 1-N ) coupled to the spare memory sub-sector and the memory sub-sector of the addressable memory sector addressed via the address bus ADDR as a candidate for access.

[0413] Note that if the main memory sector (that is to say, the memory sub-sector of the addressable memory sector as a candidate for access) addressed by the address bus ADDR is substituted by the corresponding spare memory sector (that is to say, the spare memory sub-sector), the information related to the address (that is to say, the number) of the main sense amplifier 104 to be substituted by the redundant sense amplifier 104 red is contained in the main sense amplifier bit SO of the considered extended redundancy register ERR.

[0414] Note that if the extended redundancy configuration bus A<14:0> is equal to the address bus ADDR<14:0> (that is to say, matches by identification), all the bits of the comparison bus COMP<14:0> have been set to the high logic level, thus, the masking operation performed by the OR gate OR<14:0> can not be needed. In this case, the comparison bus COMP<14:0> can be directly provided to the AND gate AND 0-14 which sets the output signal Red_Act to the high logic level.

[0415] Thus, the method described herein can comprise: in a comparison operation of an address of a memory sub-section, addressed via the addressing bus ADDR, of the addressable memory section AC 1-N,a-i of the NVM device, as access candidate, with a set of faulty memory sub-section addresses, declaring a match by the identity of the compared address, for example in response to the compared address exhibiting a bit-wise equality of bits not masked by a mask (in the example of Figure 14 all bits of the comparison bus COMP being set to a high logic level), via an output signal Red_Act.

[0416] It is further noted that the method described herein can comprise: in a comparison operation of an address of a memory sub-section, addressed via the addressing bus ADDR, of the addressable memory section AC 1-N,a-i of the NVM device, as access candidate, with a set of faulty memory sub-section addresses, declaring a match by the identity of the compared address, for example in response to the compared address exhibiting a bit-wise equality of bits not masked by a mask (in the example of Figure 14 all bits of the comparison bus COMP being set to a high logic level), via an output signal Red_Act. Figure 14 in response to bits of the comparison bus COMP differing from bits masked using a mask M (included in the redundancy mode register RMR or in a global redundancy mode register GRMR) (in the example of Figure 14 all bits of the comparison bus - i.e. both masked bits and unmasked bits - being set to a high logic level in the example of thus causing the output signal Red_Act to be set by an AND gate AND 0-14 with the identity of the compared address being applied with address masking by a mask (e.g. a bit mask M included in the redundancy mode register or in a global redundancy mode register GRMR) indicating the relevant fault type).

[0417] The technical solution as described herein facilitates obtaining a method of operating a non-volatile memory NVM device in response to a fault (with a relevant fault type) in at least one memory sub-section of an addressable memory section of the NVM device.

[0418] The NVM device further comprises a spare memory section comprising spare memory sub-sections configured to replace respective faulty memory sub-sections in the addressable memory section of the NVM device.

[0419] The method according to the technical solution described herein comprises:

[0420] comparing an address of a memory sub-section of the addressable memory section of the NVM device as a candidate for access with a set of faulty memory sub-section addresses, the set comprising at least one address of a faulty memory sub-section coupled with a mask indicating a related fault type; and

[0421] replacing the memory sub-section of the addressable memory section as a candidate for access with a spare memory sub-section of the spare memory section, wherein such address comparison indicates a match by an identification of the compared address or a match by an identification of the compared address imposed with an address mask by utilizing a mask indicating a related fault type.

[0422] It is noted that the methods described herein can be applied to a non-volatile memory, NVM, device, such as a phase change memory, PCM, device.

[0423] It is noted that the methods described herein can also be applied to other types of non-volatile memory, NVM, devices.

[0424] It is noted that the technical solutions as described herein can also refer to a non-volatile memory, NVM, device, e.g. a phase change memory device, NVM device, comprising an addressable memory section and a spare memory section comprising spare memory sub-sections configured to replace respective faulty memory sub-sections in the addressable memory section of the NVM device, wherein the NVM device is configured to implement the methods according to the present description.

[0425] It is noted that the technical solutions as described herein can also refer to a computer program product loadable in a control unit of a non-volatile memory, NVM, device, e.g. a phase change memory device, the NVM device comprising an addressable memory section and a spare memory section comprising spare memory sub-sections configured to replace respective faulty memory sub-sections in the addressable memory section of the NVM device, wherein the computer program product comprises software code configured to cause the NVM device to implement the methods according to the present description in response to the computer program product running in the control unit of the NVM device.

[0426] Thus, the technical solutions as described herein contribute to preventing loss of malfunctioning or faulty units in a non-volatile memory, NVM, by replacing such malfunctioning or faulty units with spare units, thus increasing the durability of such memories.

[0427] The details and embodiments can vary even significantly with respect to what is described by way of example only, without departing from the gist, without impairing the basic principles, without departing from the scope of the embodiments.

[0428] The limits of protection are determined by the attached claims.

Claims

1. A method for operating a non-volatile memory (NVM) device comprising an addressable memory segment and a spare memory segment, the method comprising: responsive to a failure in at least one memory sub-segment of the addressable memory bank of the NVM device, comparing an address of the memory sub-segment of the addressable memory bank that is a candidate for access with a set of failed memory sub-segment addresses, the set comprising at least one address of the failed memory sub-segment coupled with a mask, the mask indicating an associated failure type; and The memory subsegment of the addressable memory segment as an access candidate is replaced by a spare memory subsegment in the spare memory segment, wherein comparing the addresses indicates a match by identifications of the compared addresses or by identifications of the compared addresses masked with the mask, the mask being indicative of the associated fault type. 2 . The method of claim 1 , further comprising storing the failing memory addresses in the set of failing memory sub-segment addresses in corresponding redundant registers in a plurality of redundant registers.

3. The method according to claim 2, further comprising: coupling a corresponding redundant mode register to the redundant register of the plurality of redundant registers; and A corresponding mask indicating the relevant fault type is stored in the corresponding redundant mode register, and the corresponding fault memory address and the mask indicating the relevant fault type coupled thereto are respectively stored in a redundant register and the corresponding redundant mode register coupled thereto.

4. The method according to claim 3, wherein: A set of redundant registers in the plurality of redundant registers are coupled to the same respective redundant mode register; and The respective fault memory address stored in the redundant register in the set of redundant registers is coupled to the mask indicative of the associated fault type stored in the same respective redundant mode register.

5. The method according to claim 3, wherein The corresponding masks indicating the relevant fault types include at least one first mask indicating a first relevant fault type and at least one second mask indicating a second relevant fault type, the first mask and the second mask being stored in a first redundant mode register and a second redundant mode register, the first mask and the second mask being the same or different from each other. 6 . The method of claim 2 , further comprising storing the mask indicative of the associated failure type in a memory redundancy mode register, the failure type being a failure type of the addressable memory segment.

7. The method according to claim 6, further comprising: coupling a corresponding redundant mode register to the redundant register of the plurality of redundant registers; storing a corresponding mask indicating the relevant fault type in the corresponding redundant mode register, the corresponding fault memory address and the mask indicating the relevant fault type coupled thereto being stored in a redundant register and the corresponding redundant mode register coupled thereto; and Reading the mask indicating the relevant fault type based on a received read control signal having one of a first value and a second value, the comparing comprising: in response to the received read control signal having the first value, applying the mask stored in the redundant mode register to the compared address; or In response to the received read control signal having the second value, applying the mask stored in the memory redundancy mode register to the compared addresses.

8. The method according to claim 1, wherein Comparing the address of the memory sub-segment of the addressable memory bank that is a candidate for access with the set of failing memory sub-segment addresses includes declaring a match by identity of the compared addresses in response to the compared addresses exhibiting bit-wise equality.

9. The method according to claim 1, wherein Comparing the address of the memory sub-segment of the addressable memory segment that is a candidate for access with the set of faulty memory sub-segment addresses includes: in response to the compared addresses showing bit-by-bit equality of bits not masked by the mask, declaring a match by identifying the compared addresses with address mask applied using the mask, the mask indicating the relevant fault type.

10. The method according to claim 1, wherein The NVM device is a phase change memory (PCM) device.

11. A non-volatile memory (NVM) device comprising: addressable memory segments; and a spare memory bank comprising spare memory sub-banks configured to replace corresponding failed memory sub-banks in the addressable memory bank of the NVM device; Wherein, the NVM device is configured as: comparing an address of the memory subsegment of the addressable memory segment that is a candidate for access with a set of addresses of faulty memory subsegments, the set comprising at least one address of a faulty memory subsegment coupled with a mask, the mask indicating a relevant fault type; and The memory subsegment of the addressable memory segment as an access candidate is replaced by a spare memory subsegment in the spare memory segment, wherein comparing the addresses indicates a match by identifications of the compared addresses or by identifications of the compared addresses masked with the mask, the mask being indicative of the associated fault type.

12. The NVM device according to claim 11, wherein: The NVM device is further configured to store the failing memory addresses in the set of failing memory sub-segment addresses in corresponding redundant registers of a plurality of redundant registers.

13. The NVM device according to claim 12, wherein: The NVM device is further configured to: coupling a corresponding redundant mode register to the redundant register of the plurality of redundant registers; and A corresponding mask indicating a relevant fault type is stored in the corresponding redundant mode register, wherein a corresponding fault memory address and the mask indicating the relevant fault type coupled thereto are stored in a redundant register and in the corresponding redundant mode register coupled thereto, respectively.

14. The NVM device of claim 13, wherein: A set of redundant registers in the plurality of redundant registers is coupled to a same corresponding redundant mode register; and The respective fault memory address stored in the redundant register in the set of redundant registers is coupled to the mask indicative of the associated fault type stored in the same respective redundant mode register.

15. The NVM device according to claim 13, wherein: The corresponding masks indicating the relevant fault types include at least one first mask indicating a first relevant fault type and at least one second mask indicating a second relevant fault type, the first mask and the second mask being stored in a first redundant mode register and a second redundant mode register, the first mask and the second mask being the same or different from each other.

16. The NVM device according to claim 11, wherein: The NVM device is configured to compare the address of the memory sub-segment of the addressable memory segment that is a candidate for access with the set of failed memory sub-segment addresses, including the NVM device being configured to declare a match by identification of the compared addresses in response to the compared addresses exhibiting bit-wise equality.

17. The NVM device according to claim 11, wherein: The NVM device is configured to compare the address of the memory sub-segment of the addressable memory segment that is a candidate for access with the set of faulty memory sub-segment addresses, including: the NVM device is configured to declare a match by identifying the compared addresses masked with the mask in response to the compared addresses exhibiting bit-by-bit equality of bits not masked by the mask, the mask indicating the associated fault type.

18. The NVM device according to claim 11, wherein: The NVM device is a phase change memory (PCM) device.

19. A non-transitory computer program product loadable in a control unit of a non-volatile memory (NVM) device, the NVM device comprising an addressable memory segment and a spare memory segment, wherein: The computer program product includes software code configured to, in response to the computer program product being executed in the control unit of the NVM device, cause the NVM device to implement: responsive to a failure in at least one memory sub-segment of the addressable memory bank of the NVM device, comparing an address of the memory sub-segment of the addressable memory bank that is a candidate for access with a set of failed memory sub-segment addresses, the set comprising at least one address of the failed memory sub-segment coupled with a mask, the mask indicating an associated failure type; and The memory subsegment of the addressable memory segment as an access candidate is replaced by a spare memory subsegment in the spare memory segment, wherein comparing the addresses indicates a match by identifications of the compared addresses or by identifications of the compared addresses masked with the mask, the mask being indicative of the associated fault type.

20. The computer program product of claim 19, wherein: The NVM device is a phase change memory (PCM) device.

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