Chip packaging method and device, electronic equipment and computer readable storage medium

Abstract

The embodiment of the invention discloses a chip packaging method and device, electronic equipment and a computer readable storage medium. The method comprises the steps that loop parasitic parameters of a multi-chip parallel power device and key device parameters of chips are acquired; respectively constructing a first mapping relation and a second mapping relation between the loop parasitic parameter and the to-be-optimized physical characteristic parameter and between the key device parameter and the to-be-optimized physical characteristic parameter; according to the first mapping relation, the chip packaging positions on the multi-chip parallel power device are numbered in an ascending order according to the change of the physical characteristic parameters to be optimized, and according to the second mapping relation, the chips are numbered in a descending order according to the change of the physical characteristic parameters to be optimized; and traversing the serial numbers of the chip packaging positions and the serial numbers of the chips, and packaging the chip with the minimum serial number to the chip packaging position with the maximum serial number. By adopting the embodiment of the invention, the electric thermal stress difference in the multi-chip parallel power device caused by loop parasitic parameter difference or chip parameter difference can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor chip packaging, and in particular to a chip packaging method and device, an electronic device, and a computer readable storage medium. BACKGROUND

[0002] With the rapid development of the power electronics industry, the demand for high-current capacity power conversion systems has surged. To meet this requirement, more chips are needed in parallel in power modules. However, due to differences in the loop parasitic parameters between the parallel chips in the module and the key device parameters of the chips, parallel connection of multiple chips often leads to uneven current and uneven heat distribution, and even irreversible damage to the module. Therefore, how to reduce the differences in the loop parasitic parameters of the parallel power devices and the key device parameters of the chips to balance the electrical and thermal stress distribution within the parallel power devices is a technical problem that needs to be solved urgently. SUMMARY

[0003] The embodiments of the present application provide a chip packaging method and device, an electronic device, and a computer readable storage medium, which are beneficial to reduce the differences in the loop parasitic parameters of the parallel power devices and the key device parameters of the chips to balance the electrical and thermal stress distribution within the parallel power devices.

[0004] The first aspect of the embodiments of the present application provides a chip packaging method, which comprises: obtaining the loop parasitic parameters of a parallel power device and the key device parameters of a chip; respectively constructing a first mapping relationship between the loop parasitic parameters and a to-be-optimized physical characteristic parameter and a second mapping relationship between the key device parameters and the to-be-optimized physical characteristic parameter; sequentially numbering the chip packaging positions on the parallel power device in ascending order according to the change of the to-be-optimized physical characteristic parameter according to the first mapping relationship, and sequentially numbering the chips in descending order according to the change of the to-be-optimized physical characteristic parameter according to the second mapping relationship; traversing the numbers of the chip packaging positions and the numbers of the chips, and packaging the chip with the smallest serial number to the chip packaging position with the largest serial number.

[0005] Optionally, before the respective construction of the first mapping relationship between the loop parasitic parameters and the to-be-optimized physical characteristic parameter and the second mapping relationship between the key device parameters and the to-be-optimized physical characteristic parameter, the method further comprises: constructing a device behavior simulation model of the multi-chip parallel power device to quantitatively characterize electrical characteristics of the multi-chip parallel power device, to obtain device electrical characteristics, and constructing a finite element simulation model of the multi-chip parallel power device to quantitatively characterize thermal characteristics of the multi-chip parallel power device, to obtain device thermal characteristics; obtaining the physical characteristic parameter to be optimized according to the device electrical characteristics and the device thermal characteristics.

[0006] Optionally, before the obtaining of the loop parasitic parameters of the multi-chip parallel power device and the key device parameters of the chips, the method comprises: obtaining chips to be packaged in the multi-chip parallel power device; obtaining the key device parameters of the chips.

[0007] Optionally, before the obtaining of the loop parasitic parameters of the multi-chip parallel power device and the key device parameters of the chips, the method comprises: obtaining a multi-chip parallel power device; determining an internal circuit structure of the multi-chip parallel power device; determining loop parasitic parameters of the internal circuit structure.

[0008] Optionally, the loop parasitic parameters comprise at least one of the following: drain loop inductance, source loop inductance, and gate loop inductance.

[0009] Optionally, the key device parameters comprise at least one of the following: threshold voltage, on-resistance, and transconductance.

[0010] Optionally, the physical characteristic parameter to be optimized comprises at least one of the following: transient current, junction temperature, interface thermal resistance, thermal coupling coefficient, and thermal expansion coefficient.

[0011] The second aspect of the embodiments of the present application provides a chip packaging device, which comprises: a parameter obtaining unit configured to obtain loop parasitic parameters of a multi-chip parallel power device and key device parameters of chips; a mapping relationship constructing unit configured to respectively construct a first mapping relationship between the loop parasitic parameters and a physical characteristic parameter to be optimized and a second mapping relationship between the key device parameters and the physical characteristic parameter to be optimized; a numbering unit configured to number chip packaging positions on the multi-chip parallel power device in ascending order according to changes in the physical characteristic parameter to be optimized according to the first mapping relationship, and number the chips in descending order according to changes in the physical characteristic parameter to be optimized according to the second mapping relationship; The encapsulation unit is configured to traverse the numbers of the chip packaging positions and the numbers of the chips, and encapsulate the chip with the smallest serial number to the chip packaging position with the largest serial number.

[0012] The third aspect of the embodiments of the present application provides an electronic device, including: a processor and a memory; The processor and the memory are connected, wherein the memory is configured to store a computer program, and the processor is configured to invoke the computer program to execute the method in the first aspect of the embodiments of the present application.

[0013] The fourth aspect of the embodiments of the present application provides a computer readable storage medium, which stores a computer program, and the computer program includes program instructions, which, when executed by a processor, execute the method in the first aspect of the embodiments of the present application.

[0014] The chip packaging method provided by the present application comprises the following steps: obtaining loop parasitic parameters of a multi-chip parallel power device and key device parameters of chips; constructing a first mapping relationship between the loop parasitic parameters and to-be-optimized physical characteristic parameters and a second mapping relationship between the key device parameters and the to-be-optimized physical characteristic parameters; numbering chip packaging positions on the multi-chip parallel power device in ascending order according to changes in the to-be-optimized physical characteristic parameters according to the first mapping relationship, and numbering the chips in descending order according to changes in the to-be-optimized physical characteristic parameters according to the second mapping relationship; and traversing the numbers of the chip packaging positions and the numbers of the chips, and encapsulating the chip with the smallest serial number to the chip packaging position with the largest serial number.

[0015] It can be seen that, according to the first mapping relationship, the chip packaging positions on the multi-chip parallel power device are numbered in ascending order according to changes in the to-be-optimized physical characteristic parameters, so that when the key device parameters of the chips are consistent, the numbers of the chip packaging positions are in ascending order with respect to the to-be-optimized physical characteristic parameters; according to the second mapping relationship, the chips are numbered in descending order according to changes in the to-be-optimized physical characteristic parameters, so that when the loop parasitic parameters of the multi-chip parallel power device are consistent, the numbers of the chips are in descending order with respect to the to-be-optimized physical characteristic parameters; and the chip with the smallest serial number is encapsulated to the chip packaging position with the largest serial number, so that the difference in the loop parasitic parameters in the multi-chip parallel power device and the difference in the key device parameters between the parallel chips are complementary, thereby minimizing the electrical and thermal stress difference of the multi-chip parallel device without affecting the utilization rate of the chips; further, when the multi-chips are parallelly encapsulated, there is no need to perform screening or grouping, and only sequential patch encapsulation is needed, so that the dispersion and randomness of the comprehensive device parameters of the parallel chips can be fully constrained, thereby reducing the electrical and thermal imbalance between the parallel chips due to the difference in the chip parameters, and having great significance for improving the long-term operation reliability of the multi-chip parallel power device.

[0016] Based on the same inventive concept, the present application also provides a chip packaging device, an electronic device and a computer readable storage medium. The specific beneficial effect derivation process is referred to the above method embodiment, which is not described here. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] Figure 1 Fig. 1 shows a schematic diagram of a chip packaging application running environment provided by an embodiment of the present application; Figure 2 Fig. 2 shows a flowchart of a chip packaging method provided by an embodiment of the present application; Figure 3 Fig. 3 shows a structural schematic diagram of a chip packaging device provided by an embodiment of the present application; Figure 4 Fig. 4 shows a structural schematic diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0019] The technical solutions of the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0020] Reference should be made to Figure 1 Fig. 1 shows a schematic diagram of a chip packaging application running environment provided by an embodiment of the present application. The application running environment can include a terminal 10 and a server 20.

[0021] The terminal 10 includes but is not limited to a mobile phone, a computer, a smart voice interactive device, a smart home appliance, a vehicle-mounted terminal, a game console, an electronic book reader, a multimedia playback device, a wearable device, etc. The terminal 10 can install a client of an application.

[0022] In the embodiments of the present application, the application program can be any application program capable of providing a chip packaging service. Typically, the application program is an industrial application program. Of course, in addition to industrial application programs, services that depend on chip packaging can also be provided in other types of application programs. For example, scientific research application programs, browser application programs, virtual reality (VR) application programs, augmented reality (AR) application programs, and the like, are not limited in the embodiments of the present application. The embodiments of the present application are not limited in this regard. Optionally, the terminal 10 runs a client of the application program.

[0023] The server 20 is configured to provide a background service for the client of the application program in the terminal 10. For example, the server 20 can be a background server of the application program. The server 20 can be a standalone physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and basic cloud computing services such as big data and artificial intelligence platforms. Optionally, the server 20 simultaneously provides background services for application programs in multiple terminals 10.

[0024] Optionally, the terminal 10 and the server 20 can communicate with each other through the network 30. The terminal 10 and the server 20 can be directly or indirectly connected through wired or wireless communication, which is not limited in the present application.

[0025] Please refer to Figure 2 which shows a flowchart of a chip packaging method provided by an embodiment of the present application. The method can be applied in a computer device, and the computer device refers to an electronic device with data computing and processing capability, such as the terminal 10 or the server 20 in the application program running environment shown in Figure 1 The method can include the following steps: Step 201: Obtain the loop parasitic parameters of the multi-chip parallel power device and the key device parameters of the chip. The multi-chip parallel power device is a power electronic device that integrates multiple semiconductor chips (such as IGBT, SiC MOSFET) in parallel in the package to achieve higher current capability. The core design goal is to break through the current limit of a single chip to meet the demand of high-power applications, and to ensure current sharing and thermal balance between chips through optimized design.

[0026] The loop parasitic parameters refer to distributed resistance, inductance and capacitance parameters unintentionally generated by conductor layout, material characteristics and electromagnetic coupling effects in the actual physical structure of the power electronic device. For example, the loop parasitic parameters include at least one of the following: drain loop inductance, source loop inductance, and gate loop inductance.

[0027] The drain loop inductance is a closed-loop inductance formed from the chip drain terminal→ load→ power bus→ return path, the source loop inductance is a closed-loop inductance formed from the chip source terminal→ common ground→ drive return path, and the gate loop inductance is a closed-loop inductance formed from the drive chip output→ gate resistor→ gate terminal→ source return.

[0028] The key device parameters are core physical quantities that determine the performance, reliability and system compatibility of power semiconductors (such as MOSFET, IGBT, SiC / GaN devices). For example, the key device parameters include at least one of the following: threshold voltage, on-resistance, and transconductance.

[0029] The threshold voltage is the minimum gate-source voltage required to form a conductive channel between the source and drain of the MOSFET; when the MOSFET is fully on (usually refers to working in the linear region / triode region), the equivalent resistance between the drain (D) and source (S) is the on-resistance; the ratio of the change in drain current to the change in gate-source voltage that causes this change is the transconductance.

[0030] Before step 201 is performed, i.e., before the loop parasitic parameters of the multi-chip parallel power device and the key device parameters of the chip are obtained, the method includes: Obtaining a chip to be packaged in a multi-chip parallel power device; Obtaining the key device parameters of the chip.

[0031] Specifically, the key device parameters of the chip can be obtained through the official documents of the chip, can be obtained through the model files provided by the chip manufacturer for circuit simulation, or can be obtained through experimental measurement, and are not limited here.

[0032] Before step 201 is performed, i.e., before the loop parasitic parameters of the multi-chip parallel power device and the key device parameters of the chip are obtained, the method includes: Obtaining a multi-chip parallel power device; Determining the internal circuit structure of the multi-chip parallel power device; Determining the loop parasitic parameters of the internal circuit structure.

[0033] The internal circuit structure of the multi-chip parallel power device can be obtained from a corresponding official data manual, can be obtained through non-destructive physical detection such as X-ray imaging and ultrasonic scanning, or can be obtained through electrical characteristic testing, and is not specifically limited here.

[0034] Step 202: respectively constructing a first mapping relationship between the loop parasitic parameters and the physical characteristic parameters to be optimized and a second mapping relationship between the key device parameters and the physical characteristic parameters to be optimized.

[0035] For example, the physical characteristic parameters to be optimized include at least one of the following: transient current, junction temperature, interface thermal resistance, thermal coupling coefficient, and thermal expansion coefficient. The transient current experienced by the device in the switching process or fault state (duration of μs~ms level) is the transient current; the actual working temperature of the active area of the semiconductor device chip is the junction temperature; the resistance encountered by heat when crossing the contact surface of two materials is the interface thermal resistance; the quantitative index of thermal interference between adjacent chips is the thermal coupling coefficient; and the relative length change rate of the material when the temperature changes by 1℃ is the thermal expansion coefficient.

[0036] Before step 202, i.e., before the first mapping relationship between the loop parasitic parameters and the physical characteristic parameters to be optimized and the second mapping relationship between the key device parameters and the physical characteristic parameters to be optimized are constructed, the method further comprises: constructing a device behavior simulation model of the multi-chip parallel power device to quantitatively characterize the electrical characteristics of the multi-chip parallel power device, to obtain device electrical characteristics; and constructing a finite element simulation model of the multi-chip parallel power device to quantitatively characterize the thermal characteristics of the multi-chip parallel power device, to obtain device thermal characteristics; obtaining the physical characteristic parameters to be optimized according to the device electrical characteristics and the device thermal characteristics.

[0037] The device behavior simulation model (Behavioral Simulation Model) is a simulation tool that describes the characteristics of the external ports of the device through mathematical equations or equivalent circuits. The finite element simulation model (Finite Element Simulation Model) is a physical field analysis tool based on numerical calculation methods, which discretizes complex geometric structures into a finite number of simple units and solves control equations (such as heat conduction, mechanical equilibrium, and electromagnetic field equations) in each unit to quantitatively predict the behavior of real physical systems.

[0038] Step 203: according to the first mapping relationship, ascendingly numbering the chip packaging positions on the multi-chip parallel power device according to the change of the physical characteristic parameter to be optimized, and according to the second mapping relationship, descendingly numbering the chips according to the change of the physical characteristic parameter to be optimized.

[0039] Step 204: traversing the numbering of the chip packaging positions and the numbering of the chips, packaging the chip with the smallest serial number to the chip packaging position with the largest serial number.

[0040] It can be seen that, according to the first mapping relationship, ascendingly numbering the chip packaging positions on the multi-chip parallel power device according to the change of the physical characteristic parameter to be optimized, the numbering of the chip packaging positions is in ascending order with respect to the physical characteristic parameter to be optimized when the key device parameters of the chips are consistent; according to the second mapping relationship, descendingly numbering the chips according to the change of the physical characteristic parameter to be optimized, the numbering of the chips is in descending order with respect to the physical characteristic parameter to be optimized when the loop parasitic parameters of the multi-chip parallel power device are consistent; packaging the chip with the smallest serial number to the chip packaging position with the largest serial number can make the difference of the loop parasitic parameters in the multi-chip parallel power device complementary to the difference of the key device parameters between the parallel chips, so as to minimize the difference of the electrical and thermal stresses of the multi-chip parallel device without affecting the chip utilization rate; further, when the multi-chips are parallel packaged, there is no need to screen or group, but only to sequentially perform the patch packaging, so as to sufficiently constrain the dispersion and randomness of the comprehensive device parameters of the parallel chips, thereby reducing the electrical and thermal imbalance between the parallel chips due to the difference of the chip parameters, which is of great significance to improve the long-term operation reliability of the multi-chip parallel power device.

[0041] Figure 3 A structure diagram of a chip packaging device provided by an embodiment of the present application is shown. The device comprises: a parameter acquisition unit 301, configured to acquire the loop parasitic parameters of a multi-chip parallel power device and the key device parameters of a chip; a mapping relationship construction unit 302, configured to respectively construct a first mapping relationship between the loop parasitic parameters and a physical characteristic parameter to be optimized and a second mapping relationship between the key device parameters and the physical characteristic parameter to be optimized; a numbering unit 303, configured to according to the first mapping relationship, ascendingly number the chip packaging positions on the multi-chip parallel power device according to the change of the physical characteristic parameter to be optimized, and according to the second mapping relationship, descendingly number the chips according to the change of the physical characteristic parameter to be optimized; The encapsulation unit 304 encapsulates the chip with the smallest serial number in the chip encapsulation position with the largest serial number by traversing the serial numbers of the chip encapsulation positions and the serial numbers of the chips.

[0042] Figure 4 A structural diagram of a computer device provided by an embodiment of the present application is shown, which includes a memory and a processor. The memory stores a computer program, and the processor implements the function of the computer system of the chip encapsulation method in any of the above embodiments when executing the computer program.

[0043] The embodiment of the present application further provides a computer readable storage medium, which stores a computer program. The computer program is executed by a computer to make the computer execute the function of the computer system of the chip encapsulation method in any of the above embodiments.

[0044] The embodiment of the present application further provides a computer program product containing instructions. The instructions are executed by a computer to make the computer execute the function of the computer system of the chip encapsulation method in any of the above embodiments.

[0045] It can be understood that the specific examples in the present application are only to help those skilled in the art better understand the embodiments of the present application, and not to limit the scope of the present application.

[0046] It can be understood that in various embodiments of the present application, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0047] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0048] Unless otherwise specified, all technical and scientific terms used in the embodiments of the present application have the same meanings as those commonly understood by those skilled in the art of the present application. The terms used in the present application are only for the purpose of describing the specific embodiments of the present application, and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0049] It can be understood that the processor of the embodiments of the present application can be an integrated circuit chip with processing capability. In the implementation process, each step of the method embodiments described above can be completed by integrated logic circuits in hardware or instructions in software form in the processor. The processor described above can be a general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. Each method, step and logic block diagram disclosed in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read only memory, a programmable read only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method.

[0050] It can be understood that the memory in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM). It should be noted that the memory of the system and method described herein is intended to include but not limited to these and any other suitable type of memory.

[0051] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0052] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0053] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the above-described device embodiments are merely schematic, and the division of units is merely a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0054] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments.

[0055] In addition, each functional unit in the embodiments of the present application can be integrated in a processing unit, or each unit can exist physically as a separate unit, or two or more units can be integrated in one unit.

[0056] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the embodiments of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and various media that can store program codes.

[0057] The above is merely specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip packaging method, characterized in that: The method comprises: Obtain loop parasitic parameters of multi-chip parallel power devices and key device parameters of the chips; respectively constructing a first mapping relationship between the loop parasitic parameters and the physical characteristic parameters to be optimized and a second mapping relationship between the key component parameters and the physical characteristic parameters to be optimized; Numbering chip package positions on the multi-chip parallel power device in ascending order according to the first mapping relationship and changes in the physical characteristic parameters to be optimized, and numbering the chips in descending order according to the second mapping relationship and changes in the physical characteristic parameters to be optimized; Traverse the numbers of the chip packaging positions and the numbers of the chips, and package the chip with the smallest serial number to the chip packaging position with the largest serial number.

2. The method according to claim 1, characterized in that Before respectively constructing the first mapping relationship between the loop parasitic parameters and the physical characteristic parameters to be optimized and the second mapping relationship between the key component parameters and the physical characteristic parameters to be optimized, the method further includes: Constructing a device behavior simulation model of the multi-chip parallel power device to quantitatively characterize the electrical characteristics of the multi-chip parallel power device and obtain the device electrical characteristics; and constructing a finite element simulation model of the multi-chip parallel power device to quantitatively characterize the thermal characteristics of the multi-chip parallel power device and obtain the device thermal characteristics; The physical characteristic parameters to be optimized are obtained according to the electrical characteristics of the device and the thermal characteristics of the device.

3. The method according to claim 1, characterized in that Before obtaining the loop parasitic parameters of the multi-chip parallel power device and the key device parameters of the chip, the method includes: Obtaining chips to be packaged in a multi-chip parallel power device; Obtain key device parameters of the chip.

4. The method according to claim 1, wherein Before obtaining the loop parasitic parameters of the multi-chip parallel power device and the key device parameters of the chip, the method includes: Obtain multi-chip parallel power devices; Determining the internal circuit structure of the multi-chip parallel power device; Loop parasitic parameters of the internal circuit structure are determined.

5. The method according to any one of claims 1 to 4, characterized in that The loop parasitic parameters include at least one of the following: drain loop inductance, source loop inductance, and gate loop inductance.

6. The method according to any one of claims 1 to 4, characterized in that The key device parameters include at least one of the following: threshold voltage, on-resistance, and transconductance.

7. The method according to any one of claims 1 to 4, characterized in that The physical characteristic parameters to be optimized include at least one of the following: transient current, junction temperature, interface thermal resistance, thermal coupling coefficient, and thermal expansion coefficient.

8. A chip packaging device, characterized in that: The device comprises: A parameter acquisition unit, used to obtain loop parasitic parameters of multi-chip parallel power devices and key device parameters of the chips; A mapping relationship construction unit, configured to respectively construct a first mapping relationship between the loop parasitic parameters and the physical characteristic parameters to be optimized and a second mapping relationship between the key device parameters and the physical characteristic parameters to be optimized; a numbering unit, configured to number chip package positions on the multi-chip parallel power device in ascending order according to the change of the physical characteristic parameter to be optimized according to the first mapping relationship, and to number the chips in descending order according to the change of the physical characteristic parameter to be optimized according to the second mapping relationship; The packaging unit is used to traverse the numbers of the chip packaging positions and the numbers of the chips, and package the chip with the smallest serial number to the chip packaging position with the largest serial number.

9. An electronic device, characterized in that: include: processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to call the computer program to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor, the method according to any one of claims 1 to 7 is executed.

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