Low-power-consumption trigger circuit structure with test circuit and controllable asynchronous reset state

Abstract

The invention relates to the technical field of chips, in particular to an asynchronous reset state controllable low-power-consumption trigger circuit structure with a test circuit, which comprises a first selector, a second selector, a first trigger, a second trigger, a reset control gate, a set control gate and a NOT gate, a first input port of the first selector is used for receiving a first test reset signal, a second input port of the first selector is used for receiving a first function reset signal, and an enable port of the first selector is used for receiving a test enable signal; the first input port of the second selector is used for receiving a second test reset signal, the second test reset signal is controlled by the test machine, the second input port of the second selector is used for receiving a second function reset signal, and the enabling port of the second selector is used for receiving a test enabling signal. According to the invention, the asynchronous reset state of the trigger can be controlled according to application requirements, and the test of the trigger circuit structure with the controllable asynchronous reset state can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, especially to a low-power trigger circuit structure with test circuit and controllable asynchronous reset state. BACKGROUND

[0002] The reset operation of a flip-flop can be performed in a synchronous or asynchronous manner, depending on the design requirements. Synchronous reset relies on the clock signal, while asynchronous reset can take effect immediately at any time. The active level of the reset signal also affects the behavior of the reset operation. The reset signal of asynchronous reset can reset the flip-flop at any time, without relying on the clock signal. The asynchronous reset value of the flip-flop in the prior art is fixed, and the flip-flop is fixedly reset to 0 or 1 when the reset signal is active, which is uncontrollable. However, in some application scenarios, such as power management design, it is necessary to reset the flip-flop to different values in different application stages, rather than fixed values. If the asynchronous reset state is to be controlled, additional circuit structures are usually needed to achieve this, but the more components added, the greater the power consumption of the chip. In addition, in order to meet the testing requirements, it is also necessary to test the asynchronous reset state controllable flip-flop circuit structure after adding the circuit. Therefore, how to provide a low-power trigger circuit structure with test circuit and controllable asynchronous reset state becomes a technical problem to be solved. SUMMARY

[0003] The present application aims to provide a low-power trigger circuit structure with test circuit and controllable asynchronous reset state, which can control the asynchronous reset state of the flip-flop according to the application requirements under the premise of as little power consumption as possible, and can test the asynchronous reset state controllable flip-flop circuit structure.

[0004] The present application provides a low-power trigger circuit structure with test circuit and controllable asynchronous reset state, comprising a first selector, a second selector, a first flip-flop, a second flip-flop, a reset control gate, a set control gate and a NOT gate, wherein, The first input port of the first selector is used to receive a first test reset signal, the second input port of the first selector is used to receive a first function reset signal, the first test reset signal is controlled by a test machine, and the enable port of the first selector is used to receive a test enable signal. When the test enable signal is high, the first input port of the first selector is connected, and when the test enable signal is low, the second input port of the first selector is connected. The first input port of the second selector is used for receiving a second test reset signal controlled by a test machine, the second input port of the second selector is used for receiving a second function reset signal, and the enable port of the second selector is used for receiving a test enable signal; when the test enable signal is high, the first input port of the second selector is turned on; and when the test enable signal is low, the second input port of the second selector is turned on. The first flip-flop comprises a first reset end, a first set end and a first data end. The second flip-flop comprises a second reset end and a second output end. The reset control gate comprises a first reset input pin, a second reset input pin and a reset output pin. The set control gate comprises a first set input pin, a second set input pin and a set output pin. The first reset input pin and the first set input pin are connected with the output end of the first selector, and the second reset end is connected with the output end of the second selector. The NOT gate is arranged between the second output end and the second reset input pin, or the NOT gate is arranged between the second output end and the second set input pin. The reset output pin is connected with the first reset end, and the set output pin is connected with the first set end.

[0005] Compared with the prior art, the low-power consumption flip-flop circuit structure with an asynchronous reset state controllable test circuit provided by the application has obvious advantages and beneficial effects. The low-power consumption flip-flop circuit structure with an asynchronous reset state controllable test circuit provided by the application has the following beneficial effects at least: The reset control gate, the set control gate and the NOT gate are used to control the reset and set of the first flip-flop through the second flip-flop, so that the asynchronous reset state of the first flip-flop is controllable with as little power consumption as possible. The first selector and the second selector are used to select different reset signals for the first flip-flop and the second flip-flop, so that the low-power consumption flip-flop circuit structure with an asynchronous reset state controllable test circuit is measurable. The application not only controls the asynchronous reset state of the flip-flop according to application requirements, but also meets the requirements of low power consumption and testing. BRIEF DESCRIPTION OF DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0007] Figure 1 A schematic diagram of an asynchronous reset state controllable low-power consumption flip-flop circuit structure with a test circuit is provided for the first embodiment of the present application. Figure 2 A schematic diagram of an asynchronous reset state controllable low-power consumption flip-flop circuit structure with a test circuit is provided for the second embodiment of the present application. Figure 3 A schematic diagram of an asynchronous reset state controllable low-power consumption flip-flop circuit structure with a test circuit is provided for the third embodiment of the present application. Figure 4 A schematic diagram of an asynchronous reset state controllable low-power consumption flip-flop circuit structure with a test circuit is provided for the fourth embodiment of the present application. DETAILED DESCRIPTION

[0008] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0009] The embodiments of the present application provide an asynchronous reset state controllable low-power consumption flip-flop circuit structure with a test circuit, which comprises a first selector, a second selector, a first flip-flop, a second flip-flop, a reset control gate, a set control gate and a NOT gate, wherein, The first input port (1) of the first selector is used for receiving a first test reset signal, the second input port (0) of the first selector is used for receiving a first function reset signal, the first test reset signal is controlled by a test machine, the enable port of the first selector is used for receiving a test enable signal, when the test enable signal is at a high level, the first input port of the first selector is connected, and when the test enable signal is at a low level, the second input port of the first selector is connected. It should be noted that the first test reset signal is a signal used for controlling reset in a test mode, and the first function reset signal is a signal used for controlling reset in a function mode.

[0010] The first input port (1) of the second selector is used to receive a second test reset signal, which is controlled by the test machine. The second input port (0) of the second selector is used to receive a second functional reset signal. The enable port of the second selector is used to receive a test enable signal. When the test enable signal is at a high level, the first input port of the second selector is connected, and when the test enable signal is at a low level, the second input port of the second selector is connected. It should be noted that the second test reset signal is a signal for controlling reset in the test mode, and the second functional reset signal is a signal for controlling reset in the functional mode. It should be noted that the first selector and the second selector can be set in the top-level global control module to make the circuit structure as simple as possible.

[0011] As an embodiment, the first test reset signal and the second test reset signal may be two independent signals or the same signal, and are set according to specific requirements.

[0012] The first flip-flop includes a first reset terminal (R1), a first set terminal (S1), and a first data terminal (D1). It is understood that the first flip-flop also includes a first output port (Q1) and a clock port (not shown in the figure) for inputting a corresponding clock signal. The second flip-flop includes a second reset terminal (R2), a second output terminal (Q2), and a second data terminal (D2). It is understood that the second flip-flop also includes a clock port (not shown in the figure) for inputting a corresponding clock signal, and the second data terminal is connected to a combinational logic circuit.

[0013] The reset control gate includes a first reset input pin, a second reset input pin and a reset output pin. The set control gate includes a first set input pin, a second set input pin and a set output pin.

[0014] The first reset input pin and the first set input pin are both connected to the output of the first selector for receiving a reset signal output by the first selector. The second reset pin is connected to the output of the second selector for receiving a reset signal output by the second selector. The second reset signal is used to set an initial value or reset value for the second flip-flop. When the second flip-flop is in normal operation, the value in the second flip-flop is determined by the clock signal and data port of the second flip-flop.

[0015] The non-gate is arranged between the second output end and the second reset input pin, or the non-gate is arranged between the second output end and the second set input pin; the reset output pin is connected with the first reset end, and the set output pin is connected with the first set end. The signals output by the reset output end and the set output end are in a mutually exclusive relationship, when the reset signal output by the first selector is valid, the first flip-flop is reset to 0 by the first reset end or set to 1 by the first set end, that is, when the reset signal output by the first selector is valid, only one of the signals output by the reset output end and the set output end will affect the value of the first flip-flop, when the reset signal output by the first selector is invalid, the first flip-flop will update the value stored in the first flip-flop to the value input by the first data end when the rising edge of the clock connected with the first flip-flop comes.

[0016] As an embodiment, the circuit structure can further comprise an output control circuit, a data end of the output control circuit is connected with the second output end, an output end of the output control circuit is connected with the second reset data end and the second set data end, the output control circuit is used for adjusting the value output by the second output end, and transmitting the adjusted value to the second reset data end and the second set data end, thereby increasing the flexibility of the asynchronous reset state control.

[0017] As an embodiment, in the test mode, the test enable signal is high, the first input port of the first selector is connected, and the first reset data end and the first set data end are controlled by the first test reset signal. The first input port of the second selector is connected, and the second reset end of the second flip-flop is controlled by the second test reset signal.

[0018] In the loading stage (Scan Shift) of the test vector of the scan test, the value in the second flip-flop is controlled by the scan chain, in the response data capture stage (Scan Capture) of the scan test, the value in the second flip-flop keeps the last state of the scan chain or is controlled by the second test reset signal, the loading of the test vector and the second test reset signal are controlled by the test machine, and the second reset data end and the second set data end in each A m are controlled by the output value of the second flip-flop.

[0019] It should be noted that in the test mode, the first test reset signal and the second test reset signal are controlled by a test machine, and the loading of the test vector is controlled by the test machine (ATE). The first reset data end and the second reset data end of the reset setting module are measurable, so that the fan-in paths of the first reset end of the first flip-flop are measurable. The first set data end and the second set data end of the set setting module are also measurable, so that the fan-in paths of the first set end of the first flip-flop are measurable. The second reset end of the second flip-flop is also measurable. The circuit structure of the embodiment of the application makes the low-power flip-flop circuit structure with controllable asynchronous reset state measurable in the test mode, improves the test coverage, and does not need to increase additional test bypass circuit, and the circuit structure is simple.

[0020] The first reset end and the first set end can be set as asynchronous low-level effective ports or asynchronous high-level effective ports. The asynchronous low-level effective port refers to a port that is asynchronous and performs reset or set when receiving a low level. The asynchronous high-level effective port refers to a port that is asynchronous and performs reset or set when receiving a high level. If the first reset end and the first set end are both asynchronous low-level effective ports, the reset control gate and the set control gate are both set as OR gates. If the first reset end and the first set end are both asynchronous high-level effective ports, the reset control gate and the set control gate are both set as AND gates.

[0021] The following is described through several specific embodiments.

[0022] Embodiment one, As Figure 1 shown, the first reset end and the first set end are both asynchronous low-level effective ports, and the reset control gate and the set control gate are both set as OR gates. The NOT gate is set between the second output end and the second reset input pin.

[0023] In the functional mode or in the response data capture stage of the test mode, when the signal output by the first selector is a low level, if the value output by the second output end is 0, the first reset input pin inputs 0, the NOT gate converts 0 into 1 and inputs the reset control gate from the second reset input pin, the reset output pin outputs a high level, and the reset operation is not performed. The first set input pin and the second set input pin of the set control gate both input 0, and the set output pin outputs a low level, setting the first flip-flop to 1. It can be understood that for the structure of embodiment one, in the case that the first reset end and the first set end are both asynchronous low-level effective ports, in the functional mode or in the response data capture stage of the test mode, if it is needed to set the value in the first flip-flop to 1, the second flip-flop outputs 0.

[0024] In the functional mode, or in the response data capture phase of the test mode, when the signal of the first selector output is low, if the value of the second output end is 1, the first reset input pin inputs 0, the NOT gate converts 1 to 0 and inputs the reset control gate from the second reset input pin, the reset output pin outputs low, and the first flip-flop is reset to 0. The first set input pin of the set control gate inputs 0, the second set input pin inputs 1, the set output pin outputs high, and the set operation is not performed. It can be understood that for the structure described in Embodiment 1, in the case that the first reset end and the first set end are both asynchronous low-level effective ports, in the functional mode, or in the response data capture phase of the test mode, if it is needed to set the value in the first flip-flop to 0, the second flip-flop can output 1.

[0025] Embodiment two, As Figure 2 shown, the first reset end and the first set end are both asynchronous low-level effective ports, and the reset control gate and the set control gate are both set as OR gates. The NOT gate is arranged between the second output end and the second set input pin.

[0026] In the functional mode, or in the response data capture phase of the test mode, when the signal of the first selector output is low, if the value of the second output end is 0, the first set input pin inputs 0, the NOT gate converts 0 to 1 and inputs the set control gate from the second set input pin, the set output pin outputs high, and the set operation is not performed. The first reset input pin and the second reset input pin of the reset control gate both input 0, the reset output pin outputs low, and the first flip-flop is reset to 0. It can be understood that for the structure described in Embodiment 2, in the case that the first reset end and the first set end are both asynchronous low-level effective ports, in the functional mode, or in the response data capture phase of the test mode, if it is needed to set the value in the first flip-flop to 0, the second flip-flop can output 0.

[0027] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is low, if the value output by the second output terminal is 1, the first set input pin inputs 0, the NOT gate converts 1 to 0, and then inputs the value from the second set input pin to the set control gate. The set output pin outputs a low level, setting the first flip-flop to 1. The first reset input pin of the reset control gate inputs 0, the second reset input pin inputs 1, and the reset output pin outputs a high level, without performing a reset operation. It is understood that for the structure described in Example 2, when both the first reset terminal and the first set terminal are asynchronous low-level active ports, in functional mode or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 1, the second flip-flop can be controlled to output 1.

[0028] Example 3: like Figure 3 As shown, the first reset terminal and the first set terminal are both asynchronous high-level valid ports, the reset control gate and the set control gate are both configured as AND gates, and the NOT gate is configured between the second output terminal and the second reset input pin.

[0029] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is high, if the value output by the second output terminal is 0, the first reset input pin inputs 1, the NOT gate converts 0 to 1, and then inputs the reset control gate from the second reset input pin. The reset output pin outputs a high level, resetting the first flip-flop to 0. The first set input pin of the set control gate inputs 1, and the second set input pin inputs 0. The set output pin outputs a low level, and the set operation is not performed. It can be understood that for the structure described in Example 3, when the first reset terminal and the first set terminal are both asynchronous high-level active ports, in functional mode, or during the response data capture phase in test mode, if it is necessary to set the value in the first flip-flop to 0, the second flip-flop can be controlled to output 0.

[0030] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is high, if the value output by the second output terminal is 1, the first reset input pin inputs 1, the NOT gate converts 1 to 0, and then inputs the reset control gate from the second reset input pin. The reset output pin outputs a low level, and no reset operation is performed. The first set input pin of the set control gate inputs 1, the second set input pin inputs 1, and the set output pin outputs a high level, setting the first flip-flop to 1. It can be understood that for the structure described in Example 3, when the first reset terminal and the first set terminal are both asynchronous high-level active ports, in functional mode, or during the response data capture phase in test mode, if the value in the first flip-flop needs to be set to 1, the second flip-flop can be controlled to output 1.

[0031] Example 4: like Figure 4 As shown, the first reset terminal and the first set terminal are both asynchronous high-level active ports, the reset control gate and the set control gate are both configured as AND gates, and the NOT gate is configured between the second output terminal and the second set input pin.

[0032] In functional mode, or during the response data capture phase in test mode, when the signal output by the first selector is high, if the value output by the second output terminal is 0, the first set input pin inputs 1, the NOT gate converts 0 to 1, and then inputs the value from the second set input pin to the set control gate. The set output pin outputs a high level, setting the first flip-flop to 1. If the first reset input pin of the reset control gate inputs 1, and the second reset input pins both input 0, the reset output pin outputs a low level, and no reset operation is performed. With respect to the structure described in Example 4, if both the first reset terminal and the first set terminal are asynchronous high-level active ports, in functional mode, or during the response data capture phase in test mode, if the value in the first flip-flop needs to be set to 1, the second flip-flop can be controlled to output 0.

[0033] In the functional mode, or in the response data capture phase of the test mode, when the signal of the first selector output is high, if the value of the second output end is 1, the first set input pin inputs 1, the non-inverting gate inputs 1 from the second set input pin after conversion, and the set control gate outputs 0, the reset output pin outputs low, and the set operation is not performed. The first reset input pin of the reset control gate inputs 1, the second reset input pin inputs 1, and the reset output pin outputs high, and the first flip-flop is reset to 0. For the structure described in embodiment four, in the case that the first reset end and the first set end are both asynchronous high-level effective ports, in the functional mode, or in the response data capture phase of the test mode, if it is required to set the value in the first flip-flop to 0, the second flip-flop can output 1 to control.

[0034] The embodiment of the present application controls the reset and set of the first flip-flop through the reset control gate, the set control gate and the non-inverting gate, and controls the asynchronous reset state of the first flip-flop through the second flip-flop with as little power consumption as possible. The present application selects different reset signals for the first flip-flop and the second flip-flop through the first selector and the second selector, so that the low-power-consumption flip-flop circuit structure with controllable asynchronous reset state can be tested. The present application not only controls the asynchronous reset state of the flip-flop according to the application requirement, but also meets the low-power-consumption requirement and the test requirement of the circuit.

[0035] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes, without departing from the technical solution of the present application. Any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present application are still within the scope of the present application.

Claims

1. A low-power trigger circuit structure with asynchronous reset state controllable and test circuit, characterized in that: It includes a first selector, a second selector, a first trigger, a second trigger, a reset control gate, a set control gate and a NOT gate, wherein: The first input port of the first selector is used to receive a first test reset signal, the second input port of the first selector is used to receive a first functional reset signal, and the enable port of the first selector is used to receive a test enable signal. When the test enable signal is at a high level, the first input port of the first selector is connected, and when the test enable signal is at a low level, the second input port of the first selector is connected; The first input port of the second selector is used to receive a second test reset signal, which is controlled by the test machine. The second input port of the second selector is used to receive a second functional reset signal. The enable port of the second selector is used to receive a test enable signal. When the test enable signal is at a high level, the first input port of the second selector is connected. When the test enable signal is at a low level, the second input port of the second selector is connected. The first trigger includes a first reset terminal, a first set terminal, and a first data terminal; The second trigger includes a second reset terminal and a second output terminal; The reset control gate includes a first reset input pin, a second reset input pin and a reset output pin; The set control gate includes a first set input pin, a second set input pin and a set output pin; The first reset input pin and the first set input pin are both connected to the output end of the first selector, and the second reset end is connected to the output end of the second selector; The NOT gate is arranged between the second output terminal and the second reset input pin, or the NOT gate is arranged between the second output terminal and the second set input pin; The reset output pin is connected to the first reset terminal, and the set output pin is connected to the first set terminal.

2. The circuit structure according to claim 1, wherein: The signal output by the reset output terminal and the signal output by the set output terminal are mutually exclusive. When the reset signal output by the first selector is valid, the first trigger is reset to 0 by the first reset terminal or set to 1 by the first set terminal. When the reset signal output by the first selector is invalid, the first trigger updates the value stored in the first trigger to the value input by the first data terminal when the rising edge of the clock connected to the first trigger arrives.

3. The circuit structure according to claim 1, wherein: In the test mode, the test enable signal is at a high level, the first input port of the first selector is connected, and the first reset data terminal and the first set data terminal are both controlled by the first test reset signal; the first input port of the second selector is connected, and the second reset terminal of the second flip-flop is controlled by the second test reset signal; In the test vector loading phase of the scan test, the value in the second flip-flop is controlled by the scan chain. In the response data capture phase of the scan test, the value in the second flip-flop maintains the last state of the scan chain or is controlled by the second test reset signal. m The second reset data terminal and the second set data terminal are controlled by the output value of the second trigger.

4. The circuit structure according to claim 2, wherein: The first reset terminal and the first set terminal are both asynchronous low-level active ports, and the reset control gate and the set control gate are both configured as OR gates.

5. The circuit structure according to claim 2, wherein: The first reset terminal and the first set terminal are both asynchronous high-level active ports, and the reset control gate and the set control gate are both configured as AND gates.

6. The circuit structure according to claim 1, wherein: The circuit structure further includes an output control circuit, wherein the data terminal of the output control circuit is connected to the second output terminal, and the output terminal of the output control circuit is connected to the second reset data terminal and the second set data terminal.

7. The circuit structure according to claim 3, characterized in that: The first test reset signal, the second test reset signal and the loading of the test vector are all controlled by a test machine.

8. The circuit structure according to claim 1, wherein: The circuit structure may further include an output control circuit, wherein the data end of the output control circuit is connected to the second output end, and the output end of the output control circuit is connected to the second reset data end and the second set data end. The output control circuit is used to adjust the value output by the second output end and transmit the adjusted value to the second reset data end and the second set data end.

Images