Trigger circuit structure with test circuit and controllable asynchronous reset state

Abstract

The invention relates to the technical field of chips, in particular to an asynchronous reset state controllable trigger circuit structure with a test circuit, which comprises a first reset control circuit, a second reset control circuit and M groups of asynchronous reset state controllable trigger circuits {A1, A2,..., Am,..., AM}, and is characterized in that Am is the mth asynchronous reset state controllable trigger circuit; the first reset control circuit is used for providing a first test reset signal for each Am in a test mode and providing a first function reset signal for each Am in a function mode; the second reset control circuit is used for providing a second test reset signal for each Am in the test mode and providing a second function reset signal for each Am in the function mode. According to the invention, the asynchronous reset state of the trigger can be controlled according to application requirements, and the test of the trigger circuit structure with the controllable asynchronous reset state can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, especially to an asynchronous reset state controllable flip-flop circuit structure with a test circuit. BACKGROUND

[0002] The reset operation of a flip-flop can be performed in a synchronous or asynchronous manner, depending on the design requirements. Synchronous reset relies on a clock signal, while asynchronous reset can take effect immediately at any time. The active level of the reset signal also affects the behavior of the reset operation. The reset signal of asynchronous reset can reset the flip-flop at any time, without relying on the clock signal. The asynchronous reset value of the flip-flop in the prior art is fixed, and the flip-flop is fixedly reset to 0 or 1 when the reset signal is active, which is uncontrollable. However, in some application scenarios, such as power management design, it is necessary to reset the flip-flop to different values in different application stages, rather than fixed values. If the asynchronous reset state of the flip-flop needs to be controllable, further circuit structures need to be added, and in order to meet the testing requirements, the test of the asynchronous reset state controllable flip-flop circuit structure after adding the circuit needs to be implemented. Therefore, how to provide an asynchronous reset state controllable flip-flop circuit structure with a test circuit becomes a technical problem to be solved. SUMMARY

[0003] The present application aims to provide an asynchronous reset state controllable flip-flop circuit structure with a test circuit, which can control the asynchronous reset state of the flip-flop according to application requirements, and can implement the test of the asynchronous reset state controllable flip-flop circuit structure.

[0004] The present application provides an asynchronous reset state controllable flip-flop circuit structure with a test circuit, which comprises a first reset control circuit, a second reset control circuit, M groups of asynchronous reset state controllable flip-flop circuits {A1, A2,..., Am,..., AM}, and a test circuit. m ,...,A M},A m is the mth asynchronous reset state controllable flip-flop circuit, m is in the range of 1 to M, and M is the total number of asynchronous reset state controllable flip-flop circuits; The first reset control circuit is used to provide a first test reset signal for each A m in the test mode, and provide a first function reset signal for each A m in the function mode; the second reset control circuit is used to provide a second test reset signal for each A m in the test mode, and provide a second function reset signal for each A m in the function mode. The first reset control circuit comprises a first selector, a first input port of the first selector is used for receiving a first test reset signal, a second input port of the first selector is used for receiving a first function reset signal, and an enable port of the first selector is used for receiving a test enable signal; when the test enable signal is at a high level, the first input port of the first selector is connected; and when the test enable signal is at a low level, the second input port of the first selector is connected. The second reset control circuit comprises a second selector, a first input port of the second selector is used for receiving a second test reset signal, a second input port of the second selector is used for receiving a second function reset signal, and an enable port of the second selector is used for receiving a test enable signal; when the test enable signal is at a high level, the first input port of the second selector is connected; and when the test enable signal is at a low level, the second input port of the second selector is connected.

[0005] Compared with the prior art, the application has obvious advantages and beneficial effects. The asynchronous reset state controllable flip-flop circuit structure with a test circuit provided by the application can achieve considerable technical progress and practicality, and has wide industrial utilization value, and at least has the following beneficial effects: The application controls the reset signals of multiple groups of asynchronous reset state controllable flip-flop circuit structures by setting a group of first reset control circuits and second reset control circuits, so that each asynchronous reset state controllable flip-flop circuit is controlled by the first function reset signal and the second function reset signal in the function mode and is controlled by the first test reset signal and the second test reset signal in the test mode. The application simplifies the test circuit structure of the asynchronous reset state controllable flip-flop circuit structure, can control the asynchronous reset state of the flip-flop according to application requirements, and can test the asynchronous reset state controllable flip-flop circuit structure. BRIEF DESCRIPTION OF DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0007] Figure 1 The asynchronous reset state controllable flip-flop circuit structure with a test circuit provided by the embodiment of the application is shown in the schematic diagram. Figure 2 The circuit structure schematic diagram of the A m provided by the embodiment of the application is shown in the schematic diagram. Figure 3 The circuit structure schematic diagram of the A ma circuit structure schematic diagram of the first reset control circuit and the second reset control circuit; Figure 4 A provided for the second embodiment of the present application m a circuit structure schematic diagram of the first reset control circuit and the second reset control circuit; Figure 5 A provided for the third embodiment of the present application m a circuit structure schematic diagram of the first reset control circuit and the second reset control circuit; Figure 6 A provided for the fourth embodiment of the present application m a circuit structure schematic diagram of the first reset control circuit and the second reset control circuit. DETAILED DESCRIPTION

[0008] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0009] The embodiments of the present application provide a flip-flop circuit structure with testable asynchronous reset state controllable circuit, as shown in Figure 1 which comprises a first reset control circuit (U1), a second reset control circuit (U2), and M groups of asynchronous reset state controllable flip-flop circuits {A1, A2,..., A m ,..., A M}, A m is the mth asynchronous reset state controllable flip-flop circuit, the value range of m is 1 to M, and M is the total number of asynchronous reset state controllable flip-flop circuits. The asynchronous reset state controllable flip-flop circuit refers to a circuit capable of controlling the stored value in the reset flip-flop according to application requirements.

[0010] The first reset control circuit is used for providing a first test reset signal for each A m in a test mode and providing a first function reset signal for each A m in a function mode; and the second reset control circuit is used for providing a second test reset signal for each A m in the test mode and providing a second function reset signal for each A m in the function mode. It can be known that the embodiments of the present application can control the reset signals of multiple groups of asynchronous reset state controllable flip-flop circuits through a group of first reset control circuits and second reset control circuits at the same time, which greatly simplifies the circuit structure.

[0011] The first reset control circuit comprises a first selector, a first input port (1) of the first selector is used for receiving a first test reset signal, a second input port (0) of the first selector is used for receiving a first function reset signal, an enable port of the first selector is used for receiving a test enable signal, when the test enable signal is high, the first input port of the first selector is connected, and when the test enable signal is low, the second input port of the first selector is connected. It should be noted that the first test reset signal is a signal used for controlling reset in a test mode, and the first function reset signal is a signal used for controlling reset in a function mode.

[0012] The second reset control circuit comprises a second selector, a first input port (1) of the second selector is used for receiving a second test reset signal, a second input port (0) of the second selector is used for receiving a second function reset signal, an enable port of the second selector is used for receiving a test enable signal, when the test enable signal is high, the first input port of the second selector is connected, and when the test enable signal is low, the second input port of the second selector is connected. It should be noted that the second test reset signal is a signal used for controlling reset in a test mode, and the second function reset signal is a signal used for controlling reset in a function mode.

[0013] As an embodiment, the first test reset signal and the second test reset signal are both controlled by a test machine, and the first test reset signal and the second test reset signal can be two independent signals or the same signal, which is set according to specific requirements.

[0014] As an embodiment, as shown in Figure 2 A m The first trigger comprises a first reset end (R1), a first set end (S1) and a first data end (D1), and it can be understood that the first trigger further comprises a clock port (not shown in the figure) for inputting a corresponding clock signal. The second trigger comprises a second reset end (R2), a second output end (Q2) and a second data end (D2), and it can be understood that the second trigger further comprises a clock port (not shown in the figure) for inputting a corresponding clock signal.

[0015] The reset setting module comprises a first reset data end, a second reset data end and a reset output end; the set setting module comprises a first set data end, a second set data end and a set output end, and the second data end is connected with a combination logic circuit.

[0016] The first reset data terminal and the first set data terminal are both connected to the output terminal of the first selector, for receiving the reset signal output by the first selector. The second reset data terminal and the second set data terminal are both connected to the second output terminal, for receiving the reset signal output by the second selector. The reset output terminal is connected to the first reset terminal, the set output terminal is connected to the first set terminal, and the second reset terminal is connected to the output terminal of the second selector. The second reset signal is used to set the initial value or reset value of the second flip-flop. When the second flip-flop is in normal operation, the value in the second flip-flop is determined by the clock signal and data port of the second flip-flop.

[0017] The signal output by the reset output terminal and the signal output by the set output terminal are mutually exclusive. When the reset signal output by the first selector is valid, the first flip-flop is reset to 0 by the first reset terminal or set to 1 by the first set terminal. That is, when the first reset signal is valid, only one of the signal output by the reset output terminal and the signal output by the set output terminal will affect the value of the first flip-flop, thereby achieving controllable asynchronous reset state of the first flip-flop. When the reset signal output by the first selector is invalid, the signal output by the reset output terminal and the signal output by the set output terminal do not affect the value of the first flip-flop. The first flip-flop updates the value stored in the first flip-flop to the value input by the first data terminal when the rising edge of the clock connected to the first flip-flop arrives.

[0018] As an embodiment, the circuit structure may further include an output control circuit, wherein the data end of the output control circuit is connected to the second output end, and the output end of the output control circuit is connected to the second reset data end and the second set data end. The output control circuit is used to adjust the value output by the second output end and transmit the adjusted value to the second reset data end and the second set data end, thereby increasing the flexibility of asynchronous reset state control.

[0019] As an embodiment, in the test mode, the test enable signal is at a high level, the first input port of the first selector is connected, the first selector outputs a first test reset signal, and each A m The first reset data terminal and the first set data terminal are controlled by the first test reset signal; the first input port of the second selector is connected, and the second selector outputs the second test reset signal. m The second reset terminal of the second trigger is controlled by the second test reset signal.

[0020] In the scan test vector loading phase (Scan Shift), the flip-flop will be worn into the scan chain, and the value in the second flip-flop is controlled by the scan chain. In the scan test response data capture phase (Scan Capture), the value in the second flip-flop maintains the last state of the scan chain or is controlled by the second test reset signal. mThe second reset data terminal and the second set data terminal are controlled by the output value of the second trigger.

[0021] It should be noted that, in test mode, the first test reset signal and the second test reset signal are both controlled by the test machine, and the loading of the test vector is controlled by the test machine. This makes the first reset data terminal and the second reset data terminal of the reset setting module testable, thereby making the fan-in path of the first reset terminal of the first trigger testable. It also makes the first set data terminal and the second set data terminal of the set setting module testable, thereby making the fan-in path of the first set terminal of the first trigger testable. It also makes the second reset terminal of the second trigger testable. The circuit structure described in the embodiment of the present invention makes the trigger circuit structure with controllable asynchronous reset state testable in test mode, thereby improving the test coverage.

[0022] The first reset terminal and the first set terminal can be configured as asynchronous low-level active ports or asynchronous high-level active ports. An asynchronous low-level active port is an asynchronous port that performs a reset or set operation upon receiving a low level. An asynchronous high-level active port is an asynchronous port that performs a reset or set operation upon receiving a high level. This is described below using several specific embodiments.

[0023] Example 1 like Figure 3 In the example shown, both the first reset terminal and the first set terminal are asynchronous low-level active ports.

[0024] The setting module includes a third selector, wherein a first input port of the third selector is set to the first setting data terminal, a second input port of the third selector is set to be fixedly connected to a high level, an enable port of the third selector is set to the second setting data terminal, and an output port of the third selector is set to the setting output terminal. When the enable port input of the third selector is 1, the first input port of the third selector is connected, and when the enable port input of the third selector is 0, the second input port of the third selector is connected.

[0025] The reset setting module includes a fourth selector and an inverter. The first input port of the fourth selector is set to the first reset data terminal, the second input port of the fourth selector is set to be fixedly connected to a high level, the enable terminal of the fourth selector is connected to the output terminal of the inverter, the data terminal of the inverter is set to the second reset data terminal, and the output terminal of the fourth selector is set to the reset output terminal. When the enable port input of the fourth selector is 1, the first input port of the fourth selector is connected, and when the enable port input of the third selector is 0, the second input port of the third selector is connected.

[0026] In the functional mode or in the response data capture stage of the test mode, when the signal outputted by the first selector is low and the value outputted by the second output terminal is 0, the enable port input of the third selector is 0, the second input port of the third selector is enabled, the set output terminal outputs high, and the set operation is not performed. After the inverter input 0, the output is 1, the enable port input of the fourth selector is 1, the first input port of the fourth selector is enabled, the reset output terminal is low, and the first flip-flop is reset to 0. It can be understood that for the structure described in Embodiment 1, in the case that the first reset terminal and the first set terminal are both asynchronous low active ports, in the functional mode or in the response data capture stage of the test mode, if it is needed to set the value in the first flip-flop to 0, the second flip-flop can be controlled to output 0.

[0027] In the functional mode or in the response data capture stage of the test mode, when the signal outputted by the first selector is low and the value outputted by the second output terminal is 1, the enable port input of the third selector is 1, the first input port of the third selector is enabled, the set output terminal is low, and the first flip-flop is set to 1. After the inverter input 1, the output is 0, the enable port input of the fourth selector is 0, the second input port of the fourth selector is enabled, the reset output terminal is high, and the reset operation is not performed. It can be understood that for the structure described in Embodiment 1, in the case that the first reset terminal and the first set terminal are both asynchronous low active ports, in the functional mode or in the response data capture stage of the test mode, if it is needed to set the value in the first flip-flop to 1, the second flip-flop can be controlled to output 1.

[0028] Embodiment 2, As Figure 4 shown in the example, the first reset terminal and the first set terminal are both asynchronous low active ports.

[0029] The set setting module comprises a third selector and an inverter. The first input port of the third selector is set as the first reset data terminal. The second input port of the third selector is set as fixed connection high. The enable port of the third selector is connected with the output terminal of the inverter. The data terminal of the inverter is set as the second set data terminal. The output terminal of the third selector is set as the set output terminal. When the enable port input of the third selector is 1, the first input port of the third selector is enabled. When the enable port input of the third selector is 0, the second input port of the third selector is enabled.

[0030] The reset setting module comprises a fourth selector, a first input port of the fourth selector is set as the first reset data end, a second input port of the fourth selector is set as fixedly connected high level, an enable end of the fourth selector is set as the second reset data end, and an output end of the fourth selector is set as the reset output end. When the enable end port of the fourth selector inputs 1, the first input port of the fourth selector is turned on, and when the enable end port of the third selector inputs 0, the second input port of the third selector is turned on.

[0031] The first reset end and the first set end can be set as asynchronous low-level effective ports or asynchronous high-level effective ports. The asynchronous low-level effective port refers to a port that is asynchronous and performs reset or setting when a low level is received. The asynchronous high-level effective port refers to a port that is asynchronous and performs reset or setting when a high level is received. The following is described in different cases.

[0032] In the functional mode or in the response data capture stage of the test mode, when the signal output by the first selector is low level and the value output by the second output end is 0, the inverter outputs 1 after inputting 0, the enable end port of the third selector inputs 1, the first input port of the third selector is turned on, the set output end outputs low level, and the first flip-flop is set to 1. The enable end port of the fourth selector inputs 0, the second input port of the fourth selector is turned on, the reset output end is high level, and no reset operation is performed. It can be understood that for the structure described in Embodiment 2, if it is necessary to set the value in the first flip-flop to 1, the second flip-flop can output 0.

[0033] In the functional mode or in the response data capture stage of the test mode, when the signal output by the first selector is low level and the value output by the second output end is 1, the inverter outputs 0 after inputting 1, the enable end port of the third selector inputs 0, the second input port of the third selector is turned on, the set output end is high level, and no setting operation is performed. The enable end port of the fourth selector inputs 1, the first input port of the fourth selector is turned on, the reset output end is low level, and the first flip-flop is reset to 0. It can be understood that for the structure described in Embodiment 2, in the functional mode or in the response data capture stage of the test mode, if it is necessary to set the value in the first flip-flop to 0, the second flip-flop can output 1.

[0034] Embodiment three, As Figure 5 shown in the example, the first reset end and the first set end are both asynchronous high-level effective ports.

[0035] The setting module comprises a third selector, the first input port of the third selector is set as the first setting data end, the second input port of the third selector is set as a fixed low level, the enable port of the third selector is set as the second setting data end, and the output port of the third selector is set as the setting output end. When the enable port of the third selector inputs 1, the first input port of the third selector is connected; when the enable port of the third selector inputs 0, the second input port of the third selector is connected.

[0036] The resetting module comprises a fourth selector and an inverter, the first input port of the fourth selector is set as the first resetting data end, the second input port of the fourth selector is set as a fixed low level, the enable port of the fourth selector is connected with the output end of the inverter, the data end of the inverter is set as the second resetting data end, and the output end of the fourth selector is set as the resetting output end. When the enable port of the fourth selector inputs 1, the first input port of the fourth selector is connected; when the enable port of the third selector inputs 0, the second input port of the third selector is connected.

[0037] In the functional mode or in the response data capture stage of the test mode, when the signal output by the first selector is high and the value output by the second output end is 0, the enable port of the third selector inputs 0, the second input port of the third selector is connected, the setting output end outputs low, and the setting operation is not performed. After the inverter inputs 0, the output is 1, the enable port of the fourth selector inputs 1, the first input port of the fourth selector is connected, the resetting output end is high, and the first flip-flop is reset to 0. It can be understood that for the structure described in embodiment three, in the case that the first resetting end and the first setting end are both asynchronous high-level effective ports, in the functional mode or in the response data capture stage of the test mode, if it is needed to set the value in the first flip-flop to 0, the output of the second flip-flop is controlled to 0.

[0038] In the functional mode, or in the response data capture phase of the test mode, when the signal of the first selector output is high and the value of the second output is 1, the enable port input of the third selector is 1, the first input port of the third selector is connected, the set output is high, and the first flip-flop is set to 1. After the inverter input 1, the output is 0, the enable port input of the fourth selector is 0, the second input port of the fourth selector is connected, the reset output is low, and the reset operation is not performed. It can be understood that for the structure described in Embodiment Three, in the case that the first reset end and the first set end are both asynchronous high-level effective ports, in the functional mode, or in the response data capture phase of the test mode, if it is required to set the value in the first flip-flop to 1, the output of the second flip-flop is controlled to 1.

[0039] Embodiment Four, As Figure 6 shown in the example, the first reset end and the first set end are both asynchronous high-level effective ports.

[0040] The set setting module includes a third selector and an inverter. The first input port of the third selector is set as the first reset data end. The second input port of the third selector is set as a fixed connection low. The enable port of the third selector is connected with the output end of the inverter. The data end of the inverter is set as the second set data end. The output end of the third selector is set as the set output. When the enable port input of the third selector is 1, the first input port of the third selector is connected. When the enable port input of the third selector is 0, the second input port of the third selector is connected.

[0041] The reset setting module includes a fourth selector. The first input port of the fourth selector is set as the first reset data end. The second input port of the fourth selector is set as a fixed connection low. The enable port of the fourth selector is set as the second reset data end. The output end of the fourth selector is set as the reset output. When the enable port input of the fourth selector is 1, the first input port of the fourth selector is connected. When the enable port input of the third selector is 0, the second input port of the third selector is connected.

[0042] In the functional mode or in the response data capture phase of the test mode, when the signal outputted by the first selector is high and the value outputted by the second output terminal is 0, the inverter inputs 0 and then outputs 1, the enable terminal of the third selector inputs 1, the first input terminal of the third selector is enabled, the set output terminal outputs high, and the first flip-flop is set to 1. The enable terminal of the fourth selector inputs 0, the second input terminal of the fourth selector is enabled, and the reset output terminal is low, and no reset operation is performed. It can be understood that, for the structure described in Embodiment 4, in the case that the first reset terminal and the first set terminal are both asynchronous high active terminals, in the functional mode or in the response data capture phase of the test mode, if it is required to set the value in the first flip-flop to 1, the second flip-flop can be controlled to output 0.

[0043] In the functional mode or in the response data capture phase of the test mode, when the signal outputted by the first selector is high and the value outputted by the second output terminal is 1, the inverter inputs 1 and then outputs 0, the enable terminal of the third selector inputs 0, the second input terminal of the third selector is enabled, and the set output terminal is low, and no set operation is performed. The enable terminal of the fourth selector inputs 1, the first input terminal of the fourth selector is enabled, the reset output terminal is high, and the first flip-flop is reset to 0. It can be understood that, for the structure described in Embodiment 4, in the case that the first reset terminal and the first set terminal are both asynchronous high active terminals, in the functional mode or in the response data capture phase of the test mode, if it is required to set the value in the first flip-flop to 0, the second flip-flop can be controlled to output 1.

[0044] The embodiment of the present application controls the reset signals of a plurality of groups of flip-flop circuits with asynchronous reset state control by setting a group of first reset control circuits and a group of second reset control circuits, so that each flip-flop circuit with asynchronous reset state control is controlled by a first functional reset signal and a second functional reset signal in the functional mode and by a first test reset signal and a second test reset signal in the test mode. The present application simplifies the test circuit structure of the flip-flop circuit structure with asynchronous reset state control, can control the asynchronous reset state of the flip-flop according to application requirements, and can test the flip-flop circuit structure with asynchronous reset state control.

[0045] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application. Any person skilled in the art, without departing from the technical solution of the present application, can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, as long as it does not deviate from the technical solution of the present application, still belongs to the scope of the technical solution of the present application.

Claims

1. An asynchronous reset state controllable trigger circuit structure with a test circuit, characterized in that: It includes a first reset control circuit, a second reset control circuit, and M groups of asynchronous reset state controllable trigger circuits {A1, A2, ..., A m ,...,A M },A m is the mth asynchronous reset state controllable flip-flop circuit, where m ranges from 1 to M, and M is the total number of asynchronous reset state controllable flip-flop circuits; The first reset control circuit is used to reset each A in the test mode m Provides the first test reset signal, which is used for each A in functional mode. m Provides a first function reset signal; the second reset control circuit is used for each A in the test mode m Provides a second test reset signal for each A in functional mode m Providing a second function reset signal; The first reset control circuit includes a first selector, a first input port of the first selector is used to receive a first test reset signal, a second input port of the first selector is used to receive a first functional reset signal, and an enable port of the first selector is used to receive a test enable signal, when the test enable signal is at a high level, the first input port of the first selector is connected, and when the test enable signal is at a low level, the second input port of the first selector is connected; The second reset control circuit includes a second selector, the first input port of the second selector is used to receive a second test reset signal, the second input port of the second selector is used to receive a second functional reset signal, and the enable port of the second selector is used to receive a test enable signal. When the test enable signal is at a high level, the first input port of the second selector is connected, and when the test enable signal is at a low level, the second input port of the second selector is connected.

2. The circuit structure according to claim 1, wherein: The first test reset signal and the second test reset signal are both controlled by a test machine.

3. The circuit structure according to claim 1, wherein: A m It includes a first trigger, a second trigger, a reset setting module and a set setting module, wherein: The first trigger includes a first reset terminal, a first set terminal, and a first data terminal; The second trigger includes a second reset terminal and a second output terminal; The reset setting module includes a first reset data terminal, a second reset data terminal and a reset output terminal; The setting module includes a first setting data terminal, a second setting data terminal and a setting output terminal; The first reset data terminal and the first set data terminal are both connected to the output terminal of the first selector, the second reset data terminal and the second set data terminal are both connected to the second output terminal, the reset output terminal is connected to the first reset terminal, the set output terminal is connected to the first set terminal, and the second reset terminal is connected to the output terminal of the second selector; The signal output by the reset output terminal and the signal output by the set output terminal are mutually exclusive. When the reset signal output by the first selector is valid, the first trigger is reset to 0 by the first reset terminal or set to 1 by the first set terminal. When the reset signal output by the first selector is invalid, the first trigger updates the value stored in the first trigger to the value input by the first data terminal when the rising edge of the clock connected to the first trigger arrives.

4. The circuit structure according to claim 3, wherein: In the test mode, the test enable signal is high, the first input port of the first selector is connected, and each A m The first reset data terminal and the first set data terminal in the test are controlled by the first test reset signal; the first input port of the second selector is connected, and each A m The second reset terminal of the second trigger is controlled by the second test reset signal; In the test vector loading phase of the scan test, the value in the second flip-flop is controlled by the scan chain. In the response data capture phase of the scan test, the value in the second flip-flop maintains the last state of the scan chain or is controlled by the second test reset signal. m The second reset data terminal and the second set data terminal are controlled by the output value of the second trigger.

5. The circuit structure according to claim 4, characterized in that: The loading of the test vectors is controlled by a test machine.

6. The circuit structure according to claim 3, characterized in that: The first reset terminal and the first set terminal are both low-level valid ports.

7. The circuit structure according to claim 3, characterized in that: The first reset terminal and the first set terminal are both high-level valid ports.

8. The circuit structure according to claim 3, wherein: The circuit structure further includes an output control circuit, wherein the data terminal of the output control circuit is connected to the second output terminal, and the output terminal of the output control circuit is connected to the second reset data terminal and the second set data terminal.

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