Double-edge injection locking clock generator, oscillation generation method and chip
Through the design of a dual-edge injection-locked clock generator, using the injection-enable structure of the reverse delay unit and the dual-edge injection locking technology, the problems of small frequency tracking range and low injection efficiency of traditional phase-locked loops are solved, and efficient frequency correction and noise suppression are achieved, which is suitable for high-performance integrated circuits.
Patent Information
- Application Number
- CN202510895688.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-30
- Publication Date
- 2025-10-17
AI Technical Summary
Traditional phase-locked loops have a small frequency tracking range and steady-state errors, making them difficult to apply to high-performance integrated circuits. Injection-locked phase-locked loops have low injection efficiency and are difficult to suppress the out-of-band noise of voltage-controlled oscillators. In addition, the loop is difficult to correct when the voltage-controlled oscillator frequency offsets.
A dual-edge injection-locked clock generator is used, including a pulse generator, an injection-locked ring voltage-controlled oscillator, a phase detector, a charge pump and a low-pass filter. The injection-enable structure of the reverse delay unit and the dual-edge injection locking technology are used to improve the injection efficiency, suppress the in-band noise of the voltage-controlled oscillator, and correct the local oscillator frequency offset of the voltage-controlled oscillator without adding additional circuits.
It significantly improves injection efficiency, reduces clock jitter, provides a frequency output of 2.2 to 2.6 GHz, effectively suppresses the in-band noise of the voltage-controlled oscillator, and realizes the correction of the voltage-controlled oscillator local oscillator frequency offset.
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Figure CN120811364A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the field of clock generator, and relates to a double-edge injection-locked clock generator, an oscillation generation method and a chip. BACKGROUND
[0002] With the continuous development of electronic equipment and communication technology, people's demand for high-frequency and stable oscillation signals is getting higher and higher. In the field of wireless communication, a stable oscillation signal can be used as a local oscillator signal to modulate and demodulate signals for signal reception and transmission. In a large-scale digital circuit, a stable oscillation signal can be used as a clock signal to synchronize the generation and transmission of signals on a chip, and can also be used to synchronize signals between multiple chips to ensure accurate transmission and reception of data. A phase-locked loop can well track the frequency of an input signal and provide low phase noise due to the structure of its negative feedback loop, and is therefore widely used in the design of clock generators. Modern CMOS phase-locked loop circuits are small in size, low in power consumption, and produce small noise in oscillation signals, and are applied to large-scale digital integrated circuits and communication fields. Today, phase-locked loops have been widely used in communication, radar, computers, and navigation equipment. A phase-locked loop is an electronic circuit system that achieves signal phase synchronization through feedback control. Its core function is to adjust the phase of the output signal to keep it strictly synchronized with the input reference signal, thereby outputting an accurate and low-jitter oscillation signal. This characteristic makes the phase-locked loop one of the core technologies in the fields of modern communication, clock management, and frequency synthesis.
[0003] Although the traditional phase-locked loop circuit can provide a low-noise oscillation signal, it needs to be compromised between various design parameters, and has fatal defects. The frequency tracking range of the traditional phase-locked loop is small, and there is a steady-state error. These defects make it difficult to apply to high-performance integrated circuits, although it is widely used in the design of discrete devices.
[0004] Compared with the traditional phase-locked loop, the injection-locked phase-locked loop can provide a larger bandwidth and well suppress the phase noise of the voltage-controlled oscillator, ultimately providing a clock signal with lower phase noise. The injection-locked phase-locked loop periodically clears the jitter accumulated by the voltage-controlled oscillator at a fixed frequency by injecting pulses into the voltage-controlled oscillator, to obtain smaller phase noise. However, for a general injection-locked phase-locked loop, the injection efficiency is low, and it is difficult to provide a larger injection-locked bandwidth to suppress the out-of-band noise of the voltage-controlled oscillator. In addition, since the voltage-controlled oscillator is injection-locked by the reference signal, its own phase information is lost, and when the local oscillator frequency of the voltage-controlled oscillator deviates, the loop has difficulty in capturing the phase error, and the frequency correction of the voltage-controlled oscillator is hindered, resulting in a certain degree of deterioration of the phase noise of the output signal. SUMMARY
[0005] The present application aims at overcoming the above-mentioned defects of the prior art, and provides a double-edge injection-locked clock generator, an oscillation generation method and a chip, which can effectively improve injection efficiency and correct the frequency offset of a voltage-controlled oscillator local oscillator without adding extra devices.
[0006] To achieve the above-mentioned object, the present application adopts the following technical solutions: The double-edge injection-locked clock generator comprises a pulse generator, an injection-locked ring voltage-controlled oscillator, a phase detector, a charge pump and a low-pass filter. The injection-locked ring voltage-controlled oscillator comprises an injection end, a first injection enable end and a second injection enable end, the injection end of the injection-locked ring voltage-controlled oscillator is connected with a first output end of the pulse generator, the first injection enable end is connected with a second output end of the pulse generator, the second injection enable end is connected with a third output end of the pulse generator, and the injection-locked ring voltage-controlled oscillator generates an output signal. The first input end of the phase detector is connected with the output end of the injection-locked ring voltage-controlled oscillator, and the second input end of the phase detector is connected with a fifth output end of the pulse generator, and the phase detector generates a charging signal and a discharging signal. The first input end and the second input end of the charge pump are respectively connected with the first output end and the second output end of the phase detector. The input end of the low-pass filter is connected with the output end of the charge pump, and the output end of the low-pass filter is connected with a control end of the injection-locked ring voltage-controlled oscillator.
[0007] Preferably, the injection-locked ring voltage-controlled oscillator comprises a first reverse delay unit, a second reverse delay unit, a third reverse delay unit, a fourth reverse delay unit and a fifth reverse delay unit. The first injection enable end, the second injection enable end and the injection end of the first reverse delay unit are respectively connected with the first injection enable end, the second injection enable end and the injection end of the injection-locked ring voltage-controlled oscillator, the output end of the first reverse delay unit is connected with the input end of the second reverse delay unit, the output end of the second reverse delay unit is connected with the input end of the third reverse delay unit, the output end of the third reverse delay unit is connected with the input end of the fourth reverse delay unit, the output end of the fourth reverse delay unit is connected with the input end of the fifth reverse delay unit, and the output end of the fifth reverse delay unit is connected with the input end of the first reverse delay unit.
[0008] Preferably, the reverse delay unit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor. The gate end of the first MOS transistor is connected with the first injection enable end of the reverse delay unit, the source end is connected with a power supply, and the drain end is connected with the source end of the second MOS transistor. The gate end of the second MOS tube is connected with the gate end of the fifth MOS tube and the input end of the reverse delay unit, and the drain end is connected with the drain end of the fourth MOS tube, the drain end of the fifth MOS tube and the output end of the reverse delay unit; The gate end of the third MOS tube is connected with the ground, the source end is connected with the power supply, and the drain end is connected with the source end of the fourth MOS tube; The gate end of the fourth MOS tube is connected with the injection end of the reverse delay unit; The source end of the fifth MOS tube is connected with the drain end of the sixth MOS tube; The gate end of the sixth MOS tube is connected with the second injection enable end of the reverse delay unit, and the source end is connected with the ground.
[0009] Preferably, the pulse generator comprises a first buffer, a second buffer, a third buffer, a fourth buffer, a fifth buffer, a first inverter, a second inverter, a third inverter, a fourth inverter, a first AND gate, a second AND gate, a first NOR gate and a second NOR gate; The input end of the pulse generator is connected with the input end of the first buffer, the second input end of the second AND gate, the first input end of the first NOR gate and the input end of the fourth buffer; The output end of the first buffer is connected with the input end of the first inverter and the first input end of the first AND gate; The output end of the first inverter is connected with the second input end of the first AND gate and the input end of the second buffer, the output end of the first AND gate is connected with the input end of the second inverter, and the output end of the second inverter is the first output end of the pulse generator; The output end of the second AND gate is connected with the input end of the third buffer and the input end of the third inverter, the output end of the third buffer is the second output end of the pulse generator, and the output end of the third inverter is the third output end of the pulse generator; The output end of the fourth buffer is connected with the input end of the fourth inverter and the second input end of the second NOR gate; The output end of the fourth inverter is connected with the input end of the fifth buffer and the first input end of the second NOR gate, the output end of the fifth buffer is connected with the second input end of the first NOR gate, the output end of the first NOR gate is the fourth output end of the pulse generator, and the output end of the second NOR gate is the fifth output end of the pulse generator.
[0010] Preferably, the input signal buffer is further included, the input end of the input signal buffer receives a reference input signal, and the output end thereof is connected with the input end of the pulse generator.
[0011] An oscillation generation method of the double-edge injection-locked clock generator, comprising the following steps: The pulse generator receives a reference signal, and generates an injection pulse, a first injection enable signal and a second injection enable signal at the rising edge of the reference signal; The reverse delay units in the injection-locked ring voltage-controlled oscillator are enabled by the first injection enable signal and the second injection enable signal; The injection pulses generated by the pulse generator are injected into the enabled reverse delay units; The pulse generator generates the calibration pulse at the falling edge of the reference signal; The phase detector discriminates the phase error between the output signal of the injection-locked ring voltage-controlled oscillator and the calibration pulse, and generates the charging signal and the discharging signal; The charge pump and the low-pass filter generate the control voltage according to the charging signal and the discharging signal; The frequency of the injection-locked ring voltage-controlled oscillator is adjusted by the control voltage.
[0012] Preferably, the step of enabling the reverse delay units by the first injection enable signal and the second injection enable signal comprises: The charging and discharging paths in the reverse delay units are closed, and the charging path at the output end of the reverse delay units is dependent on the injection pulse.
[0013] Preferably, the step of generating the injection pulse, the first injection enable signal, the second injection enable signal and the calibration pulse by the pulse generator comprises: The reference signal is input into the first buffer and the second AND gate; The output signal of the first buffer and the output signal of the first inverter generate the injection pulse through the first AND gate and the second inverter; The output signal of the second AND gate generates the first injection enable signal and the second injection enable signal through the third buffer and the third inverter; The reference signal is input into the fourth buffer and the second NOR gate, and the output signal of the fourth buffer and the output signal of the fourth inverter generate the calibration pulse through the second NOR gate.
[0014] Preferably, before the step of receiving the reference signal by the pulse generator, the method further comprises: The duty cycle of the input reference signal is adjusted to 50% according to the input duty cycle adjustment word by the input signal buffer with adjustable duty cycle.
[0015] A chip comprising the double-edge injection-locked clock generator.
[0016] Compared with the prior art, the present application has the following beneficial effects: The application improves injection efficiency by using injection enable structure in the reverse delay unit in the ring voltage-controlled oscillator, effectively suppresses the in-band noise of the voltage-controlled oscillator, and further reduces the clock jitter of the clock generator; secondly, the frequency output can be provided in the range of 2.2 to 2.6 GHz by using the digital control capacitor array and the loop control voltage; finally, the generator uses double-edge injection locking technology, which can correct the frequency offset of the voltage-controlled oscillator without adding additional circuits. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1 It is a schematic diagram of the double-edge injection locking clock generator circuit structure of the application; Figure 2 It is a schematic diagram of the input signal buffer circuit with adjustable duty cycle in the application; Figure 3 It is a schematic diagram of the pulse generator circuit in the application; Figure 4 It is a schematic diagram of the circuit structure of the ring voltage-controlled oscillator in the application; Figure 5 It is a schematic diagram of the circuit structure of the ring voltage-controlled oscillator in the application; DETAILED DESCRIPTION The technical solutions of the application will be described in detail below with reference to the drawings and several specific embodiments. It should be pointed out that those skilled in the art can make equivalent replacements or reasonable modifications to the following embodiments based on the prior art knowledge without departing from the concept of the application, and such modifications and variations based on the essence of the application are all within the protection scope of the application. It should be understood that the embodiments described in the specification are only used to illustrate the principles and implementation methods of the application, and the protection scope of the application is subject to the claims.
[0018] The construction schematic and operation principle diagram of several exemplary embodiments of the application are shown in the drawings. It should be particularly noted that the element size ratio, relative position relationship and other elements presented in the drawings may not be drawn in equal proportion. Among them: in order to highlight the construction features of the key innovation part, the selected area may be locally enlarged; in order to clearly show the core working principle of the technical solution, the conventional structure not directly related to the invention point may be simplified. Those skilled in the art should understand that such diagram processing method is only a patent document expression habit, which does not affect the understanding of the essential technical content of the application, nor constitutes a limitation on the protection scope of the application.
[0019] The "includes", "contains" and their variants as used in the specification are meant to be within the scope of the patent law as an open transition, and its legal meaning should be interpreted as "including but not limited to", that is, allowing the existence of equivalent technical elements outside the description. Moreover, unless otherwise stated, the first, second and the like circuit numbers are only for the identification of the technical features, and do not constitute an absolute limitation on the order of steps. Under the premise of the same technical effect, the reasonable change or parallel implementation of the order of steps by those skilled in the art should be regarded as falling within the protection scope of the present application.
[0020] As shown in Figure 1 , the double-edge injection-locked clock generator based on high injection efficiency voltage-controlled oscillator described in the embodiment includes an adjustable duty cycle input signal buffer, a pulse generator, an injection-locked ring voltage-controlled oscillator, a phase detector, a charge pump and a low-pass filter.
[0021] The input end of the adjustable duty cycle input signal buffer is connected with a reference input signal, and the control end of the adjustable duty cycle input signal buffer is connected with an external duty cycle adjustment word; the input signal buffer adjusts the duty cycle of the reference input signal to 50% and increases its driving capacity according to the externally input duty cycle adjustment word; the pulse generator generates a pulse INJ after the rising edge of the reference input signal arrives and injects it into the ring voltage-controlled oscillator, and generates a correction signal V CAL and inputs it into the phase detector for providing a reference phase; the phase detector outputs a charging or discharging signal of the charge pump according to the phase difference of the two input signals; the low-pass filter converts the current signal of the charge pump into a voltage signal and performs filtering processing, and outputs a control voltage V fine , which adjusts the frequency of the voltage-controlled oscillator.
[0022] The input end of the pulse generator is connected with the output end of the input signal buffer, the first output end INJ of the pulse generator is connected with the injection end INJ of the injection-locked ring voltage-controlled oscillator, the second output end ENINJ and the third output end ENINJ b of the pulse generator are respectively connected with the first injection enable end ENINJ and the second injection enable end ENINJ b of the injection-locked ring voltage-controlled oscillator, the fourth output end ENPD of the pulse generator is connected with the enable end ENPD of the phase detector, and the fifth output end V CAL of the pulse generator is connected with the second input end of the phase detector; The phase discriminator is used to identify the phase error between the first input signal and the second input signal, and generates corresponding output signals UP and DN for adjusting the charging and discharging of the charge pump; the first output UP and the second output DN of the phase discriminator are connected with the first input and the second input of the charge pump respectively; the input of the low-pass filter is connected with the output of the charge pump, and the output of the low-pass filter is connected with the control end Vfine of the injection-locked ring voltage-controlled oscillator.
[0023] Reference Figure 2 The input signal buffer with adjustable duty cycle comprises a first inverter INV1, a second inverter INV2, a third inverter INV3, a NAND gate, first to seventh capacitors C BANK [6:0], first to seventh switches MN[6:0], a first MOS transistor MP1, a second MOS transistor MN1, and a fourth inverter INV4.
[0024] The input of the input signal buffer is connected with the input of the first inverter INV1, the output of the first inverter INV1 is connected with the input of the second inverter INV2, the upper plates of the first to fifth capacitors C BANK [4:0], the drain ends of the first to fifth switches MN[4:0] are respectively connected with the lower plates of the first to fifth capacitors C BANK [4:0], the gate ends of the first to fifth switches MN[4:0] are respectively connected with the duty cycle adjustment words [4:0] of the input signal buffer, the source ends of the first to fifth switches MN[4:0] are connected with the ground, the output of the second inverter INV2 is connected with the input of the third inverter INV3 and the first input of the NAND gate, the output of the third inverter INV3 is connected with the second input of the NAND gate, the upper plates of the sixth and seventh capacitors C BANK [6:5], the drain ends of the sixth and seventh switches MN[6:5] are respectively connected with the lower plates of the sixth and seventh capacitors C BANK [6:5], the gate ends of the sixth and seventh switches MN[6:5] are respectively connected with the duty cycle adjustment words [6:5] of the input signal buffer, the source ends of the sixth and seventh switches MN[6:5] are connected with the ground, the gate end of the first MOS transistor MP1 is connected with the output of the NAND gate, the source end is connected with the power supply, and the drain end is connected with the drain end of the second MOS transistor MN1 and the input of the fourth inverter INV4, the gate end of the second MOS transistor MN1 is connected with the input of the input signal buffer with adjustable duty cycle, the source end is connected with the ground, and the output of the fourth inverter INV4 is connected with the output of the input signal buffer with adjustable duty cycle.
[0025] Reference Figure 3, the pulse generator is used for generating a pulse INJ when the rising edge of the reference input signal comes, generating a correction signal V CAL , and generating a matching enable signal. The pulse generator comprises a first buffer BUF1, a second buffer BUF2, a third buffer BUF3, a fourth buffer BUF4, a fifth buffer BUF5, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first AND gate AND1, a second AND gate AND2, a first NOR gate NOR1, and a second NOR gate NOR2.
[0026] The input end of the pulse generator is connected with the input end of the first buffer BUF1, the second input end of the second AND gate AND2, the first input end of the first NOR gate NOR1, and the input end of the fourth buffer BUF4. The output end of the first buffer BUF1 is connected with the input end of the first inverter INV1 and the first input end of the first AND gate AND1. The output end of the first inverter INV1 is connected with the second input end of the first AND gate AND1 and the input end of the second buffer BUF2. The output end of the first AND gate AND1 is connected with the input end of the second inverter INV2. The output end of the second inverter INV2 is the first output end INJ of the pulse generator. The output end of the second AND gate AND2 is connected with the input end of the third buffer BUF3 and the input end of the third inverter INV3. The output end of the third buffer BUF3 is the second output end ENINJ of the pulse generator. The output end of the third inverter INV3 is the third output end ENINJ of the pulse generator b . The output end of the fourth buffer BUF4 is connected with the input end of the fourth inverter INV4 and the second input end of the second NOR gate NOR2. The output end of the fourth inverter INV4 is connected with the input end of the fifth buffer BUF5 and the first input end of the second NOR gate NOR2. The output end of the fifth buffer BUF5 is connected with the second input end of the first NOR gate NOR1. The output end of the first NOR gate NOR1 is the fourth output end ENPD of the pulse generator. The output end of the second NOR gate NOR2 is the fifth output end V CAL of the pulse generator.
[0027] Reference Figure 4 , the injection-locked ring voltage-controlled oscillator is used for providing an output signal, comprising a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, and a fifth inverter INV5. The output end V OUT of the injection-locked ring voltage-controlled oscillator is connected with the first input end of the phase detector.
[0028] The first injection enable end ENINJ of the first inverting delay unit INV1 is connected with the first injection enable end ENINJ of the ring voltage-controlled oscillator, the second injection enable end ENINJ of the first inverting delay unit INV1 is connected with the second injection enable end ENINJ of the ring voltage-controlled oscillator b The first injection enable end ENINJ of the ring voltage-controlled oscillator b The injection end INJ of the first inverting delay unit INV1 is connected with the injection end INJ of the ring voltage-controlled oscillator, the output end of the first inverting delay unit INV1 is connected with the input end of the second inverting delay unit INV2, the output end of the second inverting delay unit INV2 is connected with the input end of the third inverting delay unit INV3, the output end of the third inverting delay unit INV3 is connected with the input end of the fourth inverting delay unit INV4, the output end of the fourth inverting delay unit INV4 is connected with the input end of the fifth inverting delay unit INV5, the output end of the fifth inverting delay unit INV5 is connected with the input end of the first inverting delay unit INV1, the first injection enable end ENINJ of the second inverting delay unit INV2 is connected with the ground, the first injection enable end ENINJ of the third inverting delay unit INV3 is connected with the ground, the first injection enable end ENINJ of the fourth inverting delay unit INV4 is connected with the ground, the first injection enable end ENINJ of the fifth inverting delay unit INV5 is connected with the ground, the second injection enable end ENINJ b , the injection end INJ of the second inverting delay unit INV2 is connected with the power supply, the second injection enable end ENINJ b , the injection end INJ of the third inverting delay unit INV3 is connected with the power supply, the second injection enable end ENINJ b , the injection end INJ of the fourth inverting delay unit INV4 is connected with the power supply, the second injection enable end ENINJ b , the injection end INJ of the fifth inverting delay unit INV5 is connected with the power supply, the control word end of the first inverting delay unit INV1, the control word end of the second inverting delay unit INV2, the control word end of the third inverting delay unit INV3, the control word end of the fourth inverting delay unit INV4, the control word end of the fifth inverting delay unit INV5 are connected with the control word end BD[2:0] of the ring voltage-controlled oscillator, the control voltage end of the first inverting delay unit INV1, the control voltage end of the second inverting delay unit INV2, the control voltage end of the third inverting delay unit INV3, the control voltage end of the fourth inverting delay unit INV4, the control voltage end of the fifth inverting delay unit INV5 are connected with the control voltage end V fine of the ring voltage-controlled oscillator.
[0029] Reference Figure 5 The inverting delay unit comprises first to fourth MOS tubes MP1 to MP4, a fifth MOS tube MN1, a sixth MOS tube MN2, a varactor CVAR , the first capacitor C BANK [0], the second capacitor C BANK [1] The third capacitor C BANK [2], first switch SW[0], second switch SW[1], third switch SW[2].
[0030] Unlike conventional reverse delay cells, the one used in this invention includes an injection enable signal. Before the injection pulse arrives, the injection enable signal preemptively shuts down the charge and discharge paths of the reverse delay cell, making the output charging path completely dependent on the injection pulse. This structure significantly improves injection efficiency.
[0031] The gate terminal of the first MOS transistor MP1 is connected to the first injection enable terminal ENINJ of the reverse delay unit, the source terminal is connected to the power supply, and the drain terminal is connected to the source terminal of the second MOS transistor MP2. The gate terminal of the second MOS transistor MP2 is connected to the gate terminal of the fifth MOS transistor MN1 and the input terminal of the reverse delay unit, and the drain terminal is connected to the drain terminal of the fourth MOS transistor MP4, the drain terminal of the fifth MOS transistor MN1, and the varactor diode C. VAR The upper plate, the first to third capacitors C BANK The upper plate of [2:0] is connected to the output end of the reverse delay unit, the gate end of the third MOS transistor MP3 is connected to the ground, the source end is connected to the power supply, the drain end is connected to the source end of the fourth MOS transistor MP4, the gate end of the fourth MOS transistor MP4 is connected to the injection end INJ of the reverse delay unit, the source end of the fifth MOS transistor MN1 is connected to the drain end of the sixth MOS transistor MN2, and the gate end of the sixth MOS transistor MN2 is connected to the second injection enable end ENINJ of the reverse delay unit. b The source terminal is connected to the ground, and the control voltage terminal of the varactor diode is connected to the control voltage terminal V of the reverse delay unit. fine connected, the lower plate is connected to the ground, the first to third capacitors C BANK The lower plates of [2:0] are respectively connected to the upper plates of the first to third switches SW[2:0], and the lower plates of the first to third switches SW[2:0] are connected to the first, and their control signals are respectively connected to the band selection signal BD[2:0] of the reverse delay unit.
[0032] The dual-edge injection-locked clock generator based on a high-injection-efficiency voltage-controlled oscillator described in the present invention utilizes a digitally controlled capacitor array and a loop control voltage in the voltage-controlled oscillator to provide a frequency output of 2.2 to 2.6 GHz. The reverse delay unit in the ring voltage-controlled oscillator adopts an injection-enabled structure, which significantly improves the injection efficiency and effectively suppresses the in-band noise of the voltage-controlled oscillator, thereby reducing the clock jitter of the clock generator. The dual-edge injection locking technology is used to correct the local oscillator frequency offset of the voltage-controlled oscillator without adding additional circuitry.
[0033] The process of oscillation generation using the double-edge injection-locked clock generator of the present embodiment is as follows: Duty cycle correction: First, the external reference input signal is sent to the input signal buffer with adjustable duty cycle. According to the duty cycle of the reference signal at this time, the control word is adjusted to adjust the duty cycle of the reference input signal, and set it to be stable at 50%. The reference signal after duty cycle correction and enhancement of driving ability is output to the pulse generator.
[0034] Double-edge pulse generation: After the pulse generator receives the reference signal with a duty cycle of 50%, it will generate corresponding control pulses at the rising edge and falling edge of the signal.
[0035] Rising edge: At each rising edge of the reference signal, the pulse generator will generate a pulse signal as an injection pulse INJ, and also generate corresponding injection enable signals ENINJ and ENINJb for the subsequent injection locking process.
[0036] Falling edge: At each falling edge of the reference signal, the pulse generator will generate an adjustment pulse VCAL, and also generate a phase detector enable signal ENPD for the subsequent frequency adjustment process.
[0037] Injection locking and phase synchronization: When the injection pulse INJ arrives, the injection enable signals ENINJ and ENINJb generated by the pulse generator before the injection pulse will act on the first reverse delay unit of the injection-locked ring voltage-controlled oscillator VCO.
[0038] The enable signal will close the normal charging and discharging path inside the delay module, and the charging at the output end will be completely determined by the upcoming injection pulse. This design significantly improves the injection efficiency.
[0039] The injection pulse (INJ) is injected into this prepared delay unit to periodically clear the jitter accumulated by the voltage-controlled oscillator at a fixed frequency, achieving phase synchronization.
[0040] Frequency adjustment and feedback control: At the falling edge of the reference signal, the phase detector enable signal ENPD turns on the phase detector.
[0041] The phase detector receives the output signal VOUT of the voltage-controlled oscillator and the adjustment pulse VCAL generated by the pulse generator, and compares the phase difference between the two. According to the phase error, it generates corresponding UP or DN signals.
[0042] The charge pump works according to the charging and current signals, and its output current signal is converted into a smooth control voltage Vfine by a low-pass filter.
[0043] The voltage Vfine is input to an injection-locked ring voltage-controlled oscillator for adjusting the local oscillator frequency, thereby correcting frequency drift caused by factors such as process, temperature, etc., to complete closed-loop control of the entire phase-locked loop control.
[0044] The embodiment also provides a chip, which comprises the double-edge injection-locked clock generator described above.
[0045] The serial numbers of the embodiments of the present application are only for description, and do not represent the advantages or disadvantages of the embodiments.
[0046] In the above-described embodiments of the present application, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.
[0047] In the several embodiments provided by the present application, it should be understood that the disclosed technology can be implemented in other ways. Of course, the device embodiment described above is only schematic. For example, the division of the units can be a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection between the units can be indirect coupling or communication connection through some interface, electrical or other form.
[0048] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., they can be located in one place, or distributed on multiple units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiment.
[0049] The above description is only the preferred embodiment of the present application, and it should be pointed out that for those skilled in the art, without departing from the principle of the present application, some improvements and refinements can be made, which should also be considered as the protection scope of the present application.
[0050] It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and applications other than the examples provided would be apparent to those of skill in the art upon reading the above description. The scope of the application should be determined, not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are incorporated by reference for all purposes. The omission in the foregoing description of any aspect of the subject matter disclosed herein is not a disclaimer of such subject matter, nor should it be regarded that the applicant has disclaimed any such subject matter, nor should any such omission be regarded as affecting the scope of the disclosed innovations.
Claims
1. A dual-edge injection-locked clock generator, characterized in that: Includes a pulse generator, an injection-locked ring voltage-controlled oscillator, a phase detector, a charge pump, and a low-pass filter; The injection-locked ring voltage-controlled oscillator includes an injection terminal, a first injection-enable terminal, and a second injection-enable terminal. The injection terminal of the injection-locked ring voltage-controlled oscillator is connected to the first output terminal of the pulse generator, the first injection-enable terminal is connected to the second output terminal of the pulse generator, and the second injection-enable terminal is connected to the third output terminal of the pulse generator. The injection-locked ring voltage-controlled oscillator generates an output signal. The first input terminal of the phase detector is connected to the output terminal of the injection-locked ring voltage-controlled oscillator, and the second input terminal of the phase detector is connected to the fifth output terminal of the pulse generator. The phase detector generates a charging signal and a discharging signal; The first input terminal and the second input terminal of the charge pump are respectively connected to the first output terminal and the second output terminal of the phase detector; The input end of the low-pass filter is connected to the output end of the charge pump, and the output end of the low-pass filter is connected to the control end of the injection-locked ring voltage-controlled oscillator.
2. The dual-edge injection-locked clock generator according to claim 1, wherein: The injection-locked ring voltage-controlled oscillator includes a first reverse delay unit, a second reverse delay unit, a third reverse delay unit, a fourth reverse delay unit and a fifth reverse delay unit; The first injection enable terminal, the second injection enable terminal and the injection terminal of the first reverse delay unit are respectively connected to the first injection enable terminal, the second injection enable terminal and the injection terminal of the injection-locked ring voltage-controlled oscillator, the output terminal of the first reverse delay unit is connected to the input terminal of the second reverse delay unit, the output terminal of the second reverse delay unit is connected to the input terminal of the third reverse delay unit, the output terminal of the third reverse delay unit is connected to the input terminal of the fourth reverse delay unit, the output terminal of the fourth reverse delay unit is connected to the input terminal of the fifth reverse delay unit, and the output terminal of the fifth reverse delay unit is connected to the input terminal of the first reverse delay unit.
3. The dual-edge injection-locked clock generator according to claim 1, wherein: The reverse delay unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor; The gate terminal of the first MOS transistor is connected to the first injection enable terminal of the reverse delay unit, the source terminal is connected to the power supply, and the drain terminal is connected to the source terminal of the second MOS transistor; The gate end of the second MOS transistor is connected to the gate end of the fifth MOS transistor and the input end of the reverse delay unit, and the drain end is connected to the drain end of the fourth MOS transistor, the drain end of the fifth MOS transistor and the output end of the reverse delay unit; The gate terminal of the third MOS transistor is connected to the ground, the source terminal is connected to the power supply, and the drain terminal is connected to the source terminal of the fourth MOS transistor; The gate terminal of the fourth MOS tube is connected to the injection terminal of the reverse delay unit; The source end of the fifth MOS transistor is connected to the drain end of the sixth MOS transistor; The gate terminal of the sixth MOS transistor is connected to the second injection enable terminal of the reverse delay unit, and the source terminal is connected to the ground.
4. The dual-edge injection-locked clock generator according to claim 1, wherein: The pulse generator includes a first buffer, a second buffer, a third buffer, a fourth buffer, a fifth buffer, a first inverter, a second inverter, a third inverter, a fourth inverter, a first AND gate, a second AND gate, a first NOR gate and a second NOR gate; The input terminal of the pulse generator is connected to the input terminal of the first buffer, the second input terminal of the second AND gate, the first input terminal of the first NOR gate and the input terminal of the fourth buffer; The output terminal of the first buffer is connected to the input terminal of the first inverter and the first input terminal of the first AND gate; The output end of the first inverter is connected to the second input end of the first AND gate and the input end of the second buffer, the output end of the first AND gate is connected to the input end of the second inverter, and the output end of the second inverter is the first output end of the pulse generator; The output end of the second AND gate is connected to the input end of the third buffer and the input end of the third inverter, the output end of the third buffer is the second output end of the pulse generator, and the output end of the third inverter is the third output end of the pulse generator; The output terminal of the fourth buffer is connected to the input terminal of the fourth inverter and the second input terminal of the second NOR gate; The output end of the fourth inverter is connected to the input end of the fifth buffer and the first input end of the second NOR gate, the output end of the fifth buffer is connected to the second input end of the first NOR gate, the output end of the first NOR gate is the fourth output end of the pulse generator, and the output end of the second NOR gate is the fifth output end of the pulse generator.
5. The dual-edge injection-locked clock generator according to claim 1, wherein: The device also includes an input signal buffer, wherein the input end of the input signal buffer receives a reference input signal, and the output end of the input signal buffer is connected to the input end of the pulse generator.
6. An oscillation generating method based on the dual-edge injection locked clock generator according to any one of claims 1 to 5, characterized in that: The following steps are involved: The pulse generator receives a reference signal and generates an injection pulse, a first injection enable signal and a second injection enable signal at a rising edge of the reference signal; The reverse delay unit in the injection-locked ring voltage-controlled oscillator is enabled by the first injection enable signal and the second injection enable signal; The injection pulse generated by the pulse generator is injected into the enabled reverse delay unit; The pulse generator generates a calibration pulse at the falling edge of the reference signal; The phase detector identifies the phase error between the output signal of the injection-locked ring voltage-controlled oscillator and the calibration pulse, and generates a charging signal and a discharging signal; The charge pump and the low-pass filter generate a control voltage according to the charging signal and the discharging signal; The frequency of the injection-locked ring voltage-controlled oscillator is adjusted by controlling the voltage.
7. The oscillation generating method according to claim 6, characterized in that: The steps of enabling the reverse delay unit by the first injection enable signal and the second injection enable signal include: The charge and discharge path in the reverse delay unit is closed, so that the charging path of the output end of the reverse delay unit depends on the injected pulse.
8. The oscillation generating method according to claim 6, characterized in that: The steps of the pulse generator generating the injection pulse, the first injection enable signal, the second injection enable signal and the calibration pulse include: inputting a reference signal into the first buffer and the second AND gate; The output signal of the first buffer and the output signal of the first inverter are combined to generate an injection pulse through a first AND gate and a second inverter; The output signal of the second AND gate generates a first injection enable signal and a second injection enable signal through a third buffer and a third inverter; The reference signal is input to the fourth buffer and the second NOR gate, and the output signal of the fourth buffer and the output signal of the fourth inverter are combined to generate a calibration pulse through the second NOR gate.
9. The oscillation generating method according to claim 6, characterized in that: Before the step of the pulse generator receiving the reference signal, the method further includes: The duty cycle of the reference input signal is adjusted to 50% by the input signal buffer with adjustable duty cycle according to the input duty cycle adjustment word.
10. A chip, characterized in that: A dual-edge injection locked clock generator comprising any one of claims 1-5.