A device and method for dynamic allocation of shared cache quota for a switch chip

Abstract

The application belongs to the field of switching chips, and relates to a device and a method for dynamically allocating a shared cache quota of a switching chip. The device comprises a rate difference index calculator, a burst index calculator, a back pressure index calculator, a quota index calculator and a quota calculator. The application monitors the characteristics of data flow from multiple dimensions, better absorbs burst flow, adapts to the difference between the sending and receiving rates, and takes into account the waiting time of input data. The application can dynamically and adaptively adjust the shared cache quota in real time, and the weight of each source port given by the arbitrator of the destination also changes in linkage with the shared cache quota, which overall takes into account fairness and improves efficiency. Compared with the traditional dynamic shared cache method, the application can solve the situation that some paths occupy a large or all shared cache under unreasonable conditions, and make other paths have no or only a small amount of cache available.

Description

TECHNICAL FIELD

[0001] The application relates to a device and a method for dynamically allocating a shared cache quota of a switch chip. BACKGROUND

[0002] Switch chips are used to connect various computers and devices and realize data communication therebetween. Common switches include PCIe (Peripheral Component Interconnect express, a high-speed serial bus interface) switches and Ethernet switches, which implement different protocols but have a common characteristic of having multiple input and output ports and forwarding input data to corresponding output ports according to requirements.

[0003] The core architecture of a switch chip is to use an input / output interface part to process protocols of a physical layer and a data link layer, temporarily store received input data in an input data cache, and then find a routing table established in the switch chip according to corresponding field descriptions in the input data, send the input data to a corresponding output port through a crossbar inside the switch chip, and in the output port, if there are multiple input data sources, generally, an arbiter receives input data in turns according to certain preset rules, thereby completing data switching.

[0004] For convenience of description, Pm->Pn is used to represent that data is sent from a port Pm to a port Pn, for example, P0->P1 represents that data is sent from a port P0 to a port P1.

[0005] The data cache in the switch chip plays a very key role in the performance of the switch chip. It can absorb burst traffic and avoid packet discard, and can smooth the output rate and distribute uneven requests on the time axis to reduce the probability of link congestion. Generally, the larger the cache is, the better the performance of the switch chip is.

[0006] Since the cache of the switch chip occupies a large chip area and has a high cost, reasonable and effective use of the cache is an important link in designing the switch chip.

[0007] In addition, the cache of the switch chip is usually used in a FIFO (First In First Out, a data organization method for reading and writing data in a memory) form, that is, data packets written first are read out first.

[0008] Problems and defects of the prior art:

[0009] Figure 1is a case of sharing the cache of the input end in the exchange chip, P0->P1, P0->P2, P0->P3 share a data cache, the advantage is simple design, in the case of not high concurrent requirements, can be used. Once the concurrent request is generated on the network, port P0 needs to send data to port P1, port P2 and port P3 at the same time, at this time, the head blocking (HoL) problem will be generated, as shown in Figure 1 , the data of P0->P1 is arranged at the head of the cache, but the device connected to the receiving end P1 cannot take away the data in time due to reasons, which will cause the data of P0->P2 and P0->P3 cannot be sent, that is, the receiving rate of the device of a certain port is slow, which will affect the receiving rate of the device of other ports.

[0010] To solve the head blocking problem, one solution is to configure the number of caches according to the number of receiving ports, for example, P0->P1, P0->P2, P0->P3 each occupies a cache separately, so that the performance of each port will not affect each other. The scheme of configuring a data cache for each output port, although solves the mutual blocking problem, but since each cache is independent of each other, when one cache is used, other caches may not be used at the same time, thus causing the overall cache utilization rate is not high.

[0011] To solve the problem of separate cache utilization, shared cache can be used, that is, the same physical cache is still used, but according to the number of destination ports, the cache is divided into corresponding number of areas, each data channel from the input port to different destination ports occupies a certain cache quota, for example, P0->P1, P0->P2, P0->P3 each occupies a part of the same physical cache. The advantage of this is that when the cache of a channel is not used, this part of the cache can be used by other channels, thereby improving the overall efficiency and economy.

[0012] In the use of shared cache, how each channel gets its own quota is a key. The simplest method is to set some registers, and users divide the shared cache quota by configuring these registers, but such division is static, while the actual network data flow changes in real time, so this static division method has low applicability.

[0013] There are mainly two ways to dynamically divide the shared cache:

[0014] The first mode is that each channel can occupy the buffer as long as there is input data, that is, first come first served. This mode is relatively simple to implement, and the entire buffer shares a back pressure signal. However, this first come first served shared buffer mode also has limitations. For example, if the data input by a channel is not transmitted in time, the data of the channel will occupy the entire buffer, causing other channels to be unable to transmit and receive data, thereby causing congestion. For example, if the receiving end P1 does not receive data in time, the data of P0->P1 will occupy the entire buffer, and the sending end P0 will receive a back pressure signal, and P0->P2 and P0->P3 cannot transmit and receive data.

[0015] Therefore, the second mode of allocating a shared buffer is to reserve a minimum value (that is, a static minimum quota) for each channel, and then use the first come first served mode for the remaining part of the buffer (that is, the dynamic shared buffer), as shown in Figure 2 This mode can avoid the congestion caused by the use of the entire buffer by a channel, but for the shared part, the first come first served mode is still used, which still has many limitations. For example, P0->P1 has a continuous sending quantity flow characteristic, but due to the fast sending rate of port P0 and the slow receiving rate of port P1, P0->P1 occupies the shared part of the buffer for a long time, while P0->P2 or P0->P3 has an intermittent burst flow characteristic, and such burst flow needs more buffer to absorb, but the shared part of the buffer is occupied by other slow receiving data, and the burst flow that should use more buffer can only use a minimum quota, resulting in reduced efficiency.

[0016] In addition, the arbitrator in the existing switch chip uses the round robin (RR) or weighted round robin (WRR) mode, which cannot be linked in real time with the use of the shared buffer, which may cause some buffer channels to have a high occupancy rate for a long time and cannot be emptied in time, thereby affecting the overall efficiency.

[0017] Based on this, the present application is proposed. SUMMARY

[0018] The present application provides a dynamic allocation device and method for a shared buffer quota of a switch chip, and the specific technical solutions are as follows:

[0019] A dynamic allocation device for a shared buffer quota of a switch chip, comprising:

[0020] A rate difference index calculator calculates a rate difference index according to the rate difference between the data input end and the output end;

[0021] A burst index calculator calculates a burst index by counting the number of data packets continuously received by the switch chip within a unit time granularity, and the burst index is used to represent the intensity of data input.

[0022] The back pressure index calculator calculates the back pressure index by measuring the duration of the back pressure signal.

[0023] The quota index calculator calculates the weighted sum of the rate difference index, burst index, and backpressure index to obtain the quota index of the shared buffer for each channel within the switching chip.

[0024] The quota calculator calculates the shared buffer quota for each channel within the switching chip.

[0025] A further improvement is made by setting a data packet counter at both the data input and output ends of the switching chip;

[0026] The maximum data transfer rate of the switching chip is V M The data input rate is V I The data output rate is V O ;

[0027] When V O ≥ V I At that time, the rate difference index I V =0;

[0028] When V O < V I At that time, the rate difference index .

[0029] Further improvements include using I to represent the suddenness index. B express;

[0030] ;

[0031] The maximum number of data packets received per unit time is B M The actual number received is recorded as B. I .

[0032] A further improvement is made by using I as the back pressure index. H express,

[0033] ;

[0034] The statistical time granularity is T M The effective duration of the reverse voltage signal during this period is T. H .

[0035] A further improvement is made: the quota index of the shared buffer for each channel within the switching chip is I. M ;

[0036] ;

[0037] wherein k V , k B , k H are weighting coefficients.

[0038] Further improvement, the shared cache quota M D obtained by each channel in the switch chip is:

[0039] ;

[0040] wherein i is the number of the channel, I Mi denotes the quota index of the i-th channel;

[0041] The shared cache quota is added to the minimum cache reserved for each channel.

[0042] The total cache capacity dynamically available for each channel in the switch chip is M T :

[0043] M T = M m + M D ;

[0044] M m is the minimum cache reserved for each channel in the switch chip.

[0045] On the other hand, a dynamic allocation method of shared cache quota of a switch chip is provided, wherein a minimum cache quota is reserved for each channel in the switch chip, and the remaining part is dynamically allocated by the dynamic allocation device of shared cache quota of a switch chip.

[0046] Further improvement, the weight W given by the arbiter in the switch chip to each source port is calculated as:

[0047] ;

[0048] a is a coefficient.

[0049] Further improvement, in the switch chip, the total number of ports is n+1, the shared cache is divided into n parts, and the cache quota M L available for dynamic allocation is:

[0050] M L = M T - M m (n-1).

[0051] Advantages of the present application:

[0052] 1. The present application monitors the characteristics of data flow from multiple dimensions, better absorbs burst traffic, adapts to the difference between sending and receiving rates, and takes into account the waiting time of input data.

[0053] 2、The application can dynamically adjust the shared cache quota in real time, and the weight of the arbitrator of the destination end for each source port also changes in linkage with the shared cache quota, which generally takes into account fairness and improves efficiency.

[0054] 3、Compared with the traditional dynamic shared cache method, it can solve the problem that some paths occupy a large or all shared cache in unreasonable cases (for example, only the receiving rate is slow), while other paths have no or only a small amount of cache available. BRIEF DESCRIPTION OF DRAWINGS

[0055] Figure 1 Schematic diagram of head blocking of a switch chip;

[0056] Figure 2 Schematic diagram of dynamic adaptive shared cache of a switch chip;

[0057] Figure 3 Dynamic adaptive shared cache and arbitrator weight linkage of a switch chip. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the application clearer and more apparent, the application will be further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the application and do not limit the application.

[0059] Example 1

[0060] The technical problem to be solved by the application is:

[0061] The allocation of shared cache for input data in a switch chip, whether it is first-come-first-served overall or reserving a minimum value for each channel and then using first-come-first-served for the remaining cache, although the implementation algorithm is simple, does not reflect efficiency and fairness. For example, slow data traffic occupies the shared cache, while burst traffic that really needs more cache cannot get more cache. The essential feature of this implementation is that the allocation of shared cache is not based on the specific characteristics of data traffic. Therefore, the application proposes an algorithm that dynamically allocates shared cache based on the characteristics of data traffic, i.e. the shared cache quota obtained by each channel can be dynamically adjusted in real time based on its traffic characteristics and the traffic characteristics of other channels, thus reflecting fairness and improving efficiency.

[0062] As shown in Figure 3 , the weight of the arbitrator is no longer a static fixed value, and the weight can be linked with the shared cache quota for real-time adaptive dynamic adjustment.

[0063] For example, for the output port P0, the shared buffer obtained by P1->P0, P2->P0, P3->P0 is 3kB, 2kB, 1kB, and the weights of the arbitrator 0 to the ports P1, P2 and P3 can be set as 3, 2 and 1 respectively, that is, the port P0 can receive 3, 2 and 1 data packets from the ports P1, P2 and P3 respectively in each round of receiving data, so that more data in the shared buffer with larger quota can also be forwarded in time. The specific weight values are calculated in the following.

[0064] The application provides a device for dynamically allocating shared buffer quotas of a switching chip, which comprises a rate difference index calculator, a burst index calculator, a back pressure index calculator, a quota index calculator and a quota calculator.

[0065] The rate difference index calculator calculates the rate difference index according to the rate difference between the data input end and the output end. The rate difference index calculator is implemented as follows: a data packet counter is arranged at each of the data input end and the output end of the switching chip. Due to the data buffering, the input rate of data can be different from the output rate within a certain time granularity. If the input rate is greater than the output rate, the rate difference index is positive, indicating that the data channel can increase the shared buffer quota, and the value can be zero.

[0066] The burst index is used to represent the intensity of data input. The burst index calculator is implemented by counting the number of data packets continuously received by the switching chip within a unit time granularity. The higher the burst index, the more shared buffer quota the data channel can enjoy.

[0067] The back pressure index calculator: when the shared buffer of a channel in the switching chip is full, the input end of the channel receives a back pressure signal, indicating that no data is received. The back pressure index calculator obtains the back pressure index by calculating the duration of the back pressure signal.

[0068] The quota index calculator: the rate difference index, the burst index and the back pressure index are weighted and summed, that is, each index is multiplied by the corresponding coefficient and then summed to obtain the quota index of the shared buffer of each channel.

[0069] The final shared buffer quota obtained by each channel is obtained by the quota calculator.

[0070] The shared buffer quota is linked to the weight of the arbitrator at the receiving end: the weight of the arbitrator at the receiving end to different source ports is linked to the shared buffer quota from the source port to the destination port; the greater the shared buffer, the greater the weight, so that the data exchange can be more effectively completed.

[0071] The specific method is as follows:

[0072] 1. Minimum quota reservation

[0073] To avoid the situation that the whole shared cache is used up by some channels and other channels have no cache available, the minimum cache reserved for each channel in the switch chip is reserved and the remaining part is dynamically allocated by the dynamic allocation device of the shared cache quota of the switch chip according to the following method:

[0074] Let the total cache capacity be M T and the total number of ports be n+1, the shared cache is divided into n parts, and the minimum cache reserved for each channel is M m , then the cache quota M L available for dynamic allocation is:

[0075] M L = M T - M m (n-1);

[0076] 2. Rate difference index calculator

[0077] A data packet counter is arranged at the data input end and the output end of the switch chip. Due to the data cache, the input rate of data can be different from the output rate of data within a certain time granularity.

[0078] If the input rate of data is greater than the output rate of data, the rate difference index is positive, indicating that the shared cache quota of the data channel can be increased; otherwise, the value can be zero.

[0079] Let the maximum data transmission rate of the switch chip be V M , the input rate of data be V I , and the output rate of data be V O .

[0080] When V O ≥ V I , the rate difference index I V is 0.

[0081] When V O < V I , the rate difference index I .

[0082] The final value of the rate difference index I V is an integer between 0 and 10.

[0083] 2. Burst index calculator

[0084] The burst index is used to represent the intensity of data input. The implementation is the number of data packets received by the statistical switch chip in a unit of time, compared with the theoretically maximum number of received data packets. The higher the burst index, the more shared cache quota the data channel can enjoy. The maximum number of data packets received in a unit of time is denoted as B M , and the actual number of received data packets is denoted as B I . The burst index I B is:

[0085] ;

[0086] The final value of the burst index I B is an integer between 0 and 10.

[0087] 3. Backpressure index calculator

[0088] When the shared cache of a certain channel in the switch chip is full, the input end of the channel will receive a valid backpressure signal, indicating that no more data will be received. The backpressure index calculator obtains the backpressure index by calculating the duration of the backpressure signal. The higher the index, the longer the waiting time of the input data of the channel, and the larger the shared cache quota needs to be. The statistical time granularity is denoted as T M , and the duration of the valid backpressure signal during this period is denoted as T H . The backpressure index I H is:

[0089] ;

[0090] The final value of the backpressure index I H is an integer between 0 and 10.

[0091] 4. Quota index calculator

[0092] The quota index calculator performs a weighted sum of the above rate difference index, burst index, and backpressure index, i.e., each index is multiplied by the corresponding coefficient and then summed to obtain the quota index of the shared cache of each channel. The quota index I M of the shared cache of each channel in the switch chip is calculated as:

[0093] ;

[0094] wherein k V , k B , and k H are weighting coefficients, and the default value is 1. The values can be configured through software, and setting them to a value greater than or less than 1 can increase or decrease the proportion of the corresponding index in the final index quota. For example, setting k B to 2 can increase the cache capacity of the channel for burst data.

[0095] 5. Quota calculator

[0096] M is the final shared cache quota obtained by each channel in the switch chip D M = M

[0097] ;

[0098] Where i is the number of the channel, I Mi Ii represents the quota index of the ith channel, for example, I M2 I2 represents the quota index of the 2nd channel. The above summation formula means adding up the quota indexes I M of all channels.

[0099] The shared cache quota plus the minimum cache M m reserved for each channel, i.e. M T , is the total cache capacity dynamically available for each channel in the switch chip T :

[0100] M m = M D ;

[0101] 6. Linkage of shared cache quota and weight of arbiter at receiving end

[0102] The weight given by the arbiter to each source port is no longer statically configured, but is linked according to the shared cache quota obtained by each source port, and the source port obtaining a higher cache quota is given a higher weight. The weight W of each source port is calculated as:

[0103] ;

[0104] The original weight of each channel is by default 1, and the new weight reflects the size of the dynamically shared cache, and the calculation is an integer, realizing the linkage of cache and weight; the coefficient a is by default 1, and can also be configured by software according to actual needs.

[0105] 7. Adjustable statistical time granularity

[0106] The calculation of each index and quota above is performed within a preset time granularity. The size of the time granularity can be adjusted; the smaller the time granularity, the more timely the changes in cache quota adjustment, but the fluctuations of each index can be larger. The specific time granularity can be adjusted according to actual conditions. For example, when it is necessary to respond to changes in data flow as soon as possible, the time granularity can be set to 1uS (microsecond), and when it is necessary to adjust more smoothly, it can be set to several hundred uS or even mS (millisecond) level.

[0107] The above merely describes preferred embodiments of the present application, and is not used to limit the present application, any modification, equivalent replacement and improvement within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A dynamic allocation device for shared cache quotas of a switching chip, characterized in that, The application relates to a dynamic allocation device for shared buffer quota of a switching chip. The rate difference index calculator calculates the rate difference index according to the rate difference between the data input end and the output end; The burst index calculator calculates the burst index by counting the number of data packets continuously received by the switching chip in a unit time; The back pressure index calculator calculates the back pressure index by calculating the time length of the back pressure signal; The quota index calculator calculates the quota index of the shared buffer of each channel in the switching chip by weighting and summing the rate difference index, the burst index and the back pressure index; The quota calculator calculates the shared buffer quota obtained by each channel in the switching chip.

2. The apparatus for dynamic allocation of shared cache quota of a switch chip according to claim 1, wherein: The implementation of the rate difference index calculator is realized by arranging a data packet counter at the data input end and the output end of the switching chip; The maximum data transfer rate of the switch chip is V M , the input rate of data is V I , and the output rate of data is V O ; When V O ≥ V I , the rate difference index I V is 0; When V O < V I the rate difference index .

3. The apparatus of claim 2, wherein: The burst index is expressed by I B ; ； The maximum number of data packets received per unit of time is B M , the actual number of received data packets is B I .

4. The apparatus of claim 3, wherein: The inverse pressure exponent is denoted by I H , ； The statistical time granularity is T M , and the duration of the back pressure signal is T H .

5. The apparatus of claim 4, wherein: The quota index of the shared cache of each channel in the switch chip is I M ; ； wherein k V , k B , k H are weighting coefficients.

6. The apparatus of claim 5, wherein: a shared cache quota M obtained by each channel in the switch chip D is: ； where i is the number of the channel, I Mi denotes the quota index of the i-th channel; The shared buffer quota is added to the minimum buffer reserved for each channel The total cache capacity dynamically available at the end of each lane within the switch chip is M T : M T = M m + M D ; M m The minimum cache reserved for each lane within the exchange chip.

7. A method for dynamically allocating shared cache quotas for switching chips, characterized in that: A minimum buffer quota is reserved for each channel in the switching chip, and the remaining part is dynamically allocated by the dynamic allocation device for shared buffer quota of the switching chip according to any one of claims 1-6.

8. The method of claim 7, wherein: The arbitration device in the switching chip gives each source port a weight W, and the calculation method is as follows: ； a is a coefficient.

9. The method of claim 7, wherein: In the switch chip, the total number of ports is n+1, and the shared cache is divided into n parts, and the cache quota M available for dynamic allocation L is: M L = M T - M m (n-1).

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