Preparation method of novel nonvolatile memory based on RRAM + FCM structure

Abstract

The invention provides a preparation method of a novel nonvolatile memory based on an RRAM + FCM structure. The preparation method of the novel nonvolatile memory comprises the following steps: generating a SiO2 layer on a substrate through passivation, depositing an amorphous HZO layer on the SiO2 layer, and converting the amorphous HZO layer into ferroelectric phase HZO through thermal annealing; a metal layer is generated on the ferroelectric layer through sputtering, a resistive layer is deposited on the metal layer, and TaTiN metal is sputtered to form a top electrode; forming a gate pattern window through photoetching; and after ion implantation is carried out on the junction region, annealing is carried out, a layer of SiO2 is grown, a bottom electrode window is formed through photoetching, and a bottom electrode is formed through sputtering. According to the memory formed by the preparation method of the novel nonvolatile memory based on the RRAM + FCM structure, the FCM structure and the RRAM structure are connected in series, and the defects of a traditional ferroelectric capacitance memory are overcome by utilizing the advantages of high writing speed, high durability, low power consumption, high storage density, a new storage mechanism and the like of the FCM structure and the RRAM structure; a solid foundation is laid for related storage technologies; and full preparation is made for realizing industrialization.

Description

TECHNICAL FIELD

[0001] The application provides a preparation method of a new type of nonvolatile memory based on an RRAM+FCM structure, and belongs to the technical field of device preparation. BACKGROUND

[0002] The FCM has excellent application potential in real-time data evidence and high-frequency writing scenes such as automobile safety systems and industrial control due to the nanosecond-level writing speed, ultra-low power consumption and ultra-high durability. The RRAM becomes a core carrier for breaking through the storage density bottleneck and the integrated hardware of storage and calculation by virtue of the simplified metal-insulator-metal (MIM) structure, the theoretically unlimited stacking ability and the 4F² unit size. Both of them are faced with the key challenges of industrialization: the FCM is limited by the insufficient device switching ratio, and is easy to cause data storage errors in high-density storage; the RRAM is still a difficult problem for high-yield mass production due to the resistance randomness, operation voltage fluctuation and selector integration problem. The current RRAM is in the parallel stage of technical breakthrough and scene landing: it mainly focuses on data center storage class memory (SCM) and neuromorphic computing acceleration. The FCM has not realized industrial application at present. SUMMARY

[0003] The application provides a preparation method of a new type of nonvolatile memory based on an RRAM+FCM structure, which solves the technical problems in the prior art. The technical scheme adopted is as follows: the preparation method of the new type of nonvolatile memory based on the CM structure solves the technical problems in the prior art, and the technical scheme adopted is as follows: The preparation method of the new type of nonvolatile memory based on the RRAM+FCM structure comprises the following steps: An SiO2 layer is generated on a substrate, and an amorphous HZO layer is deposited on the SiO2 and is converted into a ferroelectric phase HZO through thermal annealing, comprising the following steps: The Si substrate is cleaned by using an RCA cleaning process; A heat accumulation type thermal incinerator is used to passivate the SiO2 layer on the surface of the Si substrate; An atomic deposition method is used to deposit an amorphous HZO layer on the SiO2 layer; The amorphous HZO layer on the SiO2 layer is formed into a ferroelectric phase HZO by using a thermal annealing method at 300-600 DEG C in a nitrogen N2 atmosphere.

[0004] Further, the thickness of the SiO2 layer ranges from 1 to 3 nm.

[0005] Further, the heat accumulating thermal incinerator adopts a preset temperature control strategy to passivate a SiO2 layer on the surface of the Si substrate; wherein, the temperature control strategy comprises a preheating stage, a first ladder oxidation stage, a pulse high temperature stage, a second ladder oxidation stage and a cooling stage.

[0006] Further, the target temperature corresponding to the preheating stage is 400℃; the target temperature corresponding to the first ladder oxidation stage is 560℃; the target temperature corresponding to the pulse high temperature stage is 800℃ and 650℃; and the target temperature corresponding to the cooling stage is 25℃.

[0007] Further, the temperature control strategy corresponding to the SiO2 layer is as follows: Preheating stage: from room temperature 25℃ to 400℃ at a rate not less than 18℃ / min, and keep the temperature at 400℃ for 10 min.

[0008] First ladder oxidation stage: increase the temperature to 560℃ at a first temperature gradient, keep the temperature at 560℃ for 15 min, and gradually perform passivation generation reaction at the temperature of 560℃; Pulse high temperature stage: rapidly increase the temperature to 800℃ within 1 min, maintain the temperature for 30 s, then decrease the temperature to 650℃ within 2 min, maintain the temperature for 15 s, and repeat the temperature control process for 3 times; Second ladder oxidation stage: keep the temperature at 650℃ for 18 min; Cooling stage: decrease the temperature to room temperature 25℃ at a second temperature gradient.

[0009] Further, the first temperature gradient is obtained by the following formula: T 01 =[1+norm((D m ×K) / (G0×t 01 ))]×T a Wherein, T 01 represents the first temperature gradient; D m represents the target thickness of the SiO2 layer; K represents the effective heat capacity of the circulating gas in the heat accumulating thermal incinerator; G0 represents the initial oxygen adsorption amount on the surface of the Si substrate, which is obtained by XPS detection in the pre-treatment stage; t 01 represents the maximum allowed temperature increasing time corresponding to the first ladder oxidation stage; T a represents the preset initial temperature increasing gradient; norm() represents the normalization processing of the physical quantity in the parentheses.

[0010] Further, the second temperature gradient is obtained by the following formula: T02 = [1 + norm ((Ds + J) / (alpha * t02)) ] * Tb Wherein, T 02 represents the second temperature gradient; D s represents the actual growth thickness of the SiO2 layer after the pulse high-temperature stage; J represents the heat loss coefficient of the heat accumulating type thermal incinerator; alpha represents the difference between the thermal expansion coefficients of the Si substrate and the SiO2 film; t 02 represents the maximum allowed cooling time; T b represents the preset initial cooling gradient; norm () represents the normalization processing of the physical quantity in the parentheses.

[0011] Further, a metal layer is sputtered on the ferroelectric phase, a resistive layer is deposited on the metal layer, a metal layer is deposited on the resistive layer and a gate pattern window is formed by photolithography, comprising: Pt metal is sputtered on the ferroelectric layer by physical vapor deposition to form a gate metal layer; TaO2 resistive layer is deposited on the metal layer by atomic deposition; TaTiN metal is sputtered on the TaO2 resistive layer by physical vapor deposition; The gate pattern window is formed by photolithography to define the junction region and etch the excess material.

[0012] Further, TiN metal is sputtered in the bottom electrode window, comprising: Ion implantation is performed in the junction region to form a heavily doped junction region, and then rapid annealing is performed to activate the doped ions in the junction region; A layer of SiO2 is grown on the surface of the TaTiN metal and the exposed Si layer, a bottom electrode window is formed by photolithography, TiN metal is sputtered by physical vapor deposition, and then the photoresist and SiO2 are removed.

[0013] The present application has the following advantages: The memory formed by the preparation method of the novel nonvolatile memory based on the RRAM+FCM structure aims at the shortage of the traditional ferroelectric capacitor memory technology, and improves the discrimination of different storage states by proposing a novel device structure.

[0014] The memory formed by the preparation method of the novel nonvolatile memory based on the RRAM+FCM structure adopts the series connection of the FCM and the RRAM structure, utilizes the advantages of high write speed, high durability, low power consumption, high storage density and new storage mechanism of the two to make up for the shortage of the traditional ferroelectric capacitor memory, lays a solid foundation for the related storage technology, and makes full preparation for industrialization. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is a RRAM-FCM device process flow chart.

[0016] Figure 2 It is a schematic view after the Si substrate is cleaned.

[0017] Figure 3 It is a schematic view of growing an oxide passivation layer on the Si substrate.

[0018] Figure 4 It is a schematic view of growing HZO material on the passivation layer and forming a ferroelectric phase after annealing.

[0019] Figure 5 It is a schematic view of growing a gate electrode on the FCM ferroelectric dielectric layer.

[0020] Figure 6 It is a schematic view of depositing a RRAM resistive switching dielectric layer on the gate electrode.

[0021] Figure 7 It is a schematic view of preparing a RRAM top electrode.

[0022] Figure 8 It is a schematic view of patterning after photolithography.

[0023] Figure 9 It is a schematic view of ion implantation and thermal annealing of the junction region after patterning.

[0024] Figure 10 Schematic diagram for growing bottom electrode above junction region. DETAILED DESCRIPTION

[0025] The preferred embodiments of the present application will be described below in conjunction with the accompanying drawings, it should be understood that the preferred embodiments described herein are only used to explain and illustrate the present application, and are not used to limit the present application.

[0026] Embodiment 1

[0027] The preparation method of the new non-volatile memory based on the RRAM+FCM structure comprises: Generating a SiO2 layer on a substrate, and depositing an amorphous HZO layer on the SiO2 and converting into a ferroelectric phase HZO by thermal annealing; Sputtering a metal layer on the ferroelectric layer, depositing a resistive switching layer on the metal layer, sputtering a layer of metal on the resistive switching layer, and forming a gate pattern window by photolithography; After ion implantation in the junction region and annealing; Growing a layer of SiO2 above the device, photolithography to form a bottom electrode window, and sputtering metal to form a bottom electrode.

[0028] Specifically, generating a SiO2 layer on a substrate, and depositing an amorphous HZO layer on the SiO2 and converting into a ferroelectric phase HZO by thermal annealing, comprises: S1, using RCA cleaning process to clean the Si substrate (100), as shown in Figure 2 ; S2, using a regenerative thermal oxidizer (RTO) to generate a SiO2 layer (101) on the surface of the Si substrate (100); wherein the thickness of the SiO2 layer (101) ranges from 1-3nm. The SiO2 layer (101) has the functions of preventing diffusion contamination between the ferroelectric layer and the Si substrate and serving as a photolithographic patterning sacrificial layer, as shown in Figure 3 .

[0029] S3, using atomic deposition method (ALD) to deposit an amorphous HZO layer on the SiO2 layer (101); using rapid thermal annealing (RTA) at 300-600℃ in a nitrogen N2 atmosphere to form a ferroelectric phase (102) on the amorphous HZO layer of the SiO2 layer (101), as shown in Figure 4 .

[0030] Meanwhile, sputtering a metal layer on the ferroelectric layer, depositing a resistive switching layer on the metal layer, sputtering a layer of metal on the resistive switching layer, and forming a gate pattern window by photolithography, comprises: S4, sputtering Pt metal on the ferroelectric layer (102) by physical vapor deposition (PVD) to form a metal layer (103); wherein the metal layer (103) is used as a shared electrode connecting the ferroelectric layer and the resistive switching layer, as shown in Figure 5

[0031] S5, depositing a TaO2 resistive switching layer (104) on the metal layer (103) by atomic layer deposition (ALD), as shown in Figure 6 S6, sputtering TaTiN metal (105) on the TaO2 resistive switching layer (104) by physical vapor deposition (PVD), as shown in Figure 7 S7, forming a gate pattern window by photolithography to define a junction region and etching to remove excess material, as shown in Figure 8

[0032] Specifically, sputtering TiN metal in the gate pattern window, including: S8, ion implantation in the junction region corresponding to the gate pattern window to form a heavily doped junction region, as shown in Figure 9 S9, rapid annealing to activate the doped ions in the junction region; S10, growing a layer of SiO2 on the surface of the TaTiN metal (105) and the exposed Si layer (101), forming a bottom electrode window by photolithography, and sputtering TiN metal (106) by physical vapor deposition (PVD), and then removing the photoresist and SiO2, as shown in Figure 10

[0033] Semiconductor doping includes ion implantation, diffusion doping, and epitaxial growth doping, etc.

[0034] ​​​​​​The working principle and effects of the above technical solution are as follows: the preparation method of the new nonvolatile memory based on the RRAM+FCM structure is a new device structure in which a memristor (RRAM) and a ferroelectric capacitor memory (FCM) are connected in series. To manufacture the structure, first, a SiO2 layer is formed on a Si substrate material by passivation, then a HZO ferroelectric dielectric layer and a gate electrode are deposited on the SiO2 material to form an FCM structure; a metal bottom electrode, a hafnium oxide resistance variable material, and a top electrode metal are deposited at the FCM gate electrode, and finally, a MIM structure on the original FCM port is formed by photolithography and etching processing, and the integration of RRAM and FCM is completed. The new nonvolatile memory has the advantages of simple structure, fast writing speed, high durability, low power consumption, and CMOS compatibility. The high and low capacitance ratio of the traditional capacitor is not large enough, and it is easy to be disturbed by external noise signals, which may lead to state misjudgment; the durability is reduced due to the defects of ferroelectric materials, electrode interface effects, and the like, and the number of device erase-write cycles is small; and the memory formed by the preparation method of the embodiment uses the FCM and RRAM structure in series, and uses the advantages of high writing speed, high durability, low power consumption, high storage density, and new storage mechanism to make up for the shortcomings of the traditional ferroelectric capacitor memory, thereby laying a solid foundation for related storage technology and making sufficient preparation for industrialization.

[0035] The above technical solution proposed in the embodiment solves the problem that the ferroelectric capacitor is easy to be disturbed by external signals when used to design a memory, which may lead to misjudgment. Meanwhile, the new memory architecture design is realized, and the device process flow and detailed steps are improved, thereby providing a solid guarantee for further development in the future.

[0036] Embodiment 2

[0037] In the embodiment, the thermal regenerative thermal oxidizer (RTO) uses a preset temperature control strategy to generate a SiO2 layer (101) on the surface of a Si substrate (100); wherein the temperature control strategy includes a preheating stage, a first ladder oxidation stage, a pulse high temperature stage, a second ladder oxidation stage, and a cooling stage.

[0038] The target temperature corresponding to the preheating stage is 400℃; the target temperature corresponding to the first ladder oxidation stage is 560℃; the target temperatures corresponding to the pulse high temperature stage are 800℃ and 650℃; and the target temperature corresponding to the cooling stage is 25℃.

[0039] Specifically, the temperature control strategy corresponding to the generation of the SiO2 layer is as follows: Preheating stage: from room temperature 25℃ to 400℃ at a rate of not less than 18℃ / min, and keep the temperature at 400℃ for 10min; the purpose of this stage is to slowly raise the temperature to make the overall temperature of the Si substrate (100) uniform, reduce the initial temperature difference, and lay a good foundation for the subsequent oxidation reaction.

[0040] The first ladder oxidation stage: the temperature is raised to 560℃ at a first temperature gradient (unit: ℃ / min) and kept for 15 min, and the passivation reaction is carried out at 560℃. The slow temperature rising rate and the appropriate holding time are helpful to the preliminary formation of the SiO2 layer and ensure the preliminary uniform distribution of the SiO2 layer on the substrate surface. The pulse high-temperature stage: the temperature is rapidly raised to 800℃ within 1 min, kept for 30 s, then lowered to 650℃ within 2 min, kept for 15 s, and the temperature adjustment process is repeated for 3 times. The rapid temperature rising to high temperature can promote the oxidation reaction in a short time and increase the thickness of the SiO2 layer, and the short holding time and rapid temperature lowering can avoid the increase of interface defects caused by long time high temperature.

[0041] The second ladder oxidation stage: the temperature is kept at 650℃ for 18 min. This stage is mainly to optimize the SiO2 layer, so that the oxidation reaction is more sufficient and stable, and the quality of the SiO2 layer is further improved.

[0042] The cooling stage: the temperature is lowered to room temperature 25℃ at a second temperature gradient (unit: ℃ / min). The slow temperature lowering rate can reduce the internal stress caused by sudden temperature change and prevent the SiO2 layer from having defects such as cracks.

[0043] The first temperature gradient is obtained by the following formula: T 01 =[1+norm((D m ×K) / (G0×t 01 ))]×T a Wherein, T 01 represents the first temperature gradient; D m represents the target thickness of the SiO2 layer; K represents the effective heat capacity of the circulating gas in the heat accumulating thermal incinerator; G0 represents the initial oxygen adsorption amount on the surface of the Si substrate, which is obtained by XPS detection in the pretreatment stage; t 01 represents the maximum allowed temperature rising time corresponding to the first ladder oxidation stage; T a represents the preset initial temperature rising gradient; norm() represents the normalization processing of the physical quantity in the parentheses.

[0044] The second temperature gradient is obtained by the following formula: {\mathrm{T}}_{02}=[1+norm(({\mathrm{D}}_{s}+J) / (\alpha \times {t}_{02}))]\times {\mathrm{T}}_{b} Wherein, T02 represents the second temperature gradient; D s represents the actual growth thickness of the SiO2 layer after the end of the pulse high-temperature stage, obtained by real-time optical ellipsometry detection; J represents the heat loss coefficient of the heat accumulation type thermal incinerator, calculated by the thermal conductivity coefficient and surface area of the heat preservation material of the furnace body; a represents the difference between the thermal expansion coefficients of the Si substrate and the SiO2 film; t 02 represents the maximum allowed cooling time; T b represents the preset initial cooling gradient; norm() represents the normalization processing of the physical quantity in the parentheses.

[0045] The working principle and effect of the above technical solution: The above technical solution proposed in this embodiment is different from the continuous high-temperature or monotonic temperature rising mode in the prior art. Through the pulse cycle of "rapid rise-short preservation-sudden drop", the directional diffusion of oxygen atoms in the Si lattice is promoted by using the thermal shock effect, and the phenomenon of Si atom outward diffusion caused by long time high temperature is avoided. Experimental verification can reduce the interface state density to 5×10¹ 0 cm⁻²・eV⁻¹ or less. This embodiment solves the contradiction between "thickness uniformity and density" in the traditional constant temperature process by designing an asymmetric ladder of 400℃→560℃→800℃→650℃, and respectively regulating the nucleation rate and growth rate of SiO2 in different temperature ranges. The thickness deviation of the film is controlled within 1.5%. At the same time, the slow temperature rise in the preheating stage and the gradient cooling in the cooling stage form a temperature stress buffer, which, combined with the instantaneous activation effect of the pulse high temperature, realizes the whole process optimization of "low-temperature nucleation-high-temperature growth-medium-temperature densification-cold shaping", which is essentially different from the single temperature regulation logic of the prior art.

[0046] At the same time, the first temperature gradient is dynamically related to the target thickness, the heat capacity of the circulating gas, and the initial oxygen adsorption amount, and is combined with the constraint of the maximum allowed temperature rising time, so that the temperature rising rate is self-adaptive to the initial state of the substrate surface, avoiding the thickness sudden increase caused by too fast reaction in this area, and finally controlling the in-plane thickness deviation of the SiO2 layer within ±2%, which is more than 50% higher than the traditional fixed rate process. At the same time, the pulse cycle of 800℃ and 650℃ and the first ladder oxidation controlled by the first temperature gradient form the connection from the preliminary shaping to the rapid growth of the SiO2 film, and the normalization processing ensures the consistency of the reaction activity of different batches of substrates in the pulse stage, so that the batch difference of the film thickness is reduced to 3% or less.

[0047] On the other hand, the first temperature gradient formula avoids the "over-oxidation" phenomenon of the first stage oxidation by combining the initial temperature gradient with a dynamic correction term. When the oxygen adsorption amount on the substrate surface is low, the formula will increase the temperature rise rate through normalization processing, shorten the low-temperature reaction time below 560℃, and reduce the disordered diffusion of oxygen atoms in the Si lattice; while the short 800℃ heating in the pulse high-temperature stage promotes the directional migration of oxygen atoms, reducing the Si / SiO2 interface state density to 8×10¹ 0 cm⁻²・eV⁻¹ below, which is 40% lower than the traditional process. At the same time, the association of the heat loss coefficient with the actual thickness in the second temperature gradient formula ensures that the cooling rate matches the actual growth state of the film. Further, the film is fully crystallized during slow cooling, and the density (refractive index measured by an ellipsometer) is stabilized at 1.46±0.01, close to the theoretical value of SiO2.

[0048] At the same time, the second temperature gradient formula dynamically matches the cooling rate with the stress accumulation state of the film by combining the difference in thermal expansion coefficient, the constraint of the maximum allowed cooling time, and the feedback of the actual thickness. When the difference in thermal expansion coefficient (α) between Si substrate and SiO2 increases due to temperature fluctuations, the formula will reduce the second temperature gradient through normalization processing to avoid the concentration of tensile stress caused by the difference in shrinkage rate. The incidence of micro-cracks on the surface of the film is reduced to below 0.1‰, as detected by a laser confocal microscope. At the same time, the rapid heating (≥18℃ / min) in the preheating stage and the slow cooling controlled by the second temperature gradient form a "rapid heating-slow cooling" stress balancing mechanism, combined with the 560℃ and 650℃ holding stages, to control the internal stress (measured by Raman spectroscopy) of the film to within 150MPa, which is 60% lower than the traditional process, meeting the requirements of high-frequency devices for low-stress insulating layers.

[0049] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A novel non-volatile memory preparation method based on RRAM+FCM structure, characterized in that: The novel non-volatile memory preparation method comprises: A SiO2 layer is formed on the substrate, and an amorphous HZO layer is deposited on the SiO2 and thermally annealed to convert it into a ferroelectric phase HZO; Sputtering a metal layer on the ferroelectric layer, depositing a resistive switching layer on the metal layer, sputtering a layer of metal on the resistive switching layer, and forming a gate pattern window by photolithography; After semiconductor doping and annealing in the junction region; A layer of SiO2 is grown on the device, a bottom electrode window is formed by photolithography, and a bottom electrode metal is formed in the bottom electrode window by sputtering.

2. The method for preparing a novel non-volatile memory based on the RRAM+FCM structure according to claim 1, characterized in that: A SiO2 layer is formed on a substrate, and an amorphous HZO layer is deposited on the SiO2 and thermally annealed to convert the layer into a ferroelectric HZO phase, including: The Si substrate (100) is cleaned using an RCA cleaning process; A regenerative thermal incinerator is used to passivate and generate a SiO2 layer (101) on the surface of a Si substrate (100); An amorphous HZO layer is deposited on the SiO2 layer (101) by an atomic deposition method; A ferroelectric phase HZO (102) is formed on the amorphous HZO layer of the SiO2 layer (101) by thermal annealing at 300-600°C in a nitrogen (N2) atmosphere.

3. The method for preparing a novel non-volatile memory based on the RRAM+FCM structure according to claim 1, characterized in that: The thickness of the SiO2 layer (101) is in the range of 1-3 nm.

4. The method for preparing a novel non-volatile memory based on the RRAM+FCM structure according to claim 2, characterized in that: The regenerative thermal incinerator adopts a preset temperature control strategy to passivate and generate a SiO2 layer (101) on the surface of a Si substrate (100); wherein the temperature control strategy includes a preheating stage, a first step oxidation stage, a pulse high temperature stage, a second step oxidation stage and a cooling stage.

5. The method for preparing a novel non-volatile memory based on the RRAM+FCM structure according to claim 4, characterized in that: The target temperature corresponding to the preheating stage is 400°C; the target temperature corresponding to the first-step oxidation stage is 560°C; the target temperatures corresponding to the pulse high-temperature stage are 800°C and 650°C; and the target temperature corresponding to the cooling stage is 25°C.

6. The method for preparing a novel non-volatile memory based on the RRAM+FCM structure according to claim 1 or 3, characterized in that: The temperature control strategy for generating the SiO2 layer is as follows: Preheating stage: from room temperature 25℃ to 400℃ at a rate of not less than 18℃ / min, and keep at 400℃ for 10 minutes; First step oxidation stage: the temperature is raised to 560°C at the rate of the first temperature gradient, kept at this temperature for 15 minutes, and the passivation reaction is gradually carried out at the temperature of 560°C; Pulse high temperature stage: quickly heat up to 800℃ within 1 minute, maintain for 30 seconds, then cool down to 650℃ within 2 minutes, maintain for 15 seconds, and repeat this temperature adjustment process 3 times; Second step oxidation stage: maintain constant temperature at 650℃ for 18min; Cooling stage: cooling to room temperature 25°C at the rate of the second temperature gradient.

7. The method for preparing a novel non-volatile memory based on the RRAM+FCM structure according to claim 6, characterized in that: The first temperature gradient is obtained by the following formula: T 01 =[1+norm((D m ×K) / (G0×t 01 ))]×T a Among them, T 01 Represents the first temperature gradient; D m represents the target thickness of the SiO2 layer; K represents the effective heat capacity of the circulating gas in the regenerative thermal incinerator; G0 represents the initial oxygen adsorption amount on the Si substrate surface, obtained by XPS detection in the pretreatment stage; t 01 Indicates the maximum allowable heating time corresponding to the first step oxidation stage; T a Indicates the preset initial temperature gradient; norm() indicates the normalization of the physical quantities in the brackets.

8. The method for preparing a novel non-volatile memory based on the RRAM+FCM structure according to claim 6, characterized in that: The second temperature gradient is obtained by the following formula: {\mathrm{T}}_{02}=[1+norm(({\mathrm{D}}_{s}+J) / (\alpha \times {t}_{02}))]\times {\mathrm{T}}_{b} Among them, T 02 Represents the second temperature gradient; D s represents the actual growth thickness of the SiO2 layer after the pulse high temperature stage; J represents the heat loss coefficient of the regenerative thermal incinerator; α represents the difference in thermal expansion coefficient between the Si substrate and the SiO2 film; t 02 Indicates the maximum allowable cooling time; T b Represents the preset initial cooling gradient; norm() indicates the normalization of the physical quantities in the brackets.

9. The method for preparing a novel non-volatile memory based on the RRAM+FCM structure according to claim 1, characterized in that: Sputtering a metal layer on the ferroelectric layer, depositing a resistive switching layer on the metal layer, sputtering a layer of metal on the resistive switching layer, and forming a gate pattern window by photolithography, including: Sputtering and growing Pt metal on the ferroelectric layer (102) using a physical vapor deposition method to form a metal layer (103); Depositing a TaO2 resistive layer (104) on the metal layer (103) using an atomic deposition method; Sputtering and growing TaTiN metal (105) on the TaO2 resistive layer (104) using a physical vapor deposition method; The gate pattern window is formed by photolithography, the junction area is defined, and the excess material is removed by etching.

10. The method for preparing a novel non-volatile memory based on the RRAM+FCM structure according to claim 1, characterized in that: Sputtering to form a bottom electrode metal in the bottom electrode window, comprising: Ion implantation is performed in the junction region to form a heavily doped junction region, and then rapid annealing is performed to activate the doped ions in the junction region; A layer of SiO2 is grown on the surface of the TaTiN metal (105) and the exposed Si layer (101), a bottom electrode window is formed by photolithography, and TiN metal (106) is sputtered by physical vapor deposition, and then the photoresist and SiO2 are removed.

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