Semiconductor structure and manufacturing method thereof
By integrating the upper and lower plates of the MIM capacitor in a high-k metal gate process and defining the MIM structure using a high-resistance photomask, the problem of excessive photomask usage in existing technologies is solved, resulting in cost reduction and process simplification.
Patent Information
- Application Number
- CN202510796128.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-13
- Publication Date
- 2025-10-17
AI Technical Summary
Existing MIM capacitor manufacturing methods require additional deposition of upper and lower electrodes in the copper back-end process, resulting in high manufacturing costs and complex process steps.
The fabrication of MIM capacitors is integrated into a high-k metal gate process, using a high-resistivity metal as the upper electrode and a metal gate as the lower electrode, and a high-resistivity photomask to define the MIM structure pattern, reducing the use of photomasks.
Two masks are saved, the process steps are simplified, and the manufacturing cost is reduced.
Smart Images
Figure CN120812957A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND
[0002] Metal-Insulator-Metal (MIM) capacitors are widely used in functional circuits, such as mixed-signal circuits, analog circuits, radio frequency circuits, dynamic random access memories, embedded dynamic random access memories and logic operation circuits. As the name implies, MIM capacitors include a sandwich structure of metal layers and insulating layers, and an exemplary MIM capacitor includes an upper plate, a lower plate and an insulating layer in the middle. The insulating layer can be various high-dielectric-constant materials, such as silicon nitride, aluminum oxide, etc.
[0003] In addition to MIM capacitors, metal-oxide-metal (MOM) capacitors and multi-directional field capacitors are also common. Compared with MOM capacitors, MIM capacitors are metal-plate capacitors, so their capacitance values are more accurate and do not change with bias voltage, and therefore can be applied to scenarios with higher requirements for capacitance values. In addition, MIM capacitors have higher capacitance values than MOM capacitors, and are more advantageous in scenarios requiring high capacitance values. Compared with multi-directional field capacitors, MIM capacitors have more stable capacitance densities at different frequencies, and are more advantageous in scenarios requiring high stability of capacitance densities.
[0004] The existing method for manufacturing MIM capacitors generally integrates the manufacturing of MIM capacitors in copper backend processes. In this method, the upper plate and the lower plate of the MIM capacitor need to be deposited additionally, so additional masks (upper plate mask and lower plate mask) are needed to complete the manufacturing, which increases the manufacturing cost and complicates the process steps. SUMMARY
[0005] The present application aims to provide a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure integrates the manufacturing of MIM capacitors in the process of forming high-resistance resistors in high-k metal gate processes, which can save 2 masks compared with the existing method of integrating the manufacturing of MIM capacitors in copper backend processes, and the process steps are simpler.
[0006] In a first aspect, to solve the above technical problems, the present application provides a manufacturing method of a semiconductor structure, which can at least include the following steps:
[0007] A substrate is provided, and a metal gate structure is formed on the substrate, wherein the metal gate structure includes a first metal gate, and the first metal gate serves as a lower plate of a MIM capacitor.
[0008] forming a dielectric layer on the substrate;
[0009] forming a metal layer of high resistance resistor region on the dielectric layer;
[0010] lithographing and etching the dielectric layer and the metal layer to define a MIM capacitor region, the dielectric layer in the MIM capacitor region as a dielectric layer of MIM capacitor, and the metal layer in the MIM capacitor region as an upper plate of MIM capacitor.
[0011] Further, after defining the MIM capacitor region, further comprising:
[0012] forming a passivation layer on the substrate.
[0013] Further, after forming the passivation layer on the substrate, further comprising:
[0014] etching the passivation layer to form a first metal plug and a second metal plug, the first metal plug connected with a lower plate of the MIM capacitor, and the second metal plug connected with an upper plate of the MIM capacitor.
[0015] Further, after forming the metal layer on the dielectric layer, further comprising:
[0016] forming a barrier layer on the metal layer.
[0017] Further, while lithographing and etching the dielectric layer and the metal layer, further comprising:
[0018] lithographing and etching the barrier layer.
[0019] Further, the metal gate structure further comprises a second metal gate.
[0020] Further, while defining the MIM capacitor region, further comprising:
[0021] lithographing and etching the dielectric layer and the metal layer to define a high resistance resistor region, the high resistance resistor region covering the second metal gate.
[0022] Further, while forming the first metal plug and the second metal plug, further comprising:
[0023] etching the passivation layer to form a third metal plug and a fourth metal plug, the third metal plug and the fourth metal plug connected with the metal layer in the high resistance resistor region.
[0024] In a second aspect, the present application further provides a semiconductor structure, which at least comprises:
[0025] a metal gate structure is formed on the substrate, and includes a first metal gate and a second metal gate arranged separately from each other;
[0026] a MIM capacitor is formed on the first metal gate in the MIM capacitor region, and includes the first metal gate as a lower plate, a dielectric layer formed on the first metal gate, and the metal layer in the high resistance resistor region as an upper plate;
[0027] a high resistance resistor is formed on the second metal gate in the high resistance resistor region, and includes the metal layer in the high resistance resistor region.
[0028] Further, the semiconductor structure further includes:
[0029] a plurality of metal plugs, including a first metal plug, a second metal plug, a third metal plug and a fourth metal plug arranged separately from each other, the first metal plug is formed on the first metal gate, the second metal plug is formed on the metal layer in the MIM capacitor region, and the third metal plug and the fourth metal plug are formed on the metal layer in the high resistance resistor region.
[0030] Compared with the prior art, the technical scheme of the present application has at least one of the following beneficial effects:
[0031] In the semiconductor structure and the manufacturing method thereof, the manufacturing method of the semiconductor structure provides a substrate, a metal gate structure is formed on the substrate, and the metal gate structure includes a first metal gate as a lower plate of a MIM capacitor, then a dielectric layer is formed on the substrate, then a metal layer of a high resistance resistor region is formed on the dielectric layer, and finally the dielectric layer and the metal layer are photoetched to define a MIM capacitor region, the dielectric layer in the MIM capacitor region is a dielectric layer of the MIM capacitor, and the metal layer in the MIM capacitor region is an upper plate of the MIM capacitor.
[0032] In the manufacturing method of the semiconductor structure, the metal used as a high resistance resistor is used as an upper plate of a MIM capacitor, the metal gate in the metal gate structure is used as a lower plate, and a high resistance resistor photo mask is used to define the pattern of the high resistance device and the pattern of the MIM structure at the same time, so compared with the process of forming a high resistance resistor in a high-k metal gate process, no additional photo mask is added, and compared with the existing method of integrating the manufacturing of a MIM capacitor in a copper back-end process, 2 photo masks (upper plate photo mask and lower plate photo mask) can be saved, and the process steps are simpler. BRIEF DESCRIPTION OF DRAWINGS
[0033] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:
[0034] Figures la- lk A schematic view of a structure in the manufacturing process of a semiconductor structure in the prior art;
[0035] Figure 2 A flow chart of a method for manufacturing a semiconductor structure in an embodiment of the application;
[0036] Figures 3a-3f A schematic view of a structure in the manufacturing process of a semiconductor structure in an embodiment of the application, wherein, Figure 3f A schematic view of a semiconductor structure provided by an embodiment of the application.
[0037] In the drawings, the same components have the same reference numbers. The drawings are not drawn to scale.
[0038] 100 - second substrate; 100a - MIM capacitor region; 100b - high resistance resistor region; 101 - shallow trench isolation; 102 - gate oxide layer; 103 - first side wall; 104 - second side wall; 105 - metal gate; 105a - first metal gate; 105b - second metal gate; 106 - first dielectric layer; 107 - second dielectric layer; 108 - metal layer; 109 - barrier layer; 110 - fourth passivation layer; 111 - first metal plug; 112 - second metal plug; 113 - third metal plug; 114 - fourth metal plug;
[0039] 200 - first substrate; 201 - M X etal; 202 - first passivation layer; 203 - first oxide layer; 204 - lower plate metal layer; 205 - first dielectric layer; 206 - upper plate metal layer; 207 - second passivation layer; 208 - first photoresist; 209 - third passivation layer; 210 - second photoresist; 211 - second oxide layer; 212 - protection layer; 213 - fifth metal plug region; 214 - sixth metal plug region; 215 - seventh metal plug region; 216 - M X+1 etal region; 217 - fifth metal plug; 218 - sixth metal plug; 219 - seventh metal plug; 220 - M X+1 etal.
[0040] In the drawings, the same components have the same reference numbers. The drawings are not drawn to scale. DETAILED DESCRIPTION
[0041] In order to make the technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although the accompanying drawings show exemplary implementation methods of the present invention, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.
[0042] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and are only used to conveniently and clearly assist in illustrating the purpose of the embodiments of the present invention. It is understood that the meanings of "on...", "above..." and "above..." in the present invention should be interpreted in the broadest way, so that "on..." not only means that it is "on" something and there are no intervening features or layers (i.e. directly on something), but also includes the meaning of being "on" something and having intervening features or layers. In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions recorded in the embodiments of the present invention can be arbitrarily combined without conflict.
[0043] As described in the background art, the existing method for manufacturing MIM capacitors generally integrates the manufacturing of MIM capacitors into the copper back-end process. The main steps of this manufacturing method are as follows:
[0044] First, if Figure la As shown, a first substrate 200 is provided, on which M is formed X Metal 201. Then, as Figure lb As shown, a first passivation layer 202, a first oxide layer 203, a lower plate metal layer 204, a first dielectric layer 205, an upper plate metal layer 206 and a second passivation layer 207 are sequentially formed on the first substrate 200. Then, as shown in FIG. Figure lc As shown, a first photoresist 208 is coated on the first substrate 200 to define the area of the upper plate of the MIM capacitor. Figure Id As shown, the second passivation layer 207 and the upper plate metal layer 206 are sequentially etched to form the upper plate of the MIM capacitor. Figure le As shown, a third passivation layer 209 is formed on the first substrate 200 for physical protection, interface optimization and process assistance. Figure If As shown, a second photoresist 210 is coated on the first substrate 200 to define the area of the lower plate of the MIM capacitor.Figure Ig The third passivation layer 209, the first dielectric layer 205 and the lower plate metal layer 204 are etched in sequence and stopped on the first oxide layer 203 to form the MIM capacitor dielectric layer and the lower plate. Then, as shown in Figure Ih The third passivation layer 209 is formed on the surface of the first oxide layer 203 exposed by etching and the sidewall of the first dielectric layer 205 and the lower plate metal layer 204, and then the second oxide layer 211 is formed on the first substrate 200. Then, as shown in Figure Ii The second oxide layer 211 is polished by chemical mechanical polishing. Then, as shown in Figure Ij The protection layer 212 and the second oxide layer 211 are formed on the first substrate 200 in sequence, and then the first substrate 200 is etched to form the fifth metal plug area 213, the sixth metal plug area 214, the seventh metal plug area 215 and the M X+1 metal area 216. Finally, as shown in Figure Ik The fifth metal plug 217, the sixth metal plug 218, the seventh metal plug 219 and the M X+1 metal 220 are filled in the fifth metal plug area 213, the sixth metal plug area 214, the seventh metal plug area 215 and the M X+1 metal area 216, and the extra M X+1 metal 220 is polished by chemical mechanical polishing.
[0045] Because the upper plate and the lower plate of the MIM capacitor need to be deposited additionally in this method, extra masks (the upper plate mask and the lower plate mask) are needed to complete, which results in high manufacturing cost and complex process steps.
[0046] To solve the above problems, the present application provides an improved method, i.e. using the metal as the high resistance resistor as the upper plate of the MIM capacitor, using the metal gate of the metal gate structure as the lower plate, and using one high resistance resistor mask to define the pattern of the high resistance resistor and the pattern of the MIM structure, so compared with the process of forming the high resistance resistor in the high-k metal gate process, no extra mask is needed, so compared with the existing method of integrating the MIM capacitor in the copper back-end process, 2 masks (the upper plate mask and the lower plate mask) can be saved, and the process steps are simpler.
[0047] Reference Figure 2 is shown, Figure 2 is a flowchart of the method for manufacturing the semiconductor structure provided in the embodiments of the present application; the method for manufacturing the semiconductor structure can include the following steps:
[0048] Step S201, providing a substrate, a metal gate structure is formed on the substrate, the metal gate structure includes a first metal gate, the first metal gate as the lower plate of MIM capacitor;
[0049] Step S202, forming a dielectric layer on the substrate;
[0050] Step S203, forming a metal layer of high resistance resistance region on the dielectric layer;
[0051] Step S204, photoetching and etching the dielectric layer and the metal layer to define the MIM capacitor region, the dielectric layer in the MIM capacitor region as the dielectric layer of MIM capacitor, the metal layer in the MIM capacitor region as the upper plate of MIM capacitor.
[0052] The method for manufacturing the semiconductor structure according to the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of conveniently and clearly assisting the description of the embodiments of the present application. In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, therefore the present application is not limited by the specific embodiments disclosed below.
[0053] Reference is made to Figure 3aIn step S201, a substrate, such as the second substrate 100, is provided. The second substrate 100 can be any suitable substrate material known in the art, such as at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon germanium-on-silicon-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or double side polished wafers (DSP), ceramic substrates such as alumina, quartz, or glass substrates, etc. In an example, the second substrate 100 is a silicon wafer. The second substrate 100 has a plurality of shallow trench isolations 101 formed thereon to define a plurality of active regions. In an example, the shallow trench isolations 101 are formed by etching a plurality of trenches (not shown) in the second substrate 100 and filling the trenches with one or more layers of an insulating material, such as silicon oxide, silicon nitride, and silicon oxynitride, but not limited thereto. The active regions have a metal gate structure formed thereon, which includes a gate oxide layer 102 and a metal gate 105 on the gate oxide layer 102. The metal gate 105 has a first sidewall 103 and a second sidewall 104 on the sidewalls of the metal gate 105. The metal gate 105 includes a first metal gate 105a and a second metal gate 105b, and the first metal gate 105a is used as a lower plate of a MIM capacitor.
[0054] Referring to Figure 3b In step S202, a second dielectric layer 107 is formed on the second substrate 100. The second dielectric layer 107 can be formed by at least one of physical vapor deposition, chemical vapor deposition, or atomic layer deposition, and can be silicon nitride or silicon oxynitride.
[0055] Referring to Figure 3cIn step S203, a metal layer 108 of high resistance region is formed on the dielectric layer 107. The metal layer 108 of high resistance region can be formed by sputtering deposition, evaporation deposition, chemical deposition, and preferably sputtering deposition in this embodiment. The material of the metal layer 108 of high resistance region can be nickel-chromium alloy or tantalum nitride. Then, a barrier layer 109 is formed on the metal layer 108 of high resistance region by physical vapor deposition or chemical vapor deposition, so as to prevent the invasion of moisture, oxygen and contaminants, and prevent metal oxidation or corrosion.
[0056] Referring to Figure 3d In step S204, the dielectric layer 107 and the metal layer 108 are etched by lithography and etching, so as to define the MIM capacitor region 100a and the high resistance region 100b. The dielectric layer 107 in the MIM capacitor region 100a serves as the dielectric layer of the MIM capacitor, and the metal layer 108 in the MIM capacitor region 100a serves as the upper plate of the MIM capacitor. The high resistance region 100b covers the second metal gate 105b.
[0057] Referring to Figure 3e After the MIM capacitor region and the high resistance region are defined in step S204, the method for manufacturing the semiconductor structure further comprises:
[0058] In step S204.1, a passivation layer, for example, a fourth passivation layer 110, is formed on the second substrate 100 by chemical vapor deposition, so as to protect and isolate. Then, the excess fourth passivation layer 110 is removed by chemical mechanical polishing, so as to planarize the surface of the fourth passivation layer 110.
[0059] Referring to Figure 3f After the fourth passivation layer 110 is formed in step S204.1, the method for manufacturing the semiconductor structure further comprises:
[0060] In step S204.2, the fourth passivation layer 110 and the barrier layer 109 are etched by a contact hole process, and metal filling is performed, so as to form a first metal plug 111, a second metal plug 112, a third metal plug 113 and a fourth metal plug 114.
[0061] In other embodiments, a semiconductor structure is also provided, which can specifically comprise:
[0062] The substrate, i.e. the second substrate 100, comprises the MIM capacitor region 100a and the high resistance region 100b.
[0063] a metal gate structure, located on the substrate and comprising a first metal gate 105a and a second metal gate 105b separated from each other;
[0064] A MIM capacitor is located on the first metal gate 105a in the MIM capacitor region 100a, and the MIM capacitor includes the first metal gate 105a as a lower plate, a dielectric layer located on the first metal gate 105a, i.e., the second dielectric layer 107, and the metal layer 108 located in the MIM capacitor region 100a as an upper plate;
[0065] a high-resistance resistor located on the second metal gate 105 b in the high-resistance resistor region 100 b , wherein the high-resistance resistor includes the metal layer 108 located in the high-resistance resistor region 100 b ;
[0066] Multiple metal plugs include a first metal plug 111, a second metal plug 112, a third metal plug 113, and a fourth metal plug 114 that are separated from each other. The first metal plug 111 is located on the first metal gate 105a, the second metal plug 112 is located on the metal layer 108 in the MIM capacitor area 100a, and the third metal plug 113 and the fourth metal plug 114 are located on the metal layer 108 in the high-resistance resistor area 105b.
[0067] In one embodiment, the semiconductor structure can be manufactured using the manufacturing method described above. Please refer to the above description for details, which will not be repeated here.
[0068] In summary, in a semiconductor structure and a manufacturing method thereof provided by the present invention, a substrate is provided, a metal gate structure is formed on the substrate, the metal gate structure includes a first metal gate, the first metal gate serves as the lower plate of the MIM capacitor, and then a dielectric layer is formed on the substrate, and then a metal layer of a high-resistance resistor area is formed on the dielectric layer. Finally, the dielectric layer and the metal layer are photolithographically and etched to define a MIM capacitor area, the dielectric layer in the MIM capacitor area serves as the dielectric layer of the MIM capacitor, and the metal layer in the MIM capacitor area serves as the upper plate of the MIM capacitor.
[0069] Since the method for manufacturing the semiconductor structure provided by the application uses metal as the upper plate of the MIM capacitor, uses the metal gate in the metal gate structure as the lower plate, and uses a high resistance resistor mask to define the pattern of the high resistance device and the pattern of the MIM structure at the same time, compared with the process of forming the high resistance resistor in the high-k metal gate process, no extra mask is added, and compared with the existing method of integrating the manufacturing of the MIM capacitor in the copper back-end process, 2 masks (the upper plate mask and the lower plate mask) can be saved, and the process steps are simpler.
[0070] It should be noted that although the application has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the application. For any skilled person in the art, many possible changes and modifications or equivalent embodiments of the above disclosed technical content can be made without departing from the scope of the technical solution of the application. Therefore, any simple modification, equivalent change and modification of the above embodiments made according to the technical essence of the application without departing from the content of the technical solution of the application still belongs to the protection scope of the technical solution of the application.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, on which a metal gate structure is formed, wherein the metal gate structure includes a first metal gate, and the first metal gate serves as a lower plate of the MIM capacitor; forming a dielectric layer on the substrate; forming a metal layer of a high resistance resistor region on the dielectric layer; The dielectric layer and the metal layer are photolithographically and etched to define a MIM capacitor region, wherein the dielectric layer in the MIM capacitor region serves as a dielectric layer of the MIM capacitor, and the metal layer in the MIM capacitor region serves as an upper plate of the MIM capacitor.
2. The method for manufacturing a semiconductor structure according to claim 1, wherein: After defining the MIM capacitor area, it also includes: A passivation layer is formed on the substrate.
3. The method for manufacturing a semiconductor structure according to claim 2, wherein: After forming a passivation layer on the substrate, the method further comprises: The passivation layer is etched to form a first metal plug and a second metal plug, wherein the first metal plug is connected to the lower plate of the MIM capacitor, and the second metal plug is connected to the upper plate of the MIM capacitor.
4. The method for manufacturing a semiconductor structure according to claim 1, wherein: After forming the metal layer on the dielectric layer, the method further comprises: A barrier layer is formed on the metal layer.
5. The method for manufacturing a semiconductor structure according to claim 4, wherein: While photolithography and etching the dielectric layer and the metal layer, the method further comprises: The barrier layer is photolithographically and etched.
6. The method for manufacturing a semiconductor structure according to claim 3, wherein: The metal gate structure further includes a second metal gate.
7. The method for manufacturing a semiconductor structure according to claim 6, wherein: When defining the MIM capacitor area, it also includes: The dielectric layer and the metal layer are photolithographically and etched to define a high-resistance resistor region, where the high-resistance resistor region covers the second metal gate.
8. The method for manufacturing a semiconductor structure according to claim 7, wherein: While forming the first metal plug and the second metal plug, the method further includes: The passivation layer is etched to form a third metal plug and a fourth metal plug, wherein the third metal plug and the fourth metal plug are connected to the metal layer in the high-resistance resistor region.
9. A semiconductor structure, characterized in that include: a substrate including a MIM capacitor region and a high-resistance resistor region; a metal gate structure, located on the substrate and comprising a first metal gate and a second metal gate separated from each other; A MIM capacitor is located on the first metal gate in the MIM capacitor region, the MIM capacitor comprising the first metal gate as a lower plate, a dielectric layer located on the first metal gate, and the metal layer located in the MIM capacitor region as an upper plate; A high-resistance resistor is located on the second metal gate in the high-resistance resistor region, and the high-resistance resistor includes the metal layer located in the high-resistance resistor region.
10. The semiconductor structure according to claim 9, wherein: Also includes: Multiple metal plugs include a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug that are separated from each other, the first metal plug is located on the first metal gate, the second metal plug is located on the metal layer in the MIM capacitor area, and the third metal plug and the fourth metal plug are located on the metal layer in the high-resistance resistor area.