Preparation method of short-channel two-dimensional semiconductor device
By forming a nanoscale gap in the middle of graphene and combining polymethyl methacrylate transfer and atomic layer deposition processes, the problem of high preparation cost of short-channel two-dimensional semiconductor devices was solved, and high-performance, low-cost short-channel two-dimensional semiconductor field-effect transistors were realized.
Patent Information
- Application Number
- CN202510815421.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-18
- Publication Date
- 2025-10-17
AI Technical Summary
In the existing technology, the preparation of short-channel two-dimensional semiconductor electronic devices is limited by the high cost of lithography equipment, especially the preparation of devices with a channel length below 100 nm is difficult to achieve.
Graphene is prepared by mechanical exfoliation and chemical vapor deposition, metal electrodes are prepared by laser direct writing and thermal evaporation, nanoscale gaps are formed in the middle of the graphene using electrical burning technology, and the gate structure is prepared by combining polymethyl methacrylate transfer and atomic layer deposition processes to realize short-channel two-dimensional semiconductor field-effect transistors.
High-precision and low-cost preparation of short-channel two-dimensional semiconductor field-effect transistors has been achieved, which have high switching ratio and high sensitivity. They are suitable for flexible electronic devices and low-power devices, meeting the needs of the new generation of electronic devices.
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Figure CN120812971A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of nano-electronic devices, in particular to a short channel two-dimensional semiconductor device preparation method. BACKGROUND
[0002] Two-dimensional semiconductor materials have great application potential in the field of electronic devices due to their natural atomic thickness, no dangling bond surface and excellent electrical properties, and have attracted keen attention from academia and industry. However, the preparation of short channel two-dimensional semiconductor electronic devices is limited by photolithography equipment, especially for devices with a channel length of less than 100 nm. Conventional devices with a channel length of less than 100 nm are prepared using advanced KrF photolithography machines or electron beam lithography machines, which are expensive and limit the research and application process of two-dimensional semiconductor electronic devices. SUMMARY
[0003] In order to improve the technical defects that the expensive equipment limits the research and application process of two-dimensional semiconductor electronic devices, the present application provides a short channel two-dimensional semiconductor device preparation method.
[0004] In a first aspect, the short channel two-dimensional semiconductor device preparation method provided by the present application adopts the following technical scheme: A short channel two-dimensional semiconductor device preparation method, comprising the following steps: Step one: preparing a layer of graphene on a substrate one, the preparation method including mechanical exfoliation method, chemical vapor deposition method; Step two: preparing a metal electrode above the graphene by a micron-level precision patterning method, the patterning method including laser direct writing method, and the metal electrode preparation method including thermal evaporation method; Step three: applying a voltage to both sides of the metal electrode by a source table to burn off the middle of the graphene; Step four: uniformly coating a layer of polymethyl methacrylate above the metal electrode, and placing the entire substrate one 1 on a hot plate for heating treatment, the treatment temperature being 150-200 ℃; Step five: using a metal tweezers to lift the entire structure above the substrate one 1, separate it from the substrate one, and transfer it to above the two-dimensional semiconductor on a substrate two; Step six: placing the entire structure of the substrate two in an acetone solution to remove the uppermost polymethyl methacrylate; Step seven: preparing a gate structure by conventional atomic layer deposition and thermal evaporation process methods, and completing the preparation of a short channel two-dimensional semiconductor field effect transistor.
[0005] By adopting the technical scheme, high-precision and compatibility preparation of the short-channel two-dimensional semiconductor field effect transistor is realized, and specific technical functions include: high-quality graphene is used as an electrode connection channel to realize excellent electrical performance; laser direct writing and other micro-nano processing technologies are used to realize accurate patterning of the metal electrode, so as to ensure that the channel length is controlled to be microns or even nanometers; a nanoscale gap is formed in the graphene by the electric burn-off method to form a short-channel structure; polymethyl methacrylate is used as a transfer medium to realize complete transfer of the graphene-electrode structure from the first substrate to the surface of the two-dimensional semiconductor, and pollution and damage are avoided; the transfer layer is removed by a solution method to maintain the integrity of the device structure and the cleanliness of the interface; finally, atomic layer deposition and thermal evaporation processes are combined to complete the preparation of the gate structure, thereby forming a two-dimensional semiconductor field effect transistor with short-channel characteristics, high on-off ratio and high sensitivity, which meets the core needs of new-generation flexible electronic devices, low-power devices and nanoelectronics.
[0006] Optionally, when the graphene is prepared by the mechanical exfoliation method, the raw material used is a high-quality graphite crystal, and the graphene is transferred to the surface of the substrate by using a tape and a PDMS assisted transfer method.
[0007] By adopting the technical scheme, high-quality, pollution-free preparation and accurate transfer of the graphene layer are realized, the high-quality graphite crystal ensures the integrity and excellent electrical performance of the graphene, and the tape and PDMS assisted transfer can effectively reduce cracks, pollution and wrinkles introduced in the transfer process, so as to ensure that the graphene is uniformly attached to the surface of the substrate and to improve the stability and consistency of subsequent device preparation.
[0008] Optionally, the metal electrode is a titanium / gold double-layer structure, wherein the thickness of the titanium layer is 5-10 nm, and the thickness of the gold layer is 40-60 nm.
[0009] By adopting the technical scheme, good adhesion and conductivity of the metal electrode are realized, the titanium layer serves as a bottom material and has excellent adhesion performance, which can enhance the bonding force between the metal electrode and the graphene or the surface of the substrate, and prevent the electrode from falling off or shifting; the gold layer has a low resistivity, which can effectively reduce the contact resistance of the device and improve the current transmission efficiency, so as to ensure stable operation and performance reliability of the device under high-frequency and high-sensitivity working conditions.
[0010] Optionally, in step 1.3 of the electric burn-off in the graphene, the applied voltage is 5-15 V, and the duration is 1-3 seconds, so as to control the position of the graphene fracture to be located at the center position between the metal electrodes.
[0011] By adopting the technical scheme, the length of the graphene channel is accurately controlled and the short channel structure is repeatedly constructed, the graphene is broken at the center position between the electrodes by applying a voltage of 5-15 V between the electrodes and controlling the application time within 1-3 seconds, a nanoscale gap is formed, the position and size of the channel region are effectively limited, and thus the electrical control ability and gate control efficiency of the device are improved, and the core requirement of the short channel characteristic for the high-performance field effect transistor is met.
[0012] Optionally, the spin-coating thickness of the polymethyl methacrylate is 100-300 nm, and the heating treatment time is 3-10 minutes.
[0013] By adopting the technical scheme, the spin-coating thickness of 100-300 nm can ensure that the graphene has sufficient support strength and flexibility during the transfer process, and the structure is prevented from being warped or broken; the heating treatment for 3-10 minutes helps the PMMA to be fully solidified and the adhesion to be enhanced, and the integrity and positioning accuracy of the graphene-electrode structure during the transfer process are ensured, and thus the consistency and yield of the subsequent device construction are improved.
[0014] Optionally, the two-dimensional semiconductor is single-layer or few-layer MoS2, WSe2 or black phosphorus.
[0015] By adopting the technical scheme, the single-layer or few-layer MoS2, WSe2 or black phosphorus as the two-dimensional semiconductor material has a natural atomic level thickness and excellent electrical characteristics, and can effectively improve the on-off ratio, sensitivity and response speed of the device. Meanwhile, these materials have good interface compatibility with graphene and metal electrodes, facilitating the construction of a heterostructure and meeting the requirements of flexible electronics, low-power devices and other frontier applications.
[0016] Optionally, the gate structure includes a gate dielectric layer and a gate electrode, the gate dielectric layer is an Al2O3 film prepared by atomic layer deposition, and the gate electrode is a metal layer formed by thermal evaporation.
[0017] In a second aspect, the short channel two-dimensional semiconductor device provided by the application adopts the following technical scheme.
[0018] A short channel two-dimensional semiconductor device includes a semiconductor device body, a polymethyl methacrylate and a substrate two are arranged at the bottom of the semiconductor device body, a two-dimensional semiconductor material is arranged on the upper part of the substrate two, and two pieces of graphene are arranged on the upper end of the two-dimensional semiconductor material. Two metal electrodes are arranged on the upper end of the graphene, and the two metal electrodes are arranged on the upper end of the graphene at corresponding positions. The polymethyl methacrylate covers the upper end and the sidewall of the graphene and the metal electrode and the remaining gap.
[0019] By adopting the technical scheme, high integration, high stability and excellent electrical performance of a short channel two-dimensional semiconductor device structure are achieved. The device body adopts a substrate two-bearing two-dimensional semiconductor material, such as a single layer or a few layers of MoS2, WSe2 or black phosphorus, which has excellent carrier mobility and sub-threshold swing and is suitable for low-power and high-sensitivity nanoelectronic devices. Graphene is used as a conductive channel material between the source and drain electrodes, which matches well with the two-dimensional semiconductor interface, has low contact resistance and good flexibility. The metal electrode is located above the graphene and connected to both ends of the broken region, forming a short channel structure, which effectively improves the response speed and gate control ability of the device. Meanwhile, polymethyl methacrylate is used as a protective cover layer to cover the upper end and sidewall of the graphene and metal electrode, fill the gap between the structures, provide mechanical stability and environmental isolation, prevent the device from being contaminated or damaged during preparation, transfer or later operation, and improve the yield and long-term operation stability of the device.
[0020] Optionally, the two-dimensional semiconductor material is a single layer or a few layers of molybdenum disulfide (MoS2), tungsten diselenide (WSe2) or black phosphorus.
[0021] By adopting the technical scheme, the single layer or a few layers of MoS2, WSe2 or black phosphorus as the two-dimensional semiconductor material has a natural atomic thickness and excellent electrical properties, which can effectively improve the on-off ratio, sensitivity and response speed of the device. At the same time, such materials have good interface compatibility with metal electrodes and graphene, which helps to reduce the contact resistance and significantly enhance the overall performance and integration potential of the device.
[0022] Optionally, the metal electrode is a titanium / gold composite structure, in which the titanium layer is used to improve the interface contact and the gold layer is used to improve the conductivity. The thickness of the titanium layer is 5-10 nm and the thickness of the gold layer is 40-60 nm.
[0023] By adopting the technical scheme, the titanium layer acts as an adhesive layer to effectively enhance the adhesion between the metal electrode and the graphene or semiconductor material, and reduce the interface contact resistance. The gold layer provides a low-resistance channel to improve the conductivity and current transmission efficiency of the overall electrode. The titanium / gold composite structure takes into account the adhesion and conductivity, ensuring the stable operation of the device at the micro-nano scale and providing key support for the realization of high-performance short channel field effect transistors.
[0024] In summary, the present application includes at least one of the following beneficial technical effects: Break away from the shackles of expensive high-precision photolithography equipment, the cost is reduced; Achieve lossless transfer and precise breaking of high-quality graphene electrodes, improve the electrical performance and process stability of the device; By designing a titanium / gold composite metal electrode, good adhesion and excellent conductivity of the electrode and the two-dimensional semiconductor interface are considered, the contact resistance is reduced, and the overall conductivity efficiency of the device is improved. Poly(methyl methacrylate) is used as a transfer medium and a protective layer to enhance the mechanical stability of the device structure, avoid pollution and damage, and improve the yield and long-term reliability of the device. Single-layer or few-layer two-dimensional semiconductor materials (such as MoS2, WSe2, and black phosphorus) are used to provide excellent carrier mobility and band characteristics, realizing high on-off ratio and high sensitivity short-channel field effect transistors. High-quality gate dielectric and metal gate are prepared by atomic layer deposition and thermal evaporation, realizing high gate control capability and meeting the application requirements of the next generation of low-power, flexible and nanoelectronic devices. BRIEF DESCRIPTION OF DRAWINGS
[0025] Figure 1 A flowchart of a short-channel two-dimensional semiconductor device preparation method.
[0026] Figure 2 A schematic diagram of a short-channel two-dimensional semiconductor device.
[0027] Figure 3 A partial view of the generation process of a short-channel two-dimensional semiconductor device.
[0028] BRIEF DESCRIPTION OF DRAWINGS: 1, substrate 1; 2, graphene; 3, metal electrode; 4, poly(methyl methacrylate); 5, two-dimensional semiconductor material; 6, substrate 2; 7, semiconductor device body. DETAILED DESCRIPTION
[0029] The following will be described in detail with reference to the accompanying drawings. Figures 1-3 Further detailed description of the present application.
[0030] The present application embodiment is a short-channel two-dimensional semiconductor device preparation method. Referring to Figure 1 , Figure 3 A short-channel two-dimensional semiconductor device preparation method, comprising the following steps: Step 1: A layer of graphene 2 is prepared on substrate 1, and the preparation method includes mechanical peeling method and chemical vapor deposition method; Step 2: A metal electrode 3 is prepared above the graphene 2 by a micron-level patterning method, and the patterning method includes laser direct writing method, and the metal electrode preparation method includes thermal evaporation method; Step 3: The graphene 2 is burned off in the middle by applying voltage on both sides of the metal electrode 3 through a source table; Step 4: A layer of poly(methyl methacrylate) 4 is uniformly coated on the metal electrode 3, and the entire substrate 1 is placed on a hot plate for heating treatment, and the treatment temperature is 150-200 ℃; Step five: the structure above substrate one 1 is lifted up as a whole, separated from substrate one 1, and transferred to above two-dimensional semiconductor 5 above substrate two 6; Step six: the whole structure of substrate two 6 is placed in an acetone solution to remove the uppermost polymethyl methacrylate 4; Step seven: a gate structure is prepared by a process method such as traditional atomic layer deposition and thermal evaporation, and the preparation of a short channel two-dimensional semiconductor field effect transistor is completed.
[0031] The preparation method has the advantages of simple process, clear structure, excellent device performance, etc., and the specific preparation process is as follows: Step one: preparing a graphene pattern on a substrate First, a clean Si / SiO2 substrate is selected as substrate one 1. The preparation of graphene 2 can be selected in one of two ways: one is mechanical exfoliation, preferably a high-quality natural graphite crystal is selected, and a tape and PDMS are used for the exfoliation operation of the graphite sheet in a clean environment. The obtained graphene sheet is transferred to the surface of substrate one 1. In order to ensure the transfer quality, optical microscope and Raman spectrum detection are performed after transfer to select the graphene region with single-layer or few-layer structure. The second is chemical vapor deposition (CVD), which uses methane as a carbon source to grow graphene on a copper foil, and then transfers it to substrate one 1 by a wet transfer process, and uses a patterned etching method to pretreat the graphene morphology.
[0032] Step two: metal electrode patterning preparation After the graphene pattern is completed, the laser direct writing technology is used to define the micron-scale pattern on the graphene surface to clearly define the pattern position of the metal electrode 3. This process has the characteristics of non-contact, high precision and high flexibility. Then, a metal layer is deposited by thermal evaporation, preferably a titanium / gold (Ti / Au) double-layer structure, in which the titanium layer has a thickness of 5-10 nm and is mainly used to enhance the adhesion of the electrode and the graphene interface; the gold layer has a thickness of 40-60 nm and is used to improve the conductivity of the overall electrode. After thermal evaporation is completed, the non-patterned area is removed by the Lift-off process to form a metal electrode 3 with a preset topography distributed at both ends of the graphene.
[0033] Step three: short channel formation by burning out the middle of graphene Next, a source table (SourceMeter) is used to apply a voltage at both ends of the metal electrode 3, with a voltage range of 5-15 V and a control application time of 1-3 seconds. By adjusting the current density, a local high-temperature breakdown occurs in the middle of the graphene channel, thereby forming a nanoscale gap in the middle of the graphene. This gap is the defined position of the subsequent two-dimensional semiconductor channel region, which can realize the control of the short channel characteristics of the device.
[0034] Step four: spin-coating a poly(methyl methacrylate) protective layer The above structure was placed in a spin-coating device, and a layer of poly(methyl methacrylate) (PMMA) 4 with a thickness of 100-300 nm was spin-coated on the surface as a transfer support layer. After spin-coating, the entire substrate 1 was placed on a hot plate with a temperature of 150-200 °C, and the heating treatment time was 3-10 minutes. This treatment can enhance the adhesion between PMMA and the device structure and improve its mechanical support capability.
[0035] Step five: overall transfer of the structure to the surface of a two-dimensional semiconductor After the PMMA layer was cured, the entire PMMA / metal electrode / graphene structure on the substrate 1 was peeled off using tweezers and slowly transferred to the surface of the two-dimensional semiconductor material 5 above the substrate 2 6. The two-dimensional semiconductor material, such as a single layer or a few layers of MoS2, WSe2, or black phosphorus, has excellent field effect characteristics and good electrical response performance. During the transfer process, it should be slow and precise, and the alignment position between the metal electrode and the two-dimensional semiconductor should be adjusted using a micro-manipulation device to ensure that the electrode is just above the two-dimensional material and covers the target area.
[0036] Step six: removal of the PMMA layer and cleaning of the interface The entire structure after transfer was immersed in acetone solution for 10-30 minutes to remove the uppermost PMMA support layer. Subsequently, isopropanol was used for cleaning, and then nitrogen was used for drying, obtaining a clean and complete metal electrode-graphene-two-dimensional semiconductor structure. To further improve the interface quality, vacuum annealing treatment can be selected to remove residual solvent molecules and water at the interface.
[0037] Step seven: preparation of the gate structure and completion of the device Finally, a gate structure was constructed on the surface of the substrate 2 6. The specific operation included: first, a layer of Al2O3 gate dielectric layer with a thickness of 10-30 nm was deposited using atomic layer deposition (ALD) technology. This material has excellent dielectric constant and low leakage performance, which helps to enhance the gate control ability of the device. Subsequently, a metal gate electrode was deposited using thermal evaporation method, and the metal can be selected from aluminum, gold, or molybdenum, etc. The gate pattern was pre-set controlled through a mask.
[0038] At this point, the preparation of the short-channel two-dimensional semiconductor device was completed, and the obtained device structure included, from bottom to top, the substrate 2 6, the two-dimensional semiconductor material 5, the middle broken graphene source-drain channel 2, the upper metal electrode 3, and the PMMA protective layer 4 covering the surface of the structure and serving as an auxiliary material for the manufacturing process. This device has excellent gate control performance, fast electrical response, and good structural compatibility, and is suitable for high-sensitivity field effect transistors, flexible electronic devices, and core device design of the next generation of low-power integrated circuits.
[0039] The implementation principle of the embodiment of the application is as follows: based on the excellent electrical characteristics of graphene and the excellent field effect regulation and control capability of two-dimensional semiconductors, the construction of a short channel structure is accurately realized by using electrical burnout and transfer processes, and then the preparation of a high-performance field effect transistor device is completed; the core of the method is to form a nanoscale gap as a channel region by a local burnout technology in the middle of the graphene channel; by structure overall transfer, the metal electrode / graphene segment structure is accurately placed on the two-dimensional semiconductor, and a gate structure is further constructed to realize effective regulation and control of the channel current; First, graphene is selected as the initial conductive channel material because it has extremely high electron mobility, atomic level thickness, and good patterning processing compatibility; after forming a complete graphene pattern on the substrate, a metal electrode is deposited on the graphene by micro-nano processing means, thereby forming a primary device structure with source and drain lead-out capability; then, a voltage is applied to the source table to drive high current density between the electrodes, causing local electrical breakdown in the middle of the graphene and forming a "nanoslit"; the nanoslit not only destroys the conduction but also reserves physical space for subsequent construction of a short channel structure; this method can break through the channel length limitation brought by traditional photolithography technology, shorten the channel length to the nanoscale range, and greatly improve the electrical response speed and on-off ratio of the device; After the formation of the above burnout structure, polymethyl methacrylate (PMMA) is applied as a supporting intermediate layer, the overall structure is fixed by spin coating and heat treatment, and then the structure is peeled off from the original substrate by mechanical means and transferred to the surface of a pre-prepared two-dimensional semiconductor material. Two-dimensional semiconductor materials (such as MoS2, WSe2, etc.) have the advantages of direct band gap, strong in-plane electron transport capability, and good electric field regulation and control capability at sub-nanometer thickness, and are ideal channel materials; the use of PMMA as an intermediate transfer medium can ensure that the pattern structure does not shift or deform significantly, thereby improving the transfer alignment accuracy and device consistency; After the transferred structure is firmly placed on the two-dimensional material, the PMMA layer is removed by acetone solution to restore the electrical connection capability and interface integrity of the device structure above it; the PMMA removal process is simultaneously treated by isopropanol cleaning and nitrogen blowing to effectively reduce the influence of solvent residues on the electrical performance of the device; if necessary, a post-processing process is introduced to remove interface impurities, which helps to improve the contact resistance and device stability; Finally, high-quality high-k gate dielectric materials (such as Al2O3) are deposited on the surface of the device by atomic layer deposition (ALD), and a metal gate is constructed by a thermal evaporation process to complete the complete field effect transistor structure; this gate structure can apply an external electric field to the two-dimensional semiconductor channel to effectively regulate and control the carrier concentration and migration channel, thereby having excellent switching behavior and amplification characteristics.
[0040] The embodiment of the application further discloses a short channel two-dimensional semiconductor device, referring to Figure 2 , comprising a semiconductor device body 7, a polymethyl methacrylate 4 and a substrate 2 at the bottom of the semiconductor device body 7, a two-dimensional semiconductor material 5 arranged on the upper part of the substrate 2, and two pieces of graphene 2 arranged on the upper end of the two-dimensional semiconductor material 5; two metal electrodes 3 are arranged on the upper end of the graphene 2, and the two metal electrodes 3 are arranged on the upper end of the corresponding graphene 2; the polymethyl methacrylate 4 covers the upper end and the side wall of the graphene 2 and the metal electrode 3 and the remaining gap; In a specific implementation, the lowermost layer of the device body 7 is the substrate 2, which can be made of a material with good flatness and thermal stability, such as a high-resistance silicon wafer, sapphire, glass, etc., which can be selected according to different application scenarios of the device. The substrate 2 is used to support the upper two-dimensional functional structure and ensure the mechanical stability and thermal compatibility of the whole device; On the upper part of the substrate 2, a layer of two-dimensional semiconductor material 5 is arranged, which is made of, for example, single-layer or few-layer molybdenum disulfide (MoS2), tungsten ditelluride (WTe2), tungsten diselenide (WSe2) or black phosphorus, etc. These materials have high mobility, good electric field response and suitable band gap, and are ideal materials for constructing short channel field effect devices. The two-dimensional semiconductor material 5 forms a heterojunction interface with the upper graphene electrode, thereby constituting a short channel device; On the two-dimensional semiconductor material 5, two pieces of graphene 2 are arranged on both ends of the channel region, and the graphene material is selected to be a single-layer graphene sheet which is mechanically peeled off or prepared by CVD and then transferred to the target position. The graphene 2 forms a nanoscale gap in the middle by the aforementioned electrical breakdown method, and the gap is defined as the short channel region. The two pieces of graphene serve as the source and drain, respectively, and are responsible for the injection and collection of electrons or holes; On the graphene 2, metal electrodes 3 are arranged, which are deposited by thermal evaporation and are reserved in the required position after being patterned by photolithography. A titanium / gold (Ti / Au) double-layer structure is preferably adopted to ensure that the metal electrodes 3 form a good ohmic contact with the graphene. The two metal electrodes 3 are arranged on the upper part of the corresponding two pieces of graphene 2, respectively, to complete the external leading-out structure of the source and drain electrodes, which ensures the alignment accuracy and current efficiency between the electrodes and the two-dimensional material; In order to ensure the overall stability and interface integrity of the device structure, a layer of polymethyl methacrylate (PMMA) 4 is arranged on the graphene 2 and the metal electrodes 3, which is deposited by spin coating and has a thickness of 200-300 nm. The PMMA layer is cured by heat treatment, and covers the upper end and the side wall of the graphene 2 and the metal electrode 3, and can also fill the remaining gap area, forming a packaging protective layer to prevent environmental pollutants and moisture from entering the active area of the device, thereby improving the stability and repeatability of the device in the air; Through this structural design, the short-channel two-dimensional semiconductor device in the embodiment of the present application has the following advantages: first, short-channel confinement is achieved through graphene nanogaps, thereby improving the switching speed and sensitivity of the device; second, the vertical stacking structure of metal-graphene-two-dimensional semiconductor achieves excellent electrical performance; third, the overall packaging structure of the device enhances environmental adaptability through PMMA, and has good integrability and practical application prospects.
[0041] The implementation principle of a short-channel two-dimensional semiconductor device in the embodiment of the present application is as follows: based on micro-nano device design concepts such as heterogeneous material interface control, electrode contact optimization, and channel length reduction, combined with the precise process of forming a short channel gap by electrical breakdown in the middle of graphene and the excellent electrical properties of two-dimensional semiconductor materials, a short-channel field-effect transistor device with a simple structure, sensitive response, and simple preparation is realized. Its core principles and operating mechanisms include the following aspects: 1. Short channel structure design principle The core of the short channel device is to reduce the effective channel length between the source and drain electrodes to enhance the electric field's ability to control carriers, increase switching speed, reduce the gate voltage threshold and increase the overall current density. In this embodiment, the short channel is achieved through artificial electrical breakdown technology in the middle of the graphene conductive channel. The specific operation is: applying voltage at both ends of the metal electrode to generate Joule heat in the local area of graphene, reaching the breakdown threshold, and finally forming a nanometer-scale gap. This gap not only blocks the original graphene conductive channel, but also guides the electric field at its upper and lower ends to pass through the middle two-dimensional semiconductor material to form a new type of lateral short channel. This design avoids complex graphical methods such as high-precision electron beam exposure, and greatly simplifies the preparation process; 2. Working mechanism of the vertical stacking structure of heterogeneous materials The device adopts a vertical stacking structure of metal / graphene / two-dimensional semiconductor, taking advantage of the advantages of different materials. The metal electrode is deposited on the graphene by thermal evaporation to form a stable ohmic contact. Due to its two-dimensional structure and high conductivity, graphene acts as a transition layer to effectively reduce the work function difference between the metal and the two-dimensional semiconductor, reduce the Schottky barrier effect, and thus enhance the electron injection efficiency. After the graphene breaks down, the gap in the middle exposes the two-dimensional semiconductor material underneath. Under the control of the gate electric field, the two-dimensional semiconductor material can effectively control the charge carriers. Because the channel region is extremely short, the carrier migration distance in this area is limited, exhibiting tunneling or quasi-ballistic transport characteristics, allowing the device to maintain high response speed and high current output even at low voltage. 3. Electron Control Mechanism of Two-Dimensional Semiconductor Channels Two-dimensional semiconductor materials such as MoS2, WSe2, etc. have high electron mobility and adjustable band gap, which are suitable for field effect devices. The two-dimensional semiconductor and the upper and lower graphene form a heterojunction. The charge transport path is mainly through the two-dimensional material channel at the gap. After the gate electric field is applied, the two-dimensional channel is controlled by the electric field, the control of the carrier concentration is realized, and the on-off switching function of the current is completed. The short channel length makes the electrons form a strong inversion layer under a small electric field, improves the transconductance and on-off ratio, and reduces the sub-threshold swing; Four, encapsulation and interface stability improvement principle The polymethyl methacrylate (PMMA) layer as an auxiliary encapsulation material is spin-coated on the metal electrode and graphene to improve the mechanical strength of the overall structure, isolate the influence of water vapor, oxygen and pollutants on the active area of the device surface, prevent performance degradation caused by long-term exposure of the device in the air, and at the same time, buffer the environmental mechanical disturbance and improve the adaptability of the device in the flexible electronic or wearable electronic system. Five, device electrical performance advantage embodiment Due to the extremely short channel, the time of electrons passing through the two-dimensional material is extremely short, so the device shows good high-frequency response characteristics. The ohmic contact between graphene and metal ensures low contact resistance, enhancing the overall conductivity and sensitivity of the device. The quantum confinement effect of two-dimensional materials further improves the applicability of the device in the small signal detection and amplification field.
[0042] The above are preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Therefore, any equivalent changes made in terms of structure, shape and principle based on the present application should be covered within the protection scope of the present application.
Claims
1. A method for preparing a short-channel two-dimensional semiconductor device, characterized in that: The following steps are involved: Step 1: preparing a layer of graphene (2) on substrate 1 (1), wherein the preparation method includes mechanical exfoliation method and chemical vapor deposition method; Step 2: preparing a metal electrode (3) on the graphene (2) by a micron-level precision patterning method, wherein the patterning method includes a laser direct writing method and an ultraviolet exposure method, and the metal electrode preparation method includes a thermal evaporation method; Step 3: Apply voltage to both sides of the metal electrode (3) through the source meter to burn the middle of the graphene (2); Step 4: evenly coat a layer of polymethyl methacrylate (4) on the metal electrode (3), and place the entire substrate (1) on a hot plate for heating at a temperature of 150-200°C; Step 5: Use metal tweezers to lift up the entire structure above substrate one (1), separate it from substrate one (1), and transfer it to the top of the two-dimensional semiconductor (5) above substrate two (6); Step 6: Place the entire structure of substrate 2 (6) in an acetone solution to remove the topmost polymethyl methacrylate (4); Step 7: Prepare the gate structure through traditional atomic layer deposition and thermal evaporation methods to complete the preparation of the short-channel two-dimensional semiconductor field-effect transistor.
2. The method for preparing a short channel two-dimensional semiconductor device according to claim 1, wherein: When the graphene (2) is prepared by a mechanical exfoliation method, the raw material used is high-quality graphite crystal, and the graphene is transferred to the surface of the substrate (1) by using a tape and PDMS-assisted transfer method.
3. The method for preparing a short channel two-dimensional semiconductor device according to claim 1, wherein: The metal electrode (3) is a titanium / gold double-layer structure, wherein the thickness of the titanium layer is 5-10 nm and the thickness of the gold layer is 40-60 nm.
4. The method for preparing a short channel two-dimensional semiconductor device according to claim 1, wherein: In the third step of burning the middle of the graphene, the applied voltage is 5-15 V and the duration is 1-3 seconds, so as to control the graphene fracture position to be located at the center between the metal electrodes.
5. The method for preparing a short channel two-dimensional semiconductor device according to claim 1, wherein: The spin coating thickness of the polymethyl methacrylate (4) is 100-300 nm, and the heating treatment time is 3-10 minutes.
6. The method for preparing a short channel two-dimensional semiconductor device according to claim 1, wherein: The two-dimensional semiconductor (5) is a single layer or a few layers of MoS2, WSe2 or black phosphorus.
7. The method for preparing a short channel two-dimensional semiconductor device according to claim 1, wherein: The gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer is an Al2O3 thin film made by atomic layer deposition, and the gate electrode is composed of a metal layer formed by thermal evaporation.
8. A short-channel two-dimensional semiconductor device, characterized in that: The semiconductor device comprises a main body 7, wherein polymethyl methacrylate (4) and a second substrate (6) are provided at the bottom of the main body (7), a two-dimensional semiconductor material (5) is stacked on the upper part of the second substrate (6), and two graphenes (2) are laid on the upper end of the two-dimensional semiconductor material (5); Two metal electrodes (3) are provided on the upper end of the graphene (2), and the two metal electrodes (3) are provided on the upper end of the graphene (2) at corresponding positions; The polymethyl methacrylate (4) covers the upper ends and side walls of the graphene (2) and the metal electrode (3) and the remaining gaps.
9. The short channel two-dimensional semiconductor device according to claim 8, wherein: The two-dimensional semiconductor material (5) is a single layer or a few layers of molybdenum disulfide (MoS2), tungsten diselenide (WSe2) or black phosphorus.
10. The short channel two-dimensional semiconductor device according to claim 8, wherein: The metal electrode (3) is a titanium / gold composite structure, wherein the titanium layer is used to improve interface contact, and the gold layer is used to improve conductivity. The thickness of the titanium layer is 5-10 nm, and the thickness of the gold layer is 40-60 nm.