Image sensor and preparation method thereof

Abstract

The invention provides an image sensor and a preparation method thereof, and the method comprises the steps: providing a substrate, and sequentially forming a sacrificial layer and an epitaxial layer on the substrate; supporting columns of the epitaxial layer and the sacrificial layer are formed, the supporting columns further extend in the first direction, and the first direction is perpendicular to the thickness direction of the substrate; etching the epitaxial layer to form at least one release groove exposing part of the sacrificial layer; taking the release groove as a release channel, and etching to remove the sacrificial layer so as to form a cavity between the epitaxial layer and the substrate; a capacitor structure is formed in the cavity, and the capacitor structure comprises a first electrode layer, a second electrode layer and a dielectric layer arranged between the first electrode layer and the second electrode layer; a pixel array comprising a plurality of pixel units is formed in the epitaxial layer, each pixel unit comprises at least one photodiode region, at least one floating diffusion region and at least one transistor, the photodiode regions and the floating diffusion regions are arranged at intervals, and one side, far away from the capacitor structure, of each photodiode region is a light incident side.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to an image sensor and a preparation method thereof. BACKGROUND

[0002] The sensing technology of a Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) has been widely used in applications such as a still digital camera, a digital video camera, a medical camera device, and a vehicle camera device. The CMOS image sensor is mainly divided into two structures of a front side illumination CMOS image sensor (FSI) and a backside illumination CMOS image sensor (BSI). With the development of microelectronic technology, in order to improve the overall performance of the image sensor to achieve faster operation speed, larger data storage capacity, and more functions, the capacity requirement of the capacitor in the device is higher and higher.

[0003] A Metal-Insulator-Metal Capacitor (MIM) capacitor structure has a high capacitance value, and is widely used as a storage charge, coupling, and filter device. The MIM capacitor structure includes an upper electrode plate, a lower electrode plate, and a dielectric layer sandwiched between the upper electrode plate and the lower electrode plate, and the capacitance value of the MIM capacitor structure is proportional to the area of the electrode plate.

[0004] In the related art, the front side illumination CMOS image sensor places the MIM capacitor structure in the metal layer of the back-end-of-line (BEOL), however, light needs to pass through the metal layer to reach the photodiode (PD) region, which will hinder a part of the light from entering the photodiode (PD) region, reduce the photosensitive efficiency of the photodiode (PD), and affect the sensitivity of the image sensor, thereby reducing the quality of the image. SUMMARY

[0005] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solution, and even less to determine the protection scope of the claimed technical solution.

[0006] To solve the problems, the application provides a preparation method of an image sensor, which comprises the following steps: providing a substrate, sequentially forming a sacrificial layer and an epitaxial layer on the substrate, forming support columns penetrating through the epitaxial layer and the sacrificial layer, and the support columns also extend along a first direction, and the first direction is perpendicular to the thickness direction of the substrate, etching the epitaxial layer to form at least one release groove exposing part of the sacrificial layer, etching and removing the sacrificial layer to form a cavity between the epitaxial layer and the substrate by taking the release groove as a release channel, forming a capacitor structure in the cavity, wherein the capacitor structure comprises a first electrode layer, a second electrode layer and a dielectric layer arranged between the first electrode layer and the second electrode layer, forming a pixel array comprising a plurality of pixel units in the epitaxial layer, and each pixel unit comprises at least one photodiode region, at least one floating diffusion region and at least one transistor, and the photodiode region and the floating diffusion region are arranged apart, and the side of the photodiode region away from the capacitor structure is a light-in side.

[0007] Exemplarily, the step of forming the capacitor structure in the cavity comprises the following steps: forming an electrode material layer in the cavity, wherein the electrode material layer arranged on the side of the epitaxial layer facing the substrate is the first electrode layer, the electrode material layer arranged on the side of the substrate facing the epitaxial layer is the second electrode layer, and the first electrode layer and the second electrode layer have a spatial interval; and forming the dielectric layer to fill the spatial interval.

[0008] Exemplarily, before the step of forming the capacitor structure, the method further comprises the following steps: forming an isolation layer covering the surface of the substrate facing the epitaxial layer, the surface of the epitaxial layer, the sidewall of the release groove and part of the sidewall of the support column, wherein the first electrode layer covers the isolation layer on the side of the epitaxial layer facing the substrate, and the second electrode layer covers the isolation layer on the side of the substrate facing the epitaxial layer; the electrode material layer arranged in the release groove is used as a first electrode lead wire, the first electrode lead wire is electrically connected with the first electrode layer, and the dielectric layer also fills the release groove.

[0009] Exemplarily, the electrode material layer also covers the isolation layer exposed in the cavity and located on the sidewall of the support column, and the method further comprises the following steps: after the step of forming the dielectric layer, removing the support column and part of the isolation layer, part of the electrode material layer, part of the dielectric layer and part of the epitaxial layer located outside the sidewall of the support column to form an isolation groove and electrically isolate the first electrode layer from the second electrode layer; and filling an insulating material in the isolation groove to form an insulating isolation structure.

[0010] Illustratively, after forming the capacitor structure and before forming the pixel array, the method further includes: forming at least one second electrode wire passing through the epitaxial layer, the first electrode layer and the dielectric layer, the second electrode wire being electrically connected to the second electrode layer.

[0011] Exemplarily, the step of forming at least one second electrode wire passing through the epitaxial layer, the first electrode layer and the dielectric layer includes: etching the epitaxial layer, the first electrode layer and the dielectric layer to form at least one contact hole, wherein the bottom of the contact hole is located in the second electrode layer; forming an insulating isolation layer on the side wall of the contact hole; filling the contact hole with a conductive material to form the second electrode wire, and the second electrode wire is also extended along the first direction, wherein at least one second electrode wire is located between two adjacent pixel units in the second direction; each release groove is arranged between two adjacent pixel units in the first direction, and the release groove also extends along the second direction, and a first electrode wire is formed on the side wall of the release groove, and the first electrode wire is electrically connected to the first electrode layer; wherein the first direction and the second direction are perpendicular to each other, the first electrode wire and the second electrode wire are electrically isolated, and the two cross.

[0012] Exemplarily, the transistor includes a gate structure formed on the epitaxial layer. After the pixel array is formed, it also includes: forming an interlayer dielectric layer covering the epitaxial layer and the gate structure, and forming a metal wiring layer in the interlayer dielectric layer; forming a passivation layer on the interlayer dielectric layer, and forming multiple grid structures on the passivation layer, wherein a grid structure is arranged between adjacent pixel units, and grid openings are formed between adjacent grid structures, and the grid openings expose the surface of the passivation layer; embedding a color filter film layer in the grid opening; and forming multiple microlenses on the color filter film layer, and the multiple microlenses correspond to the multiple pixel units.

[0013] On the other hand, the present application provides an image sensor, comprising: a substrate; a capacitor structure, wherein the capacitor structure is arranged on the surface of the substrate, wherein the capacitor structure includes a first electrode layer, a second electrode layer, and a dielectric layer arranged between the first electrode layer and the second electrode layer; an epitaxial layer, wherein the epitaxial layer is arranged on the capacitor structure; a pixel array including a plurality of pixel units is formed in the epitaxial layer, each of the pixel units includes: at least one photodiode region, at least one floating diffusion region, and at least one transistor, the photodiode region and the floating diffusion region are arranged at intervals, and the side of the photodiode region away from the capacitor structure is the light incident side.

[0014] Exemplarily, the image sensor further comprises an isolation layer arranged between the first electrode layer and the epitaxial layer, and between the second electrode layer and the substrate; at least one first electrode wire penetrating through the epitaxial layer and electrically connected with the first electrode layer; at least one second electrode wire penetrating through the epitaxial layer, the first electrode layer and the dielectric layer, and electrically connected with the second electrode layer, the first electrode wire and the second electrode wire being electrically isolated; wherein the first electrode wire is arranged between two adjacent pixel units arranged at a first direction, and the first electrode wire extends along a second direction, the second electrode wire is arranged between two adjacent pixel units arranged at a second direction, and the second electrode wire extends along the first direction, the first direction and the second direction being perpendicular to each other.

[0015] Exemplarily, the transistor comprises a gate structure arranged on the epitaxial layer, and the image sensor further comprises an interlayer dielectric layer covering the epitaxial layer and the gate structure, wherein a metal wiring layer is formed in the interlayer dielectric layer; a passivation layer located on the interlayer dielectric layer; a plurality of grid structures located on the passivation layer, wherein a grid structure is arranged between adjacent pixel units, and a grid opening is formed between adjacent grid structures, the grid opening exposing the surface of the passivation layer; a color filter layer embedded in the grid opening; and a plurality of microlenses located on the color filter layer, the plurality of microlenses corresponding to the plurality of pixel units.

[0016] The image sensor and the preparation method thereof provided by the present application can effectively avoid the situation that the capacitor structure blocks the incident light from entering the photodiode region, reduce the light loss, improve the photosensitive efficiency of the photodiode, thereby improving the sensitivity of the image sensor and the quality of the image. BRIEF DESCRIPTION OF DRAWINGS

[0017] The following drawings of the present application are hereby included as a part of the present application for the purpose of understanding the present application. The embodiments of the present application and its description are shown in the drawings to explain the principles of the present application.

[0018] In the drawings: Figure 1 A flow chart of the image sensor preparation method according to an embodiment of the present application is shown in the figure; Figures 2 to 23The method of fabricating an image sensor according to an embodiment of the present application is shown in the sequence of the schematic diagrams of the resulting devices. DETAILED DESCRIPTION

[0019] The present application will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. This application may, however, be embodied in different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as non-limiting examples so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions can be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0020] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0021] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] For a thorough understanding of the application, detailed descriptions will be made in the following description with specific steps and structures to illustrate the technical solutions presented by the application. The preferred embodiments of the application are described in detail as follows, however, in addition to these detailed descriptions, the application can also have other implementation manners.

[0024] In the related art, the CMOS front-illuminated image sensor is to place the MIM capacitor structure in the metal layer of the back-end-of-line (BEOL), and the photodiode (PD) region is located below the metal layer. Therefore, the incident light needs to pass through the metal layer to reach the photodiode (PD) region below, so the MIM capacitor structure in the metal layer will hinder a part of the incident light from entering the photodiode (PD) region, reducing the photosensitive efficiency of the photodiode (PD) and affecting the sensitivity of the image sensor, thereby reducing the quality of the image.

[0025] Therefore, in view of the existence of the foregoing technical problems, the application presents a preparation method of an image sensor, as shown in Figure 1 The preparation method mainly includes the following steps: Step S1, providing a substrate, and sequentially forming a sacrificial layer and an epitaxial layer on the substrate; Step S2, forming a support column penetrating through the epitaxial layer and the sacrificial layer, and the support column is also arranged in extension along a first direction, and the first direction is perpendicular to the thickness direction of the substrate; Step S3, etching the epitaxial layer to form at least one release groove exposing part of the sacrificial layer; Step S4, taking the release groove as a release channel, etching to remove the sacrificial layer to form a cavity between the epitaxial layer and the substrate; Step S5, forming a capacitor structure in the cavity, wherein the capacitor structure includes a first electrode layer, a second electrode layer, and a dielectric layer arranged between the first electrode layer and the second electrode layer; Step S6, forming a pixel array including a plurality of pixel units in the epitaxial layer, each pixel unit including: at least one photodiode region, at least one floating diffusion region, and at least one transistor, the photodiode region and the floating diffusion region being arranged apart, and the photodiode region being away from a side of the capacitor structure facing the light.

[0026] The preparation method of the image sensor of the embodiment of the present application forms a cavity between the substrate and the epitaxial layer, and forms a capacitor structure in the cavity, and then forms a photodiode region in the epitaxial layer. Since the capacitor structure is away from the light-incident side (i.e. the non-light-incident side) of the photodiode region, the capacitor structure can effectively avoid blocking the incident light from entering the photodiode region, reduce light loss, improve the photosensitive efficiency of the photodiode, thereby improving the sensitivity of the image sensor, and further improving the quality of the image.

[0027] Embodiment One Hereinafter, the preparation method of the image sensor of the present application will be described in detail with reference to the accompanying drawings. Figure 1 and Figures 2 to 23 The preparation method of the image sensor of the present application will be described in detail, wherein, Figure 1 The flow chart of the preparation method of the image sensor of the embodiment of the present application is shown, Figures 2 to 23 The schematic diagram of the device obtained by sequentially implementing the preparation method of the image sensor of the embodiment of the present application is shown, wherein, Figures 4 to 16 In each drawing, (a) shows the top view schematic diagram of the device obtained by sequentially implementing the preparation method of the image sensor of the embodiment of the present application, and (b) shows the cross-sectional schematic diagram of the device obtained by sequentially implementing the preparation method of the image sensor of the embodiment of the present application.

[0028] Exemplarily, the preparation method of the image sensor of the present application includes the following steps: Firstly, step S1 is performed to provide a substrate, and a sacrificial layer and an epitaxial layer are sequentially formed on the substrate.

[0029] In one example, as Figure 2As shown, a substrate 201 is provided. The material of substrate 201 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors, or silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). It can also be a ceramic substrate such as double-side polished silicon wafers (DSPs), alumina, quartz, or glass substrate. Although several examples of materials that can form the substrate are described here, any material that can be used as a substrate falls within the spirit and scope of the present invention. In this embodiment, substrate 201 is a silicon substrate.

[0030] In one example, if Figure 3 As shown, a sacrificial layer 202 is formed on a substrate 201. Exemplarily, the material of the sacrificial layer 202 includes, but is not limited to, amorphous silicon, polycrystalline silicon, silicon germanium (SiGe), or other suitable materials. The process for forming the sacrificial layer 202 can be selected as needed, such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable epitaxial techniques, which are not specifically limited. In this embodiment, the material of the sacrificial layer 202 is silicon germanium. The sacrificial layer facilitates the subsequent formation of a cavity between the substrate 201 and the epitaxial layer, thereby forming a capacitor structure within the cavity.

[0031] In one example, if Figure 3 As shown, an epitaxial layer 203 is continuously formed on the sacrificial layer 202. Exemplarily, the material of the epitaxial layer 203 includes, but is not limited to, silicon, silicon germanium, silicon carbide, or other suitable epitaxial materials. The process method for forming the epitaxial layer 203 can be selected as needed, such as metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), molecular beam epitaxy (MBE), or other suitable techniques, which are not specifically limited. In this embodiment, the material of the epitaxial layer 203 is silicon, the same as the material of the substrate 201. Therefore, the silicon formed by epitaxial growth can have the same crystal structure and orientation as the substrate, which helps maintain high-quality electronic properties.

[0032] Next, step S2 is performed to form a support column penetrating the epitaxial layer and the sacrificial layer, and the support column is further extended along a first direction perpendicular to the thickness direction of the substrate.

[0033] In one example, if Figure 4 and Figure 5As shown, the step of forming the support columns 205 through the epitaxial layer 203 and the sacrificial layer 202 includes: First, the sacrificial layer 202 and the epitaxial layer 203 are etched to form support grooves 204 through the sacrificial layer 202 and the epitaxial layer 203, and the support grooves 204 extend along a first direction. Specifically, a patterned photoresist layer is formed on the surface of the epitaxial layer 203, the photoresist layer exposes the area and position corresponding to the support grooves 204, and the epitaxial layer 203 and the sacrificial layer 202 are etched to form the support grooves 204 with the photoresist layer as a mask, the support grooves 204 pass through the sacrificial layer 202 and the epitaxial layer 203 and expose part of the surface of the substrate 201, and then the photoresist layer is removed; wherein the etching of the sacrificial layer 202 and the epitaxial layer 203 can be selected from dry etching, reactive ion etching (RIE), ion beam etching, plasma etching and other conventional etching processes.

[0034] Next, the support columns 205 are formed in the support grooves 204. Specifically, a support material is filled in the support grooves 204, wherein the support material includes but is not limited to silicon oxide, silicon nitride, polysilicon or other suitable materials. The process method for forming the support columns 205 includes but is not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDP-CVD) or physical vapor deposition (PVD) and the like, which are not specifically limited. The formed support columns 205 are arranged along the first direction and located in the epitaxial layer 203 and the sacrificial layer 202, and the first direction is perpendicular to the thickness direction of the substrate. After forming the support columns 205, the support material can also be subjected to a planarization treatment, for example, using chemical mechanical polishing (CMP) to remove excess support material on the epitaxial layer 203, so that the epitaxial layer 203 has a flat surface. The number of support columns can be reasonably set according to actual needs, for example, it can be 1, 2, 3 or more, wherein preferably, the support columns are formed in the edge region of the epitaxial layer to avoid occupying too much device area in the middle region. In one specific example, the number of support columns is two, and the two support columns are arranged in the second direction. Exemplarily, a support column is arranged between any two pixel units.

[0035] Continuing, step S3 is performed to etch the epitaxial layer to form at least one release trench 240 exposing part of the sacrificial layer.

[0036] In one example, as Figure 6As shown, the epitaxial layer 203 is etched to form at least one release groove 240 that exposes a portion of the sacrificial layer 202, and the release groove 240 also extends along the second direction. Specifically, a patterned photoresist layer is formed on the surface of the epitaxial layer 203, the photoresist layer exposing the area and position of the epitaxial layer corresponding to the release groove 240 to be formed. The epitaxial layer 203 is etched using the photoresist layer as a mask to form at least one release groove 240 extending along the second direction, the release groove 240 exposing a portion of the surface of the sacrificial layer 202, and then the photoresist layer is removed. The etching of the epitaxial layer 203 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, etc., which are not specifically limited. The release groove 240 is also provided between two adjacent pixel units in the first direction that will be formed later. The first direction is perpendicular to the thickness direction of the substrate 201, and the second direction is perpendicular to the first direction. The second direction is also perpendicular to the thickness direction of the substrate 201.

[0037] Next, step S4 is performed to etch away the sacrificial layer using the release groove as a release channel to form a cavity between the epitaxial layer and the substrate.

[0038] In one example, if Figure 7 As shown, the release groove 240 is used as a release channel to etch away the sacrificial layer 202 to form a cavity 206 between the epitaxial layer 203 and the substrate 201. Specifically, conventional etching processes such as, but not limited to, dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, and wet etching can be used to remove the sacrificial layer 202 between the epitaxial layer 203 and the substrate 201. For example, a gaseous hydrofluoric acid (Vapor HF, VHF) etching process can be used to release the sacrificial layer 202, that is, gaseous hydrofluoric acid is introduced into the release groove, and the sacrificial layer 202 is etched away through the release groove 240, thereby forming the cavity 206 between the epitaxial layer 203 and the substrate 201.

[0039] Then, step S5 is performed to form a capacitor structure in the cavity, wherein the capacitor structure includes a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first electrode layer and the second electrode layer.

[0040] In one example, if Figure 8As shown, before forming the capacitor structure, further comprising: forming an isolation layer 207 covering the surface of the substrate 201 facing the epitaxial layer 203, the surface of the epitaxial layer 203, the sidewall of the release trench 240 and part of the sidewall of the support column 205. Exemplarily, the material of the isolation layer 207 includes but is not limited to oxide, such as silicon oxide, etc., which is not specifically limited. The process method of forming the isolation layer 207 includes but is not limited to chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD), etc., which is not specifically limited. Among them, the isolation layer can provide a physical barrier to prevent damage caused by subsequent processing, thereby improving the reliability and stability of the device, and it can also play an insulating role.

[0041] In one example, as shown in FIG. 6, the electrode material layer 208 is formed in the cavity 206, wherein the electrode material layer 208 disposed on the side of the epitaxial layer 203 facing the substrate 201 is the first electrode layer 2081, and the electrode material layer 208 disposed on the side of the substrate 201 facing the epitaxial layer 203 is the second electrode layer 2082, and the first electrode layer 2081 and the second electrode layer 2082 have a spatial interval. Exemplarily, the material of the electrode material layer 208 includes but is not limited to titanium nitride, tungsten, copper, aluminum or other suitable electrode materials. The process method of forming the electrode material layer 208 includes but is not limited to physical vapor deposition (PVD), atomic layer deposition (ALD) or chemical vapor deposition (CVD), etc., which is not specifically limited. Figure 9

[0042] The electrode material layer 208 covers the isolation layer 207 on the side of the epitaxial layer 203 facing the substrate 201 through the release trench 240 to form the first electrode layer 2081, and the electrode material layer 208 covers the isolation layer 207 on the side of the substrate 201 facing the epitaxial layer 203 through the release trench 240 to form the second electrode layer 2082. Among them, the electrode material layer 208 also covers the isolation layer 207 exposed on the sidewall of the support column 205 in the cavity 206 through the release trench 240, and the electrode material layer 208 also covers the isolation layer 207 on the side of the epitaxial layer 203 away from the substrate 201.

[0043] In one example, as shown in FIG. 6, the electrode material layer 208 is formed in the cavity 206, wherein the electrode material layer 208 disposed on the side of the epitaxial layer 203 facing the substrate 201 is the first electrode layer 2081, and the electrode material layer 208 disposed on the side of the substrate 201 facing the epitaxial layer 203 is the second electrode layer 2082, and the first electrode layer 2081 and the second electrode layer 2082 have a spatial interval. Exemplarily, the material of the electrode material layer 208 includes but is not limited to titanium nitride, tungsten, copper, aluminum or other suitable electrode materials. The process method of forming the electrode material layer 208 includes but is not limited to physical vapor deposition (PVD), atomic layer deposition (ALD) or chemical vapor deposition (CVD), etc., which is not specifically limited. Figure 10 ​As shown, the dielectric layer 209 is formed to fill the space gap. Specifically, the dielectric layer 209 is formed in the space gap. Exemplarily, the material of the dielectric layer 209 includes but is not limited to aluminum oxide, hafnium oxide (HfO), zirconium oxide (Zr2O3), silicon oxide, barium strontium titanate or other suitable dielectric materials. The process method for forming the dielectric layer 209 includes but is not limited to physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD) or thermal oxidation, etc., which are not specifically limited. Specifically, the formed dielectric layer 209 covers the surface of the electrode material layer 208, fills the space gap through the release groove 240, and is also located between the first electrode layer 2081 and the second electrode layer 2082.

[0044] In one example, if Figures 11 to 13 As shown, after forming the dielectric layer 209, the steps of removing the support pillar 205 and the portion of the isolation layer 207, the portion of the electrode material layer 208, the portion of the dielectric layer 209, and the portion of the epitaxial layer 203 outside the sidewall of the support pillar 205 to form the isolation trench 210 include: First, if Figure 11 As shown, a portion of the isolation layer 207, a portion of the electrode material layer 208, and a portion of the dielectric layer 209 outside the sidewalls of the support pillar 205 and on the epitaxial layer 203 are removed. Specifically, a chemical mechanical polishing method can be used, but is not limited to, to remove the portion of the isolation layer 207, a portion of the electrode material layer 208, and a portion of the dielectric layer 209 outside the sidewalls of the support pillar 205 and on the epitaxial layer 203. Then, a wet cleaning method can be performed to remove the residual materials during the chemical mechanical polishing process to avoid affecting the performance of the device.

[0045] Then, if Figure 12 and Figure 13As shown, the support pillars 205 are removed and the electrode material layer 208 and the dielectric layer 209 are etched to form isolation trenches 210. First, the support pillars 205 can be removed by conventional etching processes such as, but not limited to, dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, and wet etching. Next, a patterned photoresist layer is formed on the epitaxial layer 203, and the photoresist layer exposes the area and position corresponding to the isolation groove 210. The epitaxial layer 203, the isolation layer 207, the electrode material layer 208 and the dielectric layer 209 are etched using the photoresist layer as a mask to form the isolation groove 210. The isolation groove 210 penetrates the epitaxial layer 203, the isolation layer 207, the electrode material layer 208 and the dielectric layer 209 to expose part of the surface of the substrate 201, and then the photoresist layer is removed. The etching of the epitaxial layer 203, the isolation layer 207, the electrode material layer 208 and the dielectric layer 209 can be carried out by conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, etc., which are not specifically limited. The isolation trench 210 electrically isolates the first electrode layer 2081 from the second electrode layer 2082, and the first electrode layer 2081, the dielectric layer 209, and the second electrode layer 2082 form a capacitor structure 230. Forming the capacitor structure 230 in the cavity 206 prevents the capacitor structure from blocking incident light from entering the photodiode region, thereby increasing the sensitivity of the image sensor and improving image quality.

[0046] In one example, if Figure 14 As shown, after forming the isolation trench 210, the process further includes: filling the isolation trench 210 with an insulating material to form an insulating isolation structure 211. Exemplarily, the material of the insulating isolation structure 211 includes, but is not limited to, oxides such as silicon oxide, etc., which are not specifically limited. The process methods for forming the insulating isolation structure 211 include, but are not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) and other methods, which are not specifically limited. After forming the insulating isolation structure 211, the epitaxial layer 203 can be planarized, for example, by using chemical mechanical polishing (CMP) to remove excess insulating material on the epitaxial layer 203, so that the epitaxial layer 203 has a flat surface, thereby improving the reliability of the device.

[0047] In one example, if Figure 15 and Figure 16 As shown, after forming the capacitor structure 230 and before forming the pixel array, the step of forming at least one second electrode wire 2101 penetrating the epitaxial layer 203, the first electrode layer 2081 and the dielectric layer 209 includes: First, if Figure 15As shown, the epitaxial layer 203, the first electrode layer 2081 and the dielectric layer 209 are etched to form at least one contact hole 212, wherein the bottom of the contact hole 212 is located in the second electrode layer 2082 (including contacting the surface of the second electrode layer 2082 or located below the surface). Specifically, a patterned photoresist layer is formed on the epitaxial layer 203, the photoresist layer exposing the area and position corresponding to the contact hole 212; the photoresist layer is used as a mask to etch the epitaxial layer 203, the isolation layer 207, the first electrode layer 2081, and the dielectric layer 209 to form at least one contact hole 212, the bottom of the contact hole 212 being located in the second electrode layer 2082, each contact hole 212 extending along a first direction, and the formed contact hole 212 is also located between two adjacent pixel units subsequently formed in the second direction, and then the photoresist layer is removed; the etching of the epitaxial layer 203, the isolation layer 207, the first electrode layer 2081, and the dielectric layer 209 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, etc., which are not specifically limited. The first direction is perpendicular to the thickness direction of the substrate 201, and the first direction and the second direction are perpendicular to each other. The formed contact hole 212 is used for subsequently forming the second electrode wire 2101 to form an electrical connection with the second electrode layer 2082. Optionally, the top view shape of the contact hole 212 is a strip, square, circle or other suitable shape.

[0048] Then, if Figure 16 As shown, before forming the second electrode conductor 2101, the method of the present application further includes filling the contact hole 212 with an insulating material, with the insulating material covering the sidewalls of the contact hole 212 to form an insulating isolation layer 213. The insulating material includes, but is not limited to, oxides such as silicon oxide, and is not specifically limited to this. The process methods for forming the insulating isolation layer 213 include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The insulating isolation layer 213 can be used to electrically isolate the second electrode conductor 2101 from the epitaxial layer outside it, as well as to electrically isolate it from the first electrode conductor.

[0049] Then, if Figure 16As shown, the contact hole 212 is filled with a conductive material to form the second electrode wire 2101, and the conductive material includes, but is not limited to, titanium nitride, tungsten, copper, aluminum or other suitable conductive material. The process method for forming the second electrode wire 2101 includes, but is not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD) or chemical vapor deposition (CVD) and the like, which is not limited specifically. The conductive material fills the contact hole 212 to form at least one second electrode wire 2101, so that the formed second electrode wire 2101 is arranged along the first direction, and the at least one second electrode wire 2101 is located between two adjacent pixel units formed subsequently in the second direction, wherein the bottom of the second electrode wire 2101 is located in the second electrode layer 2082. After forming the second electrode wire 2101, a planarization process can also be performed to remove the excess insulating material and conductive material on the epitaxial layer 203, for example, using chemical mechanical polishing (CMP) to remove the excess insulating material and conductive material on the epitaxial layer 203, so that the epitaxial layer 203 has a flat surface, improving the reliability of the device.

[0050] In one example, at least one first electrode wire 2100 (i.e., the electrode material layer 208 covering the isolation layer 207 on the side wall of the release trench 240) is formed on the side wall of the release trench 240, the first electrode wire 2100 and the first electrode layer 2081 are electrically connected, and the dielectric layer 209 also fills the release trench 240. The formed first electrode wire 2100 and the second electrode wire 2101 are electrically isolated and cross each other.

[0051] Finally, step S6 is performed to form a pixel array including a plurality of pixel units in the epitaxial layer, each pixel unit including: at least one photodiode region, at least one floating diffusion region and at least one transistor, and the photodiode region and the floating diffusion region are arranged separately.

[0052] In one example, as shown in Figure 17 and Figure 18 As shown, the step of forming a pixel array including a plurality of pixel units in the epitaxial layer 203 includes: First, at least one photodiode region 214 is formed in the epitaxial layer 203. Specifically, a patterned photoresist layer is formed on the epitaxial layer 203, the patterned photoresist layer defines the area of the photodiode region (PD), the epitaxial layer 203 is ion implanted with the patterned photoresist layer as a mask, so as to form at least one photodiode region 214 in the epitaxial layer 203, each photodiode region 214 extends from the surface of the epitaxial layer 203 into the epitaxial layer 203, and then the photoresist layer is removed. The type and concentration of ion implantation are selected according to actual conditions, and are not specifically limited. The function of the photodiode region is to convert the incident light signal into an electrical signal and accumulate electric charge in the subsequent image sensor.

[0053] It is worth mentioning that the pixel array including a plurality of pixel units formed in the epitaxial layer 203 can refer to part of the structure of the pixel unit located in the epitaxial layer 203, and part of the structure located on the epitaxial layer, such as the gate structure of the transistor.

[0054] Next, at least one floating diffusion region 215 is formed in the epitaxial layer 203. Specifically, a patterned photoresist layer is formed on the epitaxial layer 203, the patterned photoresist layer defines the area of the floating diffusion region (FD), the epitaxial layer 203 is ion implanted with the patterned photoresist layer as a mask, so as to form at least one floating diffusion region 215 in the epitaxial layer 203, each floating diffusion region 215 extends from the surface of the epitaxial layer 203 into the epitaxial layer 203 and is arranged in a spaced manner with the photodiode region 214, and then the photoresist layer is removed. The floating diffusion region is used to collect the electric charge transferred from the photodiode and convert it into a voltage signal for the key part of the readout circuit processing.

[0055] It should be noted that after ion implantation, annealing treatment is also performed. Due to the ion implantation process, the silicon lattice will be damaged, and annealing can repair these damages. In addition, annealing can also activate the implanted ions, thereby improving the performance of the image sensor.

[0056] Finally, the transistor is formed. The step of forming the transistor can include: First, an active area is defined by shallow trench isolation (STI) or local oxidation (LOCOS) to isolate adjacent pixels; then, a gate structure 216 is formed on the epitaxial layer 203. Specifically, first, a gate dielectric layer is formed on the epitaxial layer 203. The material of the gate dielectric layer includes but is not limited to silicon dioxide, and the method of forming the gate dielectric layer includes but is not limited to chemical vapor deposition (CVD) or thermal oxidation; second, a gate layer is formed on the gate dielectric layer. The material of the gate layer includes but is not limited to polysilicon, and the method of forming the gate layer includes but is not limited to chemical vapor deposition (CVD) or thermal oxidation. Methods such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) are used. Finally, a patterned photoresist layer is formed on the gate layer. The patterned photoresist layer defines the area and position of the gate structure. The gate layer and gate dielectric layer are etched using the patterned photoresist layer as a mask to form a gate structure 216 on the epitaxial layer. The photoresist layer is then removed. The etching of the gate layer and gate dielectric layer can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching, which are not specifically limited. The gate structure is used to control the transfer of charge accumulated in the photodiode to the floating diffusion region, thereby realizing an efficient signal readout mechanism.

[0057] It is worth mentioning that the number of gate structures can be determined according to the number of transistors in the image sensor.

[0058] Next, after forming the gate structure 216, low-concentration impurities can be introduced into the epitaxial layer below both sides of the gate structure through ion implantation to form lightly doped regions. Sidewalls (not shown) are also formed on both sides of the gate structure. The sidewalls protect the edges of the gate structure from damage during subsequent processing. The sidewall materials include, but are not limited to, insulating materials such as silicon nitride. The lightly doped regions improve the short channel effect and enhance device reliability. Next, highly doped source and drain regions are formed outside the lightly doped regions to provide low-resistance paths and enhance current drive capability. The ion implantation concentration of the highly doped source and drain regions is greater than that of the lightly doped regions. Annealing is performed after the ion implantation. Since the ion implantation process can cause damage to the silicon wafer lattice, annealing can repair this damage. Annealing also activates the implanted ions, thereby improving the performance of the image sensor.

[0059] In one example, if Figure 19 As shown, after forming the pixel array, the process further includes forming an interlayer dielectric layer 218 covering the epitaxial layer 203 and the gate structure 216, and forming a metal wiring layer 219 in the interlayer dielectric layer 218. Specifically, the steps of forming the metal wiring layer 219 include: Illustratively, before forming the interlayer dielectric layer 218, the process further includes forming a dielectric layer 217 covering the gate structure 216 and the epitaxial layer 203. Illustratively, the material of the dielectric layer 217 includes, but is not limited to, silicon dioxide, a low-k material, or other suitable dielectric materials. The method for forming the dielectric layer 217 includes, but is not limited to, deposition processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), which are not specifically limited. The formed dielectric layer 217 covers the surfaces of the photodiode region 214, the floating diffusion region 215, the gate structure 216, and the epitaxial layer 203.

[0060] Next, an interlayer dielectric layer 218 is formed on dielectric layer 217. Interlayer dielectric layer 218 may include multiple layers of interlayer dielectric material. Methods for forming the interlayer dielectric material layer include, but are not limited to, deposition processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), and are not specifically limited thereto. For example, the material of metal wiring layer 219 includes, but is not limited to, copper or aluminum, and methods for depositing the metal material include, but are not limited to, processes such as chemical vapor deposition (CVD), and are not specifically limited thereto.

[0061] It is worth mentioning that the metal connection line layer can include multiple metal layers stacked in sequence and plugs disposed between adjacent metal layers, thereby forming a stacked metal connection layer. Specifically, the metal connection line layer can be formed by any suitable method, which will not be elaborated in detail here.

[0062] In one example, if Figure 20 As shown, a passivation layer 220 is formed on the interlayer dielectric layer 218, covering the surface of the interlayer dielectric layer 218. For example, the material of the passivation layer 220 includes, but is not limited to, silicon dioxide or silicon oxynitride, and the method of forming the passivation layer 220 includes, but is not limited to, PECVD (plasma-enhanced chemical vapor deposition) or ALD (atomic layer deposition). The passivation layer helps reduce electrical crosstalk between adjacent pixels and reduces parasitic capacitance by optimizing the electrical properties of the metal layer, thereby improving signal transmission efficiency and image clarity.

[0063] In one example, if Figure 21As shown, a plurality of grid structures 221 are formed on the passivation layer 220 , grid openings 222 are formed between each grid structure 221 , and a grid structure 221 is disposed between adjacent pixel units. Specifically, a grid material layer is first formed on the passivation layer 220. The grid material layer may be made of, but is not limited to, tungsten (W), nickel (Ni), or titanium (Ti). Methods for forming the grid material layer include, but are not limited to, molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), and laser ablation deposition (LAD). Next, a patterned photoresist layer is formed on the grid material layer. The patterned photoresist layer defines the area and position of the grid structure 221. The grid material layer is etched using the patterned photoresist layer as a mask to form a grid structure 221 between adjacent pixel units. A grid opening 222 is formed between each grid structure 221, exposing the surface of the passivation layer 220. The photoresist layer is then removed. Etching the grid material layer may be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching, which are not specifically limited. The grid structure can enhance image performance by suppressing optical crosstalk.

[0064] In one example, if Figure 22 As shown, a color filter layer 223 is embedded in each grille opening 222. The primary function of the color filter layer 223 is to separate incident light by color (i.e., wavelength), ensuring that each pixel receives only light of a specific color (typically one of red, green, and blue). This is the foundation for a color image sensor to generate color images. Specifically, the color filter layer material can be deposited in each grille opening 222 using methods such as spin coating or inkjet printing. After a baking process to ensure stability and optical performance, the color filter layer 223 embedded in the grille opening 222 is formed. Materials for the color filter layer 223 include, but are not limited to, dye-based resins, pigment-based resins, or inorganic materials.

[0065] In one example, if Figure 23As shown, a plurality of microlenses 225 is formed on the color filter layer 223, and the plurality of microlenses 225 corresponds to a plurality of pixel units, for example, one or more microlenses 225 corresponds to one pixel unit. Before forming the microlenses 225, an anti-reflection layer 224 is also formed on the color filter layer 223. Exemplarily, the anti-reflection layer 224 includes but is not limited to silicon dioxide or silicon nitride, etc., and the process method for forming the anti-reflection layer 224 includes but is not limited to PECVD (plasma enhanced chemical vapor deposition), atomic layer deposition (ALD), etc. When light enters from one medium to another medium (for example, the microlens enters the color filter layer), if the difference of refractive index between the two is large, reflection loss will occur. The anti-reflection layer can effectively reduce the reflection loss at the interface by optimizing its refractive index and thickness, thereby increasing the effective light amount reaching the photodiode. By reducing the reflection loss, more incident light energy can be effectively utilized by the image sensor, which directly improves the quantum efficiency of the image sensor and the performance in low light environment. The anti-reflection layer can also act as a transition layer to provide a flat surface for the microlens, facilitating its manufacture. In other examples, the anti-reflection layer can also not be formed, which is not specifically limited.

[0066] Finally, a plurality of microlenses 225 is formed on the color filter layer 223. Specifically, first, a layer of photosensitive material suitable for making microlenses (usually positive photoresist or high-temperature resin, etc.) is coated on the anti-reflection layer 224, a patterned photoresist layer is formed on the photosensitive material layer, and the patterned photoresist layer defines the area and position of the microlenses 225. The photosensitive material layer is etched to form the basic structure of the microlens with the patterned photoresist layer as a mask; second, the photoresist is heated to a certain temperature so that the remaining photoresist melts and naturally forms the required hemispherical or approximately spherical microlens structure due to surface tension; finally, the formed microlens structure is further cured, for example, ultraviolet curing or annealing, etc., to form the final microlens 225. The microlens focuses the incident light, so that more light can directly enter the photodiode, thereby compensating for the loss, improving light utilization, enhancing signal quality, and improving image quality.

[0067] It is worth mentioning that the above steps are only examples, and the order of the above steps can also be adjusted without conflict.

[0068] So far, the process steps of the image sensor preparation method according to the embodiment of the present application have been completed. It can be understood that the image sensor preparation method of the present embodiment not only includes the above steps, but also includes other required steps before, during or after the above steps, which are all included in the scope of the preparation method of the present embodiment.

[0069] In summary, the method for manufacturing the image sensor provided in the present application forms a cavity between the substrate and the epitaxial layer, and forms the capacitor structure in the cavity, and then forms the photodiode region in the epitaxial layer. Since the capacitor structure is away from the light-incident side (i.e. the non-light-incident side) of the photodiode region, the capacitor structure can effectively avoid blocking the incident light from entering the photodiode region, reduce the light loss, improve the photosensitive efficiency of the photodiode, thereby improving the sensitivity of the image sensor, and further improving the quality of the image.

[0070] Embodiment Two The present application also provides an image sensor, which can be manufactured by the method of the aforementioned embodiment one, or can be manufactured by other suitable manufacturing methods.

[0071] Reference will be made to Figures 2 to 23 The image sensor in the embodiments of the present application is explained and described, and the same structures as those in the aforementioned embodiment one are not described in detail.

[0072] Specifically, as shown in 2 to Figure 23 The image sensor provided in the present application includes: a substrate 201; a capacitor structure 230 disposed on the surface of the substrate 201, wherein the capacitor structure 230 includes a first electrode layer 2081, a second electrode layer 2082, and a dielectric layer 209 disposed between the first electrode layer 2081 and the second electrode layer 2082; an epitaxial layer 203 disposed on the capacitor structure 230; a pixel array including a plurality of pixel units formed in the epitaxial layer 203, each pixel unit including: at least one photodiode region 214, at least one floating diffusion region 215, and at least one transistor, the photodiode region 214 and the floating diffusion region 215 are spaced apart, and the side of the photodiode region 214 away from the capacitor structure 230 is the light-incident side. By forming a cavity between the substrate and the epitaxial layer, and forming the capacitor structure in the cavity, the situation that the capacitor structure blocks the incident light from entering the photodiode region can be effectively avoided, and the quality of the image is improved.

[0073] Exemplarily, the image sensor further includes: an isolation layer 207 disposed between the first electrode layer 2081 and the epitaxial layer 203, and between the second electrode layer 2082 and the substrate 201. The isolation layer can provide a physical barrier to prevent damage caused by subsequent processing, thereby improving the reliability and stability of the device, and the isolation layer serves as an insulating layer to isolate the film layers on both sides so that they are not electrically connected.

[0074] Exemplarily, the image sensor further comprises at least one first electrode wire 2100 penetrating the epitaxial layer 203 and electrically connected with the first electrode layer 2081, and at least one second electrode wire 2101 penetrating the epitaxial layer 203, the first electrode layer 2081 and the dielectric layer 209 and electrically connected with the second electrode layer 2082, the first electrode wire 2100 and the second electrode wire 2101 being electrically isolated. The electrical isolation can prevent current leakage, improve the capacitance value, reduce parasitic effects, and enhance the reliability of the device.

[0075] Exemplarily, the first electrode wire 2100 is arranged between two adjacent pixel units arranged at intervals in a first direction and extends along a second direction, and the second electrode wire 2101 is arranged between two adjacent pixel units arranged at intervals in the second direction and extends along the first direction, the first direction and the second direction being perpendicular to each other.

[0076] Exemplarily, the first electrode wire 2100, the first electrode layer 2081 and the second electrode layer 2082 are formed synchronously. Specifically, the first electrode wire 2100, the first electrode layer 2081 and the second electrode layer 2082 are formed simultaneously when the electrode material layer 208 is deposited by releasing the trench 240.

[0077] Exemplarily, the transistor comprises a gate structure 216 arranged on the epitaxial layer 203, and the image sensor further comprises an interlayer dielectric layer 218 covering the epitaxial layer 203 and the gate structure 216, wherein a metal wiring layer 219 is formed in the interlayer dielectric layer 218; a passivation layer 220 located on the interlayer dielectric layer 218; a plurality of grid structures 221, wherein a grid opening 222 is formed between adjacent grid structures 221, and the grid opening 222 exposes the passivation layer 220; a color filter layer 223 embedded in the grid opening 222; and a plurality of microlenses 225 located on the color filter layer 223, the plurality of microlenses 225 corresponding to the plurality of pixel units.

[0078] It is worth mentioning that the image sensor in the embodiments of the present application can be a front-illuminated CMOS image sensor.

[0079] The image sensor provided by the present application can effectively avoid the situation that the capacitor structure blocks incident light from entering the photodiode region, reduce light loss, improve the photosensitive efficiency of the photodiode, thereby improve the sensitivity of the image sensor, and further improve the quality of the image.

[0080] While several embodiments have been described, it should be apparent that many modifications can be made by those skilled in the art without departing from the spirit and scope of the disclosed concept. More specifically, it is contemplated that various modifications and alterations will occur to others upon reading and understanding the specification. It is intended that the application be construed as including all such modifications and alterations and, therefore, the application should be limited only by the scope of the following claims.

Claims

1. A method for preparing an image sensor, characterized in that: include: providing a substrate, and sequentially forming a sacrificial layer and an epitaxial layer on the substrate; forming a support column penetrating the epitaxial layer and the sacrificial layer, wherein the support column is further extended along a first direction perpendicular to a thickness direction of the substrate; Etching the epitaxial layer to form at least one release trench exposing a portion of the sacrificial layer; Using the release groove as a release channel, etching and removing the sacrificial layer to form a cavity between the epitaxial layer and the substrate; forming a capacitor structure in the cavity, wherein the capacitor structure comprises a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first electrode layer and the second electrode layer; A pixel array including a plurality of pixel units is formed in the epitaxial layer, each of the pixel units including: At least one photodiode region, at least one floating diffusion region and at least one transistor, the photodiode region and the floating diffusion region are spaced apart, and a side of the photodiode region away from the capacitor structure is a light incident side.

2. The method for preparing an image sensor according to claim 1, wherein: The forming of a capacitor structure in the cavity comprises: forming an electrode material layer in the cavity, wherein the electrode material layer disposed on the side of the epitaxial layer facing the substrate is the first electrode layer, and the electrode material layer disposed on the side of the substrate facing the epitaxial layer is the second electrode layer, with a space between the first electrode layer and the second electrode layer; The dielectric layer is formed to fill the space.

3. The method for preparing an image sensor according to claim 2, wherein: Before forming the capacitor structure, the method further includes: An isolation layer is formed to cover the surface of the substrate facing the epitaxial layer, the surface of the epitaxial layer, the sidewalls of the release trench and part of the sidewalls of the support pillar, wherein: The first electrode layer covers the isolation layer on a side of the epitaxial layer facing the substrate, and the second electrode layer covers the isolation layer on a side of the substrate facing the epitaxial layer; The electrode material layer disposed in the release groove serves as a first electrode wire, the first electrode wire is electrically connected to the first electrode layer, and the dielectric layer also fills the release groove.

4. The method for preparing an image sensor according to claim 3, wherein: The electrode material layer further covers the isolation layer exposed in the cavity and located on the sidewall of the support pillar. The method further includes: After forming the dielectric layer, removing the support pillar and a portion of the isolation layer, a portion of the electrode material layer, a portion of the dielectric layer, and a portion of the epitaxial layer located outside the sidewall of the support pillar to form an isolation trench and electrically isolate the first electrode layer from the second electrode layer; The isolation trench is filled with an insulating material to form an insulating isolation structure.

5. The method for preparing an image sensor according to claim 1, wherein: After forming the capacitor structure and before forming the pixel array, the method further includes: At least one second electrode wire is formed penetrating the epitaxial layer, the first electrode layer, and the dielectric layer, wherein the second electrode wire is electrically connected to the second electrode layer.

6. The method for preparing an image sensor according to claim 5, wherein: The step of forming at least one second electrode wire penetrating the epitaxial layer, the first electrode layer and the dielectric layer comprises: Etching the epitaxial layer, the first electrode layer, and the dielectric layer to form at least one contact hole, wherein a bottom of the contact hole is located in the second electrode layer; forming an insulating isolation layer on the sidewall of the contact hole; Filling the contact hole with a conductive material to form a second electrode wire, wherein the second electrode wire is further extended along the first direction, wherein at least one second electrode wire is located between two adjacent pixel units in the second direction; Each of the release grooves is disposed between two adjacent pixel units in the first direction, and the release groove further extends along the second direction, a first electrode wire is formed on a sidewall of the release groove, and the first electrode wire is electrically connected to the first electrode layer; The first direction and the second direction are perpendicular to each other, the first electrode wire and the second electrode wire are electrically isolated from each other, and the two cross each other.

7. The method for preparing an image sensor according to claim 1, wherein: The transistor includes a gate structure formed on the epitaxial layer. After the pixel array is formed, the method further includes: forming an interlayer dielectric layer covering the epitaxial layer and the gate structure, and forming a metal wiring layer in the interlayer dielectric layer; forming a passivation layer on the interlayer dielectric layer, and forming a plurality of grid structures on the passivation layer, wherein a grid structure is disposed between adjacent pixel units, and grid openings are formed between adjacent grid structures, wherein the grid openings expose the surface of the passivation layer; embedding a color filter layer in the grille opening; A plurality of micro lenses are formed on the color filter layer, and the plurality of micro lenses correspond to the plurality of pixel units.

8. An image sensor, characterized in that: include: substrate; a capacitor structure disposed on the surface of the substrate, wherein the capacitor structure includes a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first electrode layer and the second electrode layer; an epitaxial layer, wherein the epitaxial layer is disposed on the capacitor structure; A pixel array including a plurality of pixel units is formed in the epitaxial layer, each of the pixel units including: At least one photodiode region, at least one floating diffusion region and at least one transistor, the photodiode region and the floating diffusion region are spaced apart, and a side of the photodiode region away from the capacitor structure is a light incident side.

9. The image sensor according to claim 8, wherein Also includes: an isolation layer, the isolation layer being disposed between the first electrode layer and the epitaxial layer, and between the second electrode layer and the substrate; at least one first electrode wire, the first electrode wire passing through the epitaxial layer and electrically connected to the first electrode layer; at least one second electrode wire, the second electrode wire passing through the epitaxial layer, the first electrode layer, and the dielectric layer, and being electrically connected to the second electrode layer, the first electrode wire and the second electrode wire being electrically isolated from each other; The first electrode wire is disposed between two adjacent pixel units spaced apart in the first direction, and the first electrode wire extends along the second direction. The second electrode wire is arranged between two adjacent pixel units spaced apart in the second direction, and the second electrode wire extends along the first direction. The first direction and the second direction are perpendicular to each other.

10. The image sensor according to claim 9, wherein The transistor includes a gate structure disposed on the epitaxial layer, and the image sensor further includes: an interlayer dielectric layer, the interlayer dielectric layer covering the epitaxial layer and the gate structure, wherein a metal wiring layer is formed in the interlayer dielectric layer; a passivation layer, the passivation layer being located on the interlayer dielectric layer; a plurality of grid structures, the grid structures being located on the passivation layer, wherein a grid structure is disposed between adjacent pixel units, a grid opening is formed between adjacent grid structures, and the grid opening exposes the surface of the passivation layer; a color filter film layer, wherein the color filter film layer is embedded in the grille opening; A plurality of micro lenses are located on the color filter layer, and the plurality of micro lenses correspond to the plurality of pixel units.

Images