Semiconductor device

Abstract

The present disclosure relates to a semiconductor device capable of achieving DUT measurement of a semiconductor device even mounted on a chip stack wafer of a CoW structure. A logic chip including a singulated signal processing circuit, a singulated memory circuit and the like is stacked on a wafer on which a plurality of imaging elements have been formed, terminals are formed on a scribe line surface, and the scribe line is a portion to be cut during singulation. A connection wiring connecting the terminal on the scribe surface and the DUT of the logic chip is formed between the wafer and the logic substrate, and the terminal is connected with the probe to implement the DUT without singulation. The present disclosure is applicable to semiconductor devices.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device capable of implementing a device under test (DUT) measurement at a terminal provided on a scribe line surface even in a chip on wafer (CoW) structure. BACKGROUND

[0002] As a technology of manufacturing a semiconductor device such as a solid-state imaging device, a manufacturing technology of manufacturing a semiconductor device by bonding, in a wafer state, pixel chips each including a solid-state imaging element and logic chips such as a signal processing circuit or a memory circuit, and layering the pixel chips and the logic chips into a wafer on wafer (WoW) structure is well known.

[0003] When a solid-state imaging device is manufactured in a state of being layered into a WoW structure as described above, a plurality of solid-state imaging devices layered in the WoW structure is singulated into a final product by a dicing blade, and a device under test (DUT) measurement is performed in a state before singulation, that is, in a state of the WoW structure, to secure a process.

[0004] The DUT measurement is a test measurement for confirming an operation state of a logic chip such as a signal processing circuit or a memory circuit. More specifically, in the WoW structure before singulation, a device under test (DUT) connected to a logic chip such as a signal processing circuit or a memory circuit is electrically connected to an inspection device via a probe, and thereby the inspection device performs a test measurement to confirm an operation state.

[0005] In the WoW structure, the DUT is disposed in an area in which a scribe line to be cut by the dicing blade is formed when the solid-state imaging device is singulated. Further, the DUT is connected to a measurement terminal (AL PAD) provided on a scribe line surface via a back end of line (BEOL) wiring such as Cu, and the terminal is connected to the inspection device via a probe to perform the DUT measurement.

[0006] In this way, in recent years, in order to increase a circuit scale mounted in one chip and to achieve higher functionality, in addition to the above-described wafer on wafer (WoW) structure, a wafer on chip (CoW) structure in which a logic chip obtained by singulating one or two pieces is layered on a semiconductor wafer on which a solid-state imaging element has been formed has been proposed.

[0007] The CoW structure is a structure in which one or two pieces of singulated logic chips are layered on a wafer on which a pixel chip including a solid-state imaging element has been formed.

[0008] In this CoW structure, the DUT of the logic chip is not necessarily stacked in a manner in which the DUT coincides with the region in which scribe lines have been formed on the wafer, so it can not be disposed at the same position as the terminal (AL PAD) formed on the scribe surface, it is thus not possible to electrically connect the DUT and the terminal, and it is also not possible to achieve DUT measurement on the wafer on which pixel chips each including a solid-state imaging element have been formed.

[0009] That is, in the case of the CoW structure, in order to achieve the above-described DUT measurement, it is necessary to separately form and connect a wiring for connecting the DUT of the logic chip and the terminal (AL PAD) formed on the scribe surface.

[0010] In this regard, a technology of forming and connecting a wiring layer that electrically connects a scribe region and a chip region via a guard ring has been proposed (Patent Literature 1).

[0011] Therefore, it is conceivable to connect the DUT of the logic chip in the above-described CoW structure and the AL PAD formed on the scribe surface by applying the technology according to Patent Literature 1. LIST OF CITATIONS PATENT LITERATURE

[0012] Patent Literature 1: JP 2012-204630 A SUMMARY TECHNICAL PROBLEM

[0013] However, the technology described in Patent Literature 1 is a technology of forming a wiring layer during the same wafer process, and thus cannot be applied to a technology of connecting the DUT of the logic chip and the terminal (AL PAD) formed on the scribe surface on the wafer on which a solid-state imaging element has been formed, which are generated by different wafer processes.

[0014] Further, when the logic chip is stacked on the wafer on which a solid-state imaging element has been formed, it is necessary to arrange the logic chip in contact with the region in which scribe lines have been formed, in order to connect the DUT of the logic chip and the terminal (AL-PAD) formed on the scribe surface, and the degree of freedom of the arrangement position of the logic chip is reduced.

[0015] Further, when there is a slight error in the arrangement of the logic chip, for example, when the logic chip is arranged overlapping the region in which scribe lines have been formed, there is a risk that the logic chip interferes with the cutting knife at the time of cutting and damages the cutting knife.

[0016] Further, when a plurality of logic chips are stacked in the same layer on a wafer on which a solid-state imaging device has been formed, for example, a layout in which a second logic chip is disposed between a first logic chip and a region in which scribe lines have been formed can prevent connection between a DUT of the first logic chip and a terminal (AL PAD) formed on a scribe surface due to interference of the second logic chip.

[0017] In view of this, particularly, the present disclosure achieves DUT measurement of a CoW structure by enabling electrical connection between a DUT of a logic chip and a terminal formed on a scribe surface without reducing the degree of freedom of the arrangement position of the logic chip in the CoW structure. Solution to the technical problem

[0018] A semiconductor device according to one aspect of the present disclosure is a semiconductor device including a first semiconductor chip, a second semiconductor chip different from the first semiconductor chip, and a connection wiring, the first semiconductor chip including an imaging element, the connection wiring electrically connecting an internal circuit that is a circuit within the second semiconductor chip and an external circuit that is a circuit outside the second semiconductor chip or a terminal outside the second semiconductor chip.

[0019] According to one aspect of the present disclosure, there is provided a first semiconductor chip including an imaging element, a second semiconductor chip different from the first semiconductor chip, and a connection wiring electrically connecting an internal circuit that is a circuit within the second semiconductor chip and an external circuit that is a circuit outside the second semiconductor chip or a terminal outside the second semiconductor chip. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a diagram for explaining a WoW structure. Figure 2 is a diagram for explaining a CoW structure. Figure 3 is a diagram for explaining a reason for arranging a logic chip away from a scribe line in a CoW. Figure 4 is a diagram for explaining a reason for arranging a logic chip away from a scribe line in a CoW. Figure 5 is a diagram for explaining a chip-stacked wafer related to manufacture of a solid-state imaging device according to a preferred embodiment of the present disclosure. Figure 6 is a diagram for explaining Figure 5 a cross-sectional structure of a chip-stacked wafer in Figure 7 is a bird's-eye view of a CC' cross section in Figure 6 ​Figure 8 is a view for explaining a manufacturing process of a solid-state imaging device according to the present disclosure. Figure 9 is a view for explaining a manufacturing process of a solid-state imaging device according to the present disclosure. Figure 10 is a view for explaining a first modification example of the present disclosure. Figure 11 is a view for explaining a second modification example of the present disclosure. Figure 12 is a view for explaining a third modification example of the present disclosure. Figure 13 is a view for explaining a fourth modification example of the present disclosure. Figure 14 is a view for explaining a fifth modification example of the present disclosure. Figure 15 is a view for explaining a sixth modification example of the present disclosure. Figure 16 is a view for explaining a seventh modification example of the present disclosure. Figure 17 is a view for explaining an eighth modification example of the present disclosure. Figure 18 is a view for explaining a ninth modification example of the present disclosure. Figure 19 is a view for explaining a tenth modification example of the present disclosure. DETAILED DESCRIPTION

[0021] A preferred embodiment of the present disclosure will be explained in detail below with reference to the attached drawings. Note that in the present specification and the attached drawings, components having substantially the same function are denoted with the same reference numerals, and repeated explanation thereof will be omitted.

[0022] Hereinafter, an embodiment for implementing the present technology will be explained. The explanation will be made in the following order. 1. WoW structure 2. CoW structure 3. Preferred embodiment 4. First modification example 5. Second modification example 6. Third modification example 7. Fourth modification example 8. Fifth modification example 9. Sixth modification example 10. Seventh modification example 11. Eighth modification example 12. Ninth modification example 13. Tenth modification example

[0023] <<1. WoW structure>> A wafer-on-wafer (WoW) structure will be described with reference to Figure 1

[0024] A wafer-on-wafer (WoW) structure is a form of structure in a manufacturing process of a semiconductor device as a final product. Note that although the following will be described with the case where the semiconductor device as a final product is a solid-state imaging device as an example, the semiconductor device as a final product can be a device other than the solid-state imaging device.

[0025] More specifically, when the semiconductor device as a final product is a solid-state imaging device, as shown in the upper left portion of FIG. 1, a stacked wafer 1 is generated by bonding a wafer 11 and a wafer 12 in a state where the wafer 11 and the wafer 12 are aligned, the wafer 11 including a plurality of pixel chips formed thereon and each pixel chip including a semiconductor element such as a solid-state imaging element, and the wafer 12 including a plurality of logic chips such as a signal processing circuit or a memory circuit formed thereon. Figure 1

[0026] The structure of the stacked wafer 1 adopting the configuration in which these wafers 11 and 12 are stacked is a wafer-on-wafer (WoW) structure.

[0027] In the wafer 11 constituting the stacked wafer 1 in FIG. 1, a plurality of pixel chips 11a each including a solid-state imaging element are formed in each of the square ranges in FIG. 1. Figure 1 Figure 1 In addition, a plurality of logic chips 12a each including a signal processing circuit or a memory circuit are formed in each of the square ranges in the wafer 12.

[0028] That is, in the stacked wafer 1, the wafer 11 on which the plurality of pixel chips 11a are formed and the wafer 12 on which the plurality of logic chips are formed are bonded and stacked in a state where each of the pixel chips 11a and the logic chips 12a are aligned.

[0029] A scribe line 21 indicated by a solid line extending in a horizontal direction and a vertical direction in FIG. 1 is formed around the portion of the stacked wafer 1 in which the pixel chips 11a and the logic chips 12a have been formed. Figure 1 That is, the stacked wafer 1 is cut using a dicing blade along the scribe line 21, thereby singulating and cutting out the solid-state imaging device 2 including one pixel chip 11a and one logic chip 12a as a final product.

[0030]

[0031] Figure 1 ​​​​The lower left portion of FIG. 1A shows a stacked structure of the solid-state imaging device 2 including one pixel chip (NIS) 11a and one logic chip 12a on the stacked wafer 1. In this regard, Figure 1 The lower left portion of FIG. 1A shows a state in which the solid-state imaging device 2 is not cut out from the stacked wafer 1, and only shows the stacked structure of a portion of the stacked wafer 1 corresponding to one solid-state imaging device 2.

[0032] As shown in the lower left portion of FIG. 1A, a device under test (DUT) as a test target device for confirming the operation state of the logic chip is formed just below the scribe line 21 of the pixel chip 11a. Figure 1

[0033] More specifically, as shown in the lower right portion of FIG. 1A, a terminal (PAD) 31 is formed on the surface of the scribe line 21 of the pixel chip 11a, and the terminal 31 is connected to a probe 51 to be electrically connected to an inspection device (not shown) for implementing DUT measurement. Further, the terminal 31 is connected to a DUT 33 of the logic chip 12a via a wiring 32 formed in the logic chip 12a. Figure 1

[0034] As shown in the lower right portion of FIG. 1A, the logic chip 12a includes a substrate 12ab and a logic layer 12aa in which a signal processing circuit or a memory circuit, which are not shown, and the DUT are formed. Note that, Figure 1 The lower right portion of FIG. 1A is a cross-sectional side view of a range in which the scribe line 21 is formed in the lower left portion of FIG. 1A. Figure 1 Figure 1

[0035] The stacked wafer 1 of the WoW structure is configured such that the probe 51 is connected to the terminal 31 in a state before the scribe line 21 is cut by a dicing blade and singulated, so that the DUT 33 and the inspection device are electrically connected via the wiring 32 connected to the terminal to implement DUT measurement.

[0036] Therefore, DUT measurement of a plurality of solid-state imaging devices 2 formed on the stacked wafer 1 can be efficiently implemented at one time.

[0037] <<2. CoW structure>> Next, a chip on wafer (CoW) structure will be described with reference to FIG. 1B. Figure 2 The chip on wafer (CoW) structure is also a form of structure in the manufacturing process of a semiconductor device as a final product, like the wafer on wafer (WoW) structure.

[0038] The chip on wafer (CoW) structure is also a form of structure in the manufacturing process of a semiconductor device as a final product, like the wafer on wafer (WoW) structure.

[0039] ​​​​In a chip-on-wafer (CoW) structure, logic chip 62A singulated from wafer 62 is aligned and bonded to wafer 61, a plurality of logic chips such as signal processing circuits or memory circuits are formed on wafer 62, and a plurality of pixel chips each including a semiconductor element such as a solid-state imaging element are formed on wafer 61.

[0040] The structure of the wafer 61 in which logic chips 62A singulated and cut out from the wafer 62 are stacked at respective positions of the pixel chips 61 a of the wafer 61 is a chip-on-wafer (CoW) structure.

[0041] Also in Figure 2 In wafer 61, Figure 2 Each square area of ​​the wafer 62 includes a pixel chip 61a, each including a solid-state imaging element. Furthermore, each square area of ​​the wafer 62 includes a logic chip 62A, each including a signal processing circuit or a memory circuit.

[0042] Furthermore, the individual pixel chips 61a and the logic chips 62A singulated and cut out from the wafer 62 on which the plurality of logic chips 62A are formed are stacked and attached on the wafer 61 on which the plurality of pixel chips 61a are formed in a state where the pixel chips 61a and the logic chips 62A are aligned.

[0043] Note that due to Figure 2 As shown in the lower left portion of the figure, in a CoW structure, the size of logic chip 62A is generally inconsistent with the size of pixel chip 61a. Therefore, when logic chip 62A is attached to the corresponding position of pixel chip 61a, a buried film is buried in the space around logic chip 62A. Thus, a logic layer 91 is formed, which includes buried layer 91a and substrate 91b. Buried layer 91a includes logic chip 62A and buried film.

[0044] In this case, a region formed along the edge of the wafer 61 is formed around the portion where the pixel chip 61a is formed. Figure 2 The solid lines extending in the horizontal and vertical directions in FIG. 7 indicate scribe lines 71. The scribe lines 71 are portions that are cut by a dicing blade when the solid-state imaging device 2', which is a final product including one pixel chip 61a and one logic chip 62A, is singulated and cut out.

[0045] That is, the wafer 61 is cut along the scribe lines 71 using a dicing blade, so that the solid-state imaging device 2 ′ including one pixel chip 61 a and one logic chip 62A is singulated and cut out as a final product.

[0046] However, as mentioned above, Figure 2As shown in the lower left portion of FIG, a pixel chip (NIS) 61a and a logic chip 62A in the wafer 61 do not necessarily have the same size. Therefore, even if a DUT is set on a part of the logic chip 62A, it is impossible to form the DUT directly under the scribe line 71 of the pixel chip 61a.

[0047] Therefore, if Figure 2 As shown in the lower right portion of , even if a terminal (PAD) 81 for connection to the probe 51 is formed on the surface of the scribe line 71 of the pixel chip 61a so as to be electrically connected to an inspection device (not shown) for implementing DUT measurement, and components such as wiring 82 are prepared, the terminal 81 and the DUT of the logic chip 62A will be misaligned and therefore cannot be connected.

[0048] Therefore, it is conceivable that the DUT of the logic chip 62A is bonded so as to be arranged directly below the scribe line 71 of the pixel chip 61 a .

[0049] However, if Figure 3 As shown, when the pixel chip 61a includes guard rings 61X formed at portions where the scribe lines 71 are formed, and each guard ring includes a seal ring for maintaining watertightness, the logic chip 62A needs to consider the intervals between the guard rings 61X.

[0050] Therefore, it is necessary to ensure a space between the pixel chip 61a and the logic chip 62A, for example, Figure 3 As shown by the distance Ds indicated by the arrow in , the DUT of the logic chip 62A cannot be arranged directly below the scribe line 71 in the pixel chip 61 a.

[0051] Notice, Figure 3 An example is shown in which two logic chips 62A- 1 and 62A- 2 are attached to one pixel chip 61 a .

[0052] Furthermore, even if a configuration is adopted in which the guard ring 61X is not provided, in the case of a configuration in which the DUT of the logic chip 62A is arranged right below the scribe line 71 in the pixel chip 61a, as shown in FIG. Figure 4 As shown in the left part of , the logic chip 62A can only be arranged at a position along the scribe line 71 within the range where the pixel chip 61 a is provided, so the degree of freedom of layout is reduced.

[0053] Furthermore, although it is conceivable to adopt Figure 4 The DUT of the logic chip 62A-1 shown on the right side is in contact with the scribe line 71, but in this case, if a slight misalignment causes the logic chip 62A-1 to interfere with the scribe line 71, the logic chip 62A-1 may contact the dicing blade X during dicing and damage the dicing blade X.

[0054] In addition, ifFigure 4 As shown in the right portion of FIG. 7, since the logic chip 62A-1 is disposed between the DUT and the scribe line 71, the DUT of the logic chip 62A-2 cannot be configured to contact the DUT with the scribe line 71.

[0055] As described above, the CoW structure is generally configured such that the DUT and the inspection device cannot be electrically connected even if the probe 51 is connected to the terminal 81 before the cutting knife cuts and singulates the terminal on the surface of the scribe line 71, and it is not realistic to perform the DUT measurement before singulation.

[0056] Therefore, the present disclosure enables the DUT measurement of the logic chip even for the CoW structure.

[0057] <<3. Preferred Embodiments>> <Configuration Example of Solid-state Imaging Device> Next, a configuration example of a solid-state imaging device according to the present disclosure will be described with reference to Figures 5 to 7

[0058] Note that, Figure 5 The right portion of FIG. 1 is a plan view of a chip-stacked wafer 100 including a plurality of solid-state imaging devices 110 formed therein, and includes a wafer 101 on which pixel chips 111a each including a solid-state imaging element are formed, and a logic layer 102 formed by stacking a singulated logic chip 112A on one pixel chip 111a and burying an embedding film 146 around the logic chip 112A.

[0059] Further, Figure 5 The left portion of FIG. 1 is an enlarged plan view of one solid-state imaging device 110 in the chip-stacked wafer 100 at completion.

[0060] Further, Figure 6 is a cross-sectional side view of the solid-state imaging device 110, in which the uppermost section is Figure 5 the XX' cross section of FIG. 1.

[0061] Further, Figure 6 the second section from the top in FIG. 1 is Figure 6 an enlarged view of the portion in which the logic chip 112A is stacked in the cross-sectional side view of the uppermost section in FIG. 1, Figure 6 the third section from the top in FIG. 1 is Figure 6 a cross-sectional view of the wafer 101 side in the AA' cross section of the second section from the top in FIG. 1, and Figure 6 the fourth section from the top in FIG. 1 is Figure 6 a cross-sectional view of the logic layer 102 side in the AA' cross section of the second section from the top in FIG. 1.

[0062] Further,​Figure 7 is observed from the side of the CC' section of the second to fourth sections from the top in Figure 6 Figure 6 is observed in the vicinity of the range B enclosed by a broken line in the second section from the top in Figure 6

[0063] As shown in the uppermost section and the second section from the top in Figure 5 and Figure 6 , the pixel chip 111a is provided with a terminal 111aa including a PAT for connection with a probe to confirm the operation of the pixel chip 111a. Further, the pixel chip 111a is provided with a color filter 111ab on an incident surface of incident light, which is the upper portion in Figure 5 and Figure 6 .

[0064] Further, as shown in the uppermost section in Figure 5 and Figure 6 , a scribe line 121 is formed around the pixel chip 111a, and a terminal 121a including a PAT is formed on the surface of the scribe line 121 on the left side of the pixel chip 111a in the uppermost section in Figure 5 and Figure 6 to be connected with the probe 51 in Figure 1 for DUT measurement.

[0065] Further, the terminal 121a is electrically connected with the left end portion of a connection wiring 131 shown in Figure 6 and provided on the boundary surface of the wafer 101 with respect to the logic layer 102. The right end portion of the connection wiring 131 is provided with a connection portion 131a. As shown in the range B enclosed by a broken line in Figure 6 , the connection portion 131a is connected with a connection portion 142 provided inside the logic chip 112A in the logic layer 102.

[0066] In the logic chip 112A, a DUT 144 is formed on a substrate 145 and is electrically connected with the connection portion 142 via a wiring 143.

[0067] That is, the terminal 121a formed on the surface of the scribe line 121 is electrically connected with the DUT 144 via the connection wiring 131, the connection portion 131a, the connection portion 142, and the wiring 143.

[0068] Therefore, by connecting the probe 51 of an inspection device not shown to the terminal 121a formed on the surface of the scribe line 121, the DUT 144 and the inspection device not shown can be electrically connected via the terminal 121a, the connection wiring 131, the connection portion 131a, the connection portion 142, and the wiring 143.​​

[0069] As a result, DUT measurement of the solid-state imaging device 110 can be achieved in the state of the chip stacked wafer 100 having a CoW structure, in other words, in the state before the solid-state imaging device 110 is singulated.

[0070] In addition, in the wafer 101, as Figure 6 As shown in the third row from the top in FIG. 1 , a guard ring 132 including a seal ring is formed in the area where the pixel chip 111 a is formed so as to surround the entire area except for the connection wiring 131 .

[0071] In addition, if Figure 7 As shown, connection wiring 131 includes water-resistant layers 161 and 162 formed at the front and rear ends relative to the incident direction of incident light. These layers have water resistance to sandwich connection wiring 131 and are made of, for example, silicon nitride (SiN), aluminum oxide (Al2O3), or the like. More specifically, connection wiring 131 is formed in an insulating film surrounded by water-resistant layers 161 and 162 and guard ring 132.

[0072] In this regard, regarding the portion of the connection portion 131a of the connection wiring 131, the water-resistant layer 162 is not formed in the range facing the connection portion 142 so as to be electrically connected to the connection portion 142 connected to the wiring 143 formed on the logic chip 112A, and the connection portion 131a is partially exposed.

[0073] In addition, in the logic layer 102, as Figure 6 As shown in the fourth row from the top in FIG. 1 , a guard ring 141 including a seal ring is formed within the range where the logic chip 112A is formed so as to surround the entire range except for the range where the connection portion 142 is formed.

[0074] Furthermore, a water-resistant layer 171 made of water-resistant silicon nitride (SiN) or aluminum oxide (Al2O3) is formed between connection portion 142 and wiring 143. In this regard, connection portion 142 and wiring 143 are electrically connected, and water-resistant layer 171 is not formed at the connection portion between connection portion 142 and wiring 143.

[0075] According to this construction, the terminal 121a adopts such a construction: although the terminal 121a is electrically connected to the DUT 144 via the connecting wiring 131, the connecting portion 131a, the connecting portion 142 and the wiring 143, due to the guard rings 132 and 141 and the water-resistant layers 161, 162 and 171, the pixel chip 111a and the logic chip 112A are both water-resistant.

[0076] That is, the chip stacked wafer 100 including the logic layer 102 and the wafer 101 of the CoW structure according to the present disclosure adopts a configuration in which the terminal 121a formed on the surface of the scribe line 121 in the plurality of formed pixel chips 111a is connected with the DUT 144 of the logic chip 112A via the connection wiring 131, the connection portion 131a, the connection portion 142, and the wiring 143.

[0077] Therefore, by connecting the probe of the inspection device to the terminal 121a formed on the surface of each scribe line 121 without monolithicizing the solid-state imaging device 110 formed on the chip stacked wafer 100, the inspection device can be electrically connected with the DUT 144 of the logic chip 112A, and DUT measurement can be achieved.

[0078] Further, when the connection wiring 131 is formed, the protection ring 132 including the sealing ring, the water-resistant layers 161 and 162 in the pixel chip 111a, and the protection ring 141 including the sealing ring and the water-resistant layer 171 in the logic chip 112A enable the pixel chip 111a and the logic chip 112A to ensure sufficient water resistance.

[0079] Further, as long as the above-described protection ring 132 and the water-resistant layers 161 and 162 are provided, the connection wiring 131 can be wired at various positions on the pixel chip 111a, and the connection portion 131a can be arranged at various positions, so that the degree of freedom of layout of the logic chip 112A within the pixel chip 111a can be improved.

[0080] At this time, for example, even if another logic chip is provided between the scribe line 121 and the logic chip 112A of interest, the terminal 121a and the DUT 144 can be electrically connected by bypassing the route of the connection wiring 131, and in this respect, the degree of freedom of layout can also be improved.

[0081] <Manufacturing process of solid-state imaging device> Next, a manufacturing process of the solid-state imaging device 110 according to the present disclosure will be described with reference to Figure 8 and Figure 9

[0082] In step S1 (preparation step), as shown in the uppermost row on the right in FIG. 7, a wafer 112 is generated, the wafer 112 including a plurality of logic chips 112A formed thereon, each logic chip 112A including a DUT 144 and a wiring 143 and a protection ring 141 on a substrate 145. Figure 8 Figure 8 In step S2 (formation step), as shown in the uppermost row on the right in FIG. 8, a wafer 111 is generated, the wafer 111 including a plurality of pixel chips 111a formed thereon, each pixel chip 111a including a solid-state imaging device 110 and a protection ring 132 on a substrate 151.

[0083] In step S3 (connection step), as shown in the uppermost row on the right in FIG. 9, a wafer 100 is generated, the wafer 100 including a plurality of chip stacked wafers 100 formed thereon, each chip stacked wafer 100 including a plurality of pixel chips 111a and a logic chip 112A stacked on the pixel chips 111a. Figure 8 ​​As shown in the second row from the top on the right side of FIG. 1 , a connection portion 142 is formed in each wiring 143 of the plurality of logic chips 112A on the wafer 112 .

[0084] In step S3, Figure 8 As shown in the third row from the top on the right side of FIG. , the wafer 112 is singulated into logic chips 112A.

[0085] In step S4, Figure 8 As shown in the upper left section, a wafer 111 is generated, and the wafer 111 includes a plurality of pixel chips 111a formed thereon, each pixel chip 111a includes a test device 201 for the pixel chip 111a, a terminal 111aa connected to the test device 201, and a terminal 121a formed at the position of the scribe line 121.

[0086] Note that the test device 201 and the terminal 111aa are formed inside the guard ring 132, and the terminal 121a is formed outside the guard ring 132. Figure 8 , the wafer 111 is shown in a state of being turned upside down. Therefore, although the substrate 200 is shown in the upper stage, in actual processing, it is shown in a turned-over manner and the substrate 200 is located in the lower stage.

[0087] In step S5, Figure 8 As shown in the second row from the top on the left side of FIG, a water-resistant layer 161 made of silicon nitride (SiN) is formed on the upper surface of the wafer 111 .

[0088] In step S6, Figure 8 As shown in the third row from the top on the left side of FIG. 1 , a water-resistant layer 162 is further formed on the water-resistant layer 161 made of silicon nitride (SiN) on the upper surface of the wafer 111 .

[0089] In step S7, Figure 8 As shown in the fourth row from the top on the left side of FIG. 1 , in order to electrically connect to the terminal 121 a , a portion of the water-resistant layers 161 and 162 is peeled off to form the connection wiring 131 .

[0090] Note that the processes in steps S1 to S3 and the processes in steps S4 to S7 described above may be performed in reverse order or may be performed in parallel.

[0091] In step S8, Figure 8 As shown in the fifth row from the top on the left side of FIG, the singulated logic chip 112A is stacked on each pixel chip 111a of the wafer 111. At this time, the connection portion 131a of the connection wiring 131 of the pixel chip 111a and the connection portion 142 of the logic chip 112A are stacked in a state where the connection portion 131a and the connection portion 142 are electrically connected.

[0092] In step S9, as shown in the fourth section from the top on the right side in FIG. 12B, the substrate 145 of the stacked logic chip 112A is thinned, the buried film 146 is formed around the logic chip 112A, and then the chip-stacked wafer 100 is completed. Figure 8

[0093] In step S10, as shown in the fifth section from the top on the right side in FIG. 12B, the substrate 200 is thinned, the scribe line 121 is formed, the terminal 121a is opened, the terminal 111aa is opened, and the color filter 111ab is formed. Thus, the plurality of solid-state imaging devices 110 are completed on the chip-stacked wafer 100. That is, the terminal 121a and the DUT 144 of the logic chip 112A are electrically connected, and DUT measurement can be performed. Figure 8

[0094] In step S11 (in FIG. 12C), as shown in the uppermost section and the left side of the second section from the top in FIG. 12C, the terminal 121a is connected with the probe 191A, thereby electrically connecting the not-shown inspection device and the DUT 144 of the logic chip 112A to perform DUT measurement. Figure 9 Figure 9 In addition, as shown in the uppermost section and the right side of the second section from the top in FIG. 12C, the terminal 111aa is continuously connected with the probe 191B, thereby electrically connecting the not-shown inspection device and the test device 201 of the pixel chip 111a to perform test measurement of the pixel chip 111a.

[0095] Figure 9 In step S12, as shown in the left and right views of the third section from the top in FIG. 12D, the chip-stacked wafer 100 is cut with a dicing blade along the scribe line 121 to singulate the individual solid-state imaging devices 110, thereby completing the solid-state imaging devices 110 as products.

[0096] Figure 9 Note that,

[0097] the image P1 of the fourth section in FIG. 12E is a direct facing surface image in which the scribe line 121 is formed along the horizontal direction in FIG. 12E and three terminals 121a are formed on the surface of the scribe line 121, and the image P2 is a bird's-eye view image obtained by enlarging the terminal 121a formed on the scribe line 121. In addition, Figure 9 the image P3 of the fifth section in FIG. 12E is an image of the solid-state imaging device 110 as a packaged product. Figure 9 Figure 9 <<4. First Modified Example>>

[0098] <<4. First Modified Example>> ​​​​​​Although the example in which the water-resistant layers 161 and 162 are formed so as to sandwich the connection wiring 131 has been described above, the water-resistant layers 161 and 162 can be formed at other positions, for example, the water-resistant layers can be formed so as to surround the back surface side of the pixel chip 111a and the entire logic chip 112A.

[0099] Figure 10 A configuration example of the chip stack wafer 100A in which the water-resistant layers that surround the back surface side of the pixel chip 111a and the entire logic chip 112A are formed is shown. Note that, in the chip stack wafer 100A, the water-resistant layers 161 and 162 are formed so as to sandwich the connection wiring 131. Figure 10 In the following drawings, components having the same functions as the components of the chip stack wafer 100 described with reference to Figures 5 to 7 The components having the same functions as the components of the chip stack wafer 100 described with reference to

[0100] In the chip stack wafer 100A, the water-resistant layers 161 and 162 are formed so as to surround the back surface side of the pixel chip 111a and the entire logic chip 112A. Figure 10 In the chip stack wafer 100A, the water-resistant layers 161 and 162 are formed so as to surround the back surface side of the pixel chip 111a and the entire logic chip 112A.

[0101] Note that, when the logic chip 112A is stacked on the wafer 101, the water-resistant layers 251 in the Figure 10 can be formed in a process before the buried film 146 is formed.

[0102] The chip stack wafer 100 employing the CoW structure of the above-described configuration can also achieve DUT measurement. Furthermore, Figure 10 The water-resistant layers 251 in the can provide stronger water resistance.

[0103] <<5. Second Modified Example>> Although the example in which the DUT 144 in the logic chip 112A is formed inside the guard ring 141 has been described above, the DUT 144 can be formed outside the guard ring.

[0104] Figure 11 A configuration example of the chip stack wafer 100B in which the DUT 144 is formed outside the guard ring is shown.

[0105] As shown in the uppermost paragraph in the Figure 11 , the chip stack wafer 100B includes the wafer 101 and a logic layer 102'. In the logic chip 112A of the logic layer 102', the DUT 144 is formed outside a guard ring 141' corresponding to the guard ring 141.

[0106] Furthermore, as shown in the second paragraph from the top in the Figure 11 , the configuration of the pixel chip 111a in the wafer 101 is similar to the configuration shown in Figure 6 .

[0107] However, if Figure 11 As shown in the uppermost section of FIG, since the DUT 144 is arranged outside the guard ring 141 ', as shown in FIG. Figure 11 As shown in the third section from the top in FIG. 1 , a connection portion 142 ′ connected to a DUT 144 via a wiring 143 is formed outside the guard ring 141 ′.

[0108] The chip stacked wafer 100B having the CoW structure described above can also achieve DUT measurement.

[0109] <<6. Third Modification>> Although the example in which the DUT 144 of the logic chip 112A is formed outside the guard ring 141 ′ has been described above, the DUT 144 may be formed by being further surrounded by a seal ring inside the guard ring 141 .

[0110] Figure 12 A configuration example of a chip-stacked wafer 100C is shown in which the DUT 144 is formed inside a guard ring 141 and is surrounded by a seal ring.

[0111] That is to say, Figure 12 Chip-stacked wafer 100C includes wafer 101 and logic layer 102″. Within logic layer 102″, DUT 144 is arranged surrounded by guard ring 141 and further surrounded by seal ring 261 with water resistance. Seal ring 261 is formed in the back-end-of-line (BEOL) layer. Connections 142′ and DUT 144 are electrically connected via wiring 143′ corresponding to wiring 143.

[0112] Note that in Figure 12 In the embodiment, in addition to the DUT 144 on the substrate, an internal circuit 271 is formed on the substrate 145. The internal circuit 271 is formed inside the guard ring 141 but outside the seal ring 261.

[0113] According to the above configuration, the chip-stacked wafer 100C having a CoW structure can also realize DUT measurement.

[0114] <<7. Fourth Modification>> The above description has been made of a configuration in which the connection wiring 131 is formed at the boundary between the wafer 101 and the logic layer 102 and the terminal 121 a is electrically connected to the DUT 144 via the connection wiring 131 , the connection portion 131 a , the connection portion 142 ′, and the wiring 143 .

[0115] However, the connection wiring 131 may be arranged at a position other than the boundary between the wafer 101 and the logic layer 102 , and may be provided on the back surface side of the logic chip 112A viewed from, for example, the incident direction of incident light.

[0116] Figure 13 A configuration example of the chip-stacked wafer 100D in which the connection wiring is formed on the back surface side of the logic chip 112A is shown. The chip-stacked wafer 100D includes the wafer 101' and the logic layer 102'''. Note that, in Figure 13 the uppermost section shows a configuration example of the chip-stacked wafer 100D. The chip-stacked wafer 100D is a cross-sectional side view of the wafer 101' and the logic layer 102''', the second section from the top shows a configuration example of the back surface side of the logic chip 112A, and the third section from the top is a cross-sectional view of a layer in which the connection wiring 282 is formed.

[0117] That is, the connection wiring 131 is not routed at the boundary between the wafer 101' and the logic layer 102''', and instead of the connection wiring 131, a corresponding connection wiring 282 is formed on the back surface side of the logic chip 112A of the logic layer 102'''.

[0118] The left end portion in Figure 13 of the connection wiring 282 is connected with the terminal 121a via a wiring 281 including a through silicon via (TSV).

[0119] Further, a connection portion 282a is formed at the right end portion in Figure 13 of the connection wiring 282, and the connection portion 282a is connected with a connection portion 291 formed on the back surface side of the logic chip 112A. The connection portion 291 is electrically connected with the DUT 144 via a wiring 292 including a TSV. Thus, the terminal 121a is connected with the DUT 144 via the wiring 281, the connection wiring 282, the connection portion 282a, the connection portion 291, and the wiring 292.

[0120] Further, as shown in the second section in Figure 13 , a water-resistant layer 171' corresponding to the water-resistant layer 171 and made of silicon nitride or the like is formed on the back surface side of the logic chip 112A, and the water-resistant layer 171' is configured to have water resistance. However, a portion of the water-resistant layer 171' in which the connection portion 291 is formed is configured so that the connection portion 291 is exposed, so that in this configuration, the connection portion 291 can be electrically connected with the connection portion 282a.

[0121] According to the above configuration, the chip-stacked wafer 100D having the CoW structure in Figure 13 can also achieve DUT measurement.

[0122] <<8. Fifth Modified Example>> Although the chip-stacked wafer 100 of the CoW structure including two layers of the wafer 101 and the logic layer 102 has been described above, the chip-stacked wafer 100 can include three layers.

[0123] Figure 14 A configuration example of the chip-stacked wafer 300 of the CoW structure including three layers of the wafer 301, the intermediate layer 302, and the logic layer 303 is shown. Note that the intermediate layer 302 can be a wafer on which a plurality of semiconductor chips are formed, or a semiconductor layer formed by stacking monolithic semiconductor chips.

[0124] Note that the wafer 301 is a component corresponding to the wafer 101, and the scribe line 321, the terminal 321a, the protection ring 332, the terminal 321aa, the connection wiring 331, and the connection portion 331a of the wafer 301 are components corresponding to the scribe line 121, the terminal 121a, the protection ring 132, the terminal 121a, the connection wiring 131, and the connection portion 131a of the wafer 101, respectively.

[0125] Further, in the intermediate layer 302, the internal circuit 361-11 is formed over the substrate 345-1, and the protection ring 341-1 is formed. Further, in the intermediate layer 302, the connection portion 342-1, the wiring 343-1, and the connection portion 342-2 are also formed. The connection portions 342-1 and 342-2 are formed at both end portions of the wiring 343-1, respectively. The connection portion 342-1 is connected to the connection portion 331a of the connection wiring 331. The connection portion 342-2 is connected to the connection portion 342-3 of the logic layer 303.

[0126] An interlayer insulating film 371 is formed between the substrate 345-1 of the intermediate layer 302 and the logic layer 303.

[0127] Further, the logic layer 303 includes the logic chip 312A over which the protection ring 341-2 is formed, the internal circuits 361-21 and 361-22 are formed over the substrate 345-2 and inside the protection ring 341-2, and the DUT 344 is formed outside the protection ring 341-2. Further, the DUT 344 is connected to the connection portion 342-3 via the wiring 343-2.

[0128] That is, according to such a configuration, the terminal 321a is connected to the DUT 344 via the connection wiring 331, the connection portion 331a, the connection portion 342-1, the wiring 343-1, the connection portion 342-2, the connection portion 342-3, and the wiring 343-2.

[0129] As a result, the chip-stacked wafer 300 has Figure 14The chip-stacked wafer 301 of the three-layer CoW structure in which the DUT 344 of the logic chip 312A and the inspection device not shown are electrically connected by connecting the probe to the terminal 321a, so that DUT measurement can be achieved.

[0130] <<9. Sixth Modification Example>> The above has explained an example in which, in the chip-stacked wafer 300 of the three-layer CoW structure including the wafer 301, the intermediate layer 302, and the logic layer 303, the connection wiring 331 is formed at the boundary between the wafer 301 and the intermediate layer 302, and the terminal 321a and the DUT 344 of the logic chip 312A are electrically connected to achieve DUT measurement.

[0131] However, the connection wiring 331 can be formed at a position other than the boundary between the wafer 301 and the intermediate layer 302, for example, can be formed at the boundary between the intermediate layer 302 and the logic layer 303.

[0132] Figure 15 A configuration example of the chip-stacked wafer in which the connection wiring 331 is formed between the intermediate layer 302 and the logic layer 303 is shown.

[0133] In the chip-stacked wafer 300A of the three-layer CoW structure in which the DUT 344 of the logic chip 312A and the inspection device not shown are electrically connected by connecting the probe to the terminal 321a, so that DUT measurement can be achieved. Figure 15 Figure 14

[0134] In addition, the connection portion 342-11 connected to the terminal 321a is formed on the wafer 301, and the wiring 343-11 is formed in the intermediate layer 302. The Figure 15 end portion shown on the upper side in (a) is connected to the connection portion 342-11 via the connection portion 342-12, and its Figure 15 end portion shown on the lower side in (a) is electrically connected to the left end portion of the connection wiring 331A in (b). Figure 15

[0135] In addition, the connection portion 331Aa connected to the right end portion of the connection wiring 331A in (b) is connected to the connection portion 342-3 of the logic chip 312A, and is connected to the DUT 344 via the wiring 343-2. Figure 15 According to this configuration, in the chip-stacked wafer 300A of the three-layer CoW structure in which the DUT 344 of the logic chip 312A and the inspection device not shown are electrically connected by connecting the probe to the terminal 321a, so that DUT measurement can be achieved.

[0136] Figure 15 Figure 15 ​​​​​The left end is connected and Figure 15 The connection portion 331Aa at the left end portion of the logic chip 312A is connected to the connection portion 342-3 of the logic chip 312A.

[0137] That is, according to this configuration, the terminal 321a is connected to the DUT 344 via the connection portion 342-11, the connection portion 342-12, the wiring 343-11, the connection wiring 331A, the connection portion 331Aa, the connection portion 342-3, and the wiring 343-2.

[0138] As a result, Figure 16 The three-layer CoW structured chip stacked wafer 301A can also electrically connect the DUT 344 of the logic chip 312A and an inspection device (not shown) by connecting a probe to the terminal 321 a , thereby enabling DUT measurement.

[0139] <<10. Seventh Modification>> The above describes an example in which, in a chip stacked wafer 300 having a CoW structure including three layers of a wafer 301, an intermediate layer 302, and a logic layer 303, a connecting wiring 331A is formed at the boundary between the intermediate layer 302 and the logic layer 303, and the terminal 321a and the DUT 344 of the logic chip 312A are electrically connected to realize DUT measurement.

[0140] However, the connection wiring 331 may be formed at a position other than the boundary between the intermediate layer 302 and the logic layer 303 , for example, may be formed within the interlayer insulating film 371 in the intermediate layer 302 .

[0141] Figure 16 A configuration example of a chip-stacked wafer is shown in which the connection wiring 331 is formed within the interlayer insulating film 371 of the intermediate layer 302 .

[0142] exist Figure 15 In the chip stacked wafer 300B, the connection wiring 331B is formed in the interlayer insulating film 371 of the intermediate layer 302 instead of Figure 16 The connection wiring 331A in the chip-stacked wafer 300A.

[0143] According to this construction, Figure 16 In the chip stacked wafer 300B, the terminal 321a is connected to the connection portion 342-11, and the connection portion 342-11 is connected to the wiring 343-11 via the connection portion 342-12. Figure 16 The left end of the wiring 331B is connected to Figure 16 The connection portion 331Ba at the right end of the chip 312 is connected to the connection portion 342 - 3 of the logic chip 312A.

[0144] That is, according to this configuration, the terminal 321 a is connected to the DUT 344 via the connection portion 342 - 11 , the connection portion 342 - 12 , the wiring 343 - 11 , the connection wiring 331B, the connection portion 331Ba, the connection portion 342 - 3 , and the wiring 343 - 2 .

[0145] As a result, Figure 17 The three-layer CoW structured chip stacked wafer 301B can also electrically connect the DUT 344 of the logic chip 312A and an inspection device (not shown) by connecting a probe to the terminal 321 a , thereby enabling DUT measurement.

[0146] <<11. Eighth Modification>> The connection wiring 331 may be formed at a position other than the boundary between the intermediate layer 302 and the logic layer 303 or within the interlayer insulating film 371 in the intermediate layer 302 , for example, may be formed on the substrate 345 - 1 of the intermediate layer 302 .

[0147] Figure 17 A configuration example of a chip-stacked wafer is shown in which the connection wiring 331 is formed in the substrate 345 - 1 of the intermediate layer 302 .

[0148] exist Figure 16 In the chip stacked wafer 300C, a connection wiring 331C is formed on the substrate 345-1 of the intermediate layer 302 instead of Figure 17 The connection wiring 331B in the chip-stacked wafer 300B.

[0149] According to this construction, Figure 17 In the chip stacked wafer 300C, the terminal 321a is connected to the connection portion 342-11, and the connection portion 342-11 is connected to the wiring 343-11 via the connection portion 342-12. Figure 17 and connect the left end of the wiring 331C Figure 17 The connection portion 331Ca at the right end of the circuit is connected to the connection portion 342-3 of the logic chip 312A.

[0150] That is, according to this configuration, the terminal 321 a is connected to the DUT 344 via the connection portion 342 - 11 , the connection portion 342 - 12 , the wiring 343 - 11 , the connection wiring 331C, the connection portion 331Ca, the connection portion 342 - 3 , and the wiring 343 - 2 .

[0151] As a result, Figure 18The chip-stacked wafer 301C of the three-layer CoW structure in the chip-stacked wafer 301 can also electrically connect the DUT 344 of the logic chip 312A and the inspection device not shown by connecting a probe to the terminal 321a, and thus DUT measurement can be achieved.

[0152] <<12. Ninth Modification>> The above has explained an example in which the terminal 321a and the DUT 344 of the logic chip 312A are electrically connected to achieve DUT measurement in the chip-stacked wafer 300 of the three-layer CoW structure including the wafer 301, the intermediate layer 302, and the logic layer 303.

[0153] However, if a plurality of logic chips 312A are further stacked, the plurality of logic chips 312A can be connected by connection wiring to be electrically connectable to each other.

[0154] Figure 18 A configuration example of the chip-stacked wafer in which the connection wiring connecting two logic chips 312A is formed in the interlayer insulating film 371 of the intermediate layer 302 is shown.

[0155] Figure 16 The chip-stacked wafer 300D of the three-layer CoW structure in the chip-stacked wafer 300B shows an example in which two logic chips 312A-1 and 312A-2 are stacked in the logic layer 303 of the chip-stacked wafer 300B, and connected to each other by the connection wiring 381. Figure 16 The chip-stacked wafer 300D of the three-layer CoW structure in the chip-stacked wafer 300B shows an example in which two logic chips 312A-1 and 312A-2 are stacked in the logic layer 303 of the chip-stacked wafer 300B, and connected to each other by the connection wiring 381.

[0156] Note that the logic chip 312A-1 of the logic chips 312A-1 and 312A-2 includes the DUT 344 associated with the logic chip 312A in the chip-stacked wafer 300B, and adopts the same configuration in which the terminal 321a is electrically connected to the DUT 344 by connecting a probe to the terminal 321a, and thus the explanation of the configuration will be omitted. In this regard, the difference between the chip-stacked wafer 300D and the chip-stacked wafer 300B is that the DUT 344 is formed on the outside of the protection ring 341-2-1. Figure 18 Figure 16 The chip-stacked wafer 300D of the three-layer CoW structure in the chip-stacked wafer 300B shows an example in which two logic chips 312A-1 and 312A-2 are stacked in the logic layer 303 of the chip-stacked wafer 300B, and connected to each other by the connection wiring 381.

[0157] In addition to the functions of the logic chip 312A in the chip-stacked wafer 300B, the logic chip 312A-1 includes the internal circuit 361-31 formed on the substrate 345-2-1 on the inside of the protection ring 341-2-1, and is connected to the connection portion 391-1 via the wiring 392-1. Figure 18 The logic chip 312A-2 includes the protection ring 341-2-2, includes the internal circuit 361-32 formed on the substrate 345-2-2 on the inside of the protection ring 341-2-2, and is connected to the connection portion 391-2 via the wiring 392-2.

[0158]

[0159] ​​The connection wiring 381 is formed in the interlayer insulating film 371 of the intermediate layer 302, and includes two end portions formed with connection portions 381a-1 and 381a-2. Further, the connection portion 381a-1 is connected to the connection portion 391-1 of the logic chip 312A-1, and the connection portion 381a-2 is connected to the connection portion 391-2 of the logic chip 312A-2.

[0160] According to this configuration, in the chip stack wafer 300D, Figure 18 the internal circuit 361-31 of the logic chip 312A-1 and the internal circuit 361-32 of the logic chip 312A-2 are electrically connected via the connection portion 391-1, the connection portion 381a-1, the connection wiring 381, the connection portion 381a-2, and the connection portion 391-2.

[0161] As a result, the chip stack wafer 301D having a CoW structure of three layers in Figure 19 can also electrically connect the DUT 344 of the logic chip 312A-1 and the inspection device not shown by connecting a probe to the terminal 321a, and thus DUT measurement can be achieved.

[0162] Further, the internal circuits 361-31 and 361-32 of the two logic chips 312A-1 and 312A-2 are connected by the connection wiring 381, and thus can transmit and receive data and signals to and from each other.

[0163] Note that the connection wiring 381 connecting the logic chips 312A-1 and 312A-2 can be formed not only in the interlayer insulating film 371 of the intermediate layer 302, but also at the boundary between the wafer 301 and the intermediate layer 302, or in the substrate 345-1 of the intermediate film 302.

[0164] <<13. Tenth Modification Example>> Although the example of achieving DUT measurement for one DUT 344 has been described above, a plurality of DUTs can be provided, and switching can be performed to perform DUT measurement.

[0165] Figure 19 A configuration example of a chip stack wafer of a CoW structure in which DUT measurement is achieved by switching between two DUTs is shown.

[0166] Figure 16 The chip stack wafer 300E adopts a configuration in which, in addition to the DUT 344 of the logic layer 303 in the chip stack wafer 300B, Figure 19 a DUT 344 is also added to the intermediate layer, and DUT measurement can be achieved by switching between these DUTs 344 by the switching circuit 401.

[0167] Note that, in the chip stack wafer 300E,Figure 16 In this case, the configuration of the chip-stacked wafer 300B shown in Figure 16 is adopted as a basic configuration, and the DUT of the logic layer 303 is referred to as a DUT 344-1, and the DUT of the intermediate layer 302 is referred to as a DUT 344-2.

[0168] Further, the configuration of the DUT 344-1 of the logic layer 303 after the connection wiring 331B is the same as the configuration of the chip-stacked wafer 300B shown in Figure 18 , and thus the explanation thereof will be omitted.

[0169] That is, in the chip-stacked wafer 300E shown in Figure 16 , the difference from the chip-stacked wafer 300B shown in Figure 19 is that the intermediate layer 304 is provided with a switching circuit 401, a connection wiring 331D, and a DUT 344-2.

[0170] The switching circuit 401 is connected with the wiring 343-11 and the connection wirings 331B and 331D. That is, the switching circuit 401 adopts a configuration in which the switching circuit 401 is connected with the terminal 321a via the connection portions 342-11 and 342-12 and the wiring 343-11, and the terminal 321a is connected with a probe to enable a not-shown inspection device to be connected to the terminal 321a. Further, when the switching circuit 401 is electrically connected with the inspection device, the switching circuit 401 is controlled by the inspection device, and the DUTs 344-1 and 344-2 as DUT measurement targets are switched based on an instruction from the inspection device to enable DUT measurement.

[0171] More specifically, when an instruction to set the DUT 344-1 as a DUT measurement target is received, the switching circuit 401 sets the DUT 344-1 of the logic chip 312A of the logic layer 303 as a measurement target, and enables DUT measurement via the connection wiring 331B, the connection portion 331Ba, the connection portion 342-3, and the wiring 343-2.

[0172] Further, when an instruction to set the DUT 344-2 as a DUT measurement target is received, the switching circuit 401 sets the DUT 344-2 of the intermediate layer 302 as a measurement target, and enables DUT measurement via the connection wiring 331D.

[0173] As a result, the chip-stacked wafer 300E having the three-layer CoW structure shown in ​ can switch between the DUT 344-1 of the logic chip 312A-1 in the logic layer 303 and the DUT 344-2 of the intermediate layer 302 by connecting a probe to the terminal 321a, and thus enable DUT measurement.

[0174] Note that the present disclosure can also employ the following configurations.

[0175] <1> A semiconductor device comprising: a first semiconductor chip including an image pickup element; a second semiconductor chip different from the first semiconductor chip; and a connection wiring electrically connecting an internal circuit that is a circuit within the second semiconductor chip, an external circuit that is a circuit outside the second semiconductor chip, or a terminal outside the second semiconductor chip. <2> The semiconductor device described in <1>, wherein the terminal is a terminal formed in a scribe line that is at a position cut by a dicing blade when the semiconductor device is singulated from a wafer on which the semiconductor device has been formed in a manufacturing process. <3> The semiconductor device described in <2>, wherein the terminal is formed in the scribe line formed when the semiconductor device is singulated from the wafer in a manufacturing process, the semiconductor device being manufactured by laminating the singulated second semiconductor chip on the first semiconductor chip formed on the wafer. <4> The semiconductor device described in <2>, wherein the first semiconductor chip has an end portion, a periphery of the end portion is surrounded by a protection ring, and the scribe line is formed outside the protection ring. <5> The semiconductor device described in <1>, wherein the second semiconductor chip has an end portion, a periphery of the end portion is at least partially surrounded by a protection ring, and the internal circuit is formed outside the protection ring. <6> The semiconductor device described in <1>, wherein the second semiconductor chip has an end portion, a periphery of the end portion is at least partially surrounded by a protection ring, and the internal circuit is formed inside the protection ring. <7> The semiconductor device described in <6>, wherein the second semiconductor chip has an end portion, a periphery of the end portion is at least partially surrounded by a protection ring, and the internal circuit is formed inside the protection ring further inside a sealing ring. <8> The semiconductor device described in <1>, wherein the connection wiring is formed in an insulating film within the first semiconductor chip. <9> The semiconductor device described in <8>, wherein the connection wiring is formed in a bonding interface between the first semiconductor chip and the second semiconductor chip. <10> The semiconductor device described in <8>, wherein the connection wiring is surrounded by a protection ring in at least a portion of a periphery. <11> exist <8> In the semiconductor device, the connection wiring is sandwiched by a water-resistant film having water resistance in at least one of the front section and the rear section in the incident direction of incident light with respect to the imaging plane of the imaging element. <12> exist <8> In the semiconductor device, the connection wiring is formed so as to sandwich the first semiconductor chip and the second semiconductor chip. <13> exist <1> The semiconductor device further includes an intermediate layer between a first layer including the first semiconductor chip and a second layer including the second semiconductor chip, and The connection wiring is formed in the intermediate layer. <14> exist <13> In the semiconductor device, the connection wiring is formed in the substrate of the intermediate layer. <15> exist <13> In the semiconductor device, the connection wiring is formed in the insulating film of the intermediate layer. <16> exist <15> In the semiconductor device, the connection wiring connects the internal circuit formed in the second layer and the external circuit formed in the second layer. <17> exist <16> In the semiconductor device, the external circuit in the second layer is an internal circuit formed in the second layer and included in a third semiconductor chip different from the second semiconductor chip. <18> exist <1> In the semiconductor device, the second semiconductor chip includes a first internal circuit and a second internal circuit different from the first internal circuit as the internal circuit, and The connecting wiring includes: a first connecting wiring electrically connecting the first internal circuit in the second semiconductor chip and the terminal outside the second semiconductor chip, and A second connecting wiring electrically connects the second internal circuit in the second semiconductor chip and the external circuit which is a circuit outside the second semiconductor chip. <19> exist <1> In the semiconductor device, The internal circuit is a test device for the second semiconductor chip, and An inspection device that inspects an operation state of the second semiconductor chip is electrically connected to the terminals via probes and thereby to the test device via the terminals and the connection wirings, and controls the test device to inspect the operation state of the second semiconductor chip. <20> exist <19> The semiconductor device further comprises: another test device that tests another circuit different from the test device of the second semiconductor chip; another connection wiring different from the connection wiring connected to the other test device; and a switching unit connected to the terminal, the connection wiring, and the other connection wiring, and switching whether the terminal and the test device are connected via the connection wiring or the terminal and the other test device are connected via the other connection wiring. List of Reference Numerals

[0176] 100, 100A to 100D Chip stack wafer 101 Wafer 102 Logic layer 110 Solid-state imaging device 111a Solid-state imaging element 111aa Terminal 111ab Color filter 112A Logic chip 121 Scribe line 121a Terminal 131 Connection wiring 131a Connection portion 141 Guard ring 142 Connection portion 143 Wiring 144 DUT 145 Substrate 146 Buried film 161, 162 Water-resistant layer 171, 171' Water-resistant layer 191, 191A, 191B Probe 251 Water-resistant layer 261 Sealing ring 282 Connection wiring 282a Connection portion 291 Connection portion 300, 300A to 300E Chip stack wafer 301 Wafer 302 Intermediate layer 303 Logic layer 311aa Terminal 321 Scribe line 321a Terminal 331, 331A to 331D Connection wiring 331a, 331Aa to 331Da Connection portion 344, 344-1, 344-2 DUT 381 connection wiring

Claims

1. A semiconductor device comprising: A first semiconductor chip including an imaging element; a second semiconductor chip, which is different from the first semiconductor chip; as well as The connecting wiring electrically connects an internal circuit, which is a circuit within the second semiconductor chip, to an external circuit or a terminal outside the second semiconductor chip. The internal circuit is a circuit within the second semiconductor chip, and the external circuit is a circuit outside the second semiconductor chip.

2. The semiconductor device according to claim 1, wherein the terminals are terminals formed in scribe lines located at positions cut by a dicing blade when the semiconductor devices are singulated from a wafer on which the semiconductor devices are formed during a manufacturing process.

3. A semiconductor device according to claim 2, wherein the terminals are formed in the scribe lines formed when the semiconductor device is singulated from the wafer during the manufacturing process, and the semiconductor device is manufactured by stacking the singulated second semiconductor chip on the first semiconductor chip formed on the wafer. 4 . The semiconductor device according to claim 2 , wherein the first semiconductor chip has an end portion, a periphery of the end portion is surrounded by a guard ring, and the scribe line is formed outside the guard ring. 5 . The semiconductor device according to claim 1 , wherein the second semiconductor chip has an end portion, a periphery of the end portion is at least partially surrounded by a guard ring, and the internal circuit is formed outside the guard ring. 6 . The semiconductor device according to claim 1 , wherein the second semiconductor chip has an end portion, a periphery of the end portion is at least partially surrounded by a guard ring, and the internal circuit is formed inside the guard ring. 7 . The semiconductor device according to claim 6 , wherein the second semiconductor chip has an end portion, a periphery of the end portion is at least partially surrounded by a guard ring, and the internal circuit is formed inside the guard ring and further formed inside the seal ring. 8 . The semiconductor device according to claim 1 , wherein the connection wiring is formed in an insulating film within the first semiconductor chip. 9 . The semiconductor device according to claim 8 , wherein the connection wiring is formed in a bonding interface between the first semiconductor chip and the second semiconductor chip. 10 . The semiconductor device according to claim 8 , wherein the connection wiring is surrounded by a guard ring in at least a portion of its circumference. 11 . The semiconductor device according to claim 8 , wherein the connection wiring is sandwiched by a water-resistant film having water resistance in at least one of a front section and a rear section in an incident direction of incident light with respect to an imaging plane of the imaging element. 12 . The semiconductor device according to claim 8 , wherein the connection wiring is formed so as to sandwich the first semiconductor chip and the second semiconductor chip.

13. The semiconductor device according to claim 1 , further comprising an intermediate layer between a first layer including the first semiconductor chip and a second layer including the second semiconductor chip, wherein the connecting wiring is formed in the intermediate layer. 14 . The semiconductor device according to claim 13 , wherein the connection wiring is formed in a substrate of the intermediate layer. 15 . The semiconductor device according to claim 13 , wherein the connection wiring is formed in an insulating film of the intermediate layer. 16 . The semiconductor device according to claim 15 , wherein the connection wiring connects the internal circuit formed in the second layer and the external circuit in the second layer. 17 . The semiconductor device according to claim 16 , wherein the external circuit in the second layer is an internal circuit formed in the second layer and included in a third semiconductor chip different from the second semiconductor chip.

18. The semiconductor device according to claim 1, wherein The second semiconductor chip includes a first internal circuit and a second internal circuit different from the first internal circuit as the internal circuit, and The connecting wiring includes: a first connecting wiring electrically connecting the first internal circuit in the second semiconductor chip and the terminal outside the second semiconductor chip, and A second connecting wiring electrically connects the second internal circuit in the second semiconductor chip and the external circuit which is a circuit outside the second semiconductor chip.

19. The semiconductor device according to claim 1, wherein The internal circuit is a test device for the second semiconductor chip, and An inspection device that inspects an operation state of the second semiconductor chip is electrically connected to the terminals via probes and thereby to the test device via the terminals and the connection wirings, and controls the test device to inspect the operation state of the second semiconductor chip.

20. The semiconductor device according to claim 19, further comprising: another test device for testing another circuit different from the test device of the second semiconductor chip; other connecting wires, which are different from the connecting wires connected to the other test devices; as well as A switching unit is connected to the terminal, the connection wiring, and the other connection wiring, and switches whether the terminal and the test device are connected via the connection wiring or the other connection wiring.

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