A method, system and electronic device for inter-core communication based on hardware management

Abstract

The application belongs to the technical field of electronic information, and discloses a kind of inter-core communication method, system and electronic equipment based on hardware management, comprising: first processor core inquires the communication state flag bit of second processor core;If communicable state, dynamically apply memory block in shared memory;Write the data to be sent into memory block, and generate data header node;First processor core adds data header node to the first data linked list maintained by first processor core;Hardware management module monitors first data linked list, and when monitoring data header node increases and second processor core is communicable, automatically sends interrupt signal to second processor core;Second processor core responds to interrupt signal, obtains target data header node from second data linked list, and reads data in shared memory according to the information contained in target data header node.By introducing special hardware management module and using dynamic memory management mechanism, the utilization rate of shared memory is greatly improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of electronic information technology, and particularly relates to a method and system for inter-core communication based on hardware management and electronic equipment. BACKGROUND

[0002] With the rapid development of mobile communication and embedded technology, a system on chip generally adopts a multi-core heterogeneous architecture, integrating multiple processor cores such as an application processor (AP) and a communication processor (CP) that can independently run an operating system. Frequent and efficient data exchange is required between these processor cores, and the performance and efficiency of the inter-processor communication (IPC) technology directly affect the throughput, delay and power consumption of the entire system.

[0003] In the prior art, inter-core communication is generally implemented based on shared memory combined with a message notification mechanism. Specifically, during the initialization phase, the system fixedly divides a shared memory region with a pre-set size and physical address for each communication data sending channel as a data transmission buffer dedicated to the data sending channel.

[0004] Since the size and number of shared memories are fixed at the initialization stage, in order to ensure that the maximum throughput is met, there is a large redundancy of shared memories; resulting in a large amount of memory space being idle under most normal working conditions. This not only causes waste of memory resources, but also makes the DDR (Dynamic Random-Access Memory) memory controller unable to effectively manage the low power consumption of these idle blocks. SUMMARY

[0005] The purpose of the present application is to greatly improve the utilization rate of shared memory by introducing a dedicated hardware management module and using a dynamic memory management mechanism. The key operations such as channel management, state monitoring, interrupt triggering and information synchronization are transferred from software to dedicated hardware modules for execution. The execution efficiency of hardware logic is much higher than that of software, which significantly reduces the delay of inter-core communication and meets the high real-time communication requirements.

[0006] In a first aspect, an embodiment of the present application provides a method for inter-core communication based on hardware management, applied to a system on chip comprising a first processor core, a second processor core and a hardware management module. The first processor core and the second processor core are respectively provided with independent communication state flag bits to represent their communicable states. The method comprises:

[0007] The first processor core queries a communication state flag bit of the second processor core when data needs to be sent to the second processor core;

[0008] If the second processor core is in a communicable state, the first processor core dynamically applies a memory block from the shared memory, and a size of the memory block is determined based on a size of current data to be sent;

[0009] The first processor core writes the data to be sent into the memory block, and generates a data head node containing a data sending channel identifier, a memory block address, a memory block size and a next node pointer;

[0010] The first processor core adds the data head node to a first data linked list maintained by the first processor core;

[0011] The hardware management module monitors the first data linked list, and automatically sends an interrupt signal to the second processor core when it is monitored that a data head node is added and the second processor core is communicable; and in response to an update of the first data linked list, synchronizes information contained in the newly added data head node to a second data linked list maintained by the second processor core;

[0012] The second processor core, in response to the interrupt signal, acquires a target data head node to be processed currently from the second data linked list, and reads data in the shared memory according to information contained in the target data head node.

[0013] Optionally, the method further comprises:

[0014] The hardware management module maintains a write pointer, a read pointer and a work pointer corresponding to the data sending channel;

[0015] The write pointer is used to indicate a position of a latest added data head node in the first data linked list; the read pointer is used to indicate a position of a latest read data head node in the second data linked list; and the work pointer is used to indicate a position of a released memory block.

[0016] Optionally, the method further comprises:

[0017] After the first processor core adds the data head node to the first data linked list, the hardware management module updates the write pointer;

[0018] The second processor core reads data from the shared memory;

[0019] The hardware management module, in response to the data reading operation, updates the read pointer;

[0020] The hardware management module sends an interrupt signal to the first processor core when detecting that the read pointer changes relative to the work pointer;

[0021] The first processor core releases the memory block occupied by the read data indicated by the read pointer and updates the work pointer in response to the interrupt signal.

[0022] Optionally, the method further comprises:

[0023] When the second processor core needs to send data to the first processor core, the first processor core pre-allocates a plurality of memory blocks of fixed size in a sending channel and generates a corresponding data head node for each of the memory blocks to form a third data linked list; wherein the sending channel and the receiving channel are different channels.

[0024] The first processor core notifies the hardware management module to update the work pointer through a configuration register, and the work pointer is used to indicate the position of the memory block that has been pre-allocated and can be used by the second processor core.

[0025] When the hardware management module detects that the second processor core sends data to the first processor core, the hardware management module sends an interrupt signal to the first processor core;

[0026] The first processor core determines the data head node that has been written by the second processor core from the third data linked list;

[0027] According to the memory block address in the data head node that has been written by the second processor core, data is read from the corresponding memory block.

[0028] Optionally, the method further comprises:

[0029] The first processor core releases the memory block of the read data and updates the read pointer to obtain the latest data head node position that has been read;

[0030] One or more of the memory blocks of fixed size are re-applied, and the data head node corresponding to the re-applied memory block is supplemented into the third data linked list for subsequent use by the second processor core when sending data to the first processor core.

[0031] Optionally, the method further comprises:

[0032] Before the second processor core sends data to the first processor core, the communication state flag bit of the first processor core is queried;

[0033] if the first processor core is in the communicable state, an idle data head node is obtained from a fourth data link list maintained by the second processor core, the to-be-sent data is written into a memory block corresponding to the node, and a write pointer is updated.

[0034] if the first processor core is in the communicable state, an idle data head node is obtained from a fourth data link list maintained by the second processor core, the to-be-sent data is written into a memory block corresponding to the node, and a write pointer is updated.

[0035] Optionally, when the hardware management module detects that the second processor core sends data to the first processor core, an interrupt signal is sent to the first processor core, including:

[0036] When the hardware management module detects the update of the write pointer, an interrupt signal is sent to the first processor core to inform it to read data.

[0037] Optionally, when the hardware management module detects that the write pointer is consistent with the work pointer, an interrupt signal is sent to the first processor core to instruct the first processor core to supplement an idle data head node and a memory block for the third data link list.

[0038] In a second aspect, an inter-core communication system based on hardware management is provided, which is integrated into a system on chip, and includes a first processor core, a second processor core, a hardware management module, and a shared memory.

[0039] The first processor core and the second processor core are respectively configured with independent communication state flag bits, which are used to indicate the communicable state of the first processor core and the second processor core.

[0040] The first processor core is configured to, when data needs to be sent to the second processor core, query the communication state flag bit of the second processor core; if the second processor core is in the communicable state, dynamically apply a memory block from the shared memory; write the to-be-sent data into the memory block, and generate a data head node containing a data sending channel identifier, a memory block address, a memory block size, and a next node pointer; and add the data head node to a first data link list maintained by the first processor core; the size of the memory block is determined based on the size of the current to-be-sent data.

[0041] The hardware management module is configured to monitor the first data link list, and when it is detected that a data head node is added and the second processor core is communicable, automatically send an interrupt signal to the second processor core; and in response to the update of the first data link list, synchronize the information contained in the newly added data head node to a second data link list maintained by the second processor core.

[0042] The second processor core is configured to obtain a target data head node currently to be processed from the second data link table in response to an interrupt signal, and read data in the shared memory according to information contained in the target data head node.

[0043] In a third aspect, an electronic device is provided, which comprises the hardware management-based inter-core communication system as described in the above embodiments.

[0044] The electronic device is a mobile phone, a tablet computer, a base station, a router or an Internet of Things terminal device.

[0045] The hardware management-based inter-core communication method provided by the embodiments of the present application realizes on-demand allocation of memory resources by introducing a special hardware management module and using a dynamic memory management mechanism, greatly improves the utilization rate of shared memory, and avoids waste caused by memory redundancy. This not only saves memory resources, but also reduces the power consumption of DDR memory; and the present application transfers key operations such as channel management, state monitoring, interrupt triggering and information synchronization from software to special hardware modules for execution, and the execution efficiency of hardware logic is much higher than that of software, greatly reducing the uncertainty caused by operating system scheduling delay and software processing overhead, so that the delay of inter-core communication is significantly reduced, the throughput is effectively improved, the high real-time communication demand is met, and the software burden of the processor core is greatly reduced.

[0046] In addition, the embodiments of the present application set a communication state flag bit for the processor core, and decide whether to initiate communication by querying the communication state flag bit of the second processor core, which can save the complex software handshake process in the prior art. The simple communication state flag bit query mechanism greatly reduces the risk of logical problems such as communication channel deadlock and data error caused by handshake failure, timeout or race conditions, making the inter-core communication of multiple cores more stable and reliable. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 A flowchart of a hardware management-based inter-core communication method provided by the embodiments of the present application is provided.

[0048] Figure 2 A flowchart of the updating process of the read pointer, the write pointer and the work pointer provided by the embodiments of the present application is provided.

[0049] Figure 3 A flowchart of a specific process of the second data processor core sending data to the first processor core provided by the embodiments of the present application is provided.

[0050] Figure 4 A schematic diagram of a system architecture provided by the embodiments of the present application is provided. DETAILED DESCRIPTION

[0051] The application will be described in detail below through examples.

[0052] With the rapid development of mobile communication and embedded technology, a system on chip generally adopts a multi-core heterogeneous architecture, integrating multiple processor cores such as an application processor (AP) and a communication processor (CP) that can independently run an operating system. Frequent and efficient data exchange is required between these processor cores, and the performance and efficiency of the inter-processor communication (IPC) technology directly affect the throughput, delay and power consumption of the entire system.

[0053] In the prior art, inter-processor communication is generally implemented based on shared memory combined with a message notification mechanism. Specifically, during the initialization phase, the system needs to fixedly divide a shared memory region with a pre-set size and physical address for each communication data sending channel as a data transmission buffer dedicated to the data sending channel.

[0054] Since the size and number of shared memories are fixed at the initialization stage, in order to ensure that the maximum throughput is met, there will be a large amount of redundancy in the shared memory; resulting in a large amount of memory space being idle under most normal working conditions. This not only causes waste of memory resources, but also makes the DDR (Dynamic Random-Access Memory) memory controller unable to effectively manage the low power consumption of these idle blocks.

[0055] Moreover, in the prior art, the establishment, management, state maintenance of the channel and the allocation and release of the memory are completely responsible by the software running on each processor, i.e. by the CPU. The complex handshake protocol is extremely susceptible to the influence of the operating system task scheduling, introducing unpredictable delays, and thus restricting the communication speed. At the same time, in a complex multi-task concurrent environment, software management is easy to introduce logical problems such as race conditions and deadlocks, resulting in reduced system stability.

[0056] In order to solve the above technical problems of the prior art, the embodiments of the present application provide an inter-processor communication method based on hardware management, applied to a system on chip comprising a first processor core, a second processor core and a hardware management module, the first processor core and the second processor core are respectively provided with independent communication state flag bits to represent their communicable states.

[0057] It should be noted that the embodiments of the present invention do not limit the specific type of processor core; the architecture of the first processor core, the second processor core, and the hardware management module is applicable to any processing unit in a System-on-a-Chip (SoC) that requires data exchange. This architecture provides a general, standardized, and efficient inter-core communication solution with broad applicability and good scalability.

[0058] The hardware-managed inter-core communication method provided in this invention relies on a dedicated hardware management module (SIPC SMEM IP) to replace the cumbersome software handshake and coordination process, enabling efficient and dynamic inter-core data transfer. SIPC stands for System Inter-Processor Communication. SMEM stands for Shared Memory Management. IP stands for Intellectual Property Core.

[0059] The steps of this method will be explained in detail below with reference to the accompanying drawings.

[0060] like Figure 1 As shown in the figure, an inter-core communication method based on hardware management provided by an embodiment of the present invention may include the following steps:

[0061] S110, when the first processor core needs to send data to the second processor core, it queries the communication status flag bit of the second processor core.

[0062] In this system, the first processor core acts as the data sender, for example, it could be an application processor (AP). The first processor core also acts as the data receiver, for example, it could be a communication processor (CP). When a service module on the first processor core needs to send data to the second processor core, it first queries the communication status flag of the second processor core. In practical applications, this communication status flag can be represented as SIPC_ready_flag_CPU_XX. This flag is maintained by each processor core itself and is typically set when its own software stack initialization is complete and it can handle communication transactions normally.

[0063] This step, by querying a globally visible communication status flag, allows the first processor core to quickly confirm whether the other end (i.e., the second processor core) is in a healthy and operational state before initiating any substantive communication process. This approach completely eliminates the complex software handshake protocol found in existing technologies, significantly reduces communication latency, and provides the system with a simple and unified communication status management mechanism.

[0064] S120, if the second processor core is in a communicable state, the first processor core dynamically applies a memory block from the shared memory.

[0065] The size of the memory block is determined based on the size of the current data to be sent.

[0066] If the query result is that the second processor core is in a communicable state, the first processor core dynamically applies a memory block from the shared memory pool. Here, the dynamic application of a memory block can be understood as that the size of the memory block is not fixed in advance, but is determined in real time based on the actual size of the current data packet to be sent.

[0067] It can be seen that, compared with the prior art of dividing a fixed size memory pool at initialization, the dynamic application mechanism realizes on-demand allocation, greatly improves the utilization rate of shared memory resources, avoids memory waste caused by static allocation, and thus effectively reduces the overall power consumption of the system, especially the static power consumption of DDR memory.

[0068] S130, the first processor core writes the data to be sent to the memory block, and generates a data head node containing a data sending channel identifier, a memory block address, a memory block size, and a next node pointer.

[0069] Specifically, the first processor core writes the data to be sent to the memory block applied in step S120. And generates a data head node corresponding to the memory block. The data head node does not contain actual data, but is meta-information describing the data, which at least includes: a channel identifier, a memory block address, a memory block size, and a next node pointer.

[0070] The channel identifier is used to identify the business logic channel (such as audio, video, control signaling, etc.) to which the data to be sent belongs, to ensure that the data can be processed by the correct business module of the second processor core.

[0071] The memory block address is a physical address pointing to the actual data stored in the shared memory.

[0072] The memory block size is used to represent the length of the data to be sent.

[0073] The next node pointer is used to point to the next data head node, so as to link multiple data head nodes into a linked list structure.

[0074] This step separates the data itself from the data management information (i.e. the data head node), and the linked list of the data management information provides great flexibility, which can efficiently manage multiple indefinite length and indefinite time data packets.

[0075] S140, the first processor core adds the data head node to the first data linked list maintained by the first processor core.

[0076] Specifically, the first processor core adds the data head node generated in step S130 as a new link list member to the tail of a first data link list (also referred to as a sending data link list) maintained by itself. The first data link list is specially used for managing all data packets that are ready to be sent but have not been confirmed by the receiving end.

[0077] S150, the hardware management module monitors the first data link list and automatically sends an interrupt signal to the second processor core when it detects that a data head node is added and the second processor core is communicable; and in response to the update of the first data link list, synchronizes the information contained in the newly added data head node to the second data link list maintained by the second processor core.

[0078] Specifically, the hardware management module (i.e. the SIPC SMEM IP mentioned above) continuously monitors the state of the first data link list. By comparing link list pointers and the like, it automatically detects that a new data head node is added (i.e. the link list changes from empty to non-empty, or the length of the link list increases). Once it detects that a new data head node is added and confirms that the communication status flag of the second processor core is still in a communicable state, the hardware management module automatically sends an interrupt signal to the second processor core.

[0079] This step changes the data ready notification mechanism from software implementation to hardware implementation, and the monitoring of the hardware management module is real-time and not affected by CPU scheduling delays, thereby eliminating the delay and uncertainty caused by software notification and greatly improving the real-time performance and reliability of communication.

[0080] At the same time, in response to the update of the first data link list, the hardware management module automatically synchronizes the key information (at least including the memory block address and size) contained in the newly added data head node to the second data link list (also referred to as the third data link list) maintained by the second processor core.

[0081] This step can ensure that the second processor core can losslessly obtain the data management information of the first processor core. This synchronization process is also completed by the hardware management module without the software intervention of the first processor core and the second processor core, which is extremely efficient and avoids the race conditions that may exist in software operations.

[0082] S160, the second processor core responds to the interrupt signal to obtain the target data head node currently to be processed from the second data link list, and reads the data in the shared memory according to the information contained in the target data head node.

[0083] Specifically, in response to the interrupt signal received in step S150, an interrupt service routine or a dedicated receiving thread of the second processor core is activated, and the target data head node currently to be processed is obtained from the local second data link table, and the memory block address and size information contained in the target data head node are used to directly access the specified location in the shared memory to accurately read out the complete data packet written by the first processor core, which is then delivered to the upper-layer service application.

[0084] In this step, the second processor core can quickly and accurately locate and obtain data under the accurate notification of hardware, and completes the closed loop of the entire efficient communication process.

[0085] The inter-core communication method based on hardware management provided by the embodiment of the application realizes on-demand allocation of memory resources by introducing a dedicated hardware management module and using a dynamic memory management mechanism, greatly improves the utilization rate of shared memory, and avoids waste caused by memory redundancy. This not only saves memory resources, but also reduces the power consumption of DDR memory; and the application transfers key operations such as channel management, state monitoring, interrupt triggering, and information synchronization from software to the dedicated hardware module for execution, and the execution efficiency of hardware logic is much higher than that of software, greatly reducing the uncertainty caused by operating system scheduling delay and software processing overhead, so that the delay of inter-core communication is significantly reduced, the throughput is effectively improved, and the high real-time communication demand is met. And greatly reduce the software burden of the processor core.

[0086] In addition, the embodiment of the application sets a communication state flag bit for the processor core, and determines whether to initiate communication by querying the communication state flag bit of the second processor core, which can save the complex software handshake process in the prior art. The simple communication state flag bit query mechanism greatly reduces the risk of logical problems such as communication channel deadlock and data error caused by handshake failure, timeout or race conditions, making the inter-core communication of multiple cores more stable and reliable.

[0087] To sum up, the application successfully solves the resource waste problem caused by fixed memory allocation in the traditional software solution, and the performance, delay and reliability problems caused by software management, and further provides an inter-core communication method with high performance, low power consumption and high reliability.

[0088] In Figure 1 On the basis of the embodiment shown, as an implementation manner of the embodiment of the application, the method can further include the following steps:

[0089] The hardware management module maintains the write pointer, the read pointer and the work pointer corresponding to the data sending channel;

[0090] The write pointer is used to indicate the position of the latest added data head node in the first data linked list; the read pointer is used to indicate the position of the latest read data head node in the second data linked list; and the work pointer is used to indicate the position of the memory block that has been released.

[0091] Specifically, the present implementation introduces a pointer system maintained by the hardware management module to realize accurate and efficient management of the communication channel state. The system maintains three core pointers for each data sending channel, namely, a write pointer, a read pointer, and a work pointer.

[0092] The write pointer is updated by the hardware management module when the first processor core is operating. It always points to the position of the latest added data head node in the first data linked list, and the advancement of the write pointer indicates that a new data packet is ready to be sent.

[0093] The read pointer is updated by the hardware management module when the second processor core is operating. It always points to the position of the latest successfully read data head node in the second data linked list. The advancement of the read pointer indicates that a data packet has been successfully read.

[0094] The work pointer is used for memory resource recycling management, and it indicates the position of all memory blocks that have been read and can be safely released. The memory in front of the work pointer is being used, and the memory behind the work pointer has been released and can be reused.

[0095] Through the three pointers, the hardware management module can accurately control the state of the data flow and the memory life cycle without the need for software to frequently query and modify complex linked list structures. This is the basis for subsequent automatic interrupt triggering and resource management.

[0096] On the basis of the above embodiment, as an implementation manner of the embodiment of the present application, as shown in the method can further include the following steps: Figure 2

[0097] S210, after the first processor core adds the data head node to the first data linked list, the hardware management module updates the write pointer.

[0098] S220, the second processor core reads data from the shared memory.

[0099] S230, the hardware management module updates the read pointer in response to the data reading operation.

[0100] S240, the hardware management module sends an interrupt signal to the first processor core when detecting that the read pointer changes relative to the work pointer.

[0101] S250, the first processor core releases the memory block occupied by the read data indicated by the read pointer and updates the work pointer in response to the interrupt signal.​

[0102] In this implementation, when the first processor core adds a new data head node to the first data linked list, the hardware management module updates the write pointer to record the change. After the second processor core wakes up from the interruption, it reads data from the shared memory. Once the reading operation is completed, the hardware management module updates the read pointer to indicate that the data has been successfully read. Moreover, the hardware management module continuously compares the read pointer and the work pointer. When it is detected that the read pointer has led the work pointer, that is, the read pointer has changed relative to the work pointer, it means that a new data packet has been read and the memory that has been read can be recycled. At this time, the hardware management module automatically sends an interruption signal to the first processor core.

[0103] The first processor core responds to the interruption signal and performs a memory release operation to release the memory blocks occupied by the read data indicated by the read pointer, and then updates the work pointer to indicate that the memory blocks have been released and can be used for subsequent dynamic application.

[0104] In this implementation, the time-consuming operation of memory release is separated from the real-time data path and is made asynchronous and interruption-driven. The first processor core does not need to actively poll or wait for the release confirmation of the receiver, but performs the memory release operation on demand under the notification of the hardware management module, which greatly reduces the CPU occupation and guarantees the efficiency of data transmission.

[0105] In the above embodiment, the specific process of sending data by the first processor core to the second processor core is introduced. In the following embodiment, the specific process of sending data by the second data processor core to the first processor core is introduced. At this time, the second data processor core is the data sender and the first processor core is the data receiver.

[0106] As shown in FIG. 10, the specific process of sending data by the second data processor core to the first processor core provided by the embodiment of the application can include the following processes: Figure 3

[0107] S310, when the second processor core needs to send data to the first processor core, the first processor core pre-allocates a plurality of memory blocks of a fixed size in the receiving channel and generates a corresponding data head node for each memory block to form a third data linked list.

[0108] Wherein, the sending channel and the receiving channel are different channels.

[0109] S320, the first processor core notifies the hardware management module to update the work pointer through the configuration register. The work pointer is used to indicate the position of the memory block that has been pre-allocated and can be used by the second processor core.

[0110] ​S330, when the hardware management module monitors that the second processor core sends data to the first processor core, an interrupt signal is sent to the first processor core.

[0111] S340, the first processor core determines the data head node which has been written data by the second processor core from the third data chain table.

[0112] S350, according to the memory block address in the data head node which has been written data by the second processor core, data is read from the corresponding memory block.

[0113] Specifically, the inter-core communication provided by the embodiment of the application is bidirectional. When the second processor core (such as a CP) acts as a sender and sends data to the first processor core (such as an AP), the method is also based on hardware management, but the initialization step is different, and specifically as follows:

[0114] 1. The first processor core side pre-allocates resources. As a receiver, the first processor core needs to pre-allocate a plurality of memory blocks of a fixed size in a specific receiving channel, and generate a data head node for each memory block to form a receiving data chain table (for the sake of clear description of the scheme, it can be called a third data chain table). The receiving data chain table is essentially an idle buffer pool.

[0115] 2. Initialize the work pointer. The first processor core updates the work pointer by configuring the internal register of the hardware management module, and notifies the hardware management module to update the work pointer. The work pointer is used to indicate the position of the idle memory block prepared by the receiver (the first processor core) for the sender (the second processor core) at this time.

[0116] 3. Hardware notification and data reading. When the second processor core writes data into the pre-allocated memory blocks, the hardware management module monitors the change (such as the write pointer update) and sends an interrupt to the first processor core. The first processor core further determines which data head node corresponding to the data has been written from the local third data chain table (receiving data chain table), and reads the data according to the memory address.

[0117] In summary, the present implementation mode sets forth the application of the technical scheme of the application in the reverse communication scenario. Its core idea is also that the receiver provides data, the sender reads data, and the hardware management coordinates notification, thereby proving the generality and symmetry of the technical scheme of the application.

[0118] In Figure 3 On the basis of the embodiment shown in the figure, as an implementation mode of the embodiment of the application, the method can further include the following steps:

[0119] The first processor core releases the memory block which has been read data, and updates the read pointer to obtain the latest data head node position which has been read.

[0120] reapply one or more fixed-size memory blocks and supplement the data head node corresponding to the re-applied memory blocks into the third data linked list for subsequent use by the second processor core when sending data to the first processor core.

[0121] Specifically, in the reverse communication (i.e., the second processor core sends data to the first processor core), the first processor core needs to maintain the capacity of the idle buffer pool after reading data. Therefore, the first processor core releases the memory block occupied by the data immediately after reading the data and updates its internal read pointer. Subsequently, it re-applies one or more fixed-size memory blocks and supplements the newly generated data head node to the tail of the third data linked list. This process forms a "read-release-supplement" closed loop, ensuring that the first processor core always has sufficient buffer resources for the second processor core to use, thereby maintaining the ability of continuous high throughput communication.

[0122] Through the present implementation, the dynamic cyclic use of the receiving buffer is achieved, avoiding communication interruption due to resource depletion, while maintaining the flexibility and low overhead advantages brought by the "fixed size, dynamic quantity" memory allocation strategy.

[0123] Based on the embodiment shown in Figure 3 As an implementation manner of the embodiment of the present application, the method can further include the following steps:

[0124] Before the second processor core sends data to the first processor core, the communication status flag bit of the first processor core is queried.

[0125] If the first processor core is in an incommunicable state, the data head node is prohibited from being obtained from the fourth data linked list maintained by the second processor core.

[0126] If it is in a communicable state, an idle data head node is obtained from the fourth data linked list, the data to be sent is written into the memory block corresponding to the node, and the write pointer is updated.

[0127] Specifically, in the reverse communication, the sender (the second processor core) also queries the communication status flag bit of the first processor core before sending data, which is a prerequisite for whether the communication can be initiated. If the receiver is in an incommunicable state, any operation of obtaining a buffer is prohibited to prevent unpredictable errors when the first processor core is not ready. If it is communicable, an idle data head node is obtained from the fourth data linked list, data is written into the corresponding memory block, and the write pointer is updated to notify the hardware management module that new data is ready.

[0128] The present implementation mode embodies the robustness of the technical scheme of the present application. It is efficient and can also guarantee stability. Through the simple mechanism of the state flag bit, invalid operations in the error state are effectively prevented, and the reliability of the system is ensured.

[0129] At this time, the hardware management module monitors that the second processor core sends data to the first processor core, and sends an interrupt signal to the first processor core, which can include the following steps:

[0130] When the hardware management module detects the update of the write pointer, it sends an interrupt signal to the first processor core to notify it to read data.

[0131] Specifically, in the reverse communication, the specific technical implementation of the hardware management module monitoring the sending of data by the sender is to detect the update of the write pointer. When the second processor core writes data and updates the write pointer, the hardware management module will immediately capture this change and send an interrupt signal to the first processor core, notifying it that there is data to read.

[0132] As can be seen, the hardware management module perceives the communication event by monitoring the change of the pointer, and responds accordingly, which embodies the core role of hardware automation.

[0133] On the basis of the above-mentioned embodiments, as an implementation mode of the present application, when the hardware management module detects that the write pointer is consistent with the work pointer, it sends an interrupt signal to the first processor core to instruct the first processor core to supplement the free data head node and memory block for the third data linked list.

[0134] Specifically, the present implementation mode provides a flow control and resource warning mechanism in reverse communication. When the sender (the second processor core) sends data too fast and exhausts all pre-allocated free buffers (i.e. the write pointer catches up with the work pointer), the hardware management module will immediately detect this state.

[0135] And send another type of interrupt signal to the first processor core (the receiver), which is not to notify that there is data to read, but to urgently require the first processor core to supplement the buffer.

[0136] As can be seen, the present implementation mode provides a hardware-assisted flow control mechanism. It can effectively prevent communication bottlenecks or data loss caused by the receiver's processing not being timely, and ensures that the communication process can still proceed smoothly and reliably under high load.

[0137] In order to clearly describe the scheme, the present application will be described in detail below in combination with a system architecture diagram provided by an embodiment of the present application, as shown in Figure 4 .

[0138] AsFigure 4 As shown in the figure, the embodiment of the present application can be applied to a typical mobile terminal system on chip (SOC) which comprises an application processor (AP in the above embodiment) as a host processor (Host MCU) and a plurality of coprocessors (Slave CP0...Slave CPN) as slave processors, wherein the coprocessors can be CPs, audio processors, etc. in the above embodiment. The processor cores access the shared memory through a system bus and communicate through a dedicated hardware management module.

[0139] First, communication initialization is performed. After the system is powered on, each processor core (Host MCU, Slave CP0,...Slave CPN) independently completes its own initialization, and when communication is allowed, sets its corresponding SIPC_ready_flag_CPU_XX (communication status flag bit in the above embodiment) to an active state, indicating that it is ready for inter-core communication.

[0140] Next, taking the sending of data from Host MCU to Slave CP0 as an example, the data sending process is described in detail.

[0141] 1. Dynamic memory application. A business module on Host MCU needs to send data to Slave CP0. After confirming that Slave CP0 is communicable by querying the communication status flag bit (SIPC_ready_flag_CPU_CP0) of Slave CP0, it initiates a request to the shared memory manager to dynamically apply for a memory block (Databuf1 in the figure) of a size matching the data to be sent.

[0142] 2. Construction of data packet and linked list. Host MCU writes the data to be sent into the applied Data buf1 and generates a corresponding data head node (DataHead1) containing information such as channel number, address of Data buf1, data size, etc. Host MCU adds this DataHead1 node to the sending DataList linked list it maintains.

[0143] 3. Hardware management and notification. The hardware management module continuously monitors the DataList of each channel. When it detects that the DataList of the channel to Slave CP0 has a new node added (i.e. DataHead1) and SIPC_ready_flag_CPU_CP0 is in an active state, it immediately performs two operations:

[0144] (1) Interrupt management. Automatically sends an interrupt signal to Slave CP0 to notify it of the arrival of data.

[0145] (2) Information synchronization. Synchronize the key information (memory address, size, etc.) in the DataHead1 node to the receiving DataList maintained by the SlaveCP0.

[0146] Meanwhile, the hardware management module updates the write pointer corresponding to the channel, indicating the position of the latest data node.

[0147] 4) Reading data from the processor. After receiving the interrupt, the SlaveCP0 obtains the head node information from its local receiving DataList, and directly reads data from the specified position (Data buf1) in the shared memory according to the address pointer in the node. After the data is read, the internal mechanism of the SlaveCP0 triggers the hardware management module to update the read pointer of the channel.

[0148] 5) Memory recycling. The control logic in the hardware management module continuously compares the read pointer and the work pointer. When it is detected that the read pointer has advanced (indicating that the data has been read), but the work pointer has not caught up, the hardware management module sends another interrupt to the HostMCU. The HostMCU responds to this interrupt, releases the memory occupied by the Data buf1, and updates the work pointer, completing the recycling and reuse of memory resources.

[0149] On the basis of the above process, the processor SlaveCPN can also send data to the HostMCU through the above similar process, just by reversing the roles, and the process has been described in detail in the above embodiment, which will not be repeated here.

[0150] And, from Figure 4 It can be seen that the hardware management module independently maintains a set of read pointer, write pointer, work pointer and DataList address for each communication channel (channel 1 to channel N), so as to manage multiple independent inter-core data streams in parallel without interfering with each other.

[0151] The embodiment realizes centralized and automated management of the shared memory and the communication channel through the hardware management module, separates the processor core from the heavy communication management overhead, and through the dynamic memory allocation and release mechanism, greatly improves the memory utilization efficiency and reduces the system power consumption, finally realizes efficient, reliable and flexible inter-core communication.

[0152] The embodiment of the application also provides an inter-core communication system based on hardware management, integrated in a system on chip, comprising: a first processor core, a second processor core, a hardware management module and a shared memory.

[0153] The first processor core and the second processor core are respectively configured with independent communication state flag bits for indicating their own communicable state.

[0154] The first processor core is configured to, when data needs to be sent to the second processor core, query the communication state flag bit of the second processor core; if the second processor core is in a communicable state, dynamically apply a memory block from the shared memory; write the data to be sent into the memory block, and generate a data header node containing a data sending channel identifier, a memory block address, a memory block size and a next node pointer; and add the data header node to a first data linked list maintained by the first processor core; the size of the memory block is determined based on the size of the current data to be sent;

[0155] The hardware management module is configured to monitor the first data linked list, and when it is monitored that the data header node is increased and the second processor core is communicable, automatically send an interrupt signal to the second processor core; and in response to the update of the first data linked list, synchronize the information contained in the newly added data header node to a second data linked list maintained by the second processor core;

[0156] The second processor core is configured to, in response to the interrupt signal, obtain a target data header node to be processed currently from the second data linked list, and read the data in the shared memory according to the information contained in the target data header node.

[0157] The embodiment of the present application also provides an electronic device comprising the inter-core communication system based on hardware management.

[0158] The electronic device is a mobile phone, a tablet computer, a base station, a router or an Internet of Things terminal device.

[0159] Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments without departing from the principles and purposes of the present application within the scope of the present application.

Claims

1. A hardware-managed inter-core communication method, characterized in that, The method is applied to a system-on-a-chip comprising a first processor core, a second processor core, and a hardware management module, wherein the first processor core and the second processor core are each provided with independent communication status flags to indicate their communicable states; the method includes: When the first processor core needs to send data to the second processor core, it queries the communication status flag bit of the second processor core; If the second processor core is in a communicable state, the first processor core dynamically requests a memory block from the shared memory, and the size of the memory block is determined based on the size of the data to be sent. The first processor core writes the data to be sent into a memory block and generates a data header node containing a data transmission channel identifier, a memory block address, a memory block size, and a pointer to the next node. The first processor core adds the data header node to the first data linked list maintained by the first processor core; The hardware management module monitors the first data linked list and automatically sends an interrupt signal to the second processor core when it detects an addition of a data header node and that the second processor core is communicable. In response to an update to the first data linked list, it synchronizes the information contained in the newly added data header node to the second data linked list maintained by the second processor core. The hardware management module maintains write pointers, read pointers, and working pointers corresponding to the data transmission channel. The write pointer indicates the position of the latest added data header node in the first data linked list; the read pointer indicates the position of the latest read data header node in the second data linked list; and the working pointer indicates the position of a memory block that has been released. The second processor core responds to the interrupt signal, obtains the target data header node to be processed from the second data linked list, and reads the data in the shared memory based on the information contained in the target data header node; When the second processor core needs to send data to the first processor core, the first processor core pre-allocates multiple fixed-size memory blocks in the receiving channel and generates a corresponding data header node for each memory block to form a third data linked list; wherein, the sending channel and the receiving channel are different channels; The first processor core notifies the hardware management module to update the working pointer through a configuration register. The working pointer is used to indicate the location of a memory block that has been pre-allocated and can be used by the second processor core. When the hardware management module detects that the second processor core is sending data to the first processor core, it sends an interrupt signal to the first processor core. The first processor core determines the data header node from the third data linked list that has been written with data by the second processor core; Data is read from the corresponding memory block based on the memory block address in the data header node that has been written to the data by the second processor core.

2. The method according to claim 1, characterized in that, The method further includes: After the first processor core adds the data header node to the first data linked list, the hardware management module updates the write pointer; The second processor core reads data from shared memory; The hardware management module updates the read pointer in response to the data read operation; When the hardware management module detects a change in the read pointer relative to the working pointer, it sends an interrupt signal to the first processor core. In response to an interrupt signal, the first processor core releases the memory block occupied by the read data indicated by the read pointer and updates the working pointer.

3. The method according to claim 1, characterized in that, The method further includes: The first processor core releases the memory block containing the read data and updates the read pointer to obtain the position of the latest read data header node; One or more memory blocks of the fixed size are re-allocated, and the data header node corresponding to the re-allocated memory block is added to the third data list for use by the second processor core when sending data to the first processor core.

4. The method according to claim 1, characterized in that, The method further includes: Before the second processor core sends data to the first processor core, the communication status flag of the first processor core is queried; If the first processor core is in a non-communicable state, then obtaining the data header node from the fourth data linked list maintained by the second processor core is prohibited; If the communication is enabled, a free data header node is obtained from the fourth data linked list, the data to be sent is written to the memory block corresponding to that node, and the write pointer is updated.

5. The method according to claim 4, characterized in that, When the hardware management module detects that the second processor core is sending data to the first processor core, it sends an interrupt signal to the first processor core, including: When the hardware management module detects a write pointer update, it sends an interrupt signal to the first processor core to notify it to read the data.

6. The method according to claim 1, characterized in that, When the hardware management module detects that the write pointer and the working pointer are consistent, it sends an interrupt signal to the first processor core to instruct the first processor core to supplement the third data linked list with free data header nodes and memory blocks.

7. A hardware-managed inter-core communication system, characterized in that, Integrated into the system-on-a-chip, it includes: a first processor core, a second processor core, a hardware management module, and shared memory; The first processor core and the second processor core are each configured with an independent communication status flag bit to indicate their own communicable status; The first processor core is configured to, when it needs to send data to the second processor core, query the communication status flag of the second processor core; if the second processor core is in a communicable state, dynamically allocate a memory block from shared memory; write the data to be sent into the memory block, and generate a data header node containing a data transmission channel identifier, memory block address, memory block size, and next node pointer; and add the data header node to the first data linked list maintained by the first processor core; the size of the memory block is determined based on the size of the current data to be sent. The hardware management module is configured to monitor a first data linked list and automatically send an interrupt signal to the second processor core when it detects an addition of a data header node and that the second processor core is communicable. In response to an update to the first data linked list, it synchronizes the information contained in the newly added data header node to the second data linked list maintained by the second processor core. The hardware management module is also configured to maintain write pointers, read pointers, and working pointers corresponding to the data transmission channel. The write pointer indicates the position of the latest added data header node in the first data linked list; the read pointer indicates the position of the latest read data header node in the second data linked list; and the working pointer indicates the position of a memory block that has been released. The second processor core is configured to, in response to an interrupt signal, obtain the target data header node to be processed from the second data linked list, and read the data in the shared memory based on the information contained in the target data header node; When the second processor core needs to send data to the first processor core, the first processor core is also configured to pre-allocate multiple fixed-size memory blocks in the receiving channel, and generate a corresponding data header node for each memory block to form a third data linked list; wherein, the sending channel and the receiving channel are different channels; The first processor core is also configured to notify the hardware management module to update the working pointer via a configuration register. The working pointer is used to indicate the location of a memory block that has been pre-allocated and can be used by the second processor core. The hardware management module is also configured to send an interrupt signal to the first processor core when it detects that the second processor core is sending data to the first processor core. The first processor core is also configured to determine the data header node from the third data list that has been written with data by the second processor core; and to read data from the corresponding memory block according to the memory block address in the data header node that has been written with data by the second processor core.

8. An electronic device, characterized in that, Including the hardware-managed inter-core communication system as described in claim 7; The electronic device is a mobile phone, tablet computer, base station, router, or Internet of Things (IoT) terminal device.

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