Data storage device with joint error correction code engine

Abstract

Examples described herein provide a joint LDPC and XOR (JLX) error correction scheme that utilizes parity check of the LDPC code to correct errors in XOR stripes of data, allowing for improved protection against errors. For example, when decoding of a codeword fails, XOR operations are performed on other codewords within the same XOR slice to generate a copy of the failed codeword. The copy of the failed codeword is used as a soft bit input to the LDPC decoder, providing information of possible locations of errors in the failed codeword. The LDPC decoder may then recover the failed codeword. Scrambling seeds used to encode pages of data may also be used to recover from errors in JLX ECC operations.

Description

Technical Field

[0001] The present application relates generally to data storage devices and, more particularly, to a data storage device having a joint low density parity check and XOR engine. Summary of the Invention

[0002] Solid-state device (SSD) architectures can support an error correction code (ECC) engine that performs scrambling, encoding, and decoding operations for device read and write operations. The ECC engine can include a low-density parity check (LDPC) engine for correcting random errors that occur during reading and writing data to the memory. Additionally, the SSD storage controller can include an exclusive-OR (XOR) engine for correcting data errors caused by memory defects, such as damaged word lines or pages.

[0003] Traditionally, LDPC and XOR operations are separate operations performed based on the type of errors experienced by reading (e.g., decoding) data. However, when multiple pages of data experience errors, a large amount of processing power is required to successfully decode these pages. The embodiments described herein provide a joint LDPC and XOR (also referred to herein as "JLX") error correction scheme that utilizes the parity of LDPC codes to correct errors in the XOR stripes of data, thereby allowing for improved protection against errors. For example, when decoding of more than one codeword within an XOR stripe fails, XOR operations are performed on other codewords within the same XOR stripe to generate a copy of the failed codeword. This copy of the failed codeword is used as a soft bit input to the LDPC decoder, providing information about the possible locations of errors in the failed codeword. The LDPC decoder can then recover the failed codeword.

[0004] In some embodiments, scrambling is used in data storage devices to avoid data-dependent interference effects (such as backpropagation and program interference) that can be caused by having repeating data patterns, and to avoid having correlated data between adjacent physical storage devices. The scrambling seed used to encode the data page can also be used to recover from errors in JLX ECC operations.

[0005] The present disclosure provides a data storage controller, the data storage controller including a memory for storing a plurality of codewords and a data storage device controller coupled to the memory, the data storage device controller including a processor and a controller memory. The controller memory stores a set of instructions that, when executed by the processor, instruct the controller to detect at least two undecoded failed codewords during decoding of the plurality of codewords, perform a joint low-density parity check and exclusive-or (JLX) operation using scrambling seeds associated with the at least two failed codewords, and recover at least one of the two failed codewords from the JLX operation.

[0006] The present disclosure also provides a method, comprising: detecting, during decoding of a plurality of codewords and by a memory controller executing decoding firmware, at least two failed codewords that failed to be decoded; performing, by the memory controller, a joint low-density parity check and exclusive-or (JLX) operation using a scrambling seed associated with the at least two failed codewords; and recovering, by the memory controller, at least one of the two failed codewords from the JLX operation.

[0007] The present disclosure also provides a memory device. The memory device includes: a memory for storing a plurality of codewords; and a controller coupled to the memory, the controller configured to perform a joint low-density parity check and exclusive-or (JLX) operation using a scrambling seed associated with a failed codeword in the plurality of codewords to recover the failed codeword when at least two codewords in the plurality of codewords fail during decoding.

[0008] Various aspects of the present disclosure provide improvements to data storage devices. The present disclosure may be embodied in various forms, including hardware or circuitry controlled by software, firmware, or a combination thereof. The foregoing summary is intended only to provide a general overview of the various aspects of the present disclosure and is not intended to limit the scope of the present disclosure in any way. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of a system including a data storage device and a host device according to some embodiments of the present disclosure.

[0010] Figures 2 to 3 An example is shown for correcting errors within multiple pages of data using an XOR operation, according to some embodiments of the present disclosure.

[0011] Figure 4 An example process for correcting errors in a page using an example JLX ECC scheme is shown, according to some embodiments of the present disclosure.

[0012] Figure 5 is a flow chart of an example method for storing a page of data in a buffer according to some embodiments of the present disclosure.

[0013] Figure 6 According to some embodiments of the present disclosure Figure 5 Example procedure of the method.

[0014] Figure 7 is a flow chart of an example method for correcting error pages according to some embodiments of the present disclosure.

[0015] Figure 8 According to some embodiments of the present disclosure Figure 7 Example procedure of the method.

[0016] Figure 9 According to some embodiments of the present disclosure, Figure 5 and Figure 7 Example pseudocode for the method.

[0017] Figure 10 is an example mathematical proof of the JLX ECC scheme according to some embodiments of the present disclosure.

[0018] Figure 11 is a flow chart of another example method for storing a page of data in a buffer according to some embodiments of the present disclosure.

[0019] Figure 12 is a flow chart of another example method for correcting error pages according to some embodiments of the present disclosure.

[0020] Figure 13 According to some embodiments of the present disclosure, Figure 11 and Figure 12 Example pseudocode for the method.

[0021] FIG. 14A to FIG. 14B is another example mathematical proof of the JLX ECC scheme according to some embodiments of the present disclosure.

[0022] Figure 15 is a graph illustrating the probability of decoding failure at a given bit error rate for a given number of failed adjacent codewords according to some embodiments of the present disclosure.

[0023] Figure 16 is a graph illustrating correctable log BER distribution according to some embodiments of the present disclosure.

[0024] Figure 17 is a graph illustrating example bit error rate distributions according to some embodiments of the present disclosure.

[0025] Figure 18 is a graph illustrating examples of hard bits and soft bits according to some embodiments of the present disclosure.

[0026] Figure 19 is a graph illustrating an example LN bit error rate distribution according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] In the following description, many details are set forth, such as data storage device configuration, controller operation, etc., in order to provide an understanding of one or more aspects of the present disclosure. It will be apparent to those skilled in the art that these specific details are merely exemplary and are not intended to limit the scope of the present application. Specifically, the functions associated with the data storage controller may be performed by hardware (e.g., analog or digital circuitry), a combination of hardware and software (e.g., program code or firmware stored in a non-transitory computer-readable medium executed by a processor or control circuit), or any other suitable component. The following description is intended only to give a general idea of ​​the various aspects of the present disclosure and does not limit the scope of the present disclosure in any way. In addition, it will be apparent to those skilled in the art that although the present disclosure relates to NAND flash memory, the concepts discussed herein are applicable to other types of solid-state memories, such as NOR, PCM ("phase change memory"), ReRAM, MRAM, etc.

[0028] Data storage devices

[0029] Figure 1 is a block diagram of a system including a data storage device and a host device according to some embodiments of the present disclosure. Figure 1 In the example of FIG, system 100 includes a data storage device 102 and a host device 150. The data storage device 102 includes a controller 120 (hereinafter referred to as “data storage device controller”) and a memory 104 (eg, non-volatile memory) coupled to the data storage device controller 120.

[0030] Figure 1 An example of the structural and functional features provided by the data storage device controller 120 is shown in simplified form in FIG. The data storage device controller 120 may also include Figure 1 In addition, although the data storage device 102 is Figure 1 102, but in other implementations, the data storage device controller 120 is instead located separately from the data storage device 102. Thus, operations generally performed by the data storage device controller 120 described herein may be performed by another device connected to the data storage device 102.

[0031] The data storage device 102 and the host device 150 can be operatively coupled via a connection (e.g., communication path 110) such as a bus or a wireless connection. In some examples, the data storage device 102 can be embedded within the host device 150. Alternatively, in other examples, the data storage device 102 can be removed from the host device 150 (i.e., "removably" coupled to the host device 150). For example, the data storage device 102 can be removably coupled to the host device 150 according to a removable universal serial bus (USB) configuration. In some specific implementations, the data storage device 102 can include or correspond to a solid-state drive (SSD), which can be used as an embedded storage drive (e.g., a mobile embedded storage drive), an enterprise storage drive (ESD), a client storage device or cloud storage drive, or other suitable storage drive.

[0032] The data storage device 102 can be configured to be coupled to a host device 150 via a communication path 110 (such as a wired communication path and / or a wireless communication path). For example, the data storage device 102 can include an interface 108 (e.g., a host interface) that enables communication via the communication path 110 between the data storage device 102 and the host device 150, such as when the interface 108 is communicatively coupled to the host device 150.

[0033] Host device 150 may include an electronic processor and a memory. The memory may be configured to store data and / or instructions that can be executed by the electronic processor. The memory may be a single memory, or may include one or more memories, such as one or more non-volatile memories, one or more volatile memories, or a combination thereof. Host device 150 may issue one or more commands to data storage device 102, such as one or more requests to erase data at memory 104 of data storage device 102, read data from the memory, or write data to the memory. For example, host device 150 may be configured to provide data (such as user data 132) to be stored at memory 104 or request to read data from memory 104 via request 134. Host device 150 may include a mobile smart phone, a music player, a video player, a game console, an e-book reader, a personal digital assistant (PDA), a computer (e.g., a laptop or notebook computer), any combination thereof, or other suitable electronic devices.

[0034] In some examples, host device 150 may operate in accordance with other specifications, such as the Universal Flash Storage (UFS) host controller interface specification, the Universal Serial Bus specification, or other suitable industry specifications. Host device 150 may also communicate with memory 104 according to any other suitable communication protocol.

[0035] The memory 104 of the data storage device 102 may include non-volatile memory (e.g., NAND, 3D NAND family memory, or other suitable memory). In some examples, the memory 104 may be any type of flash memory. For example, the memory 104 may be two-dimensional (2D) memory or three-dimensional (3D) flash memory. The memory 104 may include one or more memory dies 103. Each of the one or more memory dies 103 may include one or more blocks (e.g., one or more erase blocks). Each block may include one or more groups of storage elements, such as a group of representative storage elements 107A-107N. The group of storage elements 107A-107N may be configured as a codeword, a wordline, or a data page. The group of storage elements 107 may include multiple storage elements, such as representative storage elements 109A and 109N, respectively. Each representative storage element 109 may include, for example, one data bit. Portions of the group of storage elements 107 may be grouped with portions of one or more other codewords to form a stripe codeword 111. For example, stripe codeword 111 may be a vertical bit line of representative storage element 109 .

[0036] Memory 104 may include support circuits such as read / write circuits 140, LDPC circuits 141, and XOR circuits 142 to support the operation of one or more memory dies 103. Although depicted as a single component, read / write circuits 140 may be separated into separate components of memory 104, such as read circuits and write circuits. Read / write circuits 140 may be external to one or more memory dies 103 of memory 104. Alternatively, one or more separate memory dies may include corresponding read / write circuits that are operable to read from and / or write to storage elements within the separate memory dies independently of any other read and / or write operations at any other memory die.

[0037] The data storage device 102 includes a data storage device controller 120 coupled to a memory 104 (e.g., one or more memory dies 103) via a bus 106, an interface (e.g., an interface circuit), another structure, or a combination thereof. For example, the bus 106 may include a plurality of different channels to enable the data storage device controller 120 to communicate with each of the one or more memory dies 103 in parallel with and independently of communications with the other memory dies 103. In some implementations, the memory 104 may be a flash memory.

[0038] The data storage device controller 120 is configured to receive data and instructions from the host device 150 and to send data to the host device 150. For example, the data storage device controller 120 may send data to the host device 150 via the interface 108, and the data storage device controller 120 may receive data from the host device 150 via the interface 108. The data storage device controller 120 is configured to send data and commands (e.g., memory operation 136) to the memory 104 and to receive data from the memory 104. For example, the data storage device controller 120 is configured to send data and a write command to cause the memory 104 to store data at a specified address of the memory 104. The write command may specify a physical address of a portion of the memory 104 where the data is to be stored (e.g., a physical address of a word line of the memory 104).

[0039] The data storage device controller 120 is configured to send a read command to the memory 104 to access data at a specified address from the memory 104. The read command may specify a physical address of a region of the memory 104 (e.g., a physical address of a word line of the memory 104). The data storage device controller 120 may also be configured to send data and commands to the memory 104 that are associated with background scan operations, garbage collection operations, and / or wear leveling operations, or other suitable memory operations.

[0040] The data storage device controller 120 may include a memory 124 (e.g., a random access memory ("RAM"), a read-only memory ("ROM"), a non-transitory computer-readable medium, or a combination thereof), an error correction code (ECC) engine 126, and an electronic processor 128 (e.g., a microprocessor, a microcontroller, a field programmable gate array ("FPGA") semiconductor, an application-specific integrated circuit ("ASIC"), or another suitable programmable device). The memory 124 stores data and / or instructions that are executable by the electronic processor 128. For example, the memory 124 stores a first buffer 137, a second buffer 138, and an ECC selection instruction 139 that is executable by the electronic processor 128. In some examples, the first buffer 137, the second buffer 138, and the ECC selection instruction 139 are permanently stored in the memory 124. In other examples, at least the ECC selection instruction 139 is received from the host device 150. The first buffer 137 and the second buffer 138 may store one or more pages during an XOR recovery operation, as described in more detail below.

[0041] In addition, although the data storage device controller 120 Figure 1102, but in other implementations, some or all of the memory 124 is instead located separately from the data storage device controller 120 and may be executed by the electronic processor 128 or a different electronic processor external to the data storage device controller 120 and / or the data storage device 102. For example, the memory 124 may be a dynamic random access memory (DRAM) that is separate and distinct from the data storage device controller 120. Thus, operations that would typically be performed only by the data storage device controller 120 described herein may be performed by: 1) the electronic processor 128 and a different memory internal to the data storage device 102; 2) the electronic processor 128 and a different memory external to the data storage device 102; 3) a different electronic processor external to the data storage device controller 120 and in communication with the memory of the data storage device 102; and 4) a different electronic processor external to the data storage device controller 120 and in communication with the memory external to the data storage device 102.

[0042] The data storage device controller 120 may send a memory operation 136 (e.g., a read command) to the memory 104 to cause the read / write circuit 140 to sense data stored in the storage element. For example, the data storage device controller 120 may send a read command to the memory 104 in response to receiving a read access request from the host device 150.

[0043] The ECC engine 126 is configured to encode and decode data according to an LDPC ECC scheme 127, an XOR ECC scheme 129, and a JLX ECC scheme 131. During decoding of data from the memory 104, the data storage device controller 120 implements the LDPC ECC scheme 127 and the XOR ECC scheme 129 to correct errors within the data. However, if more than one page of data includes errors (as determined by the electronic processor 128 implementing the ECC select instruction 139), the data storage device controller 120 implements the JLX ECC scheme 131, which is described in more detail below. Further details regarding the example XOR ECC scheme 129 and the stripe codeword 111 can be found in U.S. Patent No. 10,536,172, "ECC and Raid-Type Decoding," which is incorporated herein in its entirety.

[0044] Error Correction Solution

[0045] Figure 2 An example 200 for correcting errors within a plurality of data pages 206 is shown. In the example 200, an XOR operation is performed on the plurality of data pages 206 to generate a parity page 208. Each data page 206 is associated with a graph (or codeword) G N1 , and associated with variable nodes (v1, v2, v3, v4, v5, v6) 202, which represent bits stored in each data page 206. Variable nodes 202 are coupled to check nodes 204 labeled C1, C2, C3, and C4, which represent parity bits used in LDPC ECC scheme 127 when detecting and correcting errors in multiple data pages 206. Generating parity page 208 results in XOR variable nodes 210 representing the bits forming parity page 208. XOR check nodes 212 are also generated for LDPC error correction of parity page 208.

[0046] The XOR variable node 210 generated by the XOR operation of multiple data pages 206 may also be referred to as a parity check. Figure 3 In example 300, the graph G is filled based on the codeword information P0304. N , such as the hard bit and soft bit data received from memory 104 when reading a codeword. N The variable node of each of is coupled to a corresponding check node 302 , thereby indicating an XOR check of the XOR ECC scheme 129 .

[0047] While the use of both the LDPC ECC scheme 127 and the XOR ECC scheme 129 provides correction for both random errors and memory errors, the LDPC ECC scheme 127 and the XOR ECC scheme 129 utilize a large amount of processing data, which results in slow correction performance on some devices, especially when there are errors in multiple data pages. Therefore, the embodiments described herein provide a JLX error correction operation (e.g., JLX ECC scheme 131) that effectively combines the LDPC ECC scheme 127 with the XOR ECC scheme 129 for correcting multiple data pages with errors.

[0048] Figure 4 An example process 400 for correcting errors in pages using the example JLX ECC scheme 131 is shown. In the example process 400, a first page 401 (e.g., page 1) includes errors that are to be corrected by the ECC engine 126 after the LDPC ECC scheme 127 fails to decode the first page 401. First, an XOR operation is performed on multiple data pages 206 and parity pages 208 at a node 404 to generate a replica page 406. The multiple data pages 206 and parity pages 208 may be in the same XOR stripe as the first page 401. However, a third page 402 (e.g., page 3) also includes multiple errors. Therefore, the replica page 406 is in the same location as the third page 402 (e.g., Figures 2 to 3 The same variable node 202) includes an error.

[0049] In the example of process 400, first page 401 and third page 402 (and therefore replica page 406) include errors in different locations. Soft bit data can be used to identify where errors may be located in first page 401 and third page 402. Process 400 includes soft bit page 408 associated with the soft bits of first page 401. Specifically, soft bit page 408 includes a plurality of cells 409, which are unreliable cells that are more prone to errors. In this way, the memory cells storing data of first page 401 that are more prone to errors are known.

[0050] First page 401, replica page 406, and soft bit page 408 are provided to LDPC decoder 410, where replica page 406 is provided as a second soft bit input. LDPC decoder 410 can be, for example, LDPC circuit 141 that performs the operations indicated by LDPC ECC scheme 127. LDPC decoder 410 copies the reliable bits from first page 401 and copies the unreliable bits (as indicated by soft bit page 408) from replica page 406 to generate a recreated first page 412. When the unreliable cells are copied from replica page 406, the recreated first page 412 has a lower bit error rate than first page 401 and is corrected by LDPC decoder 410 to generate a corrected first page 414.

[0051] In some embodiments, during encoding of data into memory 104, controller 120 scrambles the data to avoid data-dependent interference effects (such as backpropagation, program interference, NWI, etc.) that may be caused by having repeating data patterns. In addition, controller 120 can scramble the data to avoid having correlated data between adjacent physical storage elements (e.g., adjacent pages, word lines, and strings). Scrambling ensures that the data is randomly and evenly distributed, thereby reducing the probability of repeating and harmful data patterns. In addition, the distribution of scrambler seeds is controlled to ensure that the seeds of adjacent physical storage elements are not repeated or correlated (e.g., the seeds are not repeated within adjacent pages of a memory block).

[0052] In some embodiments, codewords within the same XOR stripe are assigned a scrambling seed that is different from the scrambling seed used for codewords stored in adjacent physical storage elements, and each codeword in the XOR stripe can be scrambled with a different seed. In this way, when one of the codewords within the XOR stripe is decoded, the scrambling seeds for the remaining codewords can be derived. When decoding fails for multiple pages, the JLX ECC scheme 131 can refer to the scrambling seeds used for these pages to recreate the pages with errors, such as Figures 5 to 8 shown.

[0053] To correct codewords that were unsuccessfully decoded using LDPC ECC scheme 127, each of the other codewords in the respective XOR stripes may first be separated into buffers based on whether LDPC ECC scheme 127 successfully decoded those codewords. Figure 5 An example method 500 for storing a page of data in a buffer is shown. When data is stored in the buffer, an XOR operation can be performed between the data and the buffer so that the buffer remains the same size throughout the buffering process.

[0054] Figure 5 A block diagram of an example method 500 for storing a page of data in a buffer based on whether the LDPC ECC scheme 127 is successful is shown. The data storage device controller 120 may perform the method 500 during decoding of data from the memory 104. In the example method 500, the first codeword (e.g., the first page 401) is initially unsuccessfully decoded. The method 500 refers to Figure 6 Described below, the figure visualizes an example 600 of implementing the method 500 .

[0055] Method 500 includes receiving the next codeword in the XOR stripe (at step 502). For example, referring to Figure 6 , a next page of the plurality of data pages 206 is received by the data storage device controller 120 .

[0056] Return to Figure 5 , method 500 includes determining whether the codeword received in the XOR stripe is successfully decoded (at decision step 504). For example, referring to Figure 6 , LDPC decoder 410 decodes the plurality of data pages 206 to retrieve the plurality of recovered data pages 606. The decoding by LDPC decoder 410 may be successful (indicated by "S") or unsuccessful (indicated by "F").

[0057] When the codeword in the XOR stripe is successfully decoded ("yes" at decision step 504), method 500 proceeds to step 506 and includes buffering (eg, storing) the XOR decoded information in a first buffer. Figure 6 In example 600, the decoding of page 2, page 4, and page XOR is successful, resulting in the acquisition of data 2, data 4, and data XOR in multiple recovered data pages 606. Data 2, data 4, and data XOR are buffered by first summing node 610 into first buffer 137. Summing node 610 can perform an XOR operation on the data buffered into first buffer 137.

[0058] When the codeword in the XOR stripe is not successfully decoded ("No" at decision step 504), method 500 proceeds to step 508 and buffers the XOR codeword in a second buffer. Figure 6 In the example 600, the decoding of page 3 has failed, resulting in a fault page 608. The fault page 608 is buffered by the second summing node 618 into the second buffer 138. The summing node 618 may perform an XOR operation on the fault page 608 and the second buffer 138.

[0059] The method 500 includes deriving a scrambling seed associated with a received codeword (at step 510). For example, when decoding a codeword fails, the data storage device controller 120 derives a scrambling seed associated with the failed codeword using a deterministic function based on the successfully corrected codeword. Figure 6 In example 600 , the data storage device controller 120 determines the scrambling seed 614 associated with the faulty page 608 (eg, seed 3 associated with page 3 ).

[0060] Method 500 includes encoding the all-zero payload with the derived seed at step 512. For example, as shown in example 600, LDPC encoder 616 encodes scrambling seed 614 with zero codeword 612 to produce an encoded payload.

[0061] The method 500 includes buffering the encoded payload into the second buffer at step 514. For example, the encoded payload including the scrambling seed 614 associated with the error page 608 is buffered into the second buffer 138 by the second summing node 618. The summing node 618 may perform an XOR operation on the encoded payload from the LDPC encoder 616 and the second buffer 138.

[0062] Once the decoded information is stored in the first buffer 137 (at step 506), or once the encoded payload is stored in the second buffer 138 (at step 514), the method 500 returns to step 502 and receives the next codeword in the XOR stripe. The method 500 continues until each codeword is stored in the first buffer 137 or the second buffer 138. Once each codeword is stored in the first buffer 137 or the second buffer 138, the data storage device controller 120 may proceed to step 514. Figure 7 Method 700.

[0063] Figure 7 A block diagram of a method 700 for correcting an error page is shown. The data storage device controller 120 may perform the method 500 during decoding of data from the memory 104. The method 700 may be performed by the data storage device controller 120 immediately after the method 500. The method 700 refers to Figure 8 Described below, the figure visualizes an example 800 of implementing the method 700 .

[0064] The method 700 includes receiving a fail codeword at step 702 . For example, the data storage device controller 120 receives the first page 401 .

[0065] The method 700 includes deriving a scrambling seed associated with the failed codeword (at step 704). For example, the data storage device controller 120 derives the scrambling seed associated with the failed codeword using a deterministic function based on the successfully corrected codeword. Figure 8 In example 800 , the data storage device controller 120 determines a scrambling seed 802 associated with the first page 401 (eg, Seed 1 associated with Page 1 ).

[0066] The method 700 includes encoding the first buffer 137 using the derived scrambling seed associated with the failed codeword (at step 706). Figure 8 As shown in example 800 of method 500, LDPC encoder 616 encodes a scrambling seed 802 along with the contents of first buffer 137. In this manner, the scrambling seed 802 associated with first page 401 is encoded with the data of the successfully decoded codeword (at step 504 of method 500).

[0067] The method 700 includes performing an XOR operation between the encoded codeword from step 706 and the second buffer 138, thereby generating a copy page (at step 708). Figure 8 As shown in example 800 , an XOR operation between the encoded codeword from the LDPC code 616 and the second buffer 138 generates a copy page 406 of the first page 401 .

[0068] Method 700 includes decoding a failed codeword using a duplicate page (at step 710). For example, as previously described with respect to Figure 4 As depicted, LDPC decoder 410 receives first page 401 , soft bit page 408 , and replica page 406 as input and generates a corrected first page 414 .

[0069] Figure 9 Pseudo code is shown that provides an example of implementing method 500 and method 700. Methods 500, 700 may be repeated for each failed codeword during decoding of data from memory 104. Once a failed codeword is successfully recovered, a reconstruction of the recovered codeword may be used as input for recovering additional failed codewords. Figure 10 Provided Figures 5 to 8 An example mathematical proof of the correctness of the JLXECC scheme 131.

[0070] exist Figures 5 to 8In the example, codewords within the same XOR stripe are assigned a scrambling seed that is different from the scrambling seed used for adjacent physical storage elements. The scrambling seeds can be related to each other through a function. However, in other examples, the XOR stripe spans multiple non-adjacent dies and is therefore not adversely affected by pattern dependencies. Therefore, the same scrambling seed can be used for each codeword in the XOR stripe. Figures 11 to 12 Methods are provided for recovering failed codewords when each codeword is scrambled using the same scrambling seed. In the examples described herein, a cyclic redundancy check (CRC) may be implemented to verify that the decoded information is identical to the encoded information. Figures 11 to 12 In the example of , the CRC can be designed so that all-zero information does not result in an all-zero codeword.

[0071] first, Figure 11 A block diagram is shown of an example method 1100 for storing a page of data in a buffer based on whether the LDPC ECC scheme 127 was successful. The data storage device controller 120 may perform the method 1100 during decoding of data from the memory 104. In the example method 1100, a first codeword (e.g., the first page 401) is initially unsuccessfully decoded.

[0072] The method 1100 includes receiving the next codeword in the XOR stripe (at step 1102). The method 1100 includes determining whether the received codeword in the XOR stripe was successfully decoded (at decision step 504).

[0073] When the codeword in the XOR stripe is successfully decoded ("yes" at decision step 1104), method 1100 proceeds to step 1106 and includes buffering (e.g., storing) the decoded information in a first buffer. For example, the data storage device controller 120 performs an XOR operation between the decoded information and the first buffer. When the codeword in the XOR stripe is not successfully decoded ("no" at decision step 1104), method 1100 proceeds to step 1108 and buffers the failed codeword in a second buffer. For example, the data storage device controller 120 performs an XOR operation between the decoded information and the second buffer.

[0074] Once the decoded information is stored in the first buffer (at step 1106), or once the codeword is stored in the second buffer (at step 1108), method 1100 returns to step 1102 and receives the next codeword in the XOR stripe. Method 500 continues until each codeword is stored in the first buffer or the second buffer. When a codeword fails to decode, its seed is derived using a deterministic function based on the successfully corrected codeword. This derived seed is used to encode a zero codeword and also buffer it to the second buffer, thereby "canceling" the CRC.

[0075] Figure 12 A block diagram of an example method 1200 for correcting an error page is shown. Once the number of failed codewords within an XOR stripe is established, the method 1200 can be executed by the data storage device controller 120, as determined based on the size of the first buffer and the second buffer in the method 1100. A determination is performed based on whether the number of failed codewords is even or odd. This determination is associated with a CRC design that stipulates that "all zero" information will not result in an "all zero" CRC. As such, the parity of the information and the CRC is also non-zero and is generated along an "odd" path. When in the "even" path, the parity is XORed between all even numbered failed codewords and canceled. In the "odd" path, the CRC and parity of the "all zero" information payload are recreated to cancel the parity.

[0076] Method 1200 includes determining whether the number of failed codewords is an even number or an odd number (at step 1202). When the number of failed codewords is an odd number ("ODD" at step 1202), method 1200 proceeds to step 1204. When the number of failed codewords is an even number ("EVEN" at step 1202), method 1200 proceeds to step 1214.

[0077] First, when the number of failed codewords is odd, method 1200 includes encoding the first buffer with a seed of zero (at step 1204). For example, the scrambling seed may be associated with an all-zero codeword. LDPC encoder 616 encodes the seed of zero using the first buffer, thereby generating an encoded first buffer.

[0078] The method 1200 includes buffering the encoded first buffer into the second buffer at step 1206. For example, the data storage device controller 120 performs an XOR operation between the encoded first buffer and the second buffer.

[0079] The method 1200 includes encoding the all-zero payload with a seed of zero (at step 1208). For example, the LDPC encoder 616 encodes the seed of zero using a codeword of zero, thereby generating an encoded payload.

[0080] The method 1200 includes buffering the encoded payload into the second buffer at step 1210 . For example, the data storage device controller 120 performs an XOR operation between the encoded payload from step 1208 and the second buffer, thereby generating the copy page 406 .

[0081] Method 1200 includes decoding a failed codeword using a duplicate page (at step 710). For example, as previously described with respect to Figure 4As depicted, LDPC decoder 410 receives first page 401 , soft bit page 408 , and replica page 406 as input and generates a corrected first page 414 .

[0082] Returning to step 1202, when the number of failed codewords is even, method 1200 includes encoding the first buffer with a stripe seed (at step 1214). For example, a scrambling seed is associated with all codewords within the XOR stripe. LDPC encoder 616 encodes the stripe seed using the first buffer to generate an encoded first buffer.

[0083] The method 1200 includes buffering the encoded first buffer into the second buffer at step 1216 . For example, the data storage device controller 120 performs an XOR operation between the encoded first buffer and the second buffer to generate the copy page 406 .

[0084] Method 1200 includes decoding the failed codeword using the duplicate page (at step 1218). For example, as previously described with respect to Figure 4 As depicted, LDPC decoder 410 receives first page 401 , soft bit page 408 , and replica page 406 as input and generates a corrected first page 414 .

[0085] Pseudocode provides the implementation Figure 13 Examples of method 1100 and method 1200 are shown. Figure 14A Provides an even number of failed codewords. Figures 11 to 12 An example mathematical proof of the correctness of the JLX ECC scheme 131. Figure 14B Provides an odd number of failed codewords. Figures 11 to 12 An example mathematical proof of the correctness of the JLX ECC scheme 131.

[0086] Thus, the embodiments described herein provide an improved correction success rate for the ECC engine 126 . Figure 15 Provides a plot of the probability of decoding failure for a given number of failed adjacent codewords at a given bit error rate (BER). Figure 15 In the example, the XOR stripe length is 32, the code length is 4744 bits, the payload size is 4128+8 bits, and the parity size is 608 bits. In addition, Figure 16 Graphs showing correctable log BER distributions using only the XOR ECC scheme 129 and using the JLX ECC scheme 131 are provided.

[0087] JLX mathematical analysis

[0088] The following provides a mathematical analysis of the JLX ECC scheme 131 described herein, illustrating the theoretical advantages of these implementations. The analysis described herein assumes a simple degenerate decoder with a 100% probability of failure for any BER above the LDPC correction capability. Additionally, the analysis assumes "hard" page combining (rather than soft LLR combining via an LLR table).

[0089] First, the success-failure rate (SFR) of the LDPC ECC scheme 127 LDPC ) is defined according to equation (1), and reference Figure 17 BER distribution shown:

[0090]

[0091] in:

[0092] LDPC TH -LDPC correction capability;

[0093] The length of the N-XOR stripe; and

[0094] BER j {j=1,…,N} is taken from the lognormal BER distribution f with median BERμ and slope s LN|μ,s

[0095] The success-failure rate (SFR) of JLX ECC solution 131 JLX ) is defined according to equation (2):

[0096]

[0097] in:

[0098]

[0099] In equation (2), the first integral represents the probability of target page decoding failure, and the second integral represents the probability of JLX recovery failure.

[0100] Next, the BER is identified based on the use of hard bits and soft bits (see Figure 18 ). Assume that the target page exhibits a BER of BER1 and has a normal cell voltage distribution with a standard deviation of STD=σ, where and

[0101] Next, assuming that the soft bit page of the target page is generated by reading around ±Δ of the hard bit read level, BER1 is obtained according to equation (3):

[0102]

[0103] in:

[0104]

[0105] and

[0106]

[0107] The BER (BER) of the XOR ECC scheme 129 is derived from equation (4). XOR ):

[0108]

[0109] Assume only BER>LDPC TH Pages on BER XOR Contribute, and assume that all t=∑ j＝2,…,N I(BER j >LDPC TH ) failed pages, where t is the number of additional failed pages. The combined BER is derived from Equation (5):

[0110]

[0111] Next, based on the LN BER distribution f LN|μ,s (BER) defines some auxiliary probability density functions, such as Figure 19 shown. Figure 19 The area of ​​p shown is defined by equation (6):

[0112]

[0113] The distribution of BER for a given LDPC failure is defined according to equation (7):

[0114]

[0115] The cumulative distribution of the BER for a given LDPC failure is equal to the probability that the tail BER for a given LDPC failure is below the BER value defined according to equation (8):

[0116]

[0117] The probability that the maximum tail BER on t failed pages is lower than BER is defined according to equation (9):

[0118] F Max-LN-Tail|μ,s (BER,t)=Pr(max{ber1,...,ber t}≤BER)=Pr(ber1≤BER)·...·

[0119] Pr(ber t ≤BER)=F LN-Tail|μ,s (BER) t (9)

[0120] The probability that the maximum tail BER over t failed pages is equal to BER, as defined in equation (10):

[0121]

[0122] Next, calculate the SFR JLX The n-dimensional integral of is simplified and constrained to a computationally feasible two-dimensional integral. The n-dimensional integral is constrained by re-enumerating the BER events according to the case of t=1, 2, ..., N-1 additional failed pages. Next, BER combined An upper bound (based on the number of failed pages t and the maximum BER on them) is used, as shown in Equation (11):

[0123]

[0124] It should be understood that the above description is intended to be illustrative and not restrictive. Upon reading the above description, many embodiments and applications other than the examples provided will be apparent. The scope should not be determined with reference to the above description, but rather with reference to the appended claims together with the full scope of equivalents to which such claims are entitled. It is anticipated and intended that the technology discussed herein will undergo future developments, and that the disclosed systems and methods will be incorporated into such future embodiments. In short, it should be understood that the present application is capable of modification and variation.

[0125] All terms used in the claims are intended to be given their broadest reasonable constructions and their ordinary meanings as understood by those skilled in the art unless an explicit indication to the contrary is made herein. In particular, use of singular articles such as "a," "an," "the," and the like should be understood to refer to one or more of the indicated elements unless a claim recites an explicit limitation to the contrary.

[0126] An abstract of the specification is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It should be understood that the content submitted is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in various embodiments for the purpose of simplifying the disclosure. This approach to the disclosure should not be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. On the contrary, as reflected in the following claims, the inventive subject matter lies in less than all the features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separately claimed subject matter.

Claims

1. A data storage device, comprising: a memory for storing a plurality of code words; and a data storage device controller coupled to the memory, the controller comprising a processor and a controller memory storing a set of instructions that, when executed by the processor, instruct the controller to: During decoding of the plurality of codewords, detecting at least two failed codewords that could not be decoded; performing a joint low density parity check and exclusive-or (JLX) operation using scrambling seeds associated with the at least two failing codewords; and At least one of the at least two failed codewords is recovered from the JLX operation.

2. The data storage device of claim 1 , further comprising a low-density parity check decoder, and wherein the plurality of codewords includes a first failing codeword and a set of second codewords, and wherein to perform the JLX operation, the set of instructions instructs the controller to: performing an exclusive-OR operation on the set of second codewords to generate a copy of the first failed codeword, wherein the copy of the first failed codeword includes a different error than the first failed codeword; and The first failed codeword is recovered using the copy of the first failed codeword using the low density parity check decoder. 3 . The data storage device of claim 2 , wherein the copy of the first failing codeword is used as a soft bit input to the low-density parity-check decoder. 4 . The data storage device of claim 2 , wherein the set of second codewords includes a second fail codeword, and wherein the copy of the first fail codeword includes the same error as the second fail codeword.

5. The data storage device of claim 4 , wherein to perform the JLX operation, the set of instructions instructs the controller to: The second failure codeword is recovered using the recovered first failure codeword.

6. The data storage device of claim 1 , further comprising a first buffer and a second buffer, and wherein the plurality of codewords comprises a first fail codeword and a set of second codewords, and wherein the set of instructions instructs the controller to: During decoding of the set of second codewords, buffering data from successfully decoded codewords in the first buffer; and During decoding of the set of second codewords, failed codewords are buffered in the second buffer.

7. The data storage device of claim 6, and wherein to perform the JLX operation, the set of instructions instructs the controller to: deriving a first scrambling seed associated with the failed codeword; and The first scrambled seed is buffered in the second buffer.

8. The data storage device of claim 7, wherein each codeword of the plurality of codewords is associated with a different scrambling seed.

9. The data storage device of claim 7, wherein each codeword of the plurality of codewords is associated with the same scrambling seed.

10. The data storage device of claim 7, wherein to perform the JLX operation, the set of instructions instructs the controller to: The first scrambling seed is encoded with a payload value of zero.

11. The data storage device of claim 7 , wherein to perform the JLX operation, the set of instructions instructs the controller to: deriving a second scrambling seed associated with the first failure codeword; encoding the data stored in the first buffer using the second scrambling seed to generate encoded data; and An exclusive-OR operation is performed on the encoded data and the first scrambling seed stored in the second buffer to generate a copy of the first failure codeword.

12. The data storage device of claim 11 , further comprising a low-density parity check decoder, and wherein to perform the JLX operation, the set of instructions instructs the controller to: The first failed codeword is recovered using the copy of the first failed codeword using the low density parity check decoder.

13. A method comprising: detecting, during decoding of the plurality of codewords by a memory controller executing decoding firmware, at least two failed codewords that failed to be decoded; performing, with the memory controller, a joint low density parity check and exclusive-or (JLX) operation using a scrambling seed associated with the at least two failing codewords; as well as At least one of the at least two failed codewords is recovered from the JLX operation using the memory controller.

14. The method of claim 13 , wherein the plurality of codewords comprises a first failing codeword and a set of second codewords, and wherein performing the JLX operation comprises: performing, with the memory controller, an exclusive-OR operation on the set of second codewords to generate a copy of the first fail codeword, wherein the copy of the first fail codeword includes a different error than the first fail codeword; as well as The first failing codeword is recovered using the copy of the first failing codeword using a low density parity check decoder with the memory controller.

15. The method of claim 14, wherein the set of second codewords includes a second failed codeword, and wherein the copy of the first failed codeword includes the same error as the second failed codeword.

16. The method of claim 15, wherein performing the JLX operation comprises: The second fail codeword is recovered using the recovered first fail codeword by the memory controller.

17. The method of claim 13, wherein the plurality of codewords comprises a first failing codeword and a set of second codewords, and wherein the method comprises: buffering, with the memory controller and during decoding of the set of second codewords, data from successfully decoded codewords in a first buffer; as well as Failed codewords are buffered in a second buffer using the memory controller and during decoding of the set of second codewords.

18. The method of claim 17, wherein performing the JLX operation comprises: deriving, using the memory controller, a first scrambling seed associated with the failed codeword; as well as The first scrambled seed is buffered in the second buffer using the memory controller.

19. The method of claim 18, wherein performing the JLX operation comprises: deriving, using the memory controller, a second scrambling seed associated with the first failure codeword; encoding, with the memory controller, the first buffer using the second scrambling seed to generate an encoded buffer; as well as An exclusive-OR operation is performed, using the memory controller, between the encoded buffer and the second buffer to generate a copy of the first failed codeword.

20. A memory device comprising: a memory for storing a plurality of code words; and a controller coupled to the memory, wherein the controller is configured to perform a joint low-density parity check and exclusive-or (JLX) operation using a scrambling seed associated with a failing codeword of the plurality of codewords to recover the failing codeword when at least two codewords of the plurality of codewords fail during decoding.

Images