A method for improving semiconductor chip yield based on a machine learning classifier

Abstract

The application discloses a kind of based on machine learning classifier to improve the method for yield of semiconductor chip, it is related to semiconductor chip technical field, including, obtain and process semiconductor wafer image, test parameter, process parameter and chip quality label, construct chip space relation diagram, and chip quality label, chip feature vector and chip space relation diagram are integrated into chip feature dataset;Chip feature vector is carried out spatial consistency weighted fusion based on chip space relation diagram, the fusion feature vector is processed to reduce dimension, and low-dimensional chip fusion sub-vector is generated;According to chip quality prediction probability, by intervening each dimension chip feature, the causal effect of chip is analyzed, and the SHAP value of each dimension chip feature is calculated;Based on SHAP value, process parameters are optimized using reinforcement learning, and the yield gain rate is calculated.The application maximizes yield gain rate by optimizing process parameters through reinforcement learning, and adjusting process parameters based on SHAP value.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chips, and particularly relates to a method for improving the yield of semiconductor chips based on a machine learning classifier. BACKGROUND

[0002] Semiconductor manufacturing is the core of modern electronics industry. In recent years, with the development of advanced process technologies such as 3nm and 5nm, chip yield optimization has become a key research direction. In order to improve the yield, the industry widely uses high-resolution optical detection equipment for wafer defect detection, combines with semiconductor test instruments to measure electrical parameters, and records process parameters through a manufacturing equipment control platform. Traditional methods usually extract defect features based on image processing technology (such as threshold segmentation), combine test and process parameters, and apply machine learning algorithms (such as support vector machines, random forests) or deep learning models (such as convolutional neural networks) for chip quality classification. These methods try to establish the correlation between defect patterns and chip quality through statistical analysis or feature engineering, significantly improving the automation level and classification accuracy of defect detection.

[0003] However, the prior art still has deficiencies in improving the yield of chips. First, the traditional method is insufficient in modeling the spatial distribution characteristics of wafer defects, ignoring the spatial correlation between chip grids, resulting in low recognition accuracy of high-risk defect patterns in edge areas, affecting the reliability of yield prediction. Second, the fusion effect of multi-source heterogeneous data such as images, tests and process parameters is limited, lacking systematic analysis of feature importance and causal relationship, making it difficult to provide accurate guidance for improving yield. These problems are particularly prominent in high-density integrated circuit manufacturing, which puts higher requirements on yield improvement and production efficiency, and urgently needs more efficient classification and optimization methods. SUMMARY

[0004] In view of the above existing problems, the present application is proposed.

[0005] Therefore, the present application provides a method for improving the yield of semiconductor chips based on a machine learning classifier, which solves the problem of lacking systematic analysis of feature importance and causal relationship, and difficulty in providing accurate guidance for improving yield.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a method for improving the yield of semiconductor chips based on a machine learning classifier, which comprises,

[0008] obtaining and processing semiconductor wafer images, test parameters, process parameters and chip quality labels to obtain chip feature vectors, constructing a chip spatial relationship graph, and integrating the chip quality labels, chip feature vectors and chip spatial relationship graph into a chip feature dataset;

[0009] The edge of the chip space relation graph is used for spatial consistency weighted fusion of the chip feature vector, a chip fusion vector is generated, the influence of each dimension chip feature is calculated, the dimension reduction processing is performed on the fusion feature vector, a low-dimensional chip fusion sub-vector is generated, and the chip feature dataset is updated;

[0010] The chip quality classifier is constructed by supplementing the chip feature dataset of unqualified chips to balance the proportion of qualified and unqualified chips, the neighbor low-dimensional chip fusion sub-vector in the chip space relation graph is aggregated based on the weighted attention mechanism, and a chip quality prediction probability is output;

[0011] According to the chip quality prediction probability, the chip features in each dimension are intervened, the chip causal effect is analyzed, and the SHAP value of each dimension chip feature is calculated.

[0012] Based on the SHAP value, the process parameters are optimized by using reinforcement learning, and the good product gain rate is calculated.

[0013] As a preferred scheme of the method for improving the yield of semiconductor chips based on the machine learning classifier, the chip space relation graph is constructed, and the specific steps are as follows,

[0014] The wafer is segmented into a plurality of chip grids by using the Otsu threshold method, and the defect density of each chip grid is calculated;

[0015] The chip grid is defined as the node of the chip space relation graph;

[0016] The Euclidean distance between each chip grid in the wafer is calculated, and the edge of the chip space relation graph is defined;

[0017] The edge weight of the chip space relation graph is calculated by using the Gaussian kernel function in combination with the difference between the Euclidean distance and the defect density of each chip grid, and the construction of the chip space relation graph is completed.

[0018] As a preferred scheme of the method for improving the yield of semiconductor chips based on the machine learning classifier, the influence of each dimension chip feature is calculated, and the specific steps are as follows,

[0019] The chip feature quality correlation between each dimension chip feature in the chip fusion vector and the chip quality label is calculated;

[0020] The Pearson correlation coefficient between each dimension chip feature in the chip fusion vector is calculated, and the chip feature correlation coefficient is output;

[0021] Based on the feature extraction record of all chip grids, the complexity of each dimension chip feature is calculated;

[0022] According to the chip space relationship diagram, the spatial consistency score between adjacent nodes under the same dimension chip feature is calculated;

[0023] The feature influence of each dimension chip feature is obtained by weighted summation of the chip feature quality correlation, the chip feature correlation coefficient, the complexity of the chip feature vector and the spatial consistency score.

[0024] As a preferred scheme of the method for improving the yield of semiconductor chips based on the machine learning classifier, the proportion of qualified and unqualified chips is balanced, and the specific steps are as follows,

[0025] According to the number of chips and the distribution of unqualified chips, the unqualified chip proportion threshold is set.

[0026] When the proportion of unqualified chips is less than the unqualified chip proportion threshold, a conditional generative adversarial network is used to generate a low-dimensional chip fusion sub-vector of unqualified chips, and the chip feature data set is updated.

[0027] As a preferred scheme of the method for improving the yield of semiconductor chips based on the machine learning classifier, the proportion of qualified and unqualified chips is balanced, and the specific steps are as follows,

[0028] Based on a multi-layer graph attention network, a chip quality classifier is constructed, and a chip feature data set is input.

[0029] By weighted attention, neighbor low-dimensional chip fusion sub-vectors in the chip space relationship diagram are aggregated.

[0030] According to the chip hidden features output by the last layer of the graph attention network, the chip quality prediction probability is calculated in the output layer.

[0031] The chip quality prediction probability includes a chip unqualified probability and a chip qualified probability.

[0032] If the qualified probability is greater than the unqualified probability, the chip is qualified and is a good product chip, and if the qualified probability is less than or equal to the unqualified probability, the chip is unqualified and is a defective chip.

[0033] As a preferred scheme of the method for improving the yield of semiconductor chips based on the machine learning classifier, the proportion of qualified and unqualified chips is balanced, and the specific steps are as follows,

[0034] According to the chip quality prediction probability, low-dimensional chip fusion sub-vectors of all defective chips are collected and integrated.

[0035] The standardized distribution of each dimension chip feature in the low-dimensional chip fusion sub-vector of the defective chip is obtained.

[0036] The standardized distribution of each dimensional chip feature is weighted according to the defect density of the substandard chip, an intervention value of each dimensional chip feature is set, and a substandard feature set is obtained.

[0037] As a preferred solution of the method for improving the yield of semiconductor chips based on the machine learning classifier, the SHAP value of each dimensional chip feature is calculated based on the contribution of each dimensional chip feature in the substandard feature set to the chip quality prediction probability after intervention, and the Tree SHAP algorithm is used to calculate the SHAP value.

[0038] As a preferred solution of the method for improving the yield of semiconductor chips based on the machine learning classifier, the yield gain rate is calculated as the difference between the chip qualification probability before and after the optimization of the process parameters.

[0039] In a second aspect, the present application provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and wherein the computer program, when executed by the processor, implements any step of the method for improving the yield of semiconductor chips based on the machine learning classifier according to the first aspect of the present application.

[0040] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any step of the method for improving the yield of semiconductor chips based on the machine learning classifier according to the first aspect of the present application.

[0041] The present application has the following advantages: the present application fuses the feature vectors of images, tests and process parameters through the multi-head attention mechanism and spatial consistency weighting, and generates low-dimensional fusion sub-vectors by using sparse principal component analysis, thereby improving the comprehensive expression ability of features, providing a more robust input for the classifier, quantifying the influence of each feature on the yield through causal inference and Tree SHAP algorithm, optimizing the process parameters through reinforcement learning, adjusting the process parameters based on the SHAP value, and maximizing the yield gain rate. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0043] Fig. 1 Flowchart of the method for improving the yield of semiconductor chips based on the machine learning classifier.

[0044] Fig. 2A flow chart is constructed for the chip spatial relationship graph.

[0045] Fig. 3 A flow chart is constructed for feature influence calculation and dimension reduction.

[0046] Fig. 4 A flow chart is constructed for chip quality classification and SHAP analysis. DETAILED DESCRIPTION

[0047] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0048] In the following description, a large number of specific details are set forth in order to facilitate a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present application, therefore the present application is not limited to the specific embodiments disclosed below.

[0049] Secondly, the "one embodiment" or "embodiment" referred to herein means that a specific feature, structure or characteristic can be included in at least one implementation of the present application. "In one embodiment" appearing in different places in the specification does not mean the same embodiment, nor is it an embodiment that is separate or alternative to other embodiments.

[0050] REFERENCE Figs. 1-4 For one embodiment of the present application, the embodiment provides a method for improving the yield of semiconductor chips based on a machine learning classifier, comprising the following steps:

[0051] S1, obtaining and processing semiconductor wafer images, test parameters, process parameters and chip quality labels to obtain chip feature vectors, constructing a chip spatial relationship graph, and integrating the chip quality labels, chip feature vectors and chip spatial relationship graph into a chip feature dataset.

[0052] Using a high-resolution optical detection device, wafer surface defect images at the lithography, etching and deposition stages are collected, the wafer surface defect images are divided into 100x100 chip grids to adapt to the construction of the chip spatial relationship graph, and the Otsu threshold method is used to segment the results to quantify the defect density of each chip grid. Specifically, set the pixel value greater than 200 as 1, representing a defect pixel, and the rest as 0, representing a normal pixel, traverse each chip grid to obtain a binary mask matrix of the chip grid, and calculate the ratio of the defect pixel to all pixel points in the chip grid to obtain the defect density of the chip grid.

[0053] The wafer surface defect image is subjected to low-dimensional image feature extraction by using a convolutional variational autoencoder, and the defect density is subjected to weighted processing to enhance the feature expression of the high-risk area, and a chip image matrix is output.

[0054] Specifically, a sub-image of each chip grid is cropped from the wafer surface defect image, the sub-image is reconstructed by a 4-layer convolutional encoder and a 4-layer deconvolutional decoder to generate a chip grid image vector, a linear weighting method is used to weight each dimension of the chip grid image vector based on the defect density of the chip grid, and the defect density of the chip grid is fused into the corresponding chip grid image vector. In this way, the chip grid with high defect density will moderately amplify the value of the chip grid image vector to highlight its defect features, while the chip grid with low defect density will remain small adjustment, and all the chip grid image vectors fused with the defect density are combined to form a chip image matrix.

[0055] Specifically, the electrical parameters of each chip grid test point are measured by using a wafer test device, including leakage current, threshold voltage, on-resistance and the like, and the circuit probes of each chip grid are subjected to functional test by using a chip tester to output the functional parameters, including timing delay, power consumption, precision and signal integrity and the like.

[0056] The mean and standard deviation of the test parameters are calculated, the Z-score method is used for abnormal value detection, and the mean-standard deviation normalization method is used for standardization processing to output a test feature vector.

[0057] The process parameters of the lithography, etching and deposition stages are recorded by a wafer manufacturing equipment control platform, including the exposure dose of the lithography machine, the focus depth, the gas flow of the etching machine, the etching time and the temperature of the deposition machine and the like, the process parameters are distributed to each chip grid, specifically, the process parameters closest to the chip grid timestamp are selected for the chip grid, and the mean-standard deviation normalization method is used for standardization processing to output a process feature vector.

[0058] The chip image matrix, the test feature vector and the process feature vector are spliced with the chip grid as the index to generate a chip feature vector.

[0059] A chip space relation graph is constructed, a chip grid is defined as a node of the chip space relation graph, a unique index is assigned to each chip grid according to the distribution of the chip grid on a wafer, the chip feature vector of each chip grid is associated to the node of the chip space relation graph by binding the memory address or reference of the chip feature vector of each chip grid to the feature field of the node, the Euclidean distance between nodes (between the centers of adjacent chip grids) in the wafer is calculated to determine the adjacency relationship between the nodes and serve as the edge of the chip space relation graph, and the edge weight of the chip space relation graph is calculated by combining the Euclidean distance between nodes and the difference in defect density through a Gaussian kernel function, and the calculation formula is as follows:

[0060] ;

[0061] wherein, represents the edge weight between nodes and , is the Euclidean distance between nodes and , is the standard deviation of the Gaussian kernel function, is the difference in defect density between nodes and , represents a node of the chip space relation graph, represents a neighbor node of the node .

[0062] It should be noted that the edges of the chip space relation graph are weighted by the Euclidean distance and the difference in defect density to enhance the expression ability of the chip space relation graph for defect patterns.

[0063] According to the chip specifications, such as a SOC chip, a test parameter qualified standard is defined, and the test parameters of each chip grid are compared based on the software of an automatic test equipment (ATE) to generate a binary label. When all the test parameters meet the test parameter qualified standard, it is determined to be qualified, that is, the chip quality label is 1, and when any test parameter does not meet the test parameter qualified standard, it is determined to be unqualified, that is, the chip quality label is 0.

[0064] The chip feature data set adopts a table form, each row corresponds to a chip grid, and includes a unique index of the chip grid, a node index of the chip space relation graph (a memory address pointing to the corresponding node in the chip space relation graph), a chip feature vector and a chip quality label. The integration of the chip space relation graph, the chip feature vector and the chip quality label is completed, and the chip feature data set is output.

[0065] S2, based on the chip space relation graph, the edge of the chip feature vector is subjected to spatial consistency weighting fusion, a chip fusion vector is generated, the influence of each dimension chip feature is calculated, the fusion feature vector is subjected to dimension reduction processing, a low-dimensional chip fusion sub-vector is generated, and the chip feature dataset is updated.

[0066] The chip feature vectors are fused through the multi-head attention mechanism, and the chip space relation graph is subjected to spatial consistency weighting to generate a chip fusion vector.

[0067] Specifically, according to the query weight transformation, key matrix transformation and value matrix transformation of the multi-head attention mechanism, the query vector, key vector and value vector of the single-head attention are obtained, the single-head attention is calculated multiple times, and the calculation results of each single-head attention are spliced, and then the multi-head attention function is output through linear transformation. The chip feature vectors are fused according to the query vector, key vector, value vector and multi-head attention function of the single-head attention, the chip feature vectors after fusion are subjected to spatial consistency weighting according to the edge weight of the chip space relation graph and the defect density of each chip grid, and a chip fusion vector is generated. The calculation formula is as follows:

[0068] ;

[0069] Wherein, is the chip fusion vector, is the chip feature vector fused through the multi-head attention mechanism, is a weighting coefficient, and the value range is , represents a neighbor node set of a node in the chip space relation graph, represents the defect density of the neighbor node;

[0070] The chip feature quality correlation of each dimension of the chip feature in the chip fusion vector and the chip quality label is calculated, and the correlation of each dimension of the chip feature and the chip quality is quantified. The calculation formula is as follows:

[0071] ;

[0072] Wherein, is the chip feature quality correlation, is the chip feature of the dimension in the chip fusion vector, is the chip quality label value, 0 or 1, is the joint probability, indicating the probability that the chip feature of the dimension in the chip fusion vector is , represents the edge probability of the chip feature of the dimension in the chip fusion vector, the edge probability of the chip quality label value being , is an index variable of the chip feature dimension in the chip fusion vector;

[0073] It should be noted that, , and are calculated by discretizing the chip fusion vector and estimating the probability by using a histogram. Based on the number of chip grids and the chip quality label value of each chip grid, a joint histogram is calculated and normalized to obtain , and ;

[0074] For each pair of chip feature vectors , the covariance and standard deviation are calculated, the Pearson correlation coefficient between the chip features in each dimension of the chip fusion vector is calculated to measure the feature redundancy, and the chip feature correlation coefficient is output. The calculation formula is as follows:

[0075] ;

[0076] wherein, is the chip feature correlation coefficient, represents the covariance calculation formula, represents the chip feature in the dimension of the chip fusion vector, and , represents the standard deviation of the chip feature in the dimension of the chip fusion vector, represents the standard deviation of the chip feature in the dimension of the chip fusion vector;

[0077] Based on the feature extraction records of all chip grids, for example, the 10-dimensional chip image takes 0.002 seconds, the complexity of the chip feature in each dimension is calculated, and the calculation formula is as follows:

[0078] ;

[0079] wherein, represents the complexity of the chip feature in each dimension, represents the time consumption of obtaining the chip feature vector in the dimension, is the maximum time consumption;

[0080] According to the chip space relationship diagram, the spatial consistency score between adjacent nodes under the same dimension chip feature is calculated, and the calculation formula is as follows:

[0081] ;

[0082] wherein, denotes the spatial consistency score, and denotes the node and the neighbor node in the first dimensional chip feature value;

[0083] For each chip grid, the influence of each dimensional chip feature is quantified by weighted summation of the chip feature quality correlation, the chip feature correlation coefficient, the complexity of the chip feature vector, and the spatial consistency score;

[0084] The chip features of each dimension are sorted in descending order according to the influence of the chip features, and the chip fusion sub-vectors are selected according to a preset proportion, for example, the top 50% of chip feature vectors;

[0085] The chip fusion sub-vectors are processed by dimension reduction through principal component analysis to generate low-dimensional chip fusion sub-vectors;

[0086] Specifically, the sparse principal component analysis method is used to obtain an orthogonal basis matrix by QR decomposition of the chip fusion sub-vectors, to generate a sparse loading matrix by random sampling from the chip fusion sub-vectors, to update the sparse loading matrix by fixing the orthogonal basis matrix and using the soft threshold shrinkage method, to fix the sparse loading matrix, to perform singular value decomposition on the fixed orthogonal basis matrix and reconstruction, and to iteratively optimize the orthogonal basis matrix and the sparse loading matrix. The calculation formula is as follows:

[0087] ;

[0088] wherein, is the orthogonal basis matrix, is the sparse loading matrix, is the chip fusion sub-vector, denotes the matrix transpose, is the sparse penalty coefficient, and the value range is ;

[0089] According to the sparse loading matrix, the projection of the chip fusion sub-vector is calculated to generate a low-dimensional chip fusion sub-vector, and the chip feature vector in the chip feature dataset is replaced to complete the update of the chip feature dataset. The calculation formula is as follows:

[0090] ;

[0091] wherein, is the low-dimensional chip fusion sub-vector.

[0092] S3. By supplementing the chip feature dataset of defective chips, balancing the ratio of qualified to defective chips, constructing a chip quality classifier, and based on a weighted attention mechanism, aggregating the fusion sub-vectors of neighboring low-dimensional chips in the chip spatial relationship graph, and outputting the chip quality prediction probability.

[0093] Calculate the proportion of defective chips based on the chip quality labels in the chip feature dataset;

[0094] Based on the distribution of defect density of defective chips, a defect density threshold is set. For example, the 90th percentile of the defect density distribution of defective chips is defined as the defect density threshold. The chip quality label of the chip is determined to be unqualified, and the chip with a defect density greater than the defect density threshold is a high-defect chip.

[0095] In the field of machine learning, especially in binary classification problems, sample imbalance has a significant impact on classifier performance. When the proportion of minority class (defective chips) is too low, classifiers (such as support vector machines and neural networks) tend to overfit the majority class, resulting in a decrease in the recall rate of the minority class. Therefore, based on the number of chips and the distribution of defective chips, a threshold for the proportion of defective chips is set, such as 20%, to ensure that the classifier fully learns the features of defective chips during training, while avoiding distribution bias caused by over-synthesis.

[0096] When the proportion of defective chips is less than the threshold for the proportion of defective chips, a conditional generative adversarial network is used to generate a low-dimensional chip fusion sub-vector of defective chips.

[0097] Specifically, for the selection of training samples in the training set of the Conditional Generative Adversarial Network (CGN), 80% of the chip feature datasets of high-defect chips are selected centrally, and the remaining 20% ​​are randomly selected from the remaining chips. A generator consisting of four fully connected layers outputs a synthetic low-dimensional chip fusion vector of defective chips. A discriminator consisting of three fully connected layers is used for discrimination. The CGN is trained, and the Adam optimizer is used to optimize the network parameters (weight matrix, bias term, and attention vector, etc.). The similarity of feature distributions between the synthetic low-dimensional chip fusion vector and the real low-dimensional chip fusion vector is verified. The KL divergence is calculated using histogram estimation, as shown in the following formula:

[0098] ;

[0099] in, express and KL divergence, This represents the feature distribution in the synthesized low-dimensional chip fusion subvector representing defective chips. This represents the feature distribution in the true low-dimensional chip fusion subvector of defective chips. Represents the discretized interval of the chip feature dataset;

[0100] According to With the relationship between the KL divergence and the total variation distance, the KL divergence threshold is set, when With the KL divergence is less than the KL divergence threshold, the training is completed, the synthetic low-dimensional chip fusion sub-vector of the unqualified chip is output, and the chip feature data set is updated;

[0101] The chip quality classifier adopts a three-layer graph attention network (GAT) structure, and the network parameters of the chip quality classifier are initialized by using the Xavier uniform distribution method. Based on the edge weight of the chip spatial relationship graph, the neighbor low-dimensional chip fusion sub-vector in the chip spatial relationship graph is aggregated by using weighted attention, the chip hidden feature of each layer of the attention network is calculated, and the calculation formula is as follows:

[0102] ;

[0103] ;

[0104] Wherein, represents the low-dimensional chip fusion sub-vector of the node The chip hidden feature of the first layer graph attention network, represents the low-dimensional chip fusion sub-vector of the node in the chip spatial relationship graph, is a weighted attention coefficient, and represent the weight matrix and the bias term of the first layer graph attention network, and respectively represent the chip hidden features of the nodes and in the first layer graph attention network of the chip spatial relationship graph, , represents the low-dimensional chip fusion sub-vector of the node in the chip spatial relationship graph, represents an attention vector, represents an index variable of the number of graph attention network layers;

[0105] According to the chip hidden feature output by the last layer of the graph attention network, the chip quality prediction probability is calculated at the output layer, including the qualified probability and the unqualified probability. If the qualified probability is greater than the unqualified probability, it indicates that the chip is qualified, and it is a good chip. If the qualified probability is less than or equal to the unqualified probability, it indicates that the chip is unqualified, and it is a defective chip. The calculation formula is as follows:

[0106] ;

[0107] wherein, is a chip quality prediction probability, represents a chip unqualified probability, represents a chip qualified probability, and , represents a weight matrix of the output layer, represents a chip hidden feature of the third layer graph attention network of a node in the chip spatial relation graph;

[0108] According to the cross entropy of the chip unqualified probability and the chip qualified probability, and the L2 norm of the chip hidden feature of the third layer graph attention network of two neighbor nodes in the chip spatial relation graph, a chip quality classifier loss function is defined, and the calculation formula is as follows:

[0109] ;

[0110] ;

[0111] ;

[0112] wherein, is a chip quality classifier loss function value, is a cross entropy of a chip unqualified probability and a chip qualified probability, is an L2 norm of a chip hidden feature of a third layer graph attention network of two neighbor nodes in a chip spatial relation graph, is a number of nodes in the chip spatial relation graph, represents a chip hidden feature of a node in the third layer graph attention network;

[0113] Minimizing the chip quality classifier loss function, through back propagation, using the Adam optimizer, the network parameters of the quality classifier are optimized, the training of the quality classifier is completed, and the chip quality prediction probability is output.

[0114] S4, according to the chip quality prediction probability, intervening in each dimension chip feature, analyzing the chip causal effect, calculating the SHAP value of each dimension chip feature.

[0115] Using the Do-Calculus causal inference method, the causal effect of each dimension chip feature in the low-dimensional chip fusion sub-vector on the chip quality prediction probability is analyzed;

[0116] Specifically, according to the chip quality prediction probability output by the chip quality classifier, the low-dimensional chip fusion sub-vectors of all defective chips are collected and integrated, the standardized distribution of the chip features in each dimension of the low-dimensional chip fusion sub-vectors of the defective chips is obtained, and the defective chips are weighted according to the defect density of the defective chips, the chip feature intervention value is set, the chip feature dataset of the unqualified chips is intervened, and the defective feature set is obtained, and the calculation formula is as follows:

[0117] ;

[0118] wherein, is the chip feature in the defective feature set of the node in the th dimension, is the mean value of the chip feature in the th dimension, is the standard deviation of the chip feature in the th dimension, is the defect density of the node , and is a dimension index variable of the chip feature in the defective feature set.

[0119] The defective feature set is input into the chip quality classifier to obtain the chip quality prediction probability after intervention, which is output as the causal effect analysis result.

[0120] Based on the uniform distribution, the defective feature set is randomly sampled to generate a defective feature subset.

[0121] The Tree SHAP algorithm is used to calculate the SHAP value, which reflects the contribution of each dimension chip feature in the defective feature set to the chip quality prediction probability after intervention, and the calculation formula is as follows:

[0122] ;

[0123] wherein, is the SHAP value of the node , indicating the contribution of the defective feature set in the th dimension chip feature to the chip unqualified probability of the node , is the defective feature subset, is the number of chip features in the defective feature subset, is the number of chip features in the defective feature set, represents the chip unqualified probability output by the chip quality classifier when the input is , represents the union of and , represents the input The chip unqualified probability output by the chip quality classifier.

[0124] S5, based on the SHAP value, using reinforcement learning, calculating the good product gain rate by optimizing the process parameters.

[0125] According to the process precision of the manufacturing equipment in the wafer manufacturing equipment control platform, the adjustment amount of the process parameters is set, for example, based on the 3nm process equipment precision, the exposure dose adjustment precision of the lithography machine is ±0.5 mJ / cm²;

[0126] Define the state space, action space and reward function of reinforcement learning;

[0127] Specifically, define the chip unqualified probability and the process parameter vector as the state space, define the process parameter adjustment amount as the action space, define the reward function based on the good product gain rate and by weighting the SHAP value and the defect density, and the calculation formula is as follows:

[0128] ;

[0129] Wherein, is the reward function value, represents the qualified probability of the node under the optimized process parameters, represents the initial process parameters, represents the process parameter adjustment amount, is the defect density weighting coefficient, and the value range is , is the SHAP value weighting coefficient, and the value range is , represents the number of nodes in the defective feature set;

[0130] Starting from the initial state space, the strategy network of reinforcement learning samples actions from the action space according to the SHAP value, specifically, the SHAP value size reflects the contribution degree of the chip feature to the chip unqualified probability, starting from the chip feature with the largest contribution degree (the process parameter vector here), the optimized process parameters are obtained, the chip feature data set after the optimized process parameters is input into the chip quality classifier, and the chip quality prediction probability (chip qualified probability) is output. Calculate the reward function to complete the guidance of SHAP to reinforcement learning training.

[0131] The chip good product gain rate is obtained by calculating the difference between the chip qualified probability under the optimized process parameters and the initial process parameters.

[0132] The embodiment also provides a computer device suitable for the method for improving the yield of semiconductor chips based on a machine learning classifier, including a memory and a processor; the memory is used to store computer executable instructions, and the processor is used to execute the computer executable instructions to realize the method for improving the yield of semiconductor chips based on a machine learning classifier as proposed in the above embodiment.

[0133] The computer device can be a terminal, and the computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be achieved through WIFI, an operator network, NFC (Near Field Communication) or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0134] The embodiment also provides a storage medium having a computer program stored thereon, the program being executed by a processor to realize the method for improving the yield of semiconductor chips based on a machine learning classifier as proposed in the above embodiment. The storage medium can be realized by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk or an optical disk.

[0135] To sum up, the application fuses the feature vectors of images, tests and process parameters by the multi-head attention mechanism and spatial consistency weighting, and generates a low-dimensional fusion sub-vector by using sparse principal component analysis, thereby improving the comprehensive expression ability of the features, providing a more robust input for the classifier, quantifying the influence of each feature on the yield by causal inference and Tree SHAP algorithm, optimizing the process parameters by reinforcement learning, guiding the adjustment of the process parameters based on the SHAP value, and maximizing the yield gain rate.

[0136] It should be noted that the above examples are only used to illustrate the technical solutions of the present application and are not limiting. Although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present application, and they should be covered in the scope of the claims of the present application.

Claims

1. A method of improving yield of semiconductor chips based on a machine learning classifier, the method comprising: The application relates to a semiconductor chip quality prediction method and device. ​ The chip feature vector is obtained by acquiring and processing a semiconductor wafer image, test parameters, process parameters and a chip quality label, a chip space relation graph is constructed, and the chip quality label, the chip feature vector and the chip space relation graph are integrated into a chip feature dataset; The chip space relation graph is constructed in the following specific steps, The wafer is segmented into a plurality of chip grids by using an Otsu threshold method, and the defect density of each chip grid is calculated; The chip grid is defined as a node of the chip space relation graph; The Euclidean distance between each chip grid in the wafer is calculated, and the chip space relation graph is defined as an edge; The edge weight of the chip space relation graph is calculated by using a Gaussian kernel function, combining the Euclidean distance and the difference in defect density between each chip grid, and the construction of the chip space relation graph is completed; The spatial consistency of the chip feature vector is weighted and fused based on the edge of the chip space relation graph, a chip fusion vector is generated, the fusion feature vector is processed by dimension reduction through the influence of each dimension chip feature, a low-dimensional chip fusion subvector is generated, and the chip feature dataset is updated; The proportion of qualified and unqualified chips is balanced by supplementing the chip feature dataset of unqualified chips, and the specific steps are as follows, According to the number of chips and the distribution of unqualified chips, the unqualified chip proportion threshold is set; When the unqualified chip proportion is less than the unqualified chip proportion threshold, a conditional generative adversarial network is used to generate the low-dimensional chip fusion subvector of the unqualified chip, and the chip feature dataset is updated; A chip quality classifier is constructed, the neighbor low-dimensional chip fusion subvector in the chip space relation graph is aggregated based on a weighted attention mechanism, and a chip quality prediction probability is output; According to the chip quality prediction probability, the specific steps of intervention on each dimension chip feature are as follows, According to the chip quality prediction probability, the low-dimensional chip fusion subvector of all defective chips is collected and integrated; The low-dimensional chip fusion subvector refers to that the influence of each dimension chip feature is sorted in descending order, and the chip fusion subvector is selected according to a preset proportion, the chip fusion subvector is processed by dimension reduction through principal component analysis, and the low-dimensional chip fusion subvector is generated; The standardized distribution of each dimension chip feature in the low-dimensional chip fusion subvector of the defective chip is obtained; According to the defect density of the defective chip, the standardized distribution of each dimension chip feature is weighted, the intervention value of each dimension chip feature is set, and a defective feature set is obtained; The SHAP value of each dimension chip feature is calculated by analyzing the chip causal effect; Based on the SHAP value, the process parameters are optimized by using reinforcement learning, and the good product gain rate is calculated in the following specific steps, According to the process precision of the manufacturing equipment in the manufacturing equipment control platform of the wafer, the adjustment amount of the process parameter is set; The state space, action space and reward function of reinforcement learning are defined; Starting from the initial state space, the policy network of reinforcement learning samples an action from the action space according to the SHAP value, calculates the difference between the chip qualification probability under the optimized process parameter and the initial process parameter, and obtains the chip good product gain rate.

2. The method of claim 1, wherein: The influence of each dimension chip feature is calculated in the following specific steps, calculating a chip feature quality correlation degree of each dimension of the chip feature in the chip fusion vector and the chip feature quality label; calculating a Pearson correlation coefficient between chip features of each dimension in the chip fusion vector, and outputting a chip feature correlation coefficient; calculating the complexity of the chip feature of each dimension based on the feature extraction record of the entire chip grid; calculating the spatial consistency score between adjacent nodes under the same dimension chip feature according to the chip spatial relationship graph; obtaining the feature influence of the chip feature of each dimension by weighted summation of the chip feature quality correlation degree, the chip feature correlation coefficient, the complexity of the chip feature vector, and the spatial consistency score.

3. The method for improving semiconductor chip yield based on machine learning classifiers as described in claim 1, characterized in that: The output chip quality prediction probability comprises the following specific steps, based on the multi-layer graph attention network, constructing a chip quality classifier and inputting the chip feature data set; aggregating neighbor low-dimensional chip fusion sub-vectors in the chip spatial relationship graph through weighted attention; calculating the chip quality prediction probability in the output layer according to the chip hidden feature output by the last layer of the graph attention network; The chip quality prediction probability includes chip unqualified probability and chip qualified probability. If the qualified probability is greater than the unqualified probability, it means that the chip is qualified, which is a good chip. If the qualified probability is less than or equal to the unqualified probability, it means that the chip is unqualified, which is a defective chip.

4. The method of claim 1, wherein: The SHAP value of each dimension of the chip feature refers to the contribution of each dimension of the chip feature in the defective feature set to the chip quality prediction probability after intervention, and the SHAP value is calculated by using the Tree SHAP algorithm. ​ 5. The method for improving semiconductor chip yield based on machine learning classifiers as described in claim 1, characterized in that: The calculation of the good product gain rate refers to the difference of the chip qualified probability before and after the optimization of the process parameters.

6. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that: The processor executes the computer program to realize the steps of the method for improving the yield of semiconductor chips based on the machine learning classifier according to any one of claims 1-5.

7. A computer readable storage medium having stored thereon a computer program, characterized in that: The computer program is executed by the processor to realize the steps of the method for improving the yield of semiconductor chips based on the machine learning classifier according to any one of claims 1-5.

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