A semiconductor device and a manufacturing method thereof

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, the substrate being provided with a dielectric layer; forming a mask layer on the dielectric layer, patterning the mask layer to define a pattern for forming a first groove, setting an etching device to a first mode, etching the dielectric layer to form the first groove in the dielectric layer; switching the etching device to a second mode, introducing a carbon source into a reaction chamber of the etching device, depositing a carbon film layer on the sidewall and the bottom of the first groove, forming an inner groove on the carbon film layer, the transverse size of the inner groove being smaller than that of the first groove; switching the etching device to the first mode, taking the carbon film layer as a mask, etching the carbon film layer and the dielectric layer below the bottom of the inner groove to form a through hole; and removing the remaining carbon film layer. In the embodiment of the application, only one mask and one etching process are needed to form a double damascene structure, so that the production process and the production cycle are simplified, and the production cost is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In integrated circuits, metal interconnects serve as the medium for signal conduction between peripheral circuits and internal chip devices, enabling electrical connections between different components. With continuous advancements in integrated circuit manufacturing processes, device sizes are shrinking, leading to increasingly stringent requirements for device performance and stability. Aluminum, originally used for fabricating metal interconnects, is no longer suitable as an internal metal interconnect material in advanced process technologies due to its high resistivity, high electromigration, and poor filling performance. Copper, with its low resistance, high power efficiency, and low electromigration, is an excellent conductive metal for even smaller feature sizes. However, dry etching of copper is extremely difficult.

[0003] In related technologies, the damascene process involves first etching a dielectric layer to form trenches, then forming copper seed layers on the bottom and sidewalls of the trenches, followed by epitaxial growth of copper to fill the trenches, and finally removing excess copper through chemical mechanical polishing to form copper wires. This process is quite complex. To form a double damascene structure combining vias and trenches requires an even more complex process, such as at least two photolithography and etching processes, as well as a cleaning process. After the first etching, an organic dielectric layer needs to be filled, and an anti-reflective coating for the second photolithography process needs to be deposited, making the process flow complex. Furthermore, in related technologies, the fabrication of a double damascene structure requires at least two photolithography processes and a large number of photomasks. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0006] A substrate is provided, on which a dielectric layer is disposed;

[0007] A mask layer is formed on the dielectric layer, and the mask layer is patterned using a photolithography process to define a pattern for forming a first trench in the mask layer;

[0008] The etching equipment is set to the first mode, and the patterned mask layer is used as a mask to etch the dielectric layer to form a first trench located in the dielectric layer.

[0009] The etching equipment is switched to the second mode, and a carbon source is introduced into the reaction chamber of the etching equipment to deposit and form a carbon film layer on the sidewall and bottom of the first trench, and an inner groove is formed on the carbon film layer in the first trench, wherein the lateral dimension of the inner groove is smaller than the lateral dimension of the first trench.

[0010] The etching equipment is switched to the first mode, and the carbon film layer is used as a mask to etch the carbon film layer and the dielectric layer located below the bottom of the inner groove to form a through hole;

[0011] Remove the remaining carbon film layer.

[0012] In one embodiment,

[0013] Setting the etching equipment to a first mode or switching the etching equipment to the first mode includes:

[0014] Turn on the source power and bias power of the etching equipment to set the etching equipment to a first mode;

[0015] Switching the etching device to the second mode includes: turning on the source power of the etching device and turning off the bias power of the etching device to set the etching device to the second mode.

[0016] In one embodiment, an etching stop layer is formed between the substrate and the dielectric layer, wherein etching stops at the etching stop layer when etching the carbon film layer and the dielectric layer located below the bottom of the recess.

[0017] In one embodiment, the depth ratio of the first trench to the depth of the through hole ranges from 0.55:1 to 0.95:1.

[0018] In one embodiment, an anti-reflection layer is further formed between the dielectric layer and the mask layer. The step of setting the etching apparatus to a first mode, using the patterned mask layer as a mask, and etching the dielectric layer to form a first trench located within the dielectric layer includes:

[0019] Set the etching equipment to the first mode;

[0020] Using the mask layer as a mask, the anti-reflection layer and the dielectric layer are etched sequentially;

[0021] Etching continues until a portion of the dielectric layer is removed, then etching is stopped to form a first trench within the dielectric layer;

[0022] Remove the mask layer.

[0023] In one embodiment, the substrate has a first conductive interconnect structure.

[0024] The method further includes:

[0025] The etch stop layer at the bottom of the via is etched so that the via penetrates the etch stop layer to expose at least a portion of the first conductive interconnect structure;

[0026] A conductive material is deposited to fill the first trench and the via to form a second conductive interconnect structure.

[0027] In one embodiment, the materials of the first conductive interconnect structure and the second conductive interconnect structure include one or more of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and Al.

[0028] In some embodiments, plasma is used to remove the remaining carbon film layer.

[0029] In one embodiment, the carbon source includes at least one of CH4, CO, and CO2.

[0030] In another embodiment of this application, a semiconductor device is also provided, which is manufactured using the semiconductor device manufacturing method described above.

[0031] The semiconductor device and manufacturing method of the present application embodiment form a first trench in a first mode, then switch to a second mode to form a carbon film layer by deposition, and form an inner groove on the carbon film layer. Then switch to the first mode to etch the carbon film layer and dielectric layer below the bottom of the inner groove to form a via. After removing the carbon film layer, a double damask structure of via and trench is formed. In the present application embodiment, only one photolithography and one etching process are needed to form the double damask structure, thereby reducing the number of photomasks, simplifying the production process and production cycle, and reducing the production cost. Attached Figure Description

[0032] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0033] In the attached image:

[0034] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown;

[0035] Figures 2A-2G This diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application. Detailed Implementation

[0036] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0037] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be construed as having the meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an ideal or overly formal sense, unless expressly defined herein.

[0041] To fully understand this invention, detailed steps and structures will be set forth in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0042] In integrated circuits, metal interconnects serve as the medium for signal conduction between peripheral circuits and internal chip devices, enabling electrical connections between different components. With continuous advancements in integrated circuit manufacturing processes, device sizes are shrinking, leading to increasingly stringent requirements for device performance and stability. Aluminum, originally used for fabricating metal interconnects, is no longer suitable as an internal metal interconnect material in advanced process technologies due to its high resistivity, high electromigration, and poor filling performance. Copper, with its low resistance, high power efficiency, and low electromigration, is an excellent conductive metal for even smaller feature sizes. However, dry etching of copper is extremely difficult.

[0043] In related technologies, the damascus process is used to form copper wires. In the damascus process, a dielectric layer is first etched to form trenches, then copper seeds are filled into the trenches for epitaxial growth of copper. Finally, excess copper is removed through chemical mechanical polishing, thus forming the copper wire. The manufacturing process is relatively complex, and forming a double damask structure combining vias and trenches requires an even more complex process. Specifically, the double damask process of related technologies requires photolithography processes when forming trenches and vias. That is, after forming trenches through photolithography and etching, forming vias requires spin coating to form an organic dielectric layer (ODL), depositing an anti-reflective coating (ARC), a photoresist layer, and then photolithography processes such as photolithography. The whole process includes two photolithography processes, a large number of photomasks, and two etching and cleaning processes. After the first etching, an organic dielectric layer needs to be filled and the second photolithography anti-reflective coating needs to be deposited. The process is complex, the production cycle is long, and the cost is high. Furthermore, the photolithography of smaller vias requires more advanced and expensive photolithography machines.

[0044] Therefore, in view of the aforementioned technical problems, the present invention proposes a method for manufacturing a semiconductor device, such as... Figure 1 As shown, it mainly includes the following steps:

[0045] Step S110: Provide a substrate, on which a dielectric layer is sequentially disposed;

[0046] Step S120: A mask layer is formed on the dielectric layer, and the mask layer is patterned using a photolithography process to define a pattern for forming a predetermined first trench in the mask layer.

[0047] Step S130: Set the etching equipment to the first mode, use the patterned mask layer as a mask to etch the dielectric layer to form a first trench located in the dielectric layer;

[0048] Step S140: Switch the etching device to the second mode, introduce a carbon source into the reaction chamber of the etching device to deposit and form a carbon film layer on the sidewall and bottom of the first trench, and form an inner groove on the carbon film layer in the first trench, wherein the lateral dimension of the inner groove is smaller than the lateral dimension of the first trench.

[0049] Step S150: Switch the etching equipment to the first mode, use the carbon film layer as a mask, etch the carbon film layer and the dielectric layer located below the bottom of the inner groove and stop at the etching stop layer to form a through hole;

[0050] Step S160: Remove the remaining carbon film layer.

[0051] In this embodiment, a first trench is formed in a first mode, then the process switches to a second mode to form a carbon film layer by deposition, and an inner groove is formed on the carbon film layer. Then, the process switches to the first mode to etch the carbon film layer and dielectric layer below the bottom of the inner groove to form a through hole. After removing the carbon film layer, a double damask structure combining through holes and trenches is formed. In this embodiment, the double damask structure can be formed with only one photolithography and one etching process, thereby reducing the number of photomasks, simplifying the production process and production cycle, and reducing production costs.

[0052] Example 1

[0053] Below, for reference Figure 1 , Figures 2A to 2G The method for manufacturing the semiconductor device of the present invention will be described in detail, wherein, Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown; Figures 2A-2G The diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention.

[0054] The method for manufacturing a semiconductor device according to this application includes the following steps:

[0055] First, such as Figure 1 As shown, perform step S110, as follows: Figure 2A As shown, a substrate 200 is provided, on which an etch stop layer 201 and a dielectric layer 202 are sequentially disposed. Exemplarily, the dielectric layer 202 includes a first dielectric layer 2021, a second dielectric layer 2022, and a third dielectric layer 2023 stacked sequentially from bottom to top. The first dielectric layer 2021 and the third dielectric layer 2023 may be silicon dioxide layers deposited using tetraethoxysilane (TEOS) as a precursor. The second dielectric layer 2022 may be a low-k dielectric material. Generally, a low-k dielectric material refers to a dielectric material with a dielectric constant (k value) less than 4, such as fluorosilicone glass (FSG), silicon carbide hydroxide (SiCOH), silicon oxide, carbon-containing material, porous-like material, or similar materials. Optionally, the thickness of the second dielectric layer 2022 may be greater than the thickness of the first dielectric layer 2021 and the thickness of the second dielectric layer 2022.

[0056] For example, the etch stop layer 201 includes a barrier layer with a low dielectric constant, such as a carbon / nitrogen compound of silicon. In some embodiments, the etch stop layer is made of silicon nitride, silicon carbide, or nitrogen-doped silicon carbide.

[0057] Continue as Figure 2A As shown, an anti-reflective layer 203 is formed on the dielectric layer 202. The anti-reflective layer 203 can reduce reflection and standing wave effects during the photolithography process, thereby improving the pattern resolution. For example, the anti-reflective layer is a bottom anti-reflective coating (BARC). The anti-reflective layer includes, but is not limited to, at least one of a polymer containing chromophores (such as a polyimide derivative), silicon nitride, silicon oxynitride, and TEOS.

[0058] Continue as Figure 2A As shown, the substrate 200 has a first conductive interconnect structure 210. Exemplarily, the first conductive interconnect structure 210 includes contact holes, or it may be a double damask structure (i.e., a conductive interconnect structure consisting of through holes and trenches). The first conductive interconnect structure 210 is located within the substrate 200, and the through holes formed subsequently are located on the first conductive interconnect structure 210. The material of the first conductive interconnect structure 210 includes, but is not limited to, copper.

[0059] For example, the substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate, or it can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and can also include multilayer structures made of these semiconductor materials, etc. The semiconductor substrate can be silicon on insulator (SOI), silicon on insulator stacked (SSOI), silicon on insulator stacked (S-SiGeOI), silicon on insulator germanium (SiGeOI), and germanium on insulator (GeOI), or it can be a double-side polished wafer (DSP). The substrate 200 can also be a ceramic substrate such as alumina, a quartz or glass substrate, etc.

[0060] Continue as Figure 1 As shown, step S120 is then performed to form a mask layer on the dielectric layer and to pattern the mask layer using a photolithography process to define a pattern in the mask layer that will form a predetermined first trench.

[0061] In one example, firstly, as Figure 2A As shown, a mask layer 204 is formed on the anti-reflective layer 203. Exemplarily, the mask layer 204 can be a photoresist layer. The mask layer 204 is patterned using a photolithography process to define a pattern for forming the first trench. A corresponding photomask is required in this photolithography step.

[0062] Continue as Figure 1As shown, step S130 is then executed, in which the etching equipment is set to the first mode, and the patterned mask layer is used as a mask to etch the dielectric layer to form the first trench located in the dielectric layer.

[0063] Next, set the etching equipment to the first mode. Specifically, turn on the source power and bias power of the etching equipment to set it to the first mode. Start the etching equipment to execute the first mode, as follows: Figure 2B As shown, an etching gas, such as at least one of CF4, CHF3, O2, or Ar, is introduced into the reaction chamber. Using mask layer 204 as a mask, the anti-reflective layer 203 and the dielectric layer 202 are etched sequentially. Etching stops when a portion of the second dielectric layer 2022 has been removed, forming a first trench 205 within the dielectric layer 202. This transfers the trench pattern of the mask to the second dielectric layer 2022 and the third dielectric layer 2023. In other words, during this etching process, the etching endpoint remains in the second dielectric layer 2022, without reaching the first dielectric layer 2021. This allows the first trench 205 to penetrate the third dielectric layer 2023 and at least a portion of the second dielectric layer 2022. The bottom of the first trench 205 is located within the second dielectric layer 2022, or possibly further within the first dielectric layer 2021. Next, the mask layer 204 and the anti-reflective layer 203 are removed, as... Figure 2C As shown, a first trench 205 is formed within the dielectric layer 202. Exemplarily, the first trench 205 can be formed using dry etching.

[0064] It is worth mentioning that in the etching process, source power and bias power are control parameters of the etching equipment, which can affect the morphology, uniformity, and selectivity of the etching. Typically, source power is applied to the upper electrode (e.g., an antenna coil) to excite and maintain the plasma, using radio frequency energy to dissociate the reactive gas and generate active free radicals, ions, and electrons. Bias power is applied to the lower electrode, i.e., the semiconductor device side, using a DC self-bias voltage to accelerate ions and vertically bombard the surface of the semiconductor device to be etched, enhancing the physical sputtering effect.

[0065] By controlling the bias power, the directionality of the plasma can be enhanced, resulting in anisotropic etching and reducing lateral etching. Increasing the bias power can deepen the etching depth and steepen the sidewall angle (e.g., changing from a cone shape to a rectangle). Simultaneously, adjusting the bias power can improve loading effects; for example, uneven etching rates caused by density differences can be partially compensated for by adjusting the bias power.

[0066] Since trenches need to be etched in step S130, while generating plasma, it is also necessary to accelerate the vertical bombardment of ions to the surface to be etched, enhance the physical sputtering effect, and etch the dielectric layer to form the first trench.

[0067] Continue as Figure 1 As shown, step S140 is then executed, the etching device is switched to the second mode, and a carbon source is introduced into the reaction chamber of the etching device to deposit and form a carbon film layer on the sidewall and bottom of the first trench, and an inner groove is formed on the carbon film layer in the first trench, wherein the lateral dimension of the inner groove is smaller than the lateral dimension of the first trench.

[0068] In one example, the etching equipment is first switched to the second mode, in which the source power of the etching equipment is kept on while the bias power of the etching equipment is turned off. After the bias power is turned off, the speed at which ions vertically bombard the wafer surface is slowed down, thereby reducing the physical sputtering intensity. The ability of the etching equipment to produce by-products is utilized, thereby enabling the process to be changed from etching-based to growth of free radicals, ions, etc.

[0069] After the etching equipment is switched to the second mode, a carbon source is then introduced into the reaction chamber of the etching equipment, such as... Figure 2D As shown, a carbon film layer 206 is deposited on the sidewalls and bottom of the first trench. Exemplarily, the carbon source includes, but is not limited to, at least one of CH4, CO, and CO2. Ar is also introduced into the reaction chamber to stabilize the plasma distribution and improve the uniformity of the carbon film thickness. The introduced Ar can also serve as an inert carrier gas, isolating the reactant gases from side reactions with the chamber materials and protecting the equipment components.

[0070] Continue as Figure 2D As shown, after the carbon film layer 206 is deposited, an inner groove 207 is formed on the carbon film layer 206 in the first trench. The lateral dimension of the inner groove 207 is smaller than the lateral dimension of the first trench 205, thereby forming a through-hole structure with a smaller linewidth. The lateral dimension can refer to the dimension in the direction perpendicular to the thickness direction of the dielectric layer.

[0071] Continue as Figure 1 As shown, step S150 is then executed, switching the etching apparatus to the first mode, using the carbon film layer as a mask, etching the carbon film layer and the dielectric layer located below the bottom of the inner groove and stopping at the etching stop layer to form a via. In some examples, the depth ratio of the first trench to the via ranges from 0.55:1 to 0.95:1, for example, the depth ratio of the first trench to the via is 0.55:1, 0.7:1, or 0.95:1.

[0072] In one example, after depositing a carbon film and forming grooves on it, the grooves are used as an etching mask to etch the dielectric layer again. Therefore, firstly, the etching equipment is switched to the first mode, i.e., the source power and bias power are turned on. Then, as... Figure 2EAs shown, an etching gas, such as at least one of CF4, CHF3, and O2, is introduced into the reaction chamber. Using the groove formed on the carbon film layer 206 as an etching mask, the carbon film layer 206 and the dielectric layer 202 located below the bottom of the groove are etched and the etching stops at the etching stop layer 201, thereby transferring the via pattern to the first dielectric layer 2021 to form a via 208 penetrating the dielectric layer 202. Optionally, the etching process used in this step is anisotropic dry etching.

[0073] By switching the mode of the etching equipment described above, the two functions of etching and deposition can be switched in the etching equipment. Compared with the method of performing deposition in other dedicated deposition equipment other than the etching equipment, the method of this application does not require transferring the device between the etching equipment and the deposition equipment. This can reduce the risk of contamination (such as particles and oxidation) and the time consumption during the device transfer process, simplify the process flow and reduce costs.

[0074] Furthermore, since the size and location of the via have already been defined by the groove in step 140, there is no need to perform the photolithography process again in this step. The via can be etched directly using the etching process. Therefore, the number of photomasks required to form the double damask structure is reduced from two in related technologies to one. In addition, in this embodiment, the etching of the via does not use the small critical size (CD) via photolithography process, which reduces the requirements for the photolithography machine's capabilities and thus reduces equipment costs. Moreover, since the via photolithography process is not performed, the processes of spin-coating the organic dielectric layer and depositing the anti-reflective layer are reduced, thereby reducing the number of production processes and the production cycle, and lowering production costs.

[0075] For example, such as Figure 2D and Figure 2E As shown, the lateral dimension of the through hole 208 is smaller than the lateral dimension of the first groove.

[0076] It is worth mentioning that steps S130 to S150 can be achieved in one etching process. That is, these steps belong to several stages included in one etching process, and the whole process is completed continuously in the chamber of an etching device.

[0077] Then, continue as follows Figure 1 As shown, step S160 is performed to remove the remaining carbon film layer to obtain the desired result. Figure 2F The double damask structure 209 is shown. In some examples, the remaining carbon film layer is removed using plasma, for example, using O2 plasma. This process can also be performed within an etching apparatus, for example, by introducing oxygen into the etching apparatus and ionizing it into plasma to bombard and remove the remaining carbon film layer. Then, as... Figure 2GAs shown, at least one etching gas, such as CF4, CHF3, or N2, is introduced into the reaction chamber to etch the etch stop layer 201 at the bottom of the via 208, so that the via 208 penetrates the etch stop layer 201 and exposes at least a portion of the first conductive interconnect structure 210. This allows the subsequently formed second conductive interconnect structure to be electrically connected to the first conductive interconnect structure 210 to form a conductive path. It is worth noting that the step of etching the etch stop layer at the bottom of the via can be performed after removing the remaining carbon film layer or simultaneously with the step of removing the remaining carbon film layer. That is, after etching the remaining carbon film layer and the etch stop layer at the bottom of the via, a double damascene structure penetrating the dielectric layer and the etch stop layer is formed.

[0078] Next, conductive material is deposited in the first trench and via, filling the first trench and via to form a second conductive interconnect structure (not shown) in the double damask structure. The material of the conductive material is not particularly limited. The conductive material may include one or more of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and Al, or may also be a metallic compound. Specifically, for example, the material of the second conductive interconnect structure includes copper, thereby forming a copper interconnect in the double damask structure. Exemplarily, the etch stop layer at the bottom of the via is etched using a dry etching method.

[0079] This concludes the description of the key steps in the semiconductor device manufacturing method of the present invention. The complete semiconductor device manufacturing method may also include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0080] The semiconductor device and manufacturing method of the present application embodiment form a first trench in a first mode, then switch to a second mode to form a carbon film layer by deposition, and form an inner groove on the carbon film layer. Then, in the first mode, the carbon film layer and dielectric layer below the bottom of the inner groove are etched to form a via. After removing the carbon film layer, a double damascene structure of via and trench is formed. In the present application embodiment, only one photolithography and one etching process are required to form the double damascene structure. Compared with the related technology that uses two photolithography processes to form the double damascene structure, the solution of the present application only requires one photolithography process, thus reducing the number of photomasks, simplifying the production process and production cycle, and reducing production costs.

[0081] Example 2

[0082] This invention also provides a semiconductor device, which can be prepared by the semiconductor device manufacturing method described in Embodiment 1 above. Some details of this embodiment can be found in the preceding description of the method and will not be repeated here. Since the semiconductor device provided in this application is prepared by the semiconductor device manufacturing method described in Embodiment 1 above, the semiconductor device of this application also possesses the beneficial effects of the semiconductor device manufacturing method described in Embodiment 1 above.

[0083] Semiconductor devices can be any devices that require the fabrication of a double damascene structure, such as CMOS, MEMS devices, LDMOS devices, memory devices, etc.

[0084] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A substrate is provided, on which a dielectric layer is disposed; A mask layer is formed on the dielectric layer, and the mask layer is patterned using a photolithography process to define a pattern for forming a first trench in the mask layer; The etching equipment is set to the first mode, and the patterned mask layer is used as a mask to etch the dielectric layer to form a first trench located in the dielectric layer. The etching equipment is switched to the second mode, and a carbon source is introduced into the reaction chamber of the etching equipment to deposit and form a carbon film layer on the sidewall and bottom of the first trench, and an inner groove is formed on the carbon film layer in the first trench, wherein the lateral dimension of the inner groove is smaller than the lateral dimension of the first trench. The etching equipment is switched to the first mode, and the carbon film layer is used as a mask to etch the carbon film layer and the dielectric layer located below the bottom of the inner groove to form a through hole; Remove the remaining carbon film layer; Setting the etching device to a first mode or switching the etching device to the first mode includes: turning on the source power and bias power of the etching device to set the etching device to the first mode; switching the etching device to a second mode includes: turning on the source power of the etching device and turning off the bias power of the etching device to set the etching device to the second mode.

2. The manufacturing method as described in claim 1, characterized in that, An etching stop layer is formed between the substrate and the dielectric layer, wherein etching stops at the etching stop layer when etching the carbon film layer and the dielectric layer located below the bottom of the recess.

3. The manufacturing method as described in claim 1, characterized in that, The ratio of the depth of the first trench to the depth of the through hole ranges from 0.55:1 to 0.95:

1.

4. The manufacturing method as described in claim 1, characterized in that, An anti-reflection layer is also formed between the dielectric layer and the mask layer. The etching equipment is set to a first mode, using the patterned mask layer as a mask, to etch the dielectric layer, forming a first trench located within the dielectric layer, including: Set the etching equipment to the first mode; Using the mask layer as a mask, the anti-reflection layer and the dielectric layer are etched sequentially; Etching continues until a portion of the dielectric layer is removed, then etching is stopped to form a first trench within the dielectric layer; Remove the mask layer.

5. The manufacturing method as described in claim 2, characterized in that, The substrate has a first conductive interconnect structure. The method further includes: The etch stop layer at the bottom of the via is etched so that the via penetrates the etch stop layer to expose at least a portion of the first conductive interconnect structure; A conductive material is deposited to fill the first trench and the via to form a second conductive interconnect structure.

6. The manufacturing method as described in claim 5, characterized in that, The materials of the first conductive interconnect structure and the second conductive interconnect structure include one or more of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al.

7. The manufacturing method as described in claim 1, characterized in that, The remaining carbon film layer is removed using plasma.

8. The manufacturing method as described in claim 1, characterized in that, The carbon source includes at least one of CH4, CO, and CO2.

9. A semiconductor device, characterized in that, It is manufactured using the semiconductor device manufacturing method according to any one of claims 1 to 8.

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