Method of forming a buffer layer for low dielectric constant material layers and interconnect structure

Abstract

The application discloses a method for forming a buffer layer for a low dielectric constant material layer and an interconnection structure. The method comprises the following steps: providing a semiconductor front device structure, which has an etching stop layer on the semiconductor front device structure; depositing a dielectric thin layer on the etching stop layer; cleaning the dielectric thin layer in a spiral plasma environment by using diethyl ether; and performing the depositing step and the cleaning step according to a set number of cycles to form a buffer layer with at least one layer structure. Compared with the prior art, the application has the unexpected technical effect that a buffer layer with a low dielectric constant can be formed, so that the overall dielectric constant of the interlayer dielectric layer of the interconnection structure formed by the low dielectric constant material layer and the buffer layer is reduced, and the RC delay in the interconnection structure is improved.

Description

Technical Field

[0001] This application generally relates to the field of interconnect structure fabrication technology. More specifically, this application relates to a method for forming a buffer layer for a low dielectric constant material layer, a method for fabricating an interconnect structure, and an interconnect structure. Background Technology

[0002] In the semiconductor manufacturing field, with the development of process technology, the performance requirements for circuits at 28nm and more advanced process nodes are becoming increasingly demanding. In these advanced processes, the optimization of the back-end metal interconnect structure becomes particularly important, as it directly affects chip performance and power consumption. RC delay (Resistance-Capacitance delay) is the signal transmission delay caused by resistance (R) and capacitance (C) in a circuit. In chip design, reducing RC delay is key to improving circuit speed and reducing power consumption.

[0003] In existing technologies, to reduce RC delay, a low-k material is introduced into the interlayer dielectric layer above the etch stop layer in the back-end metal interconnect structure to mitigate the RC delay caused by the high k-value of the dielectric layer. The low-k material layer typically reduces the dielectric constant by increasing porosity through carbon doping or introducing and then extracting an organic phase. However, the low-k material layer suffers from poor adhesion to the underlying etch stop layer. To address this, a buffer layer is typically introduced between the etch stop layer and the low-k material. However, the introduced buffer layer has a higher dielectric constant, leading to an increase in the overall dielectric constant of the interlayer dielectric layer in the interconnect structure formed by the low-k material layer and the buffer layer, thus worsening the RC delay.

[0004] In view of this, there is an urgent need to provide a semiconductor structure fabrication scheme to form a buffer layer with a low dielectric constant, thereby reducing the overall dielectric constant of the interlayer dielectric layer of the interconnect structure composed of the low dielectric constant material layer and the buffer layer, and improving the RC delay in the interconnect structure. Summary of the Invention

[0005] In order to at least solve one or more of the technical problems mentioned above, this application proposes a semiconductor structure preparation scheme and a corresponding semiconductor structure in several aspects.

[0006] In a first aspect, this application provides a method for forming a buffer layer for a low dielectric constant material layer, comprising: providing a semiconductor front-end device structure having an etch barrier layer thereon; depositing a dielectric thin layer on the etch barrier layer; cleaning the dielectric thin layer with diethyl ether in a spiral plasma environment; and performing the deposition step and the cleaning step for a set number of cycles to form a buffer layer having at least one layer structure.

[0007] In some embodiments, the thickness of the dielectric thin layer deposited in a single cycle is 30 Å ± 15 Å.

[0008] In some embodiments, the deposition is performed using a PECVD process, which satisfies at least one of the following conditions: pressure of 4 torr to 8 torr; temperature of 350℃ ± 50℃; electrode spacing of 240 mils ± 120 mils; reaction gas flow rate of 1000 sccm to 12000 sccm; carrier gas flow rate of 1000 sccm to 12000 sccm; high RF power of 200 W ± 100 W; low RF power of 120 W ± 100 W; and silicon source gas flow rate of 0.3 g / min to 7 g / min.

[0009] In some embodiments, the PECVD process satisfies at least one of the following conditions: pressure of 6 torr; temperature of 350°C; electrode spacing of 240 mils; reaction gas of oxygen with a flow rate of 6000 sccm; carrier gas of helium with a flow rate of 4000 sccm; high RF power of 205 W; low RF power of 125 W; and silicon source gas of tetraethyl orthosilicate (TEOS) with a flow rate of 0.8 g / min.

[0010] In some embodiments, the cleaning with ether in a helical plasma environment meets at least one of the following conditions: time is 1s to 300s; pressure is 1 torr to 600 torr; temperature is 168℃ to 450℃; the distance between electrodes is 900mils ± 850mils; the carrier gas flow rate is 12000sccm ± 11500sccm; the ether flow rate is 1g / min to 1000g / min; the low radio frequency power of the upper helix is ​​200w ± 160w; the low radio frequency power of the side helix is ​​200w ± 160w; and the high radio frequency power of the bottom helix is ​​200w ± 150w.

[0011] In some embodiments, the cleaning with ether in a helical plasma environment meets at least one of the following conditions: time is 120 s; pressure is 37 torr; temperature is 350 °C; the distance between electrodes is 350 mils; the carrier gas is helium with a flow rate of 8000 sccm; the ether flow rate is 18 g / min; the low-frequency power of the upper helix is ​​70 W; the low-frequency power of the side helix is ​​110 W; and the high-frequency power of the bottom helix is ​​85 W.

[0012] In some embodiments, the number of cycles is set according to the desired film thickness of the buffer layer.

[0013] In some embodiments, the number of cycles is 2 to 6.

[0014] In some embodiments, the dielectric thin layer is made of silicon oxide (SiOx).

[0015] In some embodiments, the method further includes forming a low dielectric constant material layer over the buffer layer.

[0016] In some embodiments, the dielectric constant of the buffer layer is reduced by 11.8% compared to the dielectric thin layer before the cleaning is performed.

[0017] In some embodiments, the dielectric constant of the buffer layer is 3.66.

[0018] In a second aspect, this application provides a method for fabricating an interconnect structure, comprising: providing a semiconductor front-end device structure having an etch stop layer thereon; forming a buffer layer above the etch stop layer, the buffer layer being prepared using the method for forming a buffer layer for a low dielectric constant material layer as described in any embodiment of the first aspect; forming a low dielectric constant material layer above the buffer layer; forming contact vias in the etch stop layer, the buffer layer, and the low dielectric constant material layer, and filling the contact vias with a metal interconnect layer.

[0019] In a third aspect, this application provides an interconnect structure comprising: a semiconductor front-end device structure having an etch stop layer; a buffer layer disposed above the etch stop layer, the buffer layer being prepared using the method for forming a buffer layer for a low dielectric constant material layer as described in any embodiment of the first aspect; a low dielectric constant material layer disposed above the buffer layer; and a contact via disposed in the etch stop layer, the buffer layer, and the low dielectric constant material layer, the contact via being filled with a metal interconnect layer.

[0020] Compared with the prior art, the unexpected technical effect of this application is that a buffer layer with a low dielectric constant can be formed, thereby reducing the overall dielectric constant of the interlayer dielectric layer of the interconnect structure composed of the low dielectric constant material layer and the buffer layer, and improving the RC delay in the interconnect structure.

[0021] This application embodiment forms a buffer layer by first depositing a thin dielectric layer and then cleaning it with diethyl ether in a helical plasma environment, using a cyclic deposition-cleaning process. During buffer layer formation, cleaning the deposited dielectric layer with diethyl ether in a helical plasma environment reduces the number of total polarized molecules per unit volume of the dielectric layer, thereby lowering the dielectric constant. Multiple cycles of deposition-cleaning allow for the treatment of the entire buffer layer, not just its surface, resulting in a buffer layer with an even lower dielectric constant. Furthermore, diethyl ether in a helical plasma environment enhances the solubility of residual unreacted substances, and compared to a typical plasma environment with only vertical oscillations, residual soluble impurities dissolved in a helical plasma are more easily volatilized and removed by a vacuum pump. Attached Figure Description

[0022] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts, wherein:

[0023] Figure 1 An exemplary flowchart of a method for forming a buffer layer for a low dielectric constant material layer according to an embodiment of this application is shown;

[0024] Figures 2A-2E A schematic diagram of a semiconductor cross-sectional structure is shown, illustrating a method for forming a buffer layer for a low dielectric constant material layer using embodiments of this application.

[0025] Figure 3A A schematic illustration of a spiral plasma environment;

[0026] Figure 3B The mercury probe test curves of the comparative example and the embodiment are shown;

[0027] Figure 3C The absorbance-wavenumber plots for the comparative example and the embodiment are shown.

[0028] Figure 4 An exemplary flowchart of a method for fabricating an interconnect structure according to an embodiment of this application is shown;

[0029] Figures 5A-5D A schematic diagram of a semiconductor cross-sectional structure is shown, illustrating the fabrication method of the interconnect structure according to an embodiment of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] It should be understood that the terms "comprising" and "including" as used in the specification and claims of this application indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0032] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0033] It should also be understood that, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "on" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers.

[0034] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0035] This application provides a scheme for forming a buffer layer for a low dielectric constant material layer. By cleaning the deposited dielectric thin layer with diethyl ether in a helical plasma environment, the number of total polarized molecules per unit volume of the dielectric thin layer can be reduced, thereby reducing the dielectric constant of the corresponding dielectric thin layer. Through multiple cycles of deposition-cleaning, the entire formed buffer layer can be processed, rather than being limited to the surface of the buffer layer, thus forming a buffer layer with an even lower dielectric constant.

[0036] Figure 1 An exemplary flowchart of a method 100 for forming a buffer layer for a low dielectric constant material layer is shown according to an embodiment of this application.

[0037] like Figure 1 As shown, in step S110, a semiconductor front-end device structure is provided, which has an etch barrier layer. Next, in step S120, a dielectric thin layer is deposited on the etch barrier layer. In step S130, the dielectric thin layer is cleaned with diethyl ether in a helical plasma environment. Then, in step S140, the deposition and cleaning steps are performed for a set number of cycles to form a buffer layer with at least one layer structure.

[0038] based on Figure 1 The fabrication process of a buffer layer for forming a low dielectric constant material layer is described below, in conjunction with... Figures 2A-2E The schematic diagram of the semiconductor cross-sectional structure shown describes in detail an exemplary process flow of a method for forming a buffer layer for a low dielectric constant material layer using some embodiments of this application.

[0039] Figure 2A This illustration shows a schematic diagram of a semiconductor cross-sectional structure in which an etch barrier layer is formed on a semiconductor front-end device structure according to an embodiment of this application.

[0040] like Figure 2A As shown, a semiconductor front-end device structure 210 is provided, on which an etch barrier layer 220 is formed.

[0041] In the embodiments of this application, the semiconductor front-end device structure 210 is a device formed before the back-end process (BEOL), and the specific structure of the front-end device is not limited here.

[0042] In one embodiment of this application, the semiconductor front-end device structure 210 may include a semiconductor substrate and electronic components disposed on the semiconductor substrate. Specifically, the semiconductor substrate may be made of at least one of the following materials: silicon, ceramic, sapphire, silicon carbide, gallium nitride, aluminum nitride, indium nitride, or silicon germanium, etc. The semiconductor substrate may be a single-layer or multi-layer semiconductor structure made of these materials, and the specific structure may be selected according to requirements. The electronic components disposed on the semiconductor substrate may be transistors, diodes, resistors, capacitors, inductors, etc.

[0043] In the embodiments of this application, the etch stop layer 220 can be a single layer or multiple layers. This etch stop layer serves two purposes: firstly, it acts as an etch stop point for subsequent etching of the corresponding semiconductor layer above it to form contact vias; secondly, after the metal interconnect layer is formed, it prevents material from diffusing from the metal interconnect layer into the corresponding semiconductor layer. The materials used for the etch stop layer 220 include one or more of polysilicon, alumina, amorphous silicon, tetraethyl orthosilicate, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxide, and boron nitride silicon carbide. The etch stop layer 220 can be formed using processes such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The embodiments of this application do not limit the specific structure and formation method of the etch stop layer.

[0044] Figure 2B This illustration shows a schematic diagram of a semiconductor cross-sectional structure in which a dielectric thin layer is deposited on an etch barrier layer, according to an embodiment of this application.

[0045] like Figure 2B As shown, a dielectric thin layer 230 is deposited on the aforementioned etch barrier layer 220. Specifically, the dielectric thin layer 230 is made of silicon oxide (SiOx), where x ranges from 1 to 2.

[0046] In the embodiments of this application, the thickness of the dielectric thin layer 230 is 30ű15Å. "30ű15Å" here means that the thickness of the dielectric thin layer 230 can be between 15Å and 45Å. For example, it can be 15Å, 20Å, 25Å, 30Å, 35Å, 40Å, 45Å, etc. Of course, it can also be other values ​​in the range of 15Å to 45Å, which are not limited here.

[0047] In the embodiments of this application, a PECVD (Plasma-Enhanced Chemical Vapor Deposition) process can be used to deposit a dielectric thin film 230. PECVD is a technique for depositing thin films on a substrate by utilizing plasma to enhance the chemical reaction between the gaseous precursor and the substrate. The basic structure of a PECVD device includes a vacuum and pressure control system, a deposition system, a gas and flow control system, etc. In the PECVD process, plasma is generated by applying radio frequency (RF) power between two electrodes. This process forms a plasma containing ions, electrons, and excited neutral atoms in the chamber. These active materials then react with the precursor gas to form a solid thin film on the substrate.

[0048] During the deposition of the dielectric thin layer 230 using PECVD, a semiconductor structure including a semiconductor front-end device structure 210 and an etch barrier layer 220 is placed in a chamber. First, a reactive gas, a carrier gas, and a silicon source gas are introduced into the chamber. Then, radio frequency power is applied to the electrodes to generate plasma within the chamber. This plasma reacts with the reactive gas, forming the dielectric thin layer 230 above the etch barrier layer 220. After the dielectric thin layer 230 is formed, the introduction of the reactive gas and silicon source gas into the chamber is stopped, and the application of radio frequency power to the electrodes is also stopped. Simultaneously, a carrier gas can be continuously introduced to remove some of the impurities formed in the chamber.

[0049] During the deposition of a dielectric thin film 230 using the PECVD process, parameters such as pressure, temperature, electrode spacing, composition and flow rate of the reactant gas, composition and flow rate of the carrier gas, high RF power, low RF power, composition and flow rate of the silicon source gas can be set. These parameters can affect the quality and characteristics of the deposited thin film.

[0050] Specifically, the pressure used is 4 torr to 8 torr, exemplarily 4 torr, 5 torr, 6 torr, 7 torr, 8 torr, etc., and of course, other values ​​within the above range are also possible, without limitation. The pressure in the chamber affects the mean free path and deposition rate of the reactants. Different pressures can alter the plasma characteristics and thin film growth kinetics.

[0051] Specifically, the temperature is 350℃±50℃. "350℃±50℃" here means that the corresponding temperature value can be between 300℃ and 400℃, for example, 300℃, 350℃, 400℃, etc., and of course, other values ​​within the range of 300℃~400℃ are also possible, without limitation. The temperature of the substrate affects the surface migration rate of the reactants and the crystallinity of the deposited film; therefore, temperature control is crucial for the quality and properties of the film.

[0052] Specifically, the spacing between the electrodes is 240 mils ± 120 mils. "240 mils ± 120 mils" here means that the corresponding electrode spacing can be between 120 mils and 360 mils, exemplarily 120 mils, 150 mils, 200 mils, 240 mils, 250 mils, 300 mils, 330 mils, 360 mils, etc., and of course, other values ​​within the range of 120 mils to 360 mils are also possible and are not limited here. The choice of electrode spacing affects the plasma density and uniformity, thereby affecting the film deposition rate, deposition uniformity, etc.

[0053] Specifically, the reactant gas can be oxygen, etc., and the flow rate of the reactant gas is 1000 sccm to 12000 sccm. Examples include 1000 sccm, 2000 sccm, 3000 sccm, 4000 sccm, 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm, 10000 sccm, 11000 sccm, and 12000 sccm, etc. Of course, other values ​​within the above range are also possible and are not limited here. The reactant gas is also called the precursor gas. The type and proportion of the selected precursor gas will determine the chemical composition and physical properties of the deposited film. The flow rate of the precursor gas affects the composition and properties of the deposited film. Adjusting the flow rate can affect the growth rate and uniformity of the film.

[0054] Specifically, the carrier gas can be an inert gas including He and Ar, with a flow rate of 1000 sccm to 12000 sccm. Examples of flow rates include 1000 sccm, 2000 sccm, 3000 sccm, 4000 sccm, 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm, 10000 sccm, 11000 sccm, and 12000 sccm, and other values ​​within the aforementioned range are also possible and are not limited here. Due to their stable chemical properties, inert gases also act as protective gases, preventing chemical reactions or oxidation during the deposition process. Inert gases can dilute the reactant gases, adjust the plasma characteristics and reaction atmosphere, thereby affecting the film growth rate and properties. For example, by adjusting the inert gas flow rate, the plasma density and reaction conditions can be changed, thus affecting the film deposition rate and quality.

[0055] Specifically, the high RF power is 200W±100W. "200W±100W" here means that the corresponding high RF power can be between 100W and 300W. For example, it can be 100W, 200W, 250W, 300W, etc. Of course, it can also be other values ​​in the range of 100W to 300W, which are not limited here.

[0056] Specifically, the low RF power is 120W±100W. "120W±100W" here means that the corresponding high and low RF power can be between 20W and 320W. Examples include 20W, 40W, 75W, 125W, 170W, 200W, 300W, 320W, etc. Of course, other values ​​in the range of 20W to 320W are also possible and are not limited here.

[0057] In PECVD processes, applying different radio frequency (RF) powers to the upper and lower electrodes allows for more precise control of plasma characteristics and the thin film deposition process. Typically, the upper electrode (also known as the RF electrode or upper plate) generates the plasma; applying high RF power helps control the plasma density and energy, dissociating the precursor and thus affecting the uniformity and quality of the thin film. The lower electrode (also known as the wafer electrode or lower plate) is in direct contact with the substrate; applying low RF power accelerates the plasma, increasing the bombardment effect, enhancing substrate reactivity, and promoting thin film nucleation and growth. By independently adjusting the RF power of the upper and lower electrodes, fine control over the plasma and thin film growth process can be achieved.

[0058] Specifically, in the PECVD deposition process, the silicon source gas decomposes under the action of plasma, releasing silicon atoms that react with other reactive gases (such as oxygen O2) to form a dielectric thin layer, which is silicon oxide. Different silicon source gases, due to their different chemical properties and reactivity, will affect the growth rate, composition, and electrical properties of the thin film. In some embodiments, the silicon source gas (such as tetraethyl orthosilicate, trimethylsilane, tetramethylsilane, octamethylcyclotetrasiloxane, bis(tert-butylamino)silane, tris(dimethylamino)silane, tetra(dimethylamino)silane, etc.) can be tetraethyl orthosilicate (TEOS). The flow rate or velocity of the silicon source gas directly affects the gas distribution and concentration in the reaction chamber, thereby affecting the growth rate and uniformity of the thin film. In some embodiments, the flow rate of the silicon source gas is 0.3 g / min to 7 g / min, and can be exemplarily 0.3 g / min, 0.5 g / min, 0.8 g / min, 3 g / min, 3.6 g / min, 5 g / min, 6 g / min, 7 g / min, etc. Of course, other values ​​within the above range are also possible, and are not limited here.

[0059] In the preferred embodiment of the deposition of dielectric thin layer 230 using PECVD process in this application, the pressure is 6 torr; the temperature is 350°C; the spacing between electrodes is 240 mils; the reaction gas is oxygen with a flow rate of 6000 sccm; the carrier gas is helium with a flow rate of 4000 sccm; the high RF power is 205 W; the low RF power is 125 W; and the silicon source gas is tetraethyl orthosilicate (TEOS) with a flow rate of 0.8 g / min.

[0060] Figure 2C This illustration shows a schematic diagram of a semiconductor cross-sectional structure of a dielectric thin layer cleaned with diethyl ether in a spiral plasma environment, according to an embodiment of this application.

[0061] like Figure 2CAs shown, the thin media layer 230 is cleaned with ether in a spiral plasma environment 240 to dissolve and remove impurities remaining after PECVD deposition.

[0062] Plasma cleaning technology can effectively remove organic contaminants and inorganic residues from the surface of dielectric thin layers through physical bombardment and chemical reactions. At the same time, it can improve the dielectric properties of the dielectric layer and reduce its dielectric constant through surface modification. By increasing the porosity of the material, the density of the material can be reduced, thereby reducing the intermolecular interactions and lowering the dielectric constant.

[0063] Figure 3A The diagram schematically illustrates a helical plasma environment. As can be seen from the figure, in addition to upper coils and lower electrodes in the upper and lower parts of the chamber, the plasma device also features helical side coils surrounding the side walls of the chamber. Helical coil plasma devices can achieve high-density plasma generation and enable uniformity across material surfaces, including the interiors of hard-to-reach microstructures.

[0064] Specifically, the residual impurities include unreacted substances deposited by PECVD. Because ether has enhanced solubility for residual impurities in a helical plasma environment, and because the helical plasma environment oscillates not only vertically but also laterally compared to a typical plasma environment with only vertical oscillations, the residual impurities dissolved and precipitated in the helical plasma environment are more easily volatilized and removed by a vacuum pump. Therefore, cleaning the dielectric film 230 with ether in a helical plasma environment 240 can increase the removal efficiency of residual impurities in the dielectric film 230 after PECVD deposition.

[0065] Cleaning the dielectric thin layer 230 with diethyl ether under a spiral plasma environment 240 increased the removal efficiency of residual impurities in the dielectric thin layer 230 after PECVD deposition, resulting in a decrease in the total number of polarized molecules per unit volume of the dielectric thin layer 230. The Clausius-Mossotti equation is an equation describing the dielectric properties of a material, relating its dielectric constant (or relative permittivity) to the polarization properties of its molecules. The general form of the Clausius-Mossotti equation is: Where K is the dielectric constant of the medium, and N is the total number of polarized molecules per unit volume. The total polarizability per unit volume. Let be the vacuum dielectric constant. According to the Clausius-Mosotti equation, the dielectric constant of a medium is directly proportional to the total number of polarized molecules per unit volume; a decrease in the total number of polarized molecules per unit volume corresponds to a decrease in the dielectric constant of the medium. Therefore, cleaning the dielectric thin layer 230 with diethyl ether in a helical plasma environment 240 can reduce the dielectric constant of the dielectric thin layer 230.

[0066] In the embodiments of this application, the cleaning of the dielectric thin layer 230 using diethyl ether in a helical plasma environment 240 can be performed in the same chamber or a different chamber as the process of depositing the dielectric thin layer 230 using a PECVD process. During the cleaning of the dielectric thin layer 230 using diethyl ether in the helical plasma environment 240, carrier gas and diethyl ether are introduced into the chamber containing the semiconductor device to be processed (including the semiconductor front-end device structure 210, the etch barrier layer 220, and the dielectric thin layer 230). Low RF power is applied to the upper coil, low RF power to the side coil, and high RF power to the bottom electrode, respectively. After cleaning the dielectric thin layer 230, the introduction of diethyl ether into the chamber is stopped, and the application of RF power to each coil or electrode is stopped. Simultaneously, carrier gas is continuously introduced to remove residual impurities from the dielectric thin layer 230.

[0067] In the embodiments of this application, during the cleaning of the dielectric thin layer 230 with diethyl ether in a helical plasma environment 240, the cleaning time, pressure, temperature, spacing between electrodes, composition of the carrier gas, flow rate of the carrier gas, flow rate of diethyl ether, low radio frequency power of the upper helix, low radio frequency power of the side helix, and high radio frequency power of the bottom helix can be set. These parameters can affect the treatment effect on the deposited thin film.

[0068] Specifically, the cleaning time is between 1 second and 300 seconds, and can be exemplified as 1 second, 100 seconds, 120 seconds, 150 seconds, 200 seconds, 300 seconds, etc., or other values ​​within the above range, without limitation. If the cleaning time is too short, contaminants on the film surface may not be effectively removed, resulting in incomplete cleaning. This may affect the surface properties of the film. Conversely, if the cleaning time is too long, it may lead to over-cleaning, which may damage the structure of the film surface.

[0069] Specifically, the pressure used is 1 torr to 600 torr, for example it can be 1 torr, 37 torr, 100 torr, 200 torr, 300 torr, 400 torr, 500 torr, 600 torr, etc. Of course, it can also be other values ​​within the above range, which are not limited here.

[0070] Specifically, the temperature used is 168℃~450℃, which can be 168℃, 200℃, 250℃, 300℃, 350℃, 400℃, 450℃, etc., and of course, other values ​​within the above range are also possible, which are not limited here.

[0071] Specifically, the spacing between the electrodes is 900 mils ± 850 mils. "900 mils ± 850 mils" here means that the spacing between the electrodes can be between 50 mils and 1750 mils. Examples include 50 mils, 350 mils, 900 mils, 1200 mils, 1400 mils, 1750 mils, etc. Of course, other values ​​within the range of 50 mils to 1750 mils are also possible and are not limited here.

[0072] Specifically, the carrier gas can be an inert gas including He, Ar, etc., and the flow rate of the carrier gas is 12000sccm±11500sccm. "12000sccm±11500sccm" means that the flow rate of the carrier gas can be between 500sccm and 23500sccm. Examples include 500sccm, 5000sccm, 8000sccm, 12000sccm, 20000sccm, 23500sccm, etc. Of course, it can also be other values ​​in the range of 500sccm to 23500sccm, which are not limited here.

[0073] Specifically, the ether flow rate is 1 g / min to 1000 g / min, and can be 1 g / min, 18 g / min, 500 g / min, 800 g / min, 1000 g / min, etc., for example. Of course, it can also be other values ​​within the above range, which are not limited here.

[0074] Specifically, the low RF power of the upper spiral is 200W±160W. "200W±160W" here means that the low RF power of the upper spiral can be between 40W and 360W. For example, it can be 40W, 70W, 200W, 300W, 360W, etc. Of course, it can also be other values ​​in the range of 40W to 360W, which are not limited here.

[0075] Specifically, the side-spiral low RF power is 200W±160W. "200W±160W" here means that the side-spiral low RF power can be between 40W and 360W. For example, it can be 40W, 110W, 200W, 300W, 360W, etc. Of course, it can also be other values ​​in the range of 40W to 360W, which are not limited here.

[0076] Specifically, the bottom high RF power is 200W±150W. "200W±150W" here means that the bottom high RF power can be between 50W and 350W. For example, it can be 50W, 85W, 200W, 300W, 350W, etc. Of course, it can also be other values ​​in the range of 50W to 350W, which are not limited here.

[0077] In the preferred embodiment of this application, in which the dielectric thin layer 230 is cleaned with ether in a helical plasma environment 240, the cleaning time is 120 s; the pressure is 37 torr; the temperature is 350 °C; the spacing between the electrodes is 350 mils; the carrier gas is helium with a flow rate of 8000 sccm; the ether flow rate is 18 g / min; the low-frequency power of the upper helix is ​​70 W; the low-frequency power of the side helix is ​​110 W; and the high-frequency power of the bottom helix is ​​85 W.

[0078] Figure 2D A schematic diagram of the semiconductor cross-sectional structure after multiple cycles of deposition-cleaning processing according to an embodiment of this application is shown.

[0079] like Figure 2D As shown, the deposition and cleaning steps are performed according to the set number of cycles to form a buffer layer 250. Specifically, the buffer layer 250 has at least one layer; when the number of cycles is one, the buffer layer 250 is one layer; when the number of cycles is multiple, the buffer layer 250 is multiple layers.

[0080] In the embodiments of this application, the number of cycles can be set according to the desired film thickness of the final buffer layer 250. Specifically, the number of cycles is 1 to 6 times, preferably 2 to 6 times. Since the thickness of the dielectric thin layer 230 is 30 Å ± 15 Å, the thickness of the final buffer layer 250 is the product of the thickness of the dielectric thin layer 230 and the number of cycles.

[0081] In one embodiment of this application, after the buffer layer 250 is formed, a low-dielectric-constant material layer is formed above the buffer layer 250, such that the buffer layer 250 and the low-dielectric-constant (low-K) material layer constitute an interlayer dielectric layer of the interconnect structure.

[0082] Figure 2E A schematic diagram of a semiconductor cross-sectional structure forming a low dielectric constant material layer according to an embodiment of this application is shown.

[0083] like Figure 2EAs shown, a low dielectric constant material layer 260 is formed on the buffer layer 250. Specifically, the low dielectric constant material layer 260 can be formed by PECVD (Plasma-Enhanced Chemical Vapor Deposition) or Chemical Vapor Deposition (CVD) processes.

[0084] Specifically, the low dielectric constant material layer 260 refers to a class of materials with a relatively low dielectric constant k (lower than silicon dioxide, whose dielectric constant k = 3.9). For example, it may include fluorine-doped quartz glass, porous materials, fluorine-doped polymers, inorganic-organic mixtures, porous polymers, etc.

[0085] Therefore, through the above process steps, a buffer layer with one or more layers can be obtained. This buffer layer can be used in conjunction with a low dielectric constant material layer that has poor adhesion to the etch barrier layer, thereby further reducing the dielectric constant of the overall dielectric layer.

[0086] The applicant will test and compare the buffer layer 250 prepared according to the embodiments of this application with the dielectric thin layer 230 prepared by conventional methods (i.e., without cleaning treatment) to more clearly demonstrate the technical effects of the embodiments of this application.

[0087] Figure 3B The mercury probe test curves for the comparative example and the embodiment are shown.

[0088] like Figure 3B As shown, T1-T6 correspond to dielectric thin layers prepared by different methods. T1 is a dielectric thin layer deposited by PECVD without any post-treatment; T6 is a dielectric thin layer prepared using the process conditions of the preferred embodiment of this application; T2-T5 are dielectric thin layers processed using the process conditions provided in the embodiments of this application with time splits of 24-96s respectively (Note: Results are not shown for conditions exceeding 120s because the K value did not continue to decrease). Each dielectric thin layer was tested using a mercury probe. Figure 3B It can be seen that the dielectric constant K of the dielectric thin layer corresponding to T1 is approximately 4.15, and the dielectric constant K of the dielectric thin layer corresponding to T6 is 3.66. Therefore, the dielectric constant of the dielectric thin layer (i.e., the buffer layer) prepared according to the embodiments of this application is reduced by approximately 11.8% compared to the dielectric thin layer before cleaning.

[0089] Figure 3C Absorption rate-wavenumber plots for the comparative and embodiment examples are shown.

[0090] like Figure 3CAs shown, the dielectric thin layer before cleaning and the buffer layer prepared according to the embodiments of this application were analyzed by Fourier transform infrared absorption spectroscopy (FTIR), respectively, and the absorbance-wavenumber curves corresponding to the dielectric thin layer and the buffer layer were obtained. At a wavenumber of 1242, the peak value corresponding to the CH polar group of Si is shown. Figure 3C It can be seen that at a wavenumber of 1242, the peak value corresponding to the dielectric thin layer before cleaning is higher than the peak value corresponding to the buffer layer prepared in this embodiment. Therefore, compared with the dielectric thin layer before cleaning, the peak intensity of the CH polar group in the buffer layer prepared in this embodiment is reduced, that is, the number of polarized molecules is reduced, thus confirming that the dielectric constant of the buffer layer prepared in this embodiment is reduced compared with the dielectric thin layer before cleaning.

[0091] In summary, compared with the prior art, the unexpected technical effect of this application is that a buffer layer with a low dielectric constant can be formed, thereby reducing the overall dielectric constant of the interlayer dielectric layer of the interconnect structure composed of the low dielectric constant material layer and the buffer layer, and improving the RC delay in the interconnect structure.

[0092] This application embodiment forms a buffer layer by depositing a dielectric thin layer using a PECVD process and then cleaning the dielectric thin layer with diethyl ether in a helical plasma environment through a cyclic deposition-cleaning process. During the formation of the buffer layer, cleaning the deposited dielectric thin layer with diethyl ether in a helical plasma environment reduces the number of total polarized molecules per unit volume of the dielectric thin layer, thereby lowering the dielectric constant of the corresponding dielectric thin layer. Through multiple cycles of deposition-cleaning, the entire formed buffer layer can be treated, rather than just the surface. Therefore, this cyclic processing mode can form a buffer layer with a lower dielectric constant. Furthermore, diethyl ether in a helical plasma environment has enhanced solubility for residual unreacted substances, and compared to a typical plasma environment with only vertical oscillations, residual soluble impurities dissolved in a helical plasma are more easily volatilized and removed by a vacuum pump.

[0093] This application also provides a method for fabricating an interconnect structure, which is described below in conjunction with... Figure 4 The method for fabricating the interconnect structure according to the embodiments of this application is described in detail.

[0094] Figure 4 An exemplary flowchart of a method 400 for fabricating an interconnect structure according to an embodiment of this application is shown.

[0095] like Figure 4As shown, in step S410, a semiconductor front-end device structure is provided, which has an etch stop layer. Next, in step S420, a buffer layer is formed over the etch stop layer, wherein the buffer layer is prepared using the method 100 for forming a buffer layer for a low-dielectric-constant material layer according to an embodiment of this application. In step S430, a low-dielectric-constant material layer is formed over the buffer layer. Then, in step S440, contact vias are formed in the etch stop layer, the buffer layer, and the low-dielectric-constant material layer, and metal interconnect layers are filled into the contact vias.

[0096] based on Figure 4 The fabrication process of the interconnect structure is described below, in conjunction with... Figures 5A-5D The schematic diagram of the semiconductor cross-sectional structure shown describes in detail an exemplary process flow of the fabrication method of the interconnect structure using some embodiments of this application.

[0097] Figure 5A A schematic diagram of a semiconductor cross-sectional structure forming a contact via according to an embodiment of this application is shown.

[0098] like Figure 5A As shown, a semiconductor front-end device structure 510 is provided, an etch barrier layer 520 is formed on the semiconductor front-end device structure 510, a buffer layer 530 is formed above the etch barrier layer 520, a low dielectric constant material layer 540 is formed above the buffer layer 530, and then a contact via 550 is formed in the etch barrier layer 520, the buffer layer 530 and the low dielectric constant material layer 540.

[0099] Specifically, the semiconductor front-end device structure 510, the etch barrier layer 520, the buffer layer 530, and the low dielectric constant material layer 540 are bonded to the front end. Figures 2A-2E The described structure and preparation process can be the same, so they will not be repeated here.

[0100] Since the buffer layer 530 is prepared using the method 100 for forming a buffer layer for a low dielectric constant material layer according to the embodiments of this application, it has a low dielectric constant. Therefore, the overall dielectric constant of the interlayer dielectric layer of the interconnect structure composed of the buffer layer 530 and the low dielectric constant material layer 540 is low, which can improve the RC delay in the interconnect structure.

[0101] Specifically, the contact via 550 is mainly fabricated using photolithography and can be formed using various known processes; the embodiments of this application are not limited in this respect. For example, the fabrication process of the contact via 550 includes: coating photoresist on a low dielectric constant material layer 540; selectively exposing the photoresist using an exposure machine; developing to remove the exposed or unexposed portions of the photoresist; etching or depositing patterns in the exposed areas; removing the remaining photoresist; and continuing to form the desired contact via in the etch barrier layer 520, buffer layer 530, and low dielectric constant material layer 540 using dry etching or wet etching.

[0102] Specifically, the bottom of the contact via 550 is flush with the bottom of the etch barrier layer 520.

[0103] Figure 5B A schematic diagram of a semiconductor cross-sectional structure forming a diffusion barrier layer according to an embodiment of this application is shown.

[0104] like Figure 5B As shown, a diffusion barrier layer 560 is deposited on the inner wall of the contact via 550. Specifically, the diffusion barrier layer 560 is used to prevent metal atoms in the subsequently filled metal interconnect layers from diffusing into the etch barrier layer 520, buffer layer 530, and low dielectric constant material layer 540, causing a short circuit in the device. The material used for the diffusion barrier layer 560 can be selected according to the material of the subsequently deposited metal interconnect layers to allow the subsequently deposited metal interconnect layers to adhere better to the diffusion barrier layer 560. The materials used for the diffusion barrier layer 560 include, but are not limited to, at least one of titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN).

[0105] Figure 5C A schematic diagram of a semiconductor cross-sectional structure of a filled metal interconnect layer according to an embodiment of this application is shown.

[0106] like Figure 5C As shown, a metal interconnect layer 570 is deposited above the diffusion barrier layer 560, such that the metal interconnect layer 570 fills the remaining area of ​​the contact via. Specifically, the metal interconnect layer 570 can be made of copper. Copper can be filled into the remaining area of ​​the contact via by a copper plating process, and then excess copper can be removed by a chemical mechanical polishing (CMP) process to form an interconnect structure with a metal interconnect layer.

[0107] In the embodiments of this application, the metal interconnect layer in the interconnect structure can be a single layer or multiple layers. When the metal interconnect layer in the fabricated interconnect structure is multiple layers, in Figure 5C The semiconductor structure shown is again fabricated using interconnect structure fabrication method 400 to prepare the metal interconnect layers of other layers.

[0108] Figure 5DA schematic diagram of a semiconductor cross-sectional structure forming a three-layer metal interconnect layer according to an embodiment of this application is shown.

[0109] like Figure 5D As mentioned above, during the fabrication of the three-layer metal interconnect layer, in Figure 5C A second semiconductor structure 580 and a third semiconductor structure 590 are fabricated on the semiconductor structure shown. Both the second semiconductor structure 580 and the third semiconductor structure 590 include an etch stop layer, a buffer layer, a low-dielectric-constant material layer, a contact via, a diffusion barrier layer, and a metal interconnect layer. The etch stop layer, buffer layer, low-dielectric-constant material layer, contact via, diffusion barrier layer, and metal interconnect layer are identical to those of the aforementioned etch stop layer 520, buffer layer 530, low-dielectric-constant material layer 540, contact via 550, diffusion barrier layer 560, and metal interconnect layer 570.

[0110] Specifically, the diffusion barrier layer at the bottom of the contact via in the second interconnect structure 580 contacts the aforementioned metal interconnect layer 570, and the diffusion barrier layer at the bottom of the contact via in the third metal interconnect layer 590 contacts the metal interconnect layer in the second interconnect structure 580.

[0111] This application also provides an interconnect structure, which can be prepared using the interconnect structure preparation method 400 provided in this application. The specific structure of this interconnect structure can be found in [reference needed]. Figures 5A-5D Specifically, the interconnect structure may include: a semiconductor front-end device structure having an etch stop layer; a buffer layer disposed above the etch stop layer, the buffer layer being prepared using the method 100 for forming a buffer layer for a low dielectric constant material layer according to the embodiments of this application; a low dielectric constant material layer disposed above the buffer layer; and a contact via disposed in the etch stop layer, the buffer layer, and the low dielectric constant material layer, the contact via being filled with a metal interconnect layer.

[0112] In one embodiment of this application, a diffusion barrier layer is deposited inside the aforementioned contact via, and a metal interconnect layer fills the remaining area of ​​the contact via.

[0113] In the embodiments of this application, the metal interconnect layer in the interconnect structure may be a single layer or multiple layers.

[0114] While numerous embodiments of this application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will arise for those skilled in the art without departing from the spirit and intent of this application. It should be understood that various alternatives to the embodiments of this application described herein may be employed in the practice of this application. The appended claims are intended to define the scope of protection of this application and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for forming a buffer layer for a low dielectric constant material layer, characterized in that, include: A semiconductor front-end device structure is provided, wherein the semiconductor front-end device structure has an etch barrier layer; A dielectric thin layer is deposited on the etching barrier layer, wherein the dielectric thin layer is made of silicon oxide (SiOx). The dielectric thin layer is cleaned with diethyl ether in a helical plasma environment to dissolve and remove residual impurities after deposition; the plasma device in the helical plasma environment has an upper coil in the upper part, a lower electrode in the lower part, and helical side coils surrounding the side walls; and The deposition and cleaning steps are performed according to the set number of cycles to form a buffer layer with at least two layers. A low dielectric constant material layer is formed above the buffer layer so that the buffer layer and the low dielectric constant material layer form an interlayer dielectric layer for interconnection.

2. The method according to claim 1, characterized in that, The thickness of the medium layer deposited in a single cycle is 30 Å ± 15 Å.

3. The method according to any one of claims 1-2, characterized in that, The cleaning with diethyl ether in a spiral plasma environment shall meet at least one of the following conditions: The duration ranges from 1 second to 300 seconds. Pressure ranges from 1 torr to 600 torr; The temperature ranges from 168℃ to 450℃. The spacing between the electrodes is 900 mils ± 850 mils; The carrier gas flow rate is 12000 sccm ± 11500 sccm; The flow rate of diethyl ether is 1 g / min to 1000 g / min; The upper spiral has a low-frequency power of 200W ± 160W; The side-spiral low-RF power is 200W±160W; The bottom high-frequency power is 200W±150W.

4. The method according to claim 3, characterized in that, The cleaning with diethyl ether in a spiral plasma environment shall meet at least one of the following conditions: The time is 120 seconds; The pressure is 37 torr; The temperature is 350℃; The spacing between the electrodes is 350 mils; The carrier gas is helium, and the helium flow rate is 8000 sccm; The ether flow rate is 18 g / min; The upper spiral has a low-frequency power of 70W; The side-spiral low-RF power is 110W; The bottom high-frequency power is 85W.

5. The method according to claim 1, characterized in that, The number of cycles is set according to the desired film thickness of the buffer layer.

6. The method according to claim 5, characterized in that, The number of cycles is 2 to 6.

7. A method for fabricating an interconnect structure, characterized in that, include: A semiconductor front-end device structure is provided, wherein the semiconductor front-end device structure has an etch barrier layer; A buffer layer is formed above the etching barrier layer, and the buffer layer is prepared by the preparation method according to any one of claims 1-6; A low dielectric constant material layer is formed above the buffer layer; Contact vias are formed in the etch barrier layer, the buffer layer, and the low dielectric constant material layer, and metal interconnect layers are filled in the contact vias.

8. An interconnection structure, characterized in that, include: A semiconductor front-end device structure, wherein the semiconductor front-end device structure has an etch barrier layer; A buffer layer is disposed above the etching barrier layer, and the buffer layer is prepared by the preparation method according to any one of claims 1-6; A low dielectric constant material layer is disposed above the buffer layer; A contact via is disposed in the etch barrier layer, the buffer layer and the low dielectric constant material layer, and the contact via is filled with a metal interconnect layer.

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