A metal interconnection method, a semiconductor device manufacturing method, and a semiconductor device

Abstract

The embodiment of the present application discloses a metal interconnection method, a semiconductor device preparation method and a semiconductor device. The technical scheme provided by the embodiment of the present application etches a first preset pattern on an optical functional layer, deposits a first metal layer and a dielectric layer on the optical functional layer with the first preset pattern etched, etches a second preset pattern on the first metal layer and the dielectric layer, and deposits a second metal layer on the first metal layer and the dielectric layer with the second preset pattern etched, so that the second metal layer is interconnected with the first metal layer, the remaining thickness of the first metal layer does not need to be controlled, the metal layer is not used as an etching stop layer, the remaining thickness of the first metal layer is not difficult to control due to a low etching selection ratio, the performance of the device is not affected, and the metal layer interconnection effect can be effectively improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and in particular to a metal interconnection method, a semiconductor device preparation method, and a semiconductor device. BACKGROUND

[0002] With the development of technology, people have put forward higher and higher requirements for devices. The manufacture of chips cannot be separated from processes such as thin film deposition, photolithography, and etching to form a series of device units to provide different device functions. In this process, device wiring layout is controlled by photolithography and etching, and thin film deposition fills the dielectric layer and metal.

[0003] At present, etching control methods include time-based control, optical emission spectrum (OES) control, laser interference method, mass spectrometry method, and the like to control etching stop and thus obtain an ideal profile. In the etching process, etching selectivity is particularly important. If the etching selectivity is high, the etching depth and the stop layer are easier to control, and a better metal layer interconnection effect can be achieved. However, in actual production processes, the metal layer is used as an etching stop layer, which makes it difficult to control the etching selectivity and accurately control the etching precision, and the metal layer interconnection effect is poor. SUMMARY

[0004] Embodiments of the present application provide a metal interconnection method, a semiconductor device preparation method, and a semiconductor device to solve the technical problem in the related art that the metal layer is used as an etching stop layer, which makes it difficult to control the etching selectivity and accurately control the etching precision, and the metal layer interconnection effect is poor. The metal layer as an etching stop layer can be avoided, and the metal layer interconnection effect can be improved.

[0005] In a first aspect, embodiments of the present application provide a metal interconnection method, comprising:

[0006] etching a first preset pattern on an optical functional layer;

[0007] depositing a first metal layer and a dielectric layer on the optical functional layer on which the first preset pattern is etched;

[0008] etching a second preset pattern on the first metal layer and the dielectric layer;

[0009] depositing a second metal layer on the first metal layer and the dielectric layer on which the second preset pattern is etched, wherein the second metal layer is interconnected with the first metal layer.

[0010] Further, after the depositing a second metal layer on the first metal layer and the dielectric layer on which the second preset pattern is etched, the method further comprises:

[0011] etching a third preset pattern on the second metal layer.

[0012] Further, the hollowed-out position of the second preset pattern penetrates the first metal layer and the medium layer.

[0013] Further, the first metal layer comprises one or more of a combination of a chromium-silicon metal layer, a tantalum nitride metal layer, a nickel-chromium alloy metal layer, and a titanium nitride metal layer.

[0014] Further, the medium layer is a non-metallic medium layer.

[0015] Further, the non-metallic medium layer is a silicon nitride medium layer.

[0016] Further, the second metal layer is a titanium nitride metal layer, or a combined metal layer formed by titanium nitride and a preset metal, wherein the preset metal comprises one or more of a combination of titanium metal, aluminum metal, and tungsten metal.

[0017] Further, the optical functional layer is a nitrogen-doped silicon carbide layer.

[0018] In a second aspect, the embodiments of the present application provide a semiconductor device preparation method, comprising the metal interconnection method according to any one of the first aspect.

[0019] In a third aspect, the embodiments of the present application provide a semiconductor device prepared by using the semiconductor device preparation method according to the second aspect.

[0020] The embodiments of the present application etch a first preset pattern on an optical functional layer, sequentially deposit a first metal layer and a medium layer on the optical functional layer on which the first preset pattern is etched, etch a second preset pattern on the first metal layer and the medium layer, and deposit a second metal layer on the first metal layer and the medium layer on which the second preset pattern is etched, so that the second metal layer is interconnected with the first metal layer, without the need to control the remaining thickness of the first metal layer, which can avoid using a metal layer as an etching stop layer, avoid the difficulty in controlling the remaining thickness of the first metal layer due to a low etching selectivity, and affect the performance of the device, and can effectively improve the metal interconnection effect. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a device structure diagram based on an existing metal interconnection scheme;

[0022] Figure 2 is a flowchart of a metal interconnection method provided by the embodiments of the present application;

[0023] Figure 3is a device structure schematic diagram based on a metal interconnection method provided in the embodiments of the present application. DETAILED DESCRIPTION

[0024] In order to make the purposes, technical solutions and advantages of the present application clearer, the specific embodiments of the present application are further described in detail below with reference to the drawings. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only parts related to the present application are shown in the drawings, but not all. In addition, it should be noted that, for the convenience of description, only parts related to the present application are shown in the drawings, but not all. In the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the terms "connected", "connected", "fixed" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0025] Before discussing the example embodiments in more detail, it should be mentioned that some example embodiments are described as processes or methods depicted as flow diagrams. Although the flow diagrams describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations can be rearranged. The above processes can be terminated when their operations are completed, but can also have additional steps not included in the drawings. The above processes can correspond to methods, functions, procedures, subroutines, subprograms, etc.

[0026] The existing metal interconnection scheme generally deposits an optical functional layer, a first metal layer and a dielectric layer on a chip, etches a pattern on the first metal layer and the dielectric layer, and then deposits a second metal layer to realize the interconnection of the first metal layer and the second metal layer. Figure 1 is a device structure schematic diagram based on the existing metal interconnection scheme, as shown in Figure 1 , an optical functional layer, a first metal layer and a dielectric layer are deposited on a chip, and the deposition of the optical functional layer, the first metal layer and the dielectric layer is shown from bottom to top in the figure. The first metal layer and the dielectric layer are etched twice to expose regions A and B as shown in Figure 1 , respectively. A second metal layer is deposited on the first metal layer and the dielectric layer, as shown in Figure 1 , at this time, the second metal layer is in contact with the first metal layer in regions A and B for interconnection. As shown in Figure 1 , finally, a corresponding pattern is selectively etched on the second metal layer for subsequent device preparation.

[0027] In the first metal layer as an etching stop layer, the remaining thickness of the first metal layer in region B needs to be controlled, but it is difficult to achieve a high etching selectivity in actual production process, and the etching depth and the stop layer are difficult to control, which has a great influence on the performance of the device, and even may cause short circuit of the device, and the metal layer interconnection effect is poor. Based on this, the metal interconnection method provided in the embodiments of the present application is provided to solve the technical problems that the existing metal interconnection scheme needs to use a metal layer as an etching stop layer, which causes the etching selectivity to be difficult to control, the etching precision is difficult to accurately control, and the metal layer interconnection effect is poor.

[0028] Figure 2 A flowchart of the metal interconnection method provided in the embodiments of the present application is given, and the metal interconnection method provided in the embodiments of the present application can be executed by a metal interconnection device, which can be realized in the form of hardware and / or software.

[0029] The metal interconnection method executed by the metal interconnection device is described below. Referring to Figure 2 , the metal interconnection method comprises:

[0030] S110: etching a first preset pattern on the optical functional layer.

[0031] S120: sequentially depositing a first metal layer and a dielectric layer on the optical functional layer on which the first preset pattern is etched.

[0032] Figure 3 A device structure diagram based on the metal interconnection method provided in the embodiments of the present application is given, as shown in Figure 3 (a), wherein the downward etching position in the first preset pattern corresponds to the position where the first metal layer and the second metal layer need to be interconnected. Further, as shown in Figure 3 (b), after etching the first preset pattern on the optical functional layer, the first metal layer and the dielectric layer can be sequentially deposited on the optical functional layer on which the first preset pattern is etched. Figure 3 (b) from bottom to top is the optical functional layer, the first metal layer and the dielectric layer. The dielectric layer is a non-conductive material layer.

[0033] In one possible embodiment, the optical functional layer provided in the present application can be a nitrogen-doped silicon carbide (NDC layer), and the nitrogen-doped silicon carbide layer can form a dense physical barrier to isolate oxygen, water vapor and pollutants, prevent the lower layer material from being oxidized or corroded, ensure the performance and reliability of the device, and can be used as an accurate stop layer for subsequent etching steps, to ensure that the etching process slows down or stops automatically when reaching the NDC layer, and to avoid damaging the lower key structure.

[0034] In one possible embodiment, the first metal layer provided in this application can be one or more combinations of a chromium-silicon metal layer (CrSi thin film layer), a tantalum nitride metal layer (TaN thin film layer), a nickel-chromium alloy metal layer (NiCr thin film layer), and a titanium nitride metal layer (TiN thin film layer). The chromium-silicon metal layer, tantalum nitride metal layer, nickel-chromium alloy metal layer, and titanium nitride metal layer, as high resistivity materials, can achieve high resistance values ​​within a small area, meeting the requirements of circuit design for compact resistors.

[0035] In one possible embodiment, the dielectric layer provided in this application is a non-metallic dielectric layer. This non-metallic dielectric layer can isolate the first metal layer and the second metal layer, and prevent oxidation of the first metal layer, thereby improving device performance. Optionally, the non-metallic dielectric layer provided in this application can be a silicon nitride dielectric layer (SiN layer). The silicon nitride dielectric layer can effectively isolate the first metal layer and the second metal layer, and effectively prevent oxidation of the first metal layer, thereby improving the stability of device performance.

[0036] S130: Etch a second preset pattern on the first metal layer and the dielectric layer.

[0037] For example, after depositing the first metal layer and the dielectric layer, a second preset pattern is etched onto the first metal layer and the dielectric layer. Optionally, the cutout position of the second preset pattern corresponds to the cutout position of the first preset pattern.

[0038] like Figure 3 As shown in (c), the cutout position of the second preset pattern penetrates the first metal layer and the dielectric layer. This application does not require the first metal layer to be used as the etching stop layer, nor does it require controlling the remaining thickness of the first metal layer. This can effectively avoid the situation where the device performance is affected due to the difficulty in controlling the remaining thickness of the first metal layer. Furthermore, the etching operation is less difficult, the etching operation is more stable and efficient, and the yield rate of device production is higher.

[0039] S140: Deposit a second metal layer on a first metal layer and a dielectric layer that have been etched with a second preset pattern, wherein the second metal layer is interconnected with the first metal layer.

[0040] For example, after etching a second preset pattern on the first metal layer and the dielectric layer, a second metal layer can be deposited on the first metal layer and the dielectric layer where the second preset pattern has been etched. Figure 3As shown in (d), the second metal layer is in contact with and interconnected with the first metal layer at the bottom side of the position corresponding to the cutout position in the second preset pattern. Optionally, the second metal layer provided in this application can be a titanium nitride metal layer (TiN layer), or a combined metal layer formed by titanium nitride and a preset metal, wherein the preset metal includes one or more combinations of titanium (Ti), aluminum (Al), and tungsten (W). For example, the combined metal layer can be a combined metal layer formed by titanium, titanium nitride, and aluminum, and the second metal layer can be formed by sequentially depositing titanium, titanium nitride, and aluminum; the combined metal layer can be a combined metal layer formed by titanium, titanium nitride, and tungsten, and the second metal layer can be formed by sequentially depositing titanium, titanium nitride, and tungsten.

[0041] In one possible embodiment, after depositing a second metal layer on a first metal layer and a dielectric layer with a second preset pattern etched out, the metal interconnect method provided in this application may also etch a third preset pattern on the second metal layer.

[0042] For example, such as Figure 3 As shown in (e), after depositing a second metal layer on the first metal layer and the dielectric layer, the excess portion on the second metal layer is etched according to the third preset pattern required by the device to be produced, so as to form the third preset pattern on the second metal layer and obtain the corresponding device structure.

[0043] As described above, by etching a first preset pattern on the optical functional layer, sequentially depositing a first metal layer and a dielectric layer on the optical functional layer with the first preset pattern etched, etching a second preset pattern on the first metal layer and the dielectric layer, and depositing a second metal layer on the first metal layer and the dielectric layer with the second preset pattern etched, the second metal layer is interconnected with the first metal layer. It is not necessary to control the remaining thickness of the first metal layer, thus avoiding the use of the metal layer as an etching stop layer and avoiding the situation where the device performance is affected due to the difficulty in controlling the remaining thickness of the first metal layer due to the low etch selectivity. This can effectively improve the interconnection effect of the metal layers.

[0044] This application also provides a method for fabricating a semiconductor device, which includes the metal interconnection method provided in any of the above embodiments.

[0045] The first metal layer and the dielectric layer are deposited on the optical functional layer in sequence after the first preset pattern is etched on the optical functional layer, the second preset pattern is etched on the first metal layer and the dielectric layer, and the second metal layer is deposited on the first metal layer and the dielectric layer after the second preset pattern is etched, so that the second metal layer is interconnected with the first metal layer, the remaining thickness of the first metal layer does not need to be controlled, the metal layer as an etching stop layer is avoided, the remaining thickness of the first metal layer is difficult to control due to a low etching selectivity, the performance of the device is affected, the interconnection effect of the metal layer is effectively improved, and the quality of the semiconductor device is better.

[0046] The application further provides a semiconductor device prepared by using the semiconductor device preparation method.

[0047] The first metal layer and the dielectric layer are deposited on the optical functional layer in sequence after the first preset pattern is etched on the optical functional layer, the second preset pattern is etched on the first metal layer and the dielectric layer, and the second metal layer is deposited on the first metal layer and the dielectric layer after the second preset pattern is etched, so that the second metal layer is interconnected with the first metal layer, the remaining thickness of the first metal layer does not need to be controlled, the metal layer as an etching stop layer is avoided, the remaining thickness of the first metal layer is difficult to control due to a low etching selectivity, the performance of the device is affected, the interconnection effect of the metal layer is effectively improved, and the quality of the semiconductor device is better.

[0048] It is worth noting that the units and modules included in the above-mentioned embodiments of the metal interconnection method, the semiconductor device preparation method and the semiconductor device device are only divided according to the function logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be realized; in addition, the specific names of each functional unit are only for easy mutual differentiation, and do not limit the protection scope of the embodiments of the application.

[0049] The above is only the preferred embodiments of the application and the technical principles used. The application is not limited to the specific embodiments provided herein, and various obvious changes, readjustments and replacements that can be made by those skilled in the art will not deviate from the protection scope of the application. Therefore, although the application is described in more detail through the above embodiments, the application is not limited to the above embodiments, and more other equivalent embodiments can be included without deviating from the concept of the application, and the scope of the application is determined by the scope of the claims.

Claims

1. A method of metal interconnection, characterized by, Comprising: etching a first preset pattern on the optical functional layer; depositing a first metal layer and a dielectric layer on the optical functional layer on which the first preset pattern is etched; etching a second preset pattern on the first metal layer and the dielectric layer, the hollowed-out position of the second preset pattern corresponding to the hollowed-out position of the first preset pattern, the hollowed-out position of the second preset pattern penetrating the first metal layer and the dielectric layer; depositing a second metal layer on the first metal layer and the dielectric layer on which the second preset pattern is etched, wherein the second metal layer is in contact and interconnection with the first metal layer at the position corresponding to the hollowed-out position in the second preset pattern.

2. The metal interconnect method of claim 1, wherein, After the step of depositing a second metal layer on the first metal layer and the dielectric layer on which the second preset pattern is etched, further comprising: etching a third preset pattern on the second metal layer.

3. The method of claim 1, wherein The first metal layer comprises a combination of one or more of a chromium-silicon metal layer, a tantalum nitride metal layer, a nickel-chromium alloy metal layer, and a titanium nitride metal layer.

4. The method of claim 1, wherein The dielectric layer is a non-metal dielectric layer.

5. The method of claim 4, wherein, The non-metal dielectric layer is a silicon nitride dielectric layer.

6. The method of claim 1, wherein The second metal layer is a titanium nitride metal layer, or a combined metal layer formed by titanium nitride and a preset metal, the preset metal comprising a combination of one or more of a titanium metal, an aluminum metal, and a tungsten metal.

7. The method of claim 1, wherein The optical functional layer is a nitrogen-doped silicon carbide layer.

8. A method of fabricating a semiconductor device, characterized by, A method for metal interconnection as claimed in any one of claims 1-7.

9. A semiconductor device, characterized by A semiconductor device prepared by using the method for semiconductor device preparation as claimed in claim 8.

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