Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes: a substrate; the bare chip is provided with a first surface and a second surface, and the bare chip is embedded in the substrate; a first heat sink disposed at a first surface of the substrate; and a second heat sink disposed at a second surface of the substrate, where the substrate includes a thermally conductive structure disposed between the first surface of the die and the first heat sink and a thermally insulating structure disposed between the first surface of the die and the first heat sink. The thermal isolation structure is disposed between a second surface of the die and a second surface of the substrate opposite the first surface.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including embedded components for high voltage applications. Background Art

[0002] As the problem of stray inductance inside a single package becomes increasingly prominent, high-voltage applications require smaller form factors. Therefore, it is desirable to embed the semiconductor die into the wiring substrate to reduce the parasitic inductance by shortening the free length of the connector and the interconnection structure between the die. However, the embedded die operating at high voltage and high switching speed will become a significant heat source. In order not to affect the normal operation of the die, the substrate, and any surface-mounted devices (SMDs) adjacent to the die, the heat energy generated by the die needs to be dissipated and directed away from the heat source. A common method of dissipating heat from the die is to attach a heat sink to one side of the substrate. However, since the heat generated by the die is conducted in all spatial directions, certain areas on the substrate may become hot, and therefore these areas may not be suitable for mounting SMDs, or may even be unusable at all. Therefore, the object of the present invention is to provide a semiconductor device with enhanced heat transfer characteristics. Summary of the Invention

[0003] The above problems are solved by the invention as defined in the independent claims. Further embodiments are defined in the dependent claims.

[0004] According to a first aspect, a semiconductor device is provided, comprising: a substrate; a die having a first surface and a second surface, wherein the die is embedded in the substrate; a first heat sink arranged at the first surface of the substrate; and a second heat sink arranged at the second surface of the substrate, wherein the substrate comprises a heat conducting structure and a heat isolating structure, the heat conducting structure being arranged between the first surface of the die and the first heat sink, and the heat isolating structure being arranged between the second surface of the die and a second surface of the substrate opposite to the first surface.

[0005] According to a first aspect, the die is embedded in a substrate to reduce parasitic inductance by reducing the free path of the interconnect structure. The substrate can be a multilayer substrate including multiple metal and non-metal layers and an epoxy resin carrier. The substrate material can be epoxy resin, imide, bismaleimide triazine and benzoxazine to achieve multi-layer embedding. In addition, the substrate can be a printed circuit board (PCB) consisting of a metal stack embedded in an epoxy resin matrix. The PCB will be described in detail below.

[0006] The layers in the substrate can be substantially symmetrical, i.e., can be evenly distributed relative to a centerline of the substrate to reduce warping of the substrate. The substrate can have a first (lower) surface and a second (upper) surface. A first heat sink can be attached to the first surface of the substrate. A heat sink is a spatially confined area or body that releases its stored or supplied thermal energy into an adjacent medium. The adjacent medium can be a solid, liquid, or gas.

[0007] The die may comprise a first side comprising the drain and collector connection structures. Furthermore, the die may comprise a second (upper) side being the control side and comprising the gate and emitter connection structures.

[0008] The die can be completely buried in the substrate and surrounded by the substrate, but it can also be only partially embedded. Embedded does not necessarily mean that the die is arranged in a recess in the substrate. The die can also be mounted on the substrate and surrounded by the substrate. Since the die will be a source of thermal energy, which will be dissipated into the surrounding substrate in all spatial directions, the substrate will become hot during operation. In particular, in high-voltage applications (typically at voltages above 200V), the substrate and its associated areas will be subject to thermal stress. In order to keep the temperature of the die below a certain threshold, it is necessary to guide the heat out of the die and dissipate the energy. Therefore, the substrate includes a heat-conducting structure that is configured to guide the heat out from the underside of the die and toward a first heat sink located at the first (lower) side of the substrate. Since the first heat sink is arranged at the first surface of the substrate, it may not be possible to attach other devices to the first surface of the substrate within the footprint of the first heat sink.

[0009] Since heat dissipates in all spatial directions, heat will also be directed out from the upper portion, the second side, of the die and toward the second surface of the substrate. Therefore, the second surface of the substrate will also become hot. Therefore, the availability of the upper surface of the substrate for attaching sensitive SMDs may be reduced. In order to reduce heat transfer from the upper side of the die to the second (upper) side of the substrate, the substrate includes a thermal isolation structure. The thermal isolation structure isolates the second side of the substrate from the heat source, i.e., the die. Therefore, the thermal isolation structure is arranged between the upper surface of the substrate and the heat source (i.e., the second, upper surface of the die). As a result, the heat flowing to the upper side of the substrate is reduced. Therefore, the temperature on the upper surface of the substrate can be reduced, and the surface area of ​​the substrate located above the heat source can be better used to attach SMDs. Therefore, SMDs can be attached in the area of ​​the second surface of the substrate located above the die and / or in the area closer to the footprint of the die, or even in the area within the footprint of the die.

[0010] Furthermore, because the thermal isolation structure has a thermal conductivity greater than zero, heat transfer through the isolation structure occurs over time, and the upper surface of the substrate will heat up as long as the heat source is operating. To further reduce the amount of heat transferred to the upper surface of the substrate through the thermal isolation structure, a second heat sink is attached to the upper surface of the substrate. The second heat sink directs the transferred thermal energy from the upper side of the substrate into a cooling medium. The cooling medium for both the first and second heat sinks can be ambient air, but both heat sinks can also include or operate in conjunction with any other cooling liquid or gas. The second heat sink further reduces the surface temperature of the upper side of the substrate. This increases the area on the upper surface of the substrate available for attaching sensitive SMDs.

[0011] The thermal isolation structure has a thermal conductivity in the range of 0.3 W / mK, preferably below 0.3 W / mK, wherein the thermal conductivity of the heat-conducting structure is in the range of 3-10 W / mK, i.e., at least ten times higher than that of the isolation structure. The thermal isolation structure may be an epoxy resin with reduced thermal conductivity, wherein the heat-conducting structure may be an epoxy resin with enhanced thermal conductivity. Both the heat-conducting structure and the heat-isolating structure may consist of one or more layers, or may be a single layer. Furthermore, the heat-isolating structure may be embedded in the substrate and arranged between a wiring layer and a metallization layer forming an upper surface or cover layer of the substrate, wherein the wiring layer may be arranged to contact the upper side of the die by means of wires, vias, or the like. The wiring layer may be electrically connected to the metallization layer to form a DC link.

[0012] In one embodiment, the footprint of the first heat sink overlaps with the footprint of the die. "Footprint" generally describes the area or space that an object or system occupies or requires in a specific application or environment. In this article, the term "footprint" refers to the size of an electronic component, in particular the total area that the component occupies on a PCB. A smaller component footprint can help achieve a higher component density on a PCB. From a top view, the footprint of the first heat sink is larger than the footprint of the die, and the footprint of the die is contained within the footprint of the first heat sink. The heat guided out from the first surface of the die through the thermally conductive structure will diffuse from the heat source in a spatially annular manner. Therefore, in order for the first heat sink to collect most of the transferred heat, the footprint of the first heat sink is larger than the footprint of the die. The efficiency of the first heat sink can be improved by a short and direct heat transfer path from the die to the first heat sink.

[0013] In another embodiment, the footprint of the second heat sink overlaps with the footprint of the die, and / or the second heat sink is a device (SMD) mounted on the second surface of the substrate. In order to achieve a short heat transfer path, the second heat sink also at least partially overlaps with the footprint of the die from a top view. In particular, non-temperature-sensitive SMDs can also be used as heat sinks, because any device attached to the upper surface of the substrate will increase the surface area available for transferring heat from this surface to a cooling medium (e.g., ambient air). If a non-temperature-sensitive SMD is used as a heat sink, the non-temperature-sensitive SMD can be mounted directly above the die, i.e., the footprint of the die can be included in the footprint of the second heat sink. The thermal isolation structure can be a continuous structure located above the die, i.e., it can not have any through-connection structure. For example, the electrical through-connection structure that connects the wiring layer of the contact die to the metallization layer on the surface of the substrate is preferably arranged outside the footprint of the die and outside the footprint of the second heat sink to prevent heat from flowing to the upper surface of the substrate.

[0014] In another embodiment, a substrate includes a leadframe, wherein the leadframe includes a heat spreading portion configured to contact a first side of a die, the heat spreading portion including a via structure to contact a metal layer disposed between the heat spreading portion and the first side of the substrate, wherein the metal layer is part of a thermally conductive structure.

[0015] The substrate may include a lead frame, for example, a metal structure on which a die or other electronic components are mounted. The lead frame connects the chip to the leads of the lead frame via thin wires (typically made of gold or copper), thereby providing an electrical connection between the die and the outside world. In this embodiment, the lead frame acts as a carrier for the die. The die can be fixedly attached to the lead frame. The lead frame may include a heat diffusion portion that acts as a heat sink, conducting heat away from the die and dispersing it. The die can be attached to the heat diffusion portion. In particular, the heat diffusion portion can be a pillow-shaped integral component of the lead frame and can contact the first (lower) side of the die. The heat diffusion portion can be a copper pillow.

[0016] The lead frame also provides physical support for the die and protects the die from damage. The lead frame can be made of materials such as copper, copper alloys, or iron-nickel alloys and is designed to be compatible with the manufacturing process used to create the die. The heat spreading portion is configured to dissipate heat away from the heat-generating device, such as the die.

[0017] In the case of an HV semiconductor die, the heat sink can also be a metal plate attached to the die, typically with a layer of thermal paste between the heat sink and the die. The heat sink helps spread the heat generated by the die over a larger surface area, making it easier for a cooling device (e.g., the first heat sink) to dissipate the heat.

[0018] The heat sink can be made of a variety of materials, including copper, aluminum, or a combination of the two. The heat diffusion portion can include a via structure for contacting another metal layer disposed between the first heat sink and the heat diffusion portion. The via structure can be a thermally conductive metal structure and can serve as a path to enhance heat flow from the heat diffusion portion to the heat conducting structure and then to the first heat sink.

[0019] The metal layer can be part of the thermally conductive structure. With the help of the heat sink, the heat energy can be dissipated better and spread over a larger area, so that it can be better absorbed by the first heat sink. This enhances the overall heat dissipation and cooling effect of the die.

[0020] In another embodiment, the thermal transfer coefficient of the isolation structure is less than 0.3 W / mK. Because heat transfer and the resulting surface temperature to the upper side of the substrate are affected by the heat transfer capability of the isolation structure, i.e., the isolation quality, a low thermal transfer coefficient is desirable for the thermal isolation structure. In particular, if the thermal transfer coefficient is less than 0.3 W / km, the surface temperature of the upper surface of the substrate will be sufficiently low to prevent damage to sensitive SMDs located in the footprint adjacent to the die, or to prevent damage to non-sensitive SMDs located directly above the die.

[0021] In particular, the insulating structure is a honeycomb structure, a brick structure, a gas-filled honeycomb structure, or a structure containing gas-filled cavities. Gas-filled structures have particularly low heat transfer coefficients. A honeycomb structure is a porous or matrix structure composed of hexagonal cells or cavities arranged in a regular pattern. The resulting structure is lightweight, strong, and rigid, making it ideal for use in a variety of applications where strength and weight are important factors. If the cavities of the honeycomb structure are filled with gas, the structure also serves as an excellent insulator.

[0022] Because the hexagonal shape of the cells in the honeycomb structure provides a high strength-to-weight ratio, the structure is able to distribute stresses and strains evenly across the surface. Under thermal stress, such as in this case, the air-filled honeycomb structure can achieve a good balance between insulation properties and mechanical strength.

[0023] The same applies to the structure including any air-filled cavities, which contribute to achieving good insulation properties.The structure may be a continuous structure without any heat-conducting through-connections.

[0024] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor device for high-voltage applications is provided, the method comprising: providing a substrate; embedding a die having a first surface and a second surface in the substrate; arranging a first heat sink at the first surface of the substrate; and arranging a second heat sink at the second surface of the substrate, wherein the embedding comprises: arranging a heat-conducting structure between the first surface of the die and the first heat sink, and arranging a thermal isolation structure between the second surface of the die and a second surface of the substrate opposite to the first surface.

[0025] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present disclosure is illustrated by way of example and not limitation in the accompanying drawings, in which like or identical reference numerals refer to like or identical elements. The elements in the drawings are not necessarily drawn to scale relative to each other. The features of the various illustrated examples may be combined unless they mutually exclude each other.

[0027] Figure 1 A semiconductor device according to a first aspect of the present disclosure is shown.

[0028] Figure 2 Shown Figure 1 Schematic top view of a semiconductor device.

[0029] Figure 3 Shown Figure 1 An embodiment of a semiconductor device.

[0030] Figure 4 is a further cross-sectional view of the semiconductor device according to the first aspect of the present disclosure.

[0031] Figure 5a and Figure 5b is a schematic cross-sectional view of a layered structure of an embedded substrate according to the first aspect of the present disclosure.

[0032] Figure 6 is a flow chart of the second aspect of the present disclosure.

[0033] Figure 7 is a further flow chart of the second aspect of the present disclosure. DETAILED DESCRIPTION

[0034] In the following, the above drawings are described by way of examples.

[0035] Figure 1A semiconductor device 1 according to a first aspect of the present disclosure is shown. The semiconductor device 1 includes a substrate 2. A semiconductor die 3 is embedded in the substrate 2. The substrate 2 completely surrounds the die 3, wherein the die 3 is arranged in a cavity 4 within the substrate 2. The substrate 2 is a PCB comprising multiple layers, as will be described in detail below.

[0036] The die 3 comprises a first (lower) surface 5 and a second (upper) surface 6. A first heat sink 7 is arranged at a first lower surface 8 of the substrate 2. Opposite to the first heat sink 7, a second heat sink 9 is arranged at the top side of the substrate 2, ie at a second surface 10.

[0037] Substrate 2 is a multi-layer substrate that includes a thermally conductive structure 11. Thermally conductive structure 11 is a layered structure located between die 3 and first lower surface 8 of substrate 2. Thermally conductive structure 11 can also be a continuous, monolithic structure. Thus, thermally conductive layer 11 transfers heat from die 3 (a heat source during operation) to first heat sink 7, where the heat is dissipated and directed away from semiconductor device 1, for example, to ambient air or another cooling medium 12. Furthermore, a thermal isolation structure 13 is disposed between die 3 (i.e., second surface 6 of the die) and the top side surface 10 of the substrate. This thermal isolation structure 13 can also be a layered, stratified, and / or continuous, monolithic structure. The transfer of heat generated by die 3 to the top side of the substrate is hindered, reducing the amount of heat flowing to the top side of the substrate, thereby lowering the temperature on top side 10 of substrate 2. Additional devices 14 (SMDs) are mounted on top side 10 of substrate 2.

[0038] Figure 2 Shown Figure 1 A schematic top view of the semiconductor device 1 is shown. Heat generated by the operating die 3 is transferred to both sides 8 and 10 of the substrate 2 and diffused through the multi-layer substrate's thermal isolation structure 13 and thermally conductive structure 11, as well as any additional layers between the die 3 and the upper and lower surfaces 8 and 10 of the substrate 2. To efficiently transfer heat from the substrate's surfaces 8 and 10 to the surrounding cooling medium 12, a first heat sink 7 is mounted on the underside of the substrate 2. The footprint of the substrate 2 can be larger than that of the first heat sink 7. The footprint of the first heat sink 7 overlaps with that of the die 3, meaning that, from a top-side perspective, the die 3 is located within the footprint of the first heat sink 7. The footprint of the second heat sink 9 is larger than that of the die 3, meaning that, from a top-side perspective, the die 3 is located within the footprint of the second heat sink 9. In another embodiment, the footprint of the second heat sink 9 is smaller than that of the die 3, meaning that the second heat sink 9 can be located within the footprint of the die 3. Heat transferred from the die 3 , which typically has a smaller footprint, through the substrate 2 to the first heat sink 7 and / or the second heat sink 9 can be better received and conducted away from the substrate 2 .

[0039] Figure 3 Shown Figure 1 An embodiment of a semiconductor device 1 is shown. Instead of a second heat sink 9, an SMD 14 is placed on the top side surface of substrate 2 in an area above die 3. Heat generated by die 3 dissipates within substrate 2 and, over time, reaches the top side of substrate 2. Consequently, the top side surface of substrate 2 heats up, requiring heat transfer to the surrounding medium 12 to prevent this top side heating. Therefore, a non-thermal-sensitive SMD 14 is placed above the die to serve as a second heat sink 9. The SMD increases the surface area above die 3 in contact with the surrounding medium 12. Thus, the SMD 14 acts as a heat exchanger. The SMD 14 is arranged within the footprint of die 3, meaning the lateral surface dimensions of die 3 can be larger than those of the SMD. However, the lateral dimensions of the second heat sink 9 / SMD can also be larger than those of die 3.

[0040] Figure 4 is a further cross-sectional view of the semiconductor device 1 according to the first aspect of the present disclosure. Figure 4 A layered substrate 2, which is a PCB, is shown having two recesses 15. The recesses 15 form a cavity 4 that accommodates a die 3. The substrate also comprises a lead frame 16.

[0041] In this example, first heat sink 7 is attached to a first side of substrate 8, which is coated with a first metal layer 16a. First metal layer 16a can be a copper layer and / or electroplated copper layer with a thickness between 70 μm and 140 μm. First metal layer 16a is followed by an epoxy layer 16b with a thickness of approximately 140 μm. Epoxy layer 16b is made of epoxy resin or polypropylene with enhanced thermal conductivity and can form or be part of thermally conductive structure 11. Second metal layer 17 is deposited on epoxy layer 16b.

[0042] Thermally conductive structure 11 may include an epoxy layer 16b and a second metal layer 17 disposed between first heat sink 7 and first (lower) surface 5 of die 3. Leadframe 16 may be made of copper or electroplated copper, wherein the epoxy layer may be a pre-impregnated thermoplastic or thermoset matrix (PP). PP may comprise a predominantly flat textile semi-finished product, such as a unidirectional thread layer, a fabric, or a scrim with threads arranged at right angles.

[0043] Leadframe 16 includes a pillow-shaped heat diffusion portion 18. Heat diffusion portion 18 is made of copper or any other suitable material. Die 3 is attached to heat diffusion portion 18 via a thermally conductive adhesive layer 19, which securely connects the underside of die 3 to heat diffusion portion 18 of leadframe 16. Heat diffusion portion 18 includes a first via structure 20 and is connected to second metal layer 17 via the first via structure 20. First via structure 20 thermally and electrically connects pillow-shaped heat diffusion portion 18 to second metal layer 17. First via structure 20 can also be part of thermally conductive structure 11, as via 20 can act as a thermal conductor.

[0044] The lead frame 16 is disposed on the heat-conducting structure 11 or as a part of the heat-conducting structure 11 , so that heat can be efficiently transferred from the die 3 via the heat diffusion portion 18 through the first via structure 20 to the heat-conducting structure 11 (in this example, the epoxy resin layer), and then to the first heat sink 7 .

[0045] On the second (upper) surface 6 of the die 3, a layered electrical contact pad 21 is provided. Connecting wires 22 are provided at the contact pad 21, connecting the die 3 to a second via structure 23 via the contact pad 21. The second via structure 23 is connected to an upper structure 24. The upper structure 24 forms a wiring layer that electrically connects the plurality of dies 3 in the parallel cavities 4 shown. The cavities 4 are filled with a molding compound 25.

[0046] Superstructure 24 is part of multilayer substrate 2 and is disposed between second (upper) surface 6 of die 3 and top side 10 of substrate 2. Thermal isolation structure 13 is disposed between superstructure 24 and top side 10 of substrate 2. Thermal isolation structure 13 is partially covered by cover layer 26, which is a second metal layer. Thermal isolation structure 13 thermally and electrically isolates superstructure 13 from cover layer 26 and top side surface 10 of substrate 2. Second heat sink 9 is disposed on cover layer 26 so as to be positioned above die 3 and is thermally connected to cover layer 26. With the aid of second heat sink 9, a surface temperature of 65-90°C can be achieved in the area above die 3, while the temperature (junction temperature) directly at die 3 during operation is approximately 150°C. During operation, the temperature of the first heat sink is approximately 80-90°C.

[0047] Figure 5a and Figure 5b is a schematic cross-sectional view of a layered structure of an embedded multi-layer substrate 2 according to the first aspect of the present disclosure.

[0048] Figure 5a is a schematic diagram focusing on several embodiments of the thermal isolation structure 13. Figure 5aDifferent embodiments are described in detail herein. However, the different embodiments are compatible with each other and can be implemented as appropriate by a person skilled in the art. The thermal insulation structure 13 is a brick structure 27 formed of a plurality of brick-like insulation elements. Generally, the thermal insulation structure 13 can include a plurality of independent insulation elements, or the thermal insulation structure can be composed of a combination of the embodiments described herein.

[0049] In addition, the thermal insulation structure 13 can be a honeycomb structure 28. The cavities of the honeycomb structure 28 can be filled with an insulating compound or filled with any suitable insulating gas. The thermal insulation structure 13 can also be a structure including gas-filled cavities 29. The gas-filled cavities are embedded in a matrix 30 composed of any suitable thermal insulation material.

[0050] Figure 5b is a schematic cross-sectional view of the layered structure of the embedded multilayer substrate 2. An interposer 31 is disposed between the first heat sink 7 and the thermally conductive structure 11. The interposer 31 forms the lower surface 8 of the substrate 2 and can be equivalent to the first metal layer 16a. A second metal layer 17 is disposed on the upper side of the thermally conductive structure 11, between the thermally conductive structure 11 and the epoxy layer 16b. The epoxy layer 16b is disposed between the second metal layer 17 and another epoxy layer (not shown) and / or the heat diffusion portion 18. The other epoxy layer can form the core of the substrate layer and has a thickness of approximately 1270 μm. The thickness of the other epoxy layer is approximately the vertical dimension of the cavity 4. The heat diffusion portion 18 is encapsulated by a molding compound 25, forming a molding layer. The molding compound 25 fills the cavity 4 and encapsulates at least the second surface 6 of the die. Connecting wires 22 connect to corresponding connection pads 21 located on the second surface 6 of the die and connect the control side of the die 3 to the second via structure 23. The upper structure 24 is arranged on the mold compound 25 and between the mold compound 25 and the thermal isolation structure 13. The thickness of the thermal isolation structure 13 is about 140 μm and is a continuous structure. In particular, the thermal isolation structure 13 does not have a through-connection structure from the second via structure 23, the upper structure 24 or the cover layer 26. The upper structure 24 is a metal layer forming a wiring layer. The upper structure 24 can be electrically connected to the cover layer 26 through a third via structure (not shown). The thermal isolation structure 13 is covered by a conductive cover layer 26, which forms the second surface 10 of the substrate 2. The SMD 14 and / or the second heat sink 9 are arranged at the top surface 10 of the substrate 2.

[0051] During operation of die 3, the junction temperature (the temperature at the hottest point of die 3) will reach approximately 150°C. Subsequently, the temperature of the core material of substrate 2 located near mold compound 25 (e.g., another epoxy layer) (adjacent to cavity 4) will be in the range of 120°C-130°C. The temperature of the core material of substrate 2, more broadly adjacent to cavity 4, will be in the range of approximately 60°C-80°C. Because heat is dispersed by heat spreading portion 18 and conducted away from die 3 through first via structure 20 and second metal layer 17 toward heat conducting structure 11, the temperature of first via structure 20 and second metal layer 17 will be in the range of 135°C-145°C. The temperature of first heat sink 7 will be in the range of 80°C-90°C. Conversely, with the aid of thermal isolation structure 13, the temperature at cover layer 26 and / or second heat sink 9 can be reduced from 130°C-140°C to 65°C-95°C. In particular, this effect can be achieved by implementing a continuous thermal isolation structure 13 and omitting any thermally and / or electrically conductive through-connection structures within the footprint of the die. The electrical connection structure, i.e., the third via structure for electrically connecting the upper structure 24 to the cover layer 26, should be spaced apart from the die 3 in the lateral dimension of the substrate 2.

[0052] Figure 6 is a flow chart of the second aspect of the present disclosure.

[0053] According to the method 32 for manufacturing the semiconductor device 1 of the first aspect of the present invention, in step S1, a substrate 2 is provided. In step S2, a die 3 having a first surface 5 and a second surface 6 opposite to the first surface 5 is embedded in the substrate 2. In step S3, a first heat sink 7 is arranged at the first surface 8 of the substrate 2. In step S4, a second heat sink 9 is arranged at the second surface 10 of the substrate 2.

[0054] Figure 7 is a further flow chart of the second aspect of the present disclosure. Figure 7 The steps further explain Figure 6 Step S2.

[0055] Embedding die 3 in substrate 2 (step S2) also includes steps S2.1 and S2.2. In step S2.1, embedding includes placing a thermally conductive structure 11 between first surface 5 of die 3 and first heat sink 7. Furthermore, according to step S2.2, a thermal isolation structure 13 is placed between second surface 6 of die 3 and second surface 10 of substrate 2, which is opposite first surface 8 of substrate 2.

[0056] Although specific examples have been shown and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent embodiments may be substituted for the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any modifications or variations of the specific examples discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

[0057] It should be noted that the methods and apparatuses, including the preferred embodiments outlined herein, can be used alone or in combination with other methods and apparatuses disclosed herein. Furthermore, features outlined in the context of an apparatus also apply to the corresponding method, and vice versa. Furthermore, all aspects of the methods and apparatuses outlined herein may be combined in any manner. In particular, features of the claims may be combined with each other in any manner.

[0058] It should be noted that the description and drawings illustrate only the principles of the proposed method and system. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or illustrated herein, embody the principles of the present invention and are intended to be within the spirit and scope of the present invention. In addition, all examples and embodiments outlined herein are primarily and explicitly provided for illustrative purposes only to help the reader understand the principles of the proposed method and system. Furthermore, all statements herein providing principles, aspects, and embodiments of the present invention and specific examples thereof are intended to encompass their equivalents.

[0059] Reference Signs List

[0060] 1. Semiconductor devices

[0061] 2 Substrate

[0062] 3 bare die

[0063] 4 Cavity

[0064] 5. First surface of the die

[0065] 6 Second surface of the die

[0066] 7 First Radiator

[0067] 8. First lower surface of substrate

[0068] 9 Second radiator

[0069] 10 Top side / second surface of substrate

[0070] 11. Thermal Conductive Structure

[0071] 12 Ambient air / cooling medium

[0072] 13 Thermal isolation structure

[0073] 14 SMD

[0074] 15 concavity

[0075] 16 lead frame

[0076] 16a First metal layer

[0077] 16b Epoxy resin layer

[0078] 17 Second Metal Layer

[0079] 18 Heat diffusion part

[0080] 19 Adhesive layer

[0081] 20 First via structure

[0082] 21 contact pads

[0083] 22 Connecting wires

[0084] 23 Second via structure

[0085] 24 Superstructure

[0086] 25 Molding Compound

[0087] 26 Covering

[0088] 27 Brick Structure

[0089] 28 honeycomb structure

[0090] 29 gas-filled cavity

[0091] 30 Matrix

[0092] 31 Intermediary Layer

[0093] 32 Method for manufacturing a semiconductor device

Claims

1. A semiconductor device comprising: substrate; a die having a first surface and a second surface, the die being embedded in the substrate; a first heat sink disposed at the first surface of the substrate; a second heat sink disposed at a second surface of the substrate opposite to the first surface; Wherein, the substrate comprises: a heat conducting structure disposed between the first surface of the die and the first heat sink; and A thermal isolation structure is disposed between the second surface of the die and the second surface of the substrate.

2. The semiconductor device according to claim 1, wherein The footprint of the first heat spreader overlaps the footprint of the die.

3. The semiconductor device according to claim 1 or 2, wherein The footprint of the second heat spreader overlaps the footprint of the die, and / or the second heat spreader is a device (SMD) mounted on the second surface of the substrate.

4. A semiconductor device according to any one of the preceding claims, wherein The substrate includes a lead frame including a heat spreading portion configured to contact a first side of a die, the heat spreading portion including a via structure to contact a metal layer disposed between the heat spreading portion and the first side of the substrate, the metal layer being part of the thermally conductive structure.

5. A semiconductor device according to any one of the preceding claims, wherein The heat transfer coefficient of the thermal isolation structure is lower than 0.3W / mK. The semiconductor device according to claim 5 , wherein: The thermal insulation structure is one of a honeycomb structure, a brick structure, an air-filled honeycomb structure, or a structure including air-filled cavities.

7. A semiconductor device according to any one of the preceding claims, wherein The thermal isolation structure is a continuous structure located above the die, and the thermal isolation structure has no through-connection structure.

8. A semiconductor device according to any one of the preceding claims, wherein An electrical through-connection structure connecting a wiring layer in contact with the die and a metal cover layer located on the surface of the substrate is arranged outside the footprint of the die and / or outside the footprint of the second heat sink.

9. A method for manufacturing a semiconductor device for high voltage applications, the method comprising: providing a substrate; embedding a die having a first surface and a second surface in the substrate; disposing a first heat sink at the first surface of the substrate; as well as disposing a second heat sink at a second surface of the substrate opposite to the first surface; Wherein, the embedding includes: disposing a thermally conductive structure between the first surface of the die and the first heat sink; and A thermal isolation structure is disposed between the second surface of the die and the second surface of the substrate.

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