Driving circuit with automatic dead-zone switching function based on double-N-power-tube DCDC architecture

Abstract

The invention discloses a driving circuit with an automatic dead-zone switching function based on a double-N power tube DCDC architecture, which comprises a driving circuit, a delay chain circuit, an SW failure prevention circuit and a sampling logic circuit, and is characterized in that the driving circuit is responsible for transmitting an input signal HSON to a signal HSG for output; the delay chain circuit is responsible for outputting a signal HSDEADB consistent with the signal HSG in delay through delay control to the sampling logic circuit for dead time control, the sampling logic circuit is responsible for judging which one of the signal SW and the signal HSDEADB delays for a longer time, and the SW failure prevention circuit part is responsible for generating a signal SWPRE of which the delay is not limited by a signal VH. According to the invention, the delay chain and the sampling SW are combined, the delay chain or the sampling SW signal is automatically selected at different SW overturning speeds to control the dead time, the dead time is reduced in a full-load range, and no series connection is ensured.

Description

Technical Field

[0001] The present invention relates to a driving circuit, in particular to a driving circuit with automatic dead zone switching based on a dual N power tube DCDC architecture, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] With the continued growth of electronic products in consumer, industrial, and automotive electronics, demand for power management ICs continues to rise. For example, DC-DC switching power supplies and driver circuits are widely used. Simultaneously, as the load and power of electronic devices increase, the demand for high-voltage, high-current power stages is increasing. Furthermore, to accommodate increasingly complex application environments, input voltage and load current must be able to vary over a wide range in real time. Furthermore, to minimize overall product power consumption, the efficiency requirements for the power stage are increasing, especially at high currents, where losses in the power stage driver circuits account for a significant proportion.

[0003] This poses an increasingly difficult challenge to the dead time of the driver circuit. Slow dead time will reduce efficiency, but fast dead time can easily cause crosstalk and lead to chip burnout. Figure 7 As shown, its driving circuit is limited by the voltage control of the upper tube, and requires high-to-low level shift to detect the upper tube signal, which limits the minimum dead time, such as Figure 8 There are several ways to optimize dead time. One is to use multi-speed or programmable control [CN119276107A] to choose a compromise between dead time and efficiency as much as possible, such as Figure 9 As shown; the second is to judge by sampling the output voltage of the driver [CN115189565A], which has the risk of collusion under high current and high frequency; the third is to sample the SW signal for judgment [CN201910145720], which is only applicable to positive current. If there is current under FPWM, it cannot be achieved, and the traditional dead time needs to be retained. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a driving circuit with automatic dead zone switching based on a dual N power tube DCDC architecture, which solves the crosstalk problem that may be introduced by reducing the dead zone time.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A driving circuit based on a dual N power tube DCDC architecture with automatic dead zone switching includes a driving circuit DRIVER, a delay chain circuit DEAD_DELAY, a SW failure prevention circuit SW_PROTECT, and a sampling logic circuit HSG_SEN_LOGIC. The first input end of the driving circuit DRIVER is connected to the signal HSON, the second input end of the driving circuit DRIVER is connected to the input signal LSG_SEN, the first output end of the driving circuit DRIVER is connected to the input end of the delay chain circuit DEAD_DELAY and generates a signal HSON_PRE, the second output end of the driving circuit DRIVER is connected to the first input end of the SW failure prevention circuit SW_PROTECT and generates a signal H SG, a first output end of the delay chain circuit DEAD_DELAY is connected to the input end of the sampling logic circuit HSG_SEN_LOGIC, a second output end of the delay chain circuit DEAD_DELAY is connected to the second input end of the SW failure prevention circuit SW_PROTECT and generates a signal HS_DELAY_B, a third input end of the SW failure prevention circuit SW_PROTECT is connected to the input signal LSG_SEN, an output end of the SW failure prevention circuit SW_PROTECT is connected to the second input end of the sampling logic circuit HSG_SEN_LOGIC and generates a signal SW_PRE, and an output end of the sampling logic circuit HSG_SEN_LOGIC generates a signal HSG_SEN.

[0006] Furthermore, the driving circuit DRIVER includes an inverter INV1, an inverter INV2, an inverter INV4, an NOR gate NOR1 and a level conversion circuit LSF1. The input end of the inverter INV1 is connected to the signal HSON as the first input end of the driving circuit DRIVER, the output end of the inverter INV1 is connected to the first input end of the NOR gate NOR1 and generates the signal HSONB, the second input end of the NOR gate NOR1 is connected to the input signal HSON_PRE as the second input end of the driving circuit DRIVER, the output end of the NOR gate NOR1 is connected to the input end of the level conversion circuit LSF1 and serves as the first output end of the driving circuit DRIVER to generate the signal HSON_PRE, the output end of the level conversion circuit LSF1 is connected to the input end of the inverter INV2 and generates the signal HSON_H, the output end of the inverter INV2 is connected to the input end of the inverter INV3 and generates the signal HSONB_H, and the output end of the inverter INV3 serves as the second output end of the driving circuit DRIVER and generates the signal HSG.

[0007] Furthermore, the power supply terminal of the inverter INV1, the power supply terminal of the NOR gate NOR1 and the VDD1 terminal of the level conversion circuit LSF1 are connected to the power supply AVDD, the VDD2 terminal of the level conversion circuit LSF1, the power supply terminal of the inverter INV2 and the power supply terminal of the inverter INV3 are connected to the signal VH, the ground terminal of the inverter INV1, the ground terminal of the NOR gate NOR1 and the VSS1 terminal of the level conversion circuit LSF1 are grounded, and the VSS2 terminal of the level conversion circuit LSF1, the ground terminal of the inverter INV2 and the ground terminal of the inverter INV3 are connected to the signal SW.

[0008] Furthermore, the delay chain circuit DEAD_DELAY includes a level conversion circuit LSF2, an inverter INV6, a delay module DELAY1, an inverter INV7, a delay module DELAY2 and an inverter INV8. The input end of the level conversion circuit LSF2 is connected to the input end of the delay chain circuit DEAD_DELAY as the input end of the delay chain circuit DEAD_DELAY. The output end of the level conversion circuit LSF2 is connected to the input end of the inverter INV6 and generates a signal HSON_L. The output end of the inverter INV6 is connected to the input end of the delay module DELAY1 and generates a signal HSON. B_L, the output end of the delay module DELAY1 is connected to the input end of the inverter INV7 and serves as the first output end of the delay chain circuit DEAD_DELAY and generates a signal HS_DEAD_B, the output end of the inverter INV7 is connected to the input end of the delay module DELAY2 and generates a signal HS_DEAD_BB, the output end of the delay module DELAY2 is connected to the input end of the inverter INV8 and generates a signal HS_DELAY, and the output end of the inverter INV8 serves as the second output end of the delay chain circuit DEAD_DELAY and generates a signal HS_DELAY_B.

[0009] Furthermore, the VDD1 end of the level conversion circuit LSF2, the VDD2 end of the level conversion circuit LSF2, the power supply end of the inverter INV6, the power supply end of the delay module DELAY1, the power supply end of the inverter INV7, the power supply end of the delay module DELAY2 and the power supply end of the inverter INV8 are connected to the power supply AVDD, and the VSS1 end of the level conversion circuit LSF2, the VSS2 end of the level conversion circuit LSF2, the ground end of the inverter INV6, the ground end of the delay module DELAY1, the ground end of the inverter INV7, the ground end of the delay module DELAY2 and the ground end of the inverter INV8 are grounded.

[0010] Furthermore, the SW failure prevention circuit SW_PROTECT includes an inverter INV5, an AND gate AND1, a PMOS transistor PM1, an NMOS transistor NM3, and an NMOS transistor NM4. The input end of the inverter INV5 is connected to the signal HSG as the first input end of the SW failure prevention circuit SW_PROTECT, the output end of the inverter INV5 is connected to the gate of the PMOS transistor PM1, the source of the PMOS transistor PM1 is connected to the signal VH, the drain of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3, the gate of the NMOS transistor NM3 is connected to the signal PVDD, and the NMOS transistor NM3 is connected to the signal VH. The source of AND gate AND1 is connected to the drain of NMOS transistor NM4 and serves as the output terminal of SW failure prevention circuit SW_PROTECT to generate signal SE_PRE. The source of NMOS transistor NM4 is grounded. The first input terminal of AND gate AND1 serves as the second input terminal of SW failure prevention circuit SW_PROTECT and is connected to signal HS_DELAY_B. The second input terminal of AND gate AND1 serves as the third input terminal of SW failure prevention circuit SW_PROTECT and is connected to input signal LSG_SEN. The output terminal of AND gate AND1 is connected to the gate of NMOS transistor NM4 and generates signal LSON_SEN2.

[0011] Furthermore, the power supply terminal of the inverter INV5 is connected to the signal VH, the ground terminal of the inverter INV5 is connected to the signal SW, the power supply terminal of the AND gate AND1 is connected to the power supply AVDD, and the ground terminal of the AND gate AND1 is grounded.

[0012] Furthermore, the sampling logic circuit HSG_SEN_LOGIC includes a resistor R3, a resistor R4, a PMOS transistor PM2, a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5, a PMOS transistor PM6, an NMOS transistor NM5, an NMOS transistor NM6, and an NMOS transistor NM7. One end of the resistor R3 is connected to the signal SW, and the other end of the resistor R3 is connected to the gate of the PMOS transistor PM2. The source of the PMOS transistor PM2, the source of the PMOS transistor PM3, the source of the PMOS transistor PM5, and the source of the PMOS transistor PM6 are connected to the power supply PVDD. The gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3 and the source of the PMOS transistor PM4. The gate of the PMOS transistor PM4 is connected to the gate of the NMOS transistor NM5 and serves as the sampling logic circuit HSG_SEN_LOGIC. A second input terminal of OGIC is connected to a signal SW_PRE, a drain of the PMOS transistor PM2 is connected to one end of the resistor R4, a gate of the NMOS transistor NM7, and a gate of the PMOS transistor PM5, the other end of the resistor R4 is connected to the drain of the NMOS transistor NM5, the drain of the PMOS transistor PM5 is connected to the drain of the PMOS transistor PM6 and the drain of the NMOS transistor NM6 and serve as an output terminal of the sampling logic circuit HSG_SEN_LOGIC to generate a signal HSG_SEN, a gate of the PMOS transistor PM6 is connected to the gate of the NMOS transistor NM6 and serves as a first input terminal of the sampling logic circuit HSG_SEN_LOGIC to be connected to a signal HS_DEAD_B, a source of the NMOS transistor NM6 is connected to the drain of the NMOS transistor NM7, and the source of the NMOS transistor NM5 and the source of the NMOS transistor NM7 are grounded.

[0013] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a driving circuit with automatic dead zone switching based on a dual N power tube DCDC architecture. By combining a delay chain and a sampling SW, the present invention automatically selects the delay chain or the sampled SW signal to control the dead zone time at different SW flip speeds, thereby reducing the dead zone time in the full load range and ensuring no collusion, thereby optimizing the overall system efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of a driving circuit based on a dual N power tube DCDC architecture with automatic dead zone switching according to the present invention.

[0015] Figure 2 4 is a circuit diagram of a driving circuit DRIVER of the present invention.

[0016] Figure 3 2 is a circuit diagram of the delay chain circuit DEAD_DELAY of the present invention.

[0017] Figure 4FIG. 4 is a circuit diagram of the SW failure prevention circuit SW_PROTECT of the present invention.

[0018] Figure 5 1 is a circuit diagram of the sampling logic circuit HSG_SEN_LOGIC of the present invention.

[0019] Figure 6 It is a timing diagram of a driving circuit based on a dual N power tube DCDC architecture with automatic dead zone switching according to the present invention.

[0020] Figure 7 FIG. 1 is a schematic diagram of a DCDC architecture of dual N power tubes in the prior art.

[0021] Figure 8 This is a schematic diagram of a driving dead zone control circuit in the prior art.

[0022] Figure 9 This is another schematic diagram of a driving dead zone control circuit in the prior art. DETAILED DESCRIPTION

[0023] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0024] like Figure 7 The figure shows the DCDC architecture of the dual N power tube in the prior art. The driving circuit DRIVER of the present invention is Figure 7 The dual-N power tube DCDC architecture includes dual-N power tubes NM1 and NM2, an external inductor L, an external capacitor C0, voltage divider resistors R1 and R2, a high-side tube drive circuit HS_DRIVER, a low-side tube drive circuit LS_DRIVER, a high-voltage power supply VBOOST, and control logic CONTROL LOGIC.

[0025] like Figure 1As shown, a driving circuit with automatic dead zone switching based on a dual N power tube DCDC architecture of the present invention includes a driving circuit DRIVER, a delay chain circuit DEAD_DELAY, a SW failure prevention circuit SW_PROTECT and a sampling logic circuit HSG_SEN_LOGIC. The first input end of the driving circuit DRIVER is connected to the signal HSON, the second input end of the driving circuit DRIVER is connected to the input signal LSG_SEN, the first output end of the driving circuit DRIVER is connected to the input end of the delay chain circuit DEAD_DELAY and generates a signal HSON_PRE, the second output end of the driving circuit DRIVER is connected to the first input end of the SW failure prevention circuit SW_PROTECT and A signal HSG is generated, a first output end of the delay chain circuit DEAD_DELAY is connected to an input end of the sampling logic circuit HSG_SEN_LOGIC, a second output end of the delay chain circuit DEAD_DELAY is connected to a second input end of the SW failure prevention circuit SW_PROTECT and generates a signal HS_DELAY_B, a third input end of the SW failure prevention circuit SW_PROTECT is connected to the input signal LSG_SEN, an output end of the SW failure prevention circuit SW_PROTECT is connected to a second input end of the sampling logic circuit HSG_SEN_LOGIC and generates a signal SW_PRE, and an output end of the sampling logic circuit HSG_SEN_LOGIC generates a signal HSG_SEN.

[0026] The driver circuit DRIVER is responsible for transmitting the input signal HSON to the output signal HSG. The delay chain circuit DEAD_DELAY is responsible for outputting a signal HS_DEAD_B with the same delay as signal HSG through the delay control of delay module DELAY1, which is sent to the sampling logic circuit HSG_SEN_LOGIC for dead-time control. It is also responsible for outputting a signal HS_DELAY_B with a greater delay than signal HSG through the delay control of delay module DELAY2, which is sent to the SW failure prevention circuit SW_PROJECT for signal SW failure protection. The sampling logic circuit HSG_SEN_LOGIC is responsible for determining which of the system input signal SW and the output signal HS_DEAD_B of the delay chain circuit DEAD_DELAY has a longer delay, and uses the longer delayed signal to control the output signal HSG_SEN. Therefore, under light load, the signal SW flips slowly, and the output signal HS_DEAD_B of the fixed delay chain flips faster, and the flip of the signal HSG_SEN is determined by the signal SW; under heavy load, the signal SW flips quickly, and the output signal HS_DEAD_B of the fixed delay chain flips slower, and the flip of the signal HSG_SEN is determined by the signal HS_DEAD_B. After the signal HSG_SEN flips low, it is output to the LS_DRIVER module, which will make the signal LSG flip high, thereby realizing the automatic switching of the dead time. The SW_PROTECT part of the SW failure prevention circuit is responsible for generating a signal SW_PRE that is not limited by the delay of the signal VH, and outputs it to the sampling logic circuit HSG_SEN_LOGIC. It can prevent the signal VH voltage from failing to rise under FPWM, causing the signal SW to be at an intermediate potential, thereby preventing the signal HSG_SEN from flipping erroneously, the signal LSG and the signal HSG from flipping high at the same time, and the system NMOS tubes NM1 and NM2 from being connected in series. The dead zone control timing is as follows Figure 6 As shown in the figure, at time t0, signal HSON turns low. Since the delay time td1 is longer than the time it takes for signal SW to turn low, at time t1, the rising edge of signal HSG_SEN is determined by signal HS_DEAD_B. After receiving signal HS_DEAD_B, LSG turns high after a certain delay. Because signal SW turns low before time t2, the delay of td2 does not participate in the dead-band control.

[0027] like Figure 2As shown, the driving circuit DRIVER includes an inverter INV1, an inverter INV2, an inverter INV4, a NOR gate NOR1 and a level shifter circuit LSF1. The input end of the inverter INV1 is connected to the first input end of the driving circuit DRIVER as the first input end and the signal HSON. The output end of the inverter INV1 is connected to the first input end of the NOR gate NOR1 and generates the signal HSONB. The second input end of the NOR gate NOR1 is connected to the input signal HSON_PRE as the second input end of the driving circuit DRIVER. The output end of the NOR gate NOR1 is connected to the input end of the level shifter circuit LSF1 and serves as the first output end of the driving circuit DRIVER to generate the signal HSON_PRE. The output end of the level shifter circuit LSF1 is connected to the input end of the inverter INV2 and generates the signal HSON_H. The output end of the inverter INV2 is connected to the input end of the inverter INV3 and generates the signal HSONB_H. The output end of the inverter INV3 serves as the second output end of the driving circuit DRIVER and generates the signal HSG.

[0028] The driver circuit DRIVER is responsible for inverting the input signal HSON into a signal HSONB, performing a logical NOR operation with the input signal LSG_SEN, and then boosting the voltage to a signal HSON_H with a high level of VH and a low level of SW. After being driven by two stages of inverters, the output signal HSG is obtained.

[0029] The power supply terminal of the inverter INV1, the power supply terminal of the NOR gate NOR1 and the VDD1 terminal of the level conversion circuit LSF1 are connected to the power supply AVDD, the VDD2 terminal of the level conversion circuit LSF1, the power supply terminal of the inverter INV2 and the power supply terminal of the inverter INV3 are connected to the signal VH, the ground terminal of the inverter INV1, the ground terminal of the NOR gate NOR1 and the VSS1 terminal of the level conversion circuit LSF1 are grounded, and the VSS2 terminal of the level conversion circuit LSF1, the ground terminal of the inverter INV2 and the ground terminal of the inverter INV3 are connected to the signal SW.

[0030] like Figure 3As shown, the delay chain circuit DEAD_DELAY includes a level conversion circuit LSF2, an inverter INV6, a delay module DELAY1, an inverter INV7, a delay module DELAY2 and an inverter INV8. The input end of the level conversion circuit LSF2 is connected to the signal HSON_PRE as the input end of the delay chain circuit DEAD_DELAY. The output end of the level conversion circuit LSF2 is connected to the input end of the inverter INV6 and generates the signal HSON_L. The output end of the inverter INV6 is connected to the input end of the delay module DELAY1 and generates the signal HSONB_ L, the output end of the delay module DELAY1 is connected to the input end of the inverter INV7 and serves as the first output end of the delay chain circuit DEAD_DELAY and generates a signal HS_DEAD_B. The output end of the inverter INV7 is connected to the input end of the delay module DELAY2 and generates a signal HS_DEAD_BB. The output end of the delay module DELAY2 is connected to the input end of the inverter INV8 and generates a signal HS_DELAY. The output end of the inverter INV8 serves as the second output end of the delay chain circuit DEAD_DELAY and generates a signal HS_DELAY_B.

[0031] The delay chain circuit DEAD_DELAY is responsible for converting the signal HSONB from the driver circuit DRIVER and the input signal LSG_SEN or the negated signal HSON_PRE through the same level shifter circuit LSF2 and inverter INV6 as the driver circuit DRIVER, outputting the signal HSONB_L and delaying the analog signal HSONB_H. The delay chain circuit DEAD_DELAY also controls the output signal HS_DEAD_B through the delay module DELAY1, aligning it with the delay of the signal HSG, to provide dead-time control for the sampling logic circuit HSG_SEN_LOGIC. The delay chain circuit DELAY2 also controls the output signal HS_DELAY_B, which has a greater delay than the signal HSG, to provide signal SW failure protection for the SW failure prevention circuit SW_PROJECT.

[0032] The VDD1 terminal of the level conversion circuit LSF2, the VDD2 terminal of the level conversion circuit LSF2, the power supply terminal of the inverter INV6, the power supply terminal of the delay module DELAY1, the power supply terminal of the inverter INV7, the power supply terminal of the delay module DELAY2 and the power supply terminal of the inverter INV8 are connected to the power supply AVDD, and the VSS1 terminal of the level conversion circuit LSF2, the VSS2 terminal of the level conversion circuit LSF2, the ground terminal of the inverter INV6, the ground terminal of the delay module DELAY1, the ground terminal of the inverter INV7, the ground terminal of the delay module DELAY2 and the ground terminal of the inverter INV8 are grounded.

[0033] like Figure 4As shown, the SW failure prevention circuit SW_PROTECT includes an inverter INV5, an AND gate AND1, a PMOS transistor PM1, an NMOS transistor NM3, and an NMOS transistor NM4. The input end of the inverter INV5 is connected to the signal HSG as the first input end of the SW failure prevention circuit SW_PROTECT, the output end of the inverter INV5 is connected to the gate of the PMOS transistor PM1, the source of the PMOS transistor PM1 is connected to the signal VH, the drain of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3, the gate of the NMOS transistor NM3 is connected to the signal PVDD, and the source of the NMOS transistor NM3 is connected to the signal VH. The gate of the AND gate AND1 is connected to the drain of the NMOS transistor NM4 and serves as the output terminal of the SW failure prevention circuit SW_PROTECT to generate the signal SE_PRE. The source of the NMOS transistor NM4 is grounded. The first input terminal of the AND gate AND1 serves as the second input terminal of the SW failure prevention circuit SW_PROTECT and is connected to the signal HS_DELAY_B. The second input terminal of the AND gate AND1 serves as the third input terminal of the SW failure prevention circuit SW_PROTECT and is connected to the input signal LSG_SEN. The output terminal of the AND gate AND1 is connected to the gate of the NMOS transistor NM4 and generates the signal LSON_SEN2.

[0034] The SW_PROTECT circuit generates a signal SW_PRE, which is not delayed by the power supply signal VH, and outputs it to the sampling logic circuit HSG_SEN_LOGIC. When the signal HSG goes high, the signal SW_PRE goes high; when the signal HSG goes low, the signal SW_PRE goes low when the signal LSON_SEN2 goes high.

[0035] A power supply terminal of the inverter INV5 is connected to the signal VH, a ground terminal of the inverter INV5 is connected to the signal SW, a power supply terminal of the AND gate AND1 is connected to the power supply AVDD, and a ground terminal of the AND gate AND1 is grounded.

[0036] like Figure 5As shown, the sampling logic circuit HSG_SEN_LOGIC includes a resistor R3, a resistor R4, a PMOS transistor PM2, a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5, a PMOS transistor PM6, an NMOS transistor NM5, an NMOS transistor NM6, and an NMOS transistor NM7. One end of the resistor R3 is connected to the signal SW, and the other end of the resistor R3 is connected to the gate of the PMOS transistor PM2. The source of the PMOS transistor PM2, the source of the PMOS transistor PM3, the source of the PMOS transistor PM5, and the source of the PMOS transistor PM6 are connected to the power supply PVDD. The gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3 and the source of the PMOS transistor PM4. The gate of the PMOS transistor PM4 is connected to the gate of the NMOS transistor NM5 and serves as the sampling logic circuit HSG_SEN_LOGIC. A second input terminal of the IC is connected to a signal SW_PRE. The drain of the PMOS transistor PM2 is connected to one end of the resistor R4, the gate of the NMOS transistor NM7, and the gate of the PMOS transistor PM5. The other end of the resistor R4 is connected to the drain of the NMOS transistor NM5. The drain of the PMOS transistor PM5 is connected to the drain of the PMOS transistor PM6 and the drain of the NMOS transistor NM6 and serves as the output terminal of the sampling logic circuit HSG_SEN_LOGIC to generate the signal HSG_SEN. The gate of the PMOS transistor PM6 is connected to the gate of the NMOS transistor NM6 and serves as the first input terminal of the sampling logic circuit HSG_SEN_LOGIC to be connected to the signal HS_DEAD_B. The source of the NMOS transistor NM6 is connected to the drain of the NMOS transistor NM7. The source of the NMOS transistor NM5 and the source of the NMOS transistor NM7 are grounded.

[0037] The sampling logic circuit HSG_SEN_LOGIC determines which of the system input signals, signal SW, or the output signal HS_DEAD_B of the delay chain circuit DEAD_DELAY, has a longer delay. The longer-delayed signal controls the output signal HSG_SEN. If signal SW goes low first and signal HS_DEAD_B goes high later, signal HSG_SEN is pulled low after signal HS_DEAD_B goes high. If signal HS_DEAD_B goes high first and signal SW goes low later, signal HSG_SEN is pulled low after signal SW goes low. If signal SW remains high, signal HS_DEAD_B goes high first, and signal HSG_SEN is pulled low after signal SW_PRE goes low.

[0038] The present invention provides a driving circuit with automatic dead-time switching based on a dual-N power tube DCDC architecture. By combining a delay chain and a sampling SW, the circuit automatically selects the delay chain or the sampled SW signal to control the dead-time at different SW flip speeds, thereby reducing the dead-time in the full load range and ensuring no crosstalk, thereby optimizing the overall system efficiency.

[0039] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A driving circuit based on a dual N-power tube DCDC architecture with automatic dead zone switching, characterized by: The system comprises a driving circuit DRIVER, a delay chain circuit DEAD_DELAY, a SW failure prevention circuit SW_PROTECT and a sampling logic circuit HSG_SEN_LOGIC, wherein the first input terminal of the driving circuit DRIVER is connected to the signal HSON, the second input terminal of the driving circuit DRIVER is connected to the input signal LSG_SEN, the first output terminal of the driving circuit DRIVER is connected to the input terminal of the delay chain circuit DEAD_DELAY and generates the signal HSON_PRE, the second output terminal of the driving circuit DRIVER is connected to the first input terminal of the SW failure prevention circuit SW_PROTECT and generates the signal HSG, the delay chain circuit DEAD_ A first output end of DELAY is connected to an input end of the sampling logic circuit HSG_SEN_LOGIC, a second output end of the delay chain circuit DEAD_DELAY is connected to a second input end of the SW failure prevention circuit SW_PROTECT and generates a signal HS_DELAY_B, a third input end of the SW failure prevention circuit SW_PROTECT is connected to the input signal LSG_SEN, an output end of the SW failure prevention circuit SW_PROTECT is connected to a second input end of the sampling logic circuit HSG_SEN_LOGIC and generates a signal SW_PRE, and an output end of the sampling logic circuit HSG_SEN_LOGIC generates a signal HSG_SEN.

2. The driving circuit based on a dual N-power tube DCDC architecture with automatic dead zone switching according to claim 1, characterized in that: The driving circuit DRIVER includes an inverter INV1, an inverter INV2, an inverter INV4, an NOR gate NOR1 and a level shifter circuit LSF1. The input end of the inverter INV1 is connected to the first input end of the driving circuit DRIVER as the first input end and the signal HSON. The output end of the inverter INV1 is connected to the first input end of the NOR gate NOR1 and generates the signal HSONB. The second input end of the NOR gate NOR1 is connected to the input signal HSON_PRE as the second input end of the driving circuit DRIVER. The output end of the NOR gate NOR1 is connected to the input end of the level shifter circuit LSF1 and serves as the first output end of the driving circuit DRIVER to generate the signal HSON_PRE. The output end of the level shifter circuit LSF1 is connected to the input end of the inverter INV2 and generates the signal HSON_H. The output end of the inverter INV2 is connected to the input end of the inverter INV3 and generates the signal HSONB_H. The output end of the inverter INV3 serves as the second output end of the driving circuit DRIVER and generates the signal HSG.

3. The driving circuit based on a dual N-power tube DCDC architecture with automatic dead zone switching according to claim 2, characterized in that: The power supply terminal of the inverter INV1, the power supply terminal of the NOR gate NOR1 and the VDD1 terminal of the level conversion circuit LSF1 are connected to the power supply AVDD, the VDD2 terminal of the level conversion circuit LSF1, the power supply terminal of the inverter INV2 and the power supply terminal of the inverter INV3 are connected to the signal VH, the ground terminal of the inverter INV1, the ground terminal of the NOR gate NOR1 and the VSS1 terminal of the level conversion circuit LSF1 are grounded, and the VSS2 terminal of the level conversion circuit LSF1, the ground terminal of the inverter INV2 and the ground terminal of the inverter INV3 are connected to the signal SW.

4. The driving circuit based on a dual N-power tube DCDC architecture with automatic dead zone switching according to claim 1, characterized in that: The delay chain circuit DEAD_DELAY includes a level conversion circuit LSF2, an inverter INV6, a delay module DELAY1, an inverter INV7, a delay module DELAY2 and an inverter INV8. The input end of the level conversion circuit LSF2 is connected to the signal HSON_PRE as the input end of the delay chain circuit DEAD_DELAY. The output end of the level conversion circuit LSF2 is connected to the input end of the inverter INV6 and generates a signal HSON_L. The output end of the inverter INV6 is connected to the input end of the delay module DELAY1 and generates a signal HSONB_L. The output end of the delay module DELAY1 is connected to the input end of the inverter INV7 and serves as the first output end of the delay chain circuit DEAD_DELAY and generates the signal HS_DEAD_B. The output end of the inverter INV7 is connected to the input end of the delay module DELAY2 and generates the signal HS_DEAD_BB. The output end of the delay module DELAY2 is connected to the input end of the inverter INV8 and generates the signal HS_DELAY. The output end of the inverter INV8 serves as the second output end of the delay chain circuit DEAD_DELAY and generates the signal HS_DELAY_B.

5. The driving circuit based on a dual N-power tube DCDC architecture with automatic dead zone switching according to claim 4, characterized in that: The VDD1 end of the level conversion circuit LSF2, the VDD2 end of the level conversion circuit LSF2, the power supply end of the inverter INV6, the power supply end of the delay module DELAY1, the power supply end of the inverter INV7, the power supply end of the delay module DELAY2 and the power supply end of the inverter INV8 are connected to the power supply AVDD, and the VSS1 end of the level conversion circuit LSF2, the VSS2 end of the level conversion circuit LSF2, the ground end of the inverter INV6, the ground end of the delay module DELAY1, the ground end of the inverter INV7, the ground end of the delay module DELAY2 and the ground end of the inverter INV8 are grounded.

6. The driving circuit based on a dual N-power transistor DCDC architecture with automatic dead zone switching according to claim 1, characterized in that: The SW failure prevention circuit SW_PROTECT includes an inverter INV5, an AND gate AND1, a PMOS transistor PM1, an NMOS transistor NM3, and an NMOS transistor NM4. The input end of the inverter INV5 is connected to the signal HSG as the first input end of the SW failure prevention circuit SW_PROTECT. The output end of the inverter INV5 is connected to the gate of the PMOS transistor PM1. The source of the PMOS transistor PM1 is connected to the signal VH. The drain of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3. The gate of the NMOS transistor NM3 is connected to the signal PVDD. The source of the NMOS transistor NM3 is connected to the signal VH. The gate of the AND gate AND1 is connected to the drain of the NMOS transistor NM4 and serves as the output terminal of the SW failure prevention circuit SW_PROTECT to generate the signal SE_PRE. The source of the NMOS transistor NM4 is grounded. The first input terminal of the AND gate AND1 serves as the second input terminal of the SW failure prevention circuit SW_PROTECT and is connected to the signal HS_DELAY_B. The second input terminal of the AND gate AND1 serves as the third input terminal of the SW failure prevention circuit SW_PROTECT and is connected to the input signal LSG_SEN. The output terminal of the AND gate AND1 is connected to the gate of the NMOS transistor NM4 and generates the signal LSON_SEN2.

7. The driving circuit based on a dual N-power transistor DCDC architecture with automatic dead zone switching according to claim 6, characterized in that: The power supply terminal of the inverter INV5 is connected to the signal VH, the ground terminal of the inverter INV5 is connected to the signal SW, the power supply terminal of the AND gate AND1 is connected to the power supply AVDD, and the ground terminal of the AND gate AND1 is grounded.

8. The driving circuit based on a dual N power tube DCDC architecture with automatic dead zone switching according to claim 1, characterized in that: The sampling logic circuit HSG_SEN_LOGIC includes a resistor R3, a resistor R4, a PMOS transistor PM2, a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5, a PMOS transistor PM6, an NMOS transistor NM5, an NMOS transistor NM6, and an NMOS transistor NM7. One end of the resistor R3 is connected to the signal SW, the other end of the resistor R3 is connected to the gate of the PMOS transistor PM2, the source of the PMOS transistor PM2, the source of the PMOS transistor PM3, the source of the PMOS transistor PM5, and the source of the PMOS transistor PM6 are connected to the power supply PVDD, the gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3 and the source of the PMOS transistor PM4, the gate of the PMOS transistor PM4 is connected to the gate of the NMOS transistor NM5, and serves as the sampling logic circuit HSG_SEN_LOGIC. A second input terminal of the IC is connected to a signal SW_PRE. The drain of the PMOS transistor PM2 is connected to one end of the resistor R4, the gate of the NMOS transistor NM7, and the gate of the PMOS transistor PM5. The other end of the resistor R4 is connected to the drain of the NMOS transistor NM5. The drain of the PMOS transistor PM5 is connected to the drain of the PMOS transistor PM6 and the drain of the NMOS transistor NM6 and serves as the output terminal of the sampling logic circuit HSG_SEN_LOGIC to generate the signal HSG_SEN. The gate of the PMOS transistor PM6 is connected to the gate of the NMOS transistor NM6 and serves as the first input terminal of the sampling logic circuit HSG_SEN_LOGIC to be connected to the signal HS_DEAD_B. The source of the NMOS transistor NM6 is connected to the drain of the NMOS transistor NM7. The source of the NMOS transistor NM5 and the source of the NMOS transistor NM7 are grounded.

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