An edge acceleration circuit capable of self-shutdown

Abstract

The application discloses a self-off edge acceleration circuit, and relates to the technical field of electronics.The edge acceleration circuit comprises a basic circuit, a rising edge acceleration circuit and a falling edge acceleration circuit.The basic circuit comprises a control logic converter and an output end OUT.The control logic converter is opened or closed by an enabling signal, receives an input signal and converts the input signal into an internal signal DATA_n.The rising edge acceleration circuit receives the signal DATA_n, processes the signal DATA_n to obtain a signal PDRI, and sends the signal PDRI to the output end OUT through a MOS tube PM1.The falling edge acceleration circuit receives the signal DATA_n, processes the signal DATA_n to obtain a signal NDRI, and sends the signal NDRI to the output end OUT through a MOS tube NM1.The scheme can effectively solve the influence of slow signal edges under heavy load capacitance conditions, and improve the transmission speed of signals.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and in particular to an edge acceleration circuit capable of self-shutoff. BACKGROUND

[0002] With the development of communication technology, modern electronic systems have higher and higher requirements for signal transmission speed, signal transmission quality and power consumption, and the application environment is also more complex. In order to improve the transmission speed of signals, an edge acceleration circuit can be used to reduce the rising edge / falling edge time of signals. It can effectively solve the problem of slow signal edge under heavy load capacitance and improve the transmission speed of signals. However, due to the existence of P-type MOS tube and N-type MOS tube in the ordinary driving circuit, the power consumption of the circuit is also high under high-speed conditions. In the application of light load capacitance, the transmission quality of signals can be improved without using the edge acceleration circuit, and the probability of electromagnetic interference problem can be reduced. SUMMARY

[0003] Therefore, the present application provides an edge acceleration circuit capable of self-shutoff to effectively solve the problem of slow signal edge under heavy load capacitance and improve the transmission speed of signals.

[0004] The present application provides an edge acceleration circuit capable of self-shutoff, which comprises a basic circuit, a rising edge acceleration circuit and a falling edge acceleration circuit. The basic circuit comprises a control logic converter and an output terminal OUT. The control logic converter is enabled or disabled by an enable signal, receives an input signal and converts it into an internal signal DATA_n. The rising edge acceleration circuit receives the signal DATA_n and processes it to obtain a signal PDRI, which is sent to the output terminal OUT through a MOS tube PM1. The falling edge acceleration circuit receives the signal DATA_n and processes it to obtain a signal NDRI, which is sent to the output terminal OUT through a MOS tube NM1. When the control logic converter is in a disabled state, the MOS tubes PM1 and NM1 are always in a shutdown state, and the edge acceleration circuit remains closed. When the control logic converter is in an enabled state, the edge acceleration circuit is opened.

[0005] For example, in the edge acceleration circuit provided by the present disclosure, the rising edge acceleration circuit receives a signal DATA_n through the common gate terminal of MOS PM2, NM2 and the second input terminal of NOR1; the MOS PM2 is configured to have the source connected to the power supply VCC, the drain connected to the source of MOS PM3, and the input terminal of buffer BUFF1 connected through resistor R1; the MOS PM3 is configured to have the gate connected to the common terminal of inverter INV1 and buffer BUFF2, the output terminal of the buffer BUFF2 connected to the input terminal of the inverter INV1, the drain connected to the source of MOS NM2 and the input terminal of the buffer BUFF1; and the drain of the MOS NM2 is connected to the ground.

[0006] For example, in the edge acceleration circuit provided by the present disclosure, the MOS PM3 receives a signal FB_n and sends a signal NET1; the signal FB_n is sent from the output terminal of the buffer BUFF2 to the input terminal of the inverter INV1; and the signal NET1 is sent from the drain of the MOS PM3 to the source of the MOS NM2 and the input terminal of the buffer BUFF1.

[0007] For example, in the edge acceleration circuit provided by the present disclosure, the output terminal of the buffer BUFF1 is connected to the first input terminal of NOR1; the output terminal of the NOR1 is connected to the first input terminal of NAND1; the output terminal of the NAND1 is connected to the gate of the MOS PM1; the source of the MOS PM1 is connected to the power supply VCC, and the drain is connected to the output terminal OUT of the edge acceleration circuit.

[0008] For example, in the edge acceleration circuit provided by the present disclosure, the output terminal of the buffer BUFF1 sends a signal NET2 to the first input terminal of NOR1; the output terminal of the NOR1 sends a signal NET3 to the first input terminal of NAND1; and the output terminal of the NAND1 sends a signal PDRI to the gate of the MOS PM1.

[0009] For example, in the edge acceleration circuit provided by the present disclosure, the falling edge acceleration circuit receives a signal DATA_n through the common gate terminal of MOS PM4, NM4 and the second input terminal of NAND2; the MOS PM4 is configured to have the source connected to the power supply VCC and the drain connected to the source of MOS NM3; the MOS NM3 is configured to have the gate connected to the output terminal of the inverter INV1, the drain connected to the source of the MOS NM4 and the input terminal of the buffer BUFF3 connected through resistor R2; and the drain of the MOS NM4 is connected to the ground.

[0010] For example, in the edge acceleration circuit provided by the present disclosure, the MOS NM3 receives the signal FB and sends the signal NET4; the signal FB is sent by the inverter INV1 to the gate of the MOS NM3; the signal NET4 is sent by the source of the MOS NM3 to the drain of the MOS PM4 and the input of the buffer BUFF3.

[0011] For example, in the edge acceleration circuit provided by the present disclosure, the output of the buffer BUFF3 is connected to the first input of the NAND2; the output of the NAND2 is connected to the second input of the NOR2; the output of the NOR2 is connected to the gate of the MOS NM1; the drain of the MOS NM1 is grounded, and the source is connected to the output OUT of the edge acceleration circuit and the drain of the MOS PM1.

[0012] For example, in the edge acceleration circuit provided by the present disclosure, the output of the buffer BUFF3 sends the signal NET5 to the first input of the NAND2; the output of the NAND2 sends the signal NET6 to the second input of the NOR2. The output of the NOR2 sends the signal NDRI to the gate of the MOS NM1.

[0013] For example, in the edge acceleration circuit provided by the present disclosure, the output OUT of the edge acceleration circuit is connected to the input of the Schmitt trigger SCHIT1, the output of the Schmitt trigger SCHIT1 is connected to the input of the buffer BUFF2, and the output of the buffer BUFF2 is connected to the second input of the NAND1 and the first input of the NOR2. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0015] Figure 1 is a schematic diagram of an edge acceleration circuit provided by the present disclosure;

[0016] Figure 2 is a schematic diagram of an edge acceleration circuit provided by the present disclosure;

[0017] Figure 3 is a schematic diagram of an edge acceleration circuit provided by the present disclosure; DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0019] In the present application, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitation, the element defined by the statement "including a" does not exclude the presence of another same element in the process, method, article or equipment including the element.

[0020] Embodiments

[0021] As Figure 1 , Figure 1 is a schematic diagram of an edge acceleration circuit, in which the enable signal is responsible for the function of switching the entire module. Due to the difference in control logic design, the enable signal can be high enable or low enable. The input signal is converted into an internal signal DATA_n after passing through the control logic. When the module is in the disabled state, MOS PM1 and NM1 are always in the off state and will not affect the edge of the signal;

[0022] Need further explanation, the Figure 1 all MOS triodes in the present application are represented by characters in the prior art, in which G is the gate, S is the source, and D is the drain.

[0023] Figure 2 is a rising edge acceleration related signal waveform diagram; Figure 3 is a falling edge acceleration related signal waveform diagram. In the case of starting the edge acceleration circuit, the working process of the circuit is as follows, and the waveform diagram of the circuit is as shown in Figure 2 and Figure 3 ;

[0024] The first state

[0025] When the input signal is 0, the output signal is 0, and the state of the internal signal is: signal DATA_n is 1. Signal NET1 is 0, signal NET2 is 0, signal NET3 is 0, signal FB_n is 1, signal PRDI is 1, signal NET4 is 0, signal NET5 is 0, signal NET6 is 1, and signal NDRI is 0.

[0026] According to the above circuit state, MOS tubes PM1, PM3 and NM1 are in the off state, MOS tube NM3 is in the on state, and the entire circuit is in the non-working state.

[0027] The second state

[0028] When the input signal changes from 0 to 1, the output signal also changes from 0 to 1 due to the load capacitance and transmission delay, and the change of the internal signal is: signal DATA_n changes from 1 to 0, signal NET1 changes from 0 to 1 after delay, signal NET2 changes from 0 to 1 after delay, signal NET3 generates a high-level pulse, FB_n changes from 1 to 0 after delay, signal PRDI generates a low-level pulse, signal NET4 changes from 0 to 1, signal NET5 changes from 0 to 1, signal NET6 remains 1, and signal NDRI is 0.

[0029] According to the function, it is divided into rising edge acceleration part and falling edge acceleration part, and the above two parts are analyzed respectively.

[0030] In the above circuit state changes, the signal NET1 is slow to change from 0 to 1 due to the influence of the resistor R1 and the parasitic capacitance in the circuit, and the transmission delay of the signal NET2 to change to 1 is large, so the input signal of the NOR gate NOR1 will exist at the same time for a period of 0, so that the output of the NOR gate NOR1 forms a high level pulse. When the output end OUT does not rise in time due to the external heavy load capacitance, and the Schmidt trigger SCHIT1 exists, the signal FB_n will exist for a period of 1, and when the period of the signal FB_n is 1 overlaps with the high level pulse output by the NOR gate NOR1, the signal PDRI will generate a low level pulse, causing the MOS tube PM1 to open, increasing the driving capability and accelerating the rising of the output end OUT. Before the output end OUT completes the rising, the signal FB_n remains 1, and the MOS tube PM3 remains in a closed state, so that the signal NET1 is still in a slow rising state. When the output end OUT reaches the high level of the Schmidt trigger SCHIT, the signal FB_n changes from 1 to 0, and the NAND gate NAND1 outputs 1 in time, turning off the MOS tube PM1, and the circuit considers that the rising edge of the signal has completed the conversion. At the same time, after the signal FB_n is 0, the MOS tube PM3 is opened, and the resistor R1 is short-circuited, so that the signal NET1 rises rapidly to 1, the signal NET2 changes to 1, and the output signal NET3 of the NOR gate NOR1 changes to 0, and the circuit reaches a stable state.

[0031] In the above circuit state changes, the input signal changes from 0 to 1, and the signal DATA_n changes from 1 to 0. The signal NET4 changes rapidly from 0 to 1, and the signal NET5 changes from 0 to 1. The input signal DATA_n of the NAND gate NAND2 changes before the signal NET5, so the output signal NET6 of the NAND gate NAND2 remains 1, and the output signal NDRI of the NOR gate NOR2 remains 0, keeping the MOS tube NM1 closed. The change of the signal FB_n and the change of the MOS tube NM3 do not affect the above process, but after the output end OUT completes the rising, the MOS tube NM3 is in a closed state.

[0032] From the above analysis, it can be seen that in the process of the MOS tube PM1 opening for edge acceleration, the MOS tube NM1 does not work, so that the MOS tubes PM1 and NM1 are not turned on at the same time, thereby achieving the effect of reducing the dynamic power consumption of the system.

[0033] The third state

[0034] When the input signal is 1 and the output signal is 1, the internal signals are as follows: signal DATA_n is 0, signal NET1 is 1, signal NET2 is 1, signal NET3 is 0, signal FB_n is 0, signal PRDI is 1, signal NET4 is 1, signal NET5 is 1, signal NET6 is 1, and signal NDRI is 0.

[0035] According to the above circuit state, MOS PM1, NM3 and NM1 are in the off state, PM3 is in the on state, and the entire circuit is in the inactive state.

[0036] The fourth state

[0037] When the input signal changes from 1 to 0, the output signal also changes from 1 to 0 due to the load capacitance and transmission delay, and the internal signals change as follows: signal DATA_n changes from 0 to 1, signal NET1 changes from 1 to 0, signal NET2 changes from 1 to 0, signal NET3 remains 0, signal PDRI remains 1, signal NET4 changes from 1 to 0 after a delay, signal NET5 changes from 1 to 0 after a delay, signal NET6 generates a low-level pulse signal, signal FB_n changes from 0 to 1 after a delay, and signal NDRI generates a high-level pulse signal.

[0038] In the above change of circuit state, the input signal changes from 1 to 0, and signal DATA_n changes from 0 to 1. Signal NET1 quickly changes from 1 to 0, and signal NET2 changes from 1 to 0. The input signal DATA_n of NOR1 changes before signal NET2, so the output signal NET3 of NOR1 remains 0, which in turn causes the output signal PDRI of NAND1 to remain 1, keeping MOS PM1 off. The change of signal FB_n and the change of MOS PM3 do not affect the above process, but after the falling is completed, MOS PM3 is in the off state.

[0039] In the above-mentioned change of circuit state, the edge of signal NET4 from 1 to 0 is slow due to the influence of resistor R2 and the parasitic capacitance in the circuit, the transmission delay of signal NET5 to 0 is large, the input signal of NAND gate NAND2 can exist in the period of 1 at the same time, and a low-level pulse is formed at the output of NAND gate NAND2. When the output terminal OUT does not rise in time due to the external heavy load capacitance and the existence of Schmitt trigger SCHIT1, the signal FB_n can exist in the period of 0, and when the period of signal FB_n being 0 overlaps with the low-level pulse output by NAND gate NAND2, a high-level pulse is generated at signal NDRI, which causes MOS transistor NM1 to open, increases the driving capability, and accelerates the falling of OUT. Before the falling of output terminal OUT is completed, signal FB_n remains 0, and MOS transistor NM3 remains in the closed state, so that signal NET4 is still in the slow rising state. When the output terminal OUT reaches the low level of Schmitt trigger SCHIT1, signal FB_n changes from 0 to 1, or NOR gate NOR2 outputs 0 in time, MOS transistor NM1 is turned off, and the circuit considers that the rising edge of the signal has been completed. At the same time, MOS transistor NM3 is turned on after signal FB_n is 1, resistor R2 is short-circuited, signal NET4 rapidly falls to 0, signal NET5 becomes 0, and output signal NET6 of NAND gate NAND2 becomes 1, and the circuit reaches the stable state.

[0040] Through the above-mentioned functional description, the beneficial effects of the present disclosure can be clearly obtained. In the design of the present disclosure, due to the existence of Schmitt trigger SCHIT1 and the global design, the circuit can be self- turned off in time, and the conversion speed of the circuit is improved.

[0041] The skilled person can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized in electronic hardware, computing software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0042] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0043] Obviously, many modifications and variations of the present application are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A self-turn-off edge acceleration circuit, characterized in that, The edge acceleration circuit includes a basic circuit, a rising edge acceleration circuit, and a falling edge acceleration circuit. The basic circuit includes a control logic converter and an output terminal OUT. The control logic converter is enabled or disabled by an enable signal, and receives input signals and converts them into internal signals DATA_n. Specifically, the rising edge acceleration circuit receives the signal DATA_n through the common gate of MOSFETs PM2 and NM2 and the second input of NOR1; MOSFET PM2 is configured such that its source is connected to power supply VCC, its drain is connected to the source of MOSFET PM3 and connected to the input of buffer BUFF1 through resistor R1; MOSFET PM3 is configured such that its gate is connected to the common terminal of inverter INV1 and buffer BUFF2, the output of buffer BUFF2 is connected to the input of inverter INV1, its drain is connected to the source of MOSFET NM2 and the input of buffer BUFF1; the drain of MOSFET NM2 is grounded; the output of buffer BUFF1 is connected to the first input of NOR1; the output of NOR1 is connected to the first input of NAND1; the output of NAND1 is connected to the gate of MOSFET PM1; the source of MOSFET PM1 is connected to power supply VCC, and its drain is connected to the output terminal OUT of the rising edge acceleration circuit; The falling edge acceleration circuit receives the signal DATA_n through the common gate of MOSFETs PM4 and NM4 and the second input of NAND gate NAND2. MOSFET PM4 is configured such that its source is connected to power supply VCC and its drain is connected to the source of MOSFET NM3. MOSFET NM3 is configured such that its gate is connected to the output of inverter INV1 and its drain is connected to the source of MOSFET NM4 and, through resistor R2, to the input of buffer BUFF3. The drain of MOSFET NM4 is grounded. The output of buffer BUFF3 is connected to the first input of NAND gate NAND2. The output of NAND gate NAND2 is connected to the second input of NOR gate NOR2. The output of NOR gate NOR2 is connected to the gate of MOSFET NM1. The drain of MOSFET NM1 is grounded, and its source is connected to the output of the edge acceleration circuit OUT and the drain of MOSFET PM1. The output terminal OUT of the edge acceleration circuit is connected to the input terminal of Schmitt trigger SCHIT1. The output terminal of Schmitt trigger SCHIT1 is connected to the input terminal of buffer BUFF2. The output terminal of buffer BUFF2 is connected to the second input terminal of NAND gate NAND1 and the first input terminal of NOR gate NOR2. When the control logic converter is in a disabled state, MOS transistors PM1 and NM1 are always turned off, and the edge acceleration circuit remains closed; when the control logic converter is in an enabled state, the edge acceleration circuit is turned on.

2. The edge acceleration circuit capable of self-turn-off according to claim 1, characterized in that, The MOS transistor PM3 receives the signal FB_n and sends the signal NET1; The output of the buffer BUFF2 sends the signal FB_n to the input of the inverter INV1. Signal NET1 is sent from the drain of MOSFET PM3 to the source of MOSFET NM2 and then to the input of buffer BUFF1.

3. The edge acceleration circuit capable of self-turn-off according to claim 1, characterized in that, The output of the buffer BUFF1 sends a signal NET2 to the first input of the NOR gate NOR1; The output of the NOR gate NOR1 sends the signal NET3 to the first input of the NAND gate NAND1; The output of the NAND gate NAND1 sends a signal PDRI to the gate of the MOS transistor PM1.

4. The edge acceleration circuit capable of self-turn-off according to claim 1, characterized in that, The MOS transistor NM3 receives signal FB and sends signal NET4; Signal FB: Inverter INV1 sends signal FB to the gate of MOSFET NM3; Signal NET4: The source of MOS transistor NM3 is connected to the drain of MOS transistor PM4 and sends signal NET4 to the input of buffer BUFF3.

5. The edge acceleration circuit capable of self-turn-off according to claim 1, characterized in that, The output of the buffer BUFF3 sends the signal NET5 to the first input of the NAND gate NAND2; The output of the NAND gate NAND2 sends the signal NET6 to the second input of the NOR gate NOR2; The output of the NOR2 gate sends the signal NDRI to the gate of the MOS transistor NM1.

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