Hall switch signal processing circuit and method thereof

Abstract

The application discloses a kind of Hall switch signal processing circuit and method thereof, including Hall module, threshold voltage generation module, amplifier, offset elimination module, comparator and output latch module, Hall signal generated by Hall module is input to offset elimination module after being amplified by amplifier, threshold voltage generation module generates threshold voltage and is sent to offset elimination module, after the offset elimination module after the amplified Hall signal and threshold voltage are removed, it is sent to comparator comparison and is output to output latch module and is latched.The application generates a comparison threshold with the same temperature coefficient and voltage coefficient of Hall induction voltage by the way of resistance voltage division, offsets the influence of temperature and power voltage change, while the application separates Hall signal voltage and offset voltage in frequency domain, and uses the offset elimination circuit of capacitor to offset the influence of offset voltage.

Description

Technical Field

[0001] This invention relates to a signal processing circuit and method, particularly a Hall switch signal processing circuit and method, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] A Hall switch is a type of Hall sensor. It primarily works by comparing an effectively amplified Hall voltage with a reference voltage set in a signal processing circuit, outputting a high or low level to control the on / off state of an output transistor. The high or low level output indicates whether the magnetic field strength has reached a certain level. A typical Hall switch module includes... Figure 3 As shown, it includes a Hall effect device, an amplifier, a comparator, and a latched output. The Hall effect device senses a magnetic field and converts the magnetic signal into a voltage signal. The amplifier amplifies the voltage signal, and then compares the amplified signal with the comparator's threshold voltage. The digital signal output by the comparator is latched and then output.

[0003] Hall devices are generally constructed using N-type semiconductor materials such as N-type epitaxial layers or N-wells. Under a certain magnetic field strength, the relative change rate of the Hall voltage with respect to temperature in a Hall device operating in voltage-driven mode is:

[0004]

[0005] The temperature coefficient of the Hall voltage of a Hall plate under voltage-driven mode actually depends on the temperature coefficient of the carrier mobility of the semiconductor material and the temperature coefficient of the driving voltage.

[0006] The relative change rate of Hall voltage with respect to voltage is:

[0007]

[0008] The Hall effect sensor voltage varies with temperature and power supply voltage, which can introduce significant errors into practical applications or measurements. Therefore, a temperature and power supply voltage compensation circuit must be used to stabilize the Hall effect switch output in response to temperature and power supply voltage changes. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a Hall switch signal processing circuit and method, which realizes power supply voltage and temperature compensation with a simple circuit.

[0010] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0011] A Hall switch signal processing circuit includes a Hall module, a threshold voltage generation module, an amplifier, an offset cancellation module, a comparator, and an output latch module. The amplifier amplifies the Hall signal generated by the Hall module and inputs it to the offset cancellation module. The threshold voltage generation module generates a threshold voltage and sends it to the offset cancellation module. The offset cancellation module clears the offset between the amplified Hall signal and the threshold voltage and sends it to the comparator for comparison before outputting it to the output latch module for latching.

[0012] Furthermore, the Hall module includes a Hall device, switches S0-S3 and switches S8-S11. Terminal A of the Hall device is connected to one end of switch S0 and one end of switch S8. Terminal B of the Hall device is connected to one end of switch S1 and one end of switch S9. Terminal C of the Hall device is connected to one end of switch S2 and one end of switch S10. Terminal D of the Hall device is connected to one end of switch S3 and one end of switch S11. The other ends of switches S0 and S1 are connected to the voltage signal Vhall. The other ends of switches S2 and S3 are grounded. The other ends of switches S8 and S9 are connected to the first input terminal of the amplifier and generate the voltage signal VIN. The other ends of switches S10 and S11 are connected to the second input terminal of the amplifier and generate the voltage signal VIP. Switches S0, S2, S9 and S11 are controlled by the control signal CLK, and switches S1, S3, S8 and S10 are controlled by the control signal CLK'.

[0013] Furthermore, the control signal CLK and the control signal CLK' are a pair of inverted signals.

[0014] Furthermore, the threshold voltage generation module includes resistors R1 to R4 and switches S4 to S7. One end of resistor R1 is connected to power supply VDD, and the other end of resistor R1 is connected to voltage signal Vhall and one end of resistor R2. The other end of resistor R2 is connected to one end of resistor R3, one end of switch S6, and one end of switch S4 to generate threshold voltage Vref2. The other end of resistor R3 is connected to one end of resistor R4, one end of switch S5, and one end of switch S7 to generate threshold voltage Vref1. The other end of resistor R4 is connected to power supply VDD. The other ends of switches S4 and S5 are connected to voltage signal V1. The other ends of switches S6 and S7 are connected to voltage signal V2. Switches S5 and S6 are controlled by control signal CLK, and switches S4 and S7 are controlled by control signal CLK'.

[0015] Furthermore, the offset cancellation module includes capacitors C1 to C4, switches S13 and S14. One end of capacitor C1 is connected to voltage signal V1, one end of capacitor C2 is connected to the first output terminal of the amplifier and generates voltage signal Vout1, one end of capacitor C3 is connected to the second output terminal of the amplifier and generates voltage signal Vout2, one end of capacitor C4 is connected to voltage signal V2, the other end of capacitor C1 is connected to the other end of capacitor C2, one end of switch S12 and the first input terminal of the comparator and generates voltage signal Vx, the other end of capacitor C3 is connected to the other end of capacitor C4, one end of switch S13 and the second input terminal of the comparator and generates voltage signal Vy, the other ends of switch S12 and switch S13 are connected to voltage signal VCM, and switches S12 and S13 are controlled by control signal CLK.

[0016] A Hall switch signal processing method based on a Hall switch signal processing circuit includes the following steps:

[0017] Under a fixed magnetic field B, the magnitude of the Hall voltage generated by the Hall device is:

[0018]

[0019] Among them, S I The current sensitivity of the Hall device, and n is the charge number of the Hall device, q is the electron charge, and d is the thickness of the Hall device; R hall These are the resistance values ​​of the Hall effect device. R1 is the resistance value of resistor R1, R2 is the resistance value of resistor R2, R3 is the resistance value of resistor R3, and R4 is the resistance value of resistor R4. V DD It is the voltage value of the power supply VDD;

[0020] The charge Q on the capacitor at the moment of offset cancellation module reset reset for:

[0021]

[0022] Where C1 is the capacitance of capacitor C1, C2 is the capacitance of capacitor C2, and V x1 It is the voltage value of the voltage signal Vx at the reset moment of the offset cancellation module. ref1 It is the voltage value of the reference voltage Vref1, V out1 It is the voltage value of the voltage signal Vout1 at the reset moment of the offset cancellation module;

[0023] The offset cancellation module compares the charge Q on the capacitor at the time of comparison. comp for:

[0024]

[0025] Among them, Vx2 It is the voltage value of the voltage signal Vx at the comparison moment of the offset cancellation module, V ref2 It is the voltage value of the reference voltage Vref2, V out1’ It is the voltage value of the voltage signal Vout1 at the comparison moment of the offset cancellation module;

[0026] According to the principle of charge conservation, we can obtain:

[0027]

[0028] Let C1=C2=C3=C4, and V x1 =V y1 V y1 It is the voltage value of the voltage signal Vy at the reset moment of the offset cancellation module, from which we can obtain:

[0029]

[0030] Where ΔV is the voltage value V y2 With V x2 The voltage difference, V y2 It is the voltage value of the voltage signal Vy at the comparison moment of the offset cancellation module, V out2 It is the voltage value of the voltage signal Vout2 at the reset moment of the offset cancellation module. out2’ It is the voltage value of the voltage signal Vout2 at the comparison moment of the offset cancellation module;

[0031] Due to Hall voltage V H The offset signal V is modulated to a high frequency. OS At low frequencies, the amplifier's gain is A, resulting in:

[0032]

[0033] Further results were obtained:

[0034]

[0035] The offset signal V is obtained from the above equation. OS The eliminated and amplified signal is sent to the input of the comparator and compared with the difference in the threshold voltage.

[0036] The threshold voltage is:

[0037]

[0038] Since the comparator compares the difference between the amplified signal and the threshold voltage, the difference in the threshold voltage is obtained as follows:

[0039]

[0040] The magnitude of the magnetic field that causes the comparator to flip is characterized as follows:

[0041]

[0042] Where A is the amplifier's amplification factor, and S is the current sensitivity of the Hall device. I The resistance values ​​of resistors R1, R2, R3, and R4 are temperature-dependent, regardless of temperature. By selecting resistors with small temperature coefficients, it is possible to obtain an output reversing magnetic field that does not change with temperature and power supply voltage.

[0043] Compared with the prior art, the present invention has the following advantages and effects:

[0044] 1. This invention uses modulation technology to separate the Hall signal and the offset signal in the frequency domain;

[0045] 2. The offset cancellation circuit of this invention uses capacitors to eliminate the offset of Hall devices and operational amplifiers, resulting in a simple circuit structure and low power consumption;

[0046] 3. This invention uses a resistor voltage divider to generate the comparator threshold voltage, while simultaneously achieving power supply voltage and temperature compensation, thus reducing circuit complexity. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of a Hall switch signal processing circuit according to the present invention.

[0048] Figure 2 This is a circuit diagram of a Hall switch signal processing circuit according to the present invention.

[0049] Figure 3 This is a schematic diagram of a Hall effect switch module in the prior art. Detailed Implementation

[0050] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0051] like Figure 1 and Figure 2As shown, a Hall switch signal processing circuit of the present invention includes a Hall module, a threshold voltage generation module, an amplifier, an offset cancellation module, a comparator, and an output latch module. The amplifier amplifies the Hall signal generated by the Hall module and inputs it to the offset cancellation module. The threshold voltage generation module generates a threshold voltage and sends it to the offset cancellation module. The offset cancellation module clears the offset between the amplified Hall signal and the threshold voltage and sends them to the comparator for comparison before outputting them to the output latch module for latching.

[0052] The Hall module includes Hall devices, switches S0-S3 and switches S8-S11. Terminal A of the Hall device is connected to one end of switch S0 and one end of switch S8. Terminal B of the Hall device is connected to one end of switch S1 and one end of switch S9. Terminal C of the Hall device is connected to one end of switch S2 and one end of switch S10. Terminal D of the Hall device is connected to one end of switch S3 and one end of switch S11. The other ends of switches S0 and S1 are connected to the voltage signal Vhall. The other ends of switches S2 and S3 are grounded. The other ends of switches S8 and S9 are connected to the first input terminal of the amplifier and generate the voltage signal VIN. The other ends of switches S10 and S11 are connected to the second input terminal of the amplifier and generate the voltage signal VIP. Switches S0, S2, S9 and S11 are controlled by the control signal CLK, and switches S1, S3, S8 and S10 are controlled by the control signal CLK'.

[0053] The control signal CLK and the control signal CLK' are a pair of inverted signals.

[0054] The threshold voltage generation module includes resistors R1 to R4 and switches S4 to S7. One end of resistor R1 is connected to the power supply VDD, and the other end of resistor R1 is connected to the voltage signal Vhall and one end of resistor R2. The other end of resistor R2 is connected to one end of resistor R3, one end of switch S6, and one end of switch S4 to generate the threshold voltage Vref2. The other end of resistor R3 is connected to one end of resistor R4, one end of switch S5, and one end of switch S7 to generate the threshold voltage Vref1. The other end of resistor R4 is connected to the power supply VDD. The other ends of switches S4 and S5 are connected to the voltage signal V1. The other ends of switches S6 and S7 are connected to the voltage signal V2. Switches S5 and S6 are controlled by the control signal CLK, and switches S4 and S7 are controlled by the control signal CLK'.

[0055] The offset cancellation module includes capacitors C1 to C4, switches S13 and S14. One end of capacitor C1 is connected to voltage signal V1. One end of capacitor C2 is connected to the first output terminal of the amplifier and generates voltage signal Vout1. One end of capacitor C3 is connected to the second output terminal of the amplifier and generates voltage signal Vout2. One end of capacitor C4 is connected to voltage signal V2. The other end of capacitor C1 is connected to the other end of capacitor C2, one end of switch S12, and the first input terminal of the comparator to generate voltage signal Vx. The other end of capacitor C3 is connected to the other end of capacitor C4, one end of switch S13, and the second input terminal of the comparator to generate voltage signal Vy. The other ends of switches S12 and S13 are connected to voltage signal VCM. Switches S12 and S13 are controlled by control signal CLK.

[0056] A Hall switch signal processing method based on a Hall switch signal processing circuit includes the following steps:

[0057] Hall devices generate Hall signals and offset signals when sensing magnetic fields. The modulation function can separate the offset signal of the Hall signal in the frequency domain and modulate the Hall signal to a high frequency.

[0058] Under a fixed magnetic field B, the magnitude of the Hall voltage generated by the Hall device is:

[0059]

[0060] Among them, S I The current sensitivity of the Hall device, and n is the charge number of the Hall device, q is the electron charge, and d is the thickness of the Hall device; R hall These are the resistance values ​​of the Hall effect device. R1 is the resistance value of resistor R1, R2 is the resistance value of resistor R2, R3 is the resistance value of resistor R3, and R4 is the resistance value of resistor R4. V DD It is the voltage value of the power supply VDD.

[0061] The offset cancellation module has two states: reset and offset cancellation. It completes offset cancellation within one clock cycle. The inputs are the Hall-sensed voltage amplified by the amplifier, the offset signal, and the threshold voltage.

[0062] The charge Q on the capacitor at the moment of offset cancellation module reset reset for:

[0063]

[0064] Where C1 is the capacitance of capacitor C1, C2 is the capacitance of capacitor C2, and V x1 It is the voltage value of the voltage signal Vx at the reset moment of the offset cancellation module. ref1 It is the voltage value of the reference voltage Vref1, Vout1 It is the voltage value of the voltage signal Vout1 at the reset time of the offset cancellation module.

[0065] The offset cancellation module compares the charge Q on the capacitor at the time of comparison. comp for:

[0066]

[0067] Among them, V x2 It is the voltage value of the voltage signal Vx at the comparison moment of the offset cancellation module, V ref2 It is the voltage value of the reference voltage Vref2, V out1’ It is the voltage value of the voltage signal Vout1 at the comparison moment of the offset cancellation module.

[0068] According to the principle of charge conservation, we can obtain:

[0069]

[0070] Let C1=C2=C3=C4, and V x1 =V y1 V y1 It is the voltage value of the voltage signal Vy at the reset moment of the offset cancellation module, from which we can obtain:

[0071]

[0072] Where ΔV is the voltage value V y2 With V x2 The voltage difference, V y2 It is the voltage value of the voltage signal Vy at the comparison moment of the offset cancellation module, V out2 It is the voltage value of the voltage signal Vout2 at the reset moment of the offset cancellation module. out2’ It is the voltage value of the voltage signal Vout2 at the comparison moment of the offset cancellation module.

[0073] Due to Hall voltage V H The offset signal V is modulated to a high frequency. OS At low frequencies, the amplifier's gain is A, resulting in:

[0074]

[0075] Further results were obtained:

[0076]

[0077] The offset signal V is obtained from the above equation. OS The eliminated and amplified signal is sent to the input of the comparator and compared with the difference in threshold voltage.

[0078] The threshold voltage is:

[0079]

[0080] Since the comparator compares the difference between the amplified signal and the threshold voltage, the difference in the threshold voltage is obtained as follows:

[0081]

[0082] The magnitude of the magnetic field that causes the comparator to flip is characterized as follows:

[0083]

[0084] Where A is the amplifier's amplification factor, and S is the current sensitivity of the Hall device. I The resistance values ​​of resistors R1, R2, R3, and R4 are temperature-dependent, regardless of temperature. By selecting resistors with small temperature coefficients, it is possible to obtain an output reversing magnetic field that does not change with temperature and power supply voltage.

[0085] This invention provides a Hall switch signal processing circuit and method. It compensates for temperature and power supply voltage variations in the Hall induced voltage within the comparator's hysteresis window. A comparison threshold with the same temperature and voltage coefficients as the Hall induced voltage is generated using a resistor voltage divider, thus counteracting the effects of temperature and power supply voltage changes. Simultaneously, this invention separates the Hall signal voltage and offset voltage in the frequency domain, employing an offset cancellation circuit composed of capacitors to counteract the influence of the offset voltage.

[0086] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A Hall switch signal processing circuit, characterized by: The application relates to a Hall module, a threshold voltage generating module, an amplifier, an offset cancellation module, a comparator and an output latch module, the Hall module generates a Hall signal which is amplified by the amplifier and input into the offset cancellation module, the threshold voltage generating module generates a threshold voltage which is input into the offset cancellation module, the offset cancellation module removes the offset of the amplified Hall signal and the threshold voltage, and then the Hall signal and the threshold voltage are compared by the comparator and output into the output latch module for latching; the Hall module comprises a Hall device, switches S0-S3 and switches S8-S11, the A end of the Hall device is connected with one end of the switch S0 and one end of the switch S8, the B end of the Hall device is connected with one end of the switch S1 and one end of the switch S9, the C end of the Hall device is connected with one end of the switch S2 and one end of the switch S10, the D end of the Hall device is connected with one end of the switch S3 and one end of the switch S11, the other end of the switch S0 and the other end of the switch S1 are connected with a voltage signal Vhall, the other end of the switch S2 and the other end of the switch S3 are grounded, the other end of the switch S8 and the other end of the switch S9 are connected with a first input end of the amplifier and generate a voltage signal VIN, the other end of the switch S10 and the other end of the switch S11 are connected with a second input end of the amplifier and generate a voltage signal VIP, the switches S0, S2, S9 and S11 are controlled by a control signal CLK, and the switches S1, S3, S8 and S10 are controlled by a control signal CLK'; the threshold voltage generating module comprises resistors R1-R4 and switches S4-S7, one end of the resistor R1 is connected with a power supply VDD, the other end of the resistor R1 is connected with the voltage signal Vhall and one end of the resistor R2, the other end of the resistor R2 is connected with one end of the resistor R3, one end of the switch S6 and one end of the switch S4 and generates a threshold voltage Vref2, the other end of the resistor R3 is connected with one end of the resistor R4, one end of the switch S5 and one end of the switch S7 and generates a threshold voltage Vref1, the other end of the resistor R4 is connected with the power supply VDD, the other end of the switch S4 and the other end of the switch S5 are connected with a voltage signal V1, the other end of the switch S6 and the other end of the switch S7 are connected with a voltage signal V2, the switches S5 and S6 are controlled by the control signal CLK, and the switches S4 and S7 are controlled by the control signal CLK'.

2. A Hall switch signal processing circuit according to claim 1, characterized in that: The control signal CLK and the control signal CLK' are a pair of inverse signals.

3. The Hall switch signal processing circuit according to claim 1, wherein: The imbalance elimination module comprises capacitors C1-C4, switch S13 and switch S14, one end of capacitor C1 is connected with voltage signal V1, one end of capacitor C2 is connected with the first output end of the amplifier and generates voltage signal Vout1, one end of capacitor C3 is connected with the second output end of the amplifier and generates voltage signal Vout2, one end of capacitor C4 is connected with voltage signal V2, the other end of capacitor C1 is connected with the other end of capacitor C2, one end of switch S12 and the first input end of the comparator and generates voltage signal Vx, the other end of capacitor C3 is connected with the other end of capacitor C4, one end of switch S13 and the second input end of the comparator and generates voltage signal Vy, the other end of switch S12 and the other end of switch S13 is connected with voltage signal VCM, and switch S12 and switch S13 are controlled by control signal CLK.

4. A method of processing a Hall switch signal based on the Hall switch signal processing circuit according to any one of claims 1 to 3, characterized by The method comprises the following steps: Under the fixed magnetic field B, the Hall voltage generated by the Hall device is: wherein S I is the current sensitivity of the Hall device, and n is the charge number of the Hall device, q is the electron charge, and d is the thickness of the Hall device; R hall is the resistance value of the Hall device, R1 is the resistance value of the resistor R1, R2 is the resistance value of the resistor R2, R3 is the resistance value of the resistor R3, R4 is the resistance value of the resistor R4, and V DD is the voltage value of the power supply VDD; The charge Q on the capacitor at the reset moment of the disorder elimination module reset is: wherein C1 is a capacitance value of the capacitor C1, C2 is a capacitance value of the capacitor C2, V x1 is a voltage value of the voltage signal Vx at the reset time of the offset cancellation module, V ref1 is a voltage value of the reference voltage Vref1, V out1 is a voltage value of the voltage signal Vout1 at the reset time of the offset cancellation module; The disorder cancellation module compares the charge Q on the time capacitor comp is: wherein V x2 is the voltage value of the voltage signal Vx at the comparison time of the offset cancellation module, V ref2 is the voltage value of the reference voltage Vref2, V out1’ is the voltage value of the voltage signal Vout1 at the comparison time of the offset cancellation module; According to the principle of charge conservation, we can get: Take C1=C2, and V x1 =V y1 , V y1 is the voltage value of the voltage signal Vy at the reset moment of the imbalance elimination module, thus we can get: wherein ΔV is the voltage value V y2 and V x2 is the voltage difference, V y2 is the voltage value of the voltage signal V out2 is the voltage value of the voltage signal V out2’ out2 at the reset time of the offset cancellation module; Since the Hall voltage V H is modulated to high frequencies, the offset signal V OS At low frequencies, the amplification of the amplifier is A, and we obtain: Further obtained: The misadjustment signal V is obtained from the above equation OS The amplified signal is supplied to the input of the comparator, where it is compared with the threshold voltage. The size of the threshold voltage is: Because the comparator compares the difference between the amplified signal and the threshold voltage, the difference of the threshold voltage is: The magnetic field size of the comparator flip is represented as: Wherein, A is the amplification of the amplifier, the current sensitivity S of the Hall device I The resistance values of the resistors R1, R2, R3 and R4 are related to temperature, and the output flipping magnetic field can be obtained without change with temperature and power voltage by selecting the resistors with small temperature coefficient.

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