A capacitor-to-analog converter circuit based on hybrid switching

Abstract

This invention provides a capacitor digital-to-analog converter (CDAC) circuit based on hybrid switching. The circuit includes a high-segment split DAC structure, a mid-segment common-mode voltage-based switching structure, and a low-segment monotonic switching structure working in concert. The high-segment structure includes multiple sets of differentially configured split capacitor units. The top plate of each capacitor set is connected to the output port and the top plate of the bridging capacitor Cb, and the bottom plate is connected to the high-segment sampling switch. The mid-segment structure includes multiple sets of differentially configured capacitors. The top plate of each capacitor set is connected to the top plate of the high-segment capacitors and the top plate of the bridging capacitor Cb, and is also connected to the output port. The bottom plate of each capacitor is connected to the corresponding mid-segment sampling switch. The low-segment structure includes multiple sets of differentially configured capacitors. The top plate of each capacitor is connected to the bottom plate of the bridging capacitor Cb, and the bottom plate of the capacitors is connected to the low-segment sampling switch circuit. This invention's hybrid switching scheme effectively reduces the overall circuit power consumption and design complexity while ensuring the linearity and accuracy of the CDAC.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design, and more particularly to a capacitor-to-analog converter circuit based on hybrid switching. Background Technology

[0002] In the design of capacitor-to-analog converters (CDACs), existing switching architectures face a technical bottleneck that makes it difficult to balance performance metrics. Split-capacitor structures, through differential charge redistribution, significantly reduce switching power consumption while maintaining common-mode voltage stability; however, their complex board routing increases layout design difficulty, leading to significant parasitic effects, especially in high-bit-width applications. Common-mode voltage switching structures, while simple in routing and with clear control logic, require additional common-mode voltage drive circuitry, increasing system power consumption and introducing new design constraints. Monotonic switching structures, while the simplest to implement and with the lowest dynamic power consumption, generate large common-mode voltage jumps during high-bit switching, severely impacting conversion accuracy. These three mainstream switching architectures each have inherent drawbacks, forcing high-precision successive approximation analog-to-digital converter (SAR ADC) designs to make difficult trade-offs between power consumption, area, and performance. This is particularly true in 14-bit and higher resolution applications, where traditional single architectures can no longer meet the stringent requirements of modern low-power chips for energy efficiency and integration. An innovative hybrid architecture is urgently needed to synergistically optimize these key metrics. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention proposes a capacitor-to-analog converter circuit based on hybrid switching. Through the coordinated operation of three different structures and switching methods, multiple optimizations are achieved, including power saving, reduced driving requirements, and area optimization.

[0004] A capacitor-based digital-to-analog converter (CDAC) circuit based on hybrid switching is disclosed. The CDAC circuit comprises a three-segment CDAC architecture working collaboratively: a high-segment split DAC structure, a mid-segment common-mode voltage-based switching structure, and a low-segment monotonic switching structure. The high-segment split DAC structure includes multiple sets of differentially configured split capacitor units, referred to as high-segment split capacitor units. Each set of split capacitor units contains two capacitors of equal capacitance, and the top plates of the two capacitors are connected together and connected to the output port. It is also connected to the bridging capacitor. The top plate and one end of the switch, and the bottom plates of the two capacitors are connected to the high-segment sampling switch circuit; the middle segment structure based on common-mode voltage switching includes multiple sets of differentially configured capacitors, called middle segment capacitors. The top plate of each set of middle segment capacitors is connected to the top plate of the capacitors in the high-segment split capacitor unit and the bridging capacitor. Connect to the top plate and to the output port. The connection involves the base plate of each group of mid-section capacitors being connected to the corresponding mid-section sampling switch; the low-section monotonic switching structure includes multiple groups of differentially configured capacitors, referred to as low-section capacitors, with the top plate of each group of low-section capacitors connected to a bridging capacitor. The base plate is connected to the base plate of each group of low-segment capacitors, and the low-segment sampling switch circuit is connected to the base plate of each group of low-segment capacitors.

[0005] Furthermore, the high-segment sampling switch includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The source of the first PMOS transistor is connected to the high reference voltage VREFH, the drain is connected to the first output port CA_B, and the gate is connected to the first input port CA_UP. The source of the second PMOS transistor is connected to the high reference voltage VREFH, the drain is connected to the second output port CB_B, and the gate is connected to the second input port CB_UP. The source of the first NMOS transistor is connected to the low reference voltage VREFH. The EFL connection is as follows: the drain is connected to the first output port CA_B, and the gate is connected to the third input port CA_DOWN. The source of the second NMOS transistor is connected to the low reference voltage VREFL, the drain is connected to the second output port CB_B, and the gate is connected to the fourth input port CB_DOWN. The source of the third NMOS transistor is connected to the fifth input port VIN, the drain is connected to the first output port CA_B, and the gate is connected to the sixth input port S_EN. The source of the fourth NMOS transistor is connected to the fifth input port VIN, the drain is connected to the second output port CB_B, and the gate is connected to the sixth input port S_EN.

[0006] Furthermore, the sixth input port S_EN is a sampling control signal. When the sixth input port S_EN is high, the CDAC enters the sampling state. The base plate of the high-segment split capacitor is connected to the signal input terminal. The fifth input port VIN is a signal input port. The first input port CA_UP controls the pull-up operation of the first output port CA_B, and the second input port CB_UP controls the pull-up operation of the second output port CB_B. When the first input port CA_UP and the second input port CB_UP are low, the voltage of the first output port CA_B and the second output port CB_B is the high reference voltage VREFH. The third input port CA_DOWN controls the pull-down operation of the first output port CA_B, and the fourth input port CB_DOWN controls the pull-down operation of the second output port CB_B. When the first input port CA_DOWN and the second input port CB_DOWN are high, the voltage of the first output port CA_B and the second output port CB_B is the low reference voltage VREFL.

[0007] Furthermore, the working process of the capacitor digital-to-analog converter circuit is as follows: first, sampling is performed, and after sampling, high-segment DAC comparison, mid-segment DAC comparison and low-segment DAC comparison are performed in sequence.

[0008] Furthermore, during the sampling phase, the top-plate switches of the high-segment split capacitor and the middle-segment capacitor are closed to connect to the common-mode voltage. The base plates of the high-segment split capacitor and the middle-segment capacitor are connected to the input signal ports VINP and VINN, while the top plate of the low-segment capacitor is connected to the bridging capacitor. The base plate of the low-segment capacitors is connected to the high reference voltage VREFH.

[0009] Furthermore, during the high-segment DAC comparison stage, in the first comparison, the base plate of capacitor a in all high-segment split capacitor units is connected to VREFH, the base plate of capacitor b is connected to VREFL, and the base plate of capacitor b in the middle segment is connected to the common-mode voltage. The low-segment capacitors remain unchanged. When the first comparison result is high, all the highest-order capacitors on the P side are connected to VREFH, and all the highest-order capacitors on the N side are connected to VREFL. When the first comparison result is low, all the highest-order capacitors on the P side are connected to VREFL, and all the highest-order capacitors on the N side are connected to VREFH. Then, all the capacitors in the high segment are compared in turn.

[0010] Furthermore, after completing the high-segment DAC comparison, the process moves to the mid-segment DAC comparison stage. During the first mid-segment capacitor comparison, all mid-segment capacitor base plates are connected to common-mode voltage. When the comparison result is high, the first middle capacitor base plate on the P side is connected to VREFH, and the first middle capacitor base plate on the N side is connected to VREFL. When the comparison result is low, the first middle capacitor base plate on the P side is connected to VREFL, and the first middle capacitor base plate on the N side is connected to VREFH. Then, all the middle capacitors are compared in sequence.

[0011] Further, after completing the comparison of the middle-section DAC, the comparison of the low-section DAC begins. The low-section DAC comparison adopts a single-ended switching method. When comparing the first low-section capacitor, all the low-section capacitor base plates are connected to VREFH. When the comparison result is high, the first low-section capacitor base plate on the N side is connected to VREFL, while the P side remains unchanged. When the comparison result is low, the first low-section capacitor base plate on the P side is connected to VREFL, while the N side remains unchanged. Then, the comparison of all low-section capacitors is completed in sequence.

[0012] Furthermore, bridging capacitors Total capacitance of high and mid sections The voltage division relationship formed between them introduces an attenuation coefficient β, which satisfies the following equation:

[0013] ;

[0014] Cdum is a redundant capacitor used to ensure that the capacitance value satisfies the binary relationship.

[0015] Furthermore, the number of bits in the high-segment capacitor, mid-segment capacitor, and low-segment capacitor is dynamically adjusted according to the target number of bits to optimize power consumption and area.

[0016] This invention provides a capacitor-based digital-to-analog converter (CDAC) circuit based on hybrid switching. It is a segmented hybrid CDAC circuit structure. Through the collaborative design of a high-segment split DAC, a mid-segment common-mode voltage-based switching structure, and a low-segment monotonic switching structure, it achieves a balance between high precision, low power consumption, and small area, bringing significant technological advancements to the field of analog-to-digital conversion. Specifically:

[0017] During the conversion process, through the differential symmetrical operation of the high-segment split DAC and the synergistic effect of the mid-segment common-mode voltage network, the charging and discharging operation of large capacitance nodes in the traditional structure is eliminated, reducing the common-mode voltage driving requirements; the high segment adopts a split DAC structure, which reduces the switching power consumption of the high-level capacitor through the charge sharing mechanism and its switching strategy.

[0018] The mid-section capacitor array adopts a simplified binary weighted structure, which reduces wiring complexity and parasitic capacitance compared to the high-section split layout, achieving the best balance between layout area and conversion accuracy.

[0019] The low-end adopts a monotonic single-ended switching scheme, which only needs to change the state of the capacitor on one side (P or N) for each switch, reducing the number of switching actions by more than 50% compared with traditional differential switching, and further saving dynamic power consumption.

[0020] The hybrid switching scheme of this invention effectively reduces the power consumption and design complexity of the overall circuit while ensuring the linearity and accuracy of the CDAC. It is suitable for applications such as high-precision, low-power successive approximation analog-to-digital converters (SAR ADCs), and is especially beneficial for high-resolution, high-energy-efficiency integrated circuit design. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a capacitor digital-to-analog converter circuit based on hybrid switch switching provided in an embodiment of the present invention;

[0023] Figure 2This is a circuit schematic and truth table of the high-segment sampling switch provided in an embodiment of the present invention;

[0024] Figure 3 This is a high-segment split DAC switch switching diagram provided in an embodiment of the present invention;

[0025] Figure 4 This is a mid-process DAC switch switching diagram provided in an embodiment of the present invention;

[0026] Figure 5 This is a low-segment DAC switching diagram of the conversion process provided in an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] This invention provides a CDAC circuit based on hybrid switching, comprising a high-segment split DAC structure, a mid-segment DAC based on common-mode voltage switching, and a low-segment monotonic switching DAC. The three circuits work together, and each segment includes multiple sets of differentially configured capacitors, referred to as high-segment split capacitors, mid-segment capacitors, and low-segment capacitors, respectively. The number of bits of the high-segment split capacitors, mid-segment capacitors, and low-segment capacitors can be dynamically adjusted according to the target number of bits to optimize power consumption and area.

[0029] In this embodiment, a high-segment of 6 bits, a middle-segment of 4 bits, and a low-segment of 6 bits are configured to achieve 16-bit precision analog-to-digital conversion through coordinated operation. The number of bits can be selected and set according to actual needs. A bridging capacitor is used between the low-segment, high-segment, and middle-segment. The attenuation coefficient β is constructed to satisfy the binary ratio between the voltage during low-segment switching and the voltage during mid-segment switching. The high-segment split DAC contains multiple sets of differentially configured split capacitor units, each set consisting of two matched first and second capacitors. The overall circuit principle is as follows: Figure 1 As shown, the CDAC circuit is configured as a differential structure. The capacitors and switches on the positive (P) side and the negative (N) side are the same, but they differ in their switching methods.

[0030] The high-end DAC is a split DAC structure, including the eleventh capacitor a ( ), Eleventh capacitor b ( ), the twelfth capacitor a ( ), the twelfth capacitor b ( ), the thirteenth capacitor a ( ), the thirteenth capacitor b ( ), the fourteenth capacitor a ( ), the fourteenth capacitor b ( ), the fifteenth capacitor a ( ), the fifteenth capacitor b ( ), the sixteenth capacitor a ( ), the sixteenth capacitor b ( In this embodiment, the single-sided high-segment split DAC has a total of 6 split capacitor units. Each split capacitor unit has two perfectly matched equal-value capacitors, namely capacitor a and capacitor b, which are called high-segment split capacitors. The top plate of each high-segment split capacitor is connected to the output port. It is also connected to the bridging capacitor. The top plate and one end of the switch, the other end of the switch is connected to the common-mode voltage. It is used for reset during the sampling stage. The base plate of each high-segment split capacitor is connected to the corresponding high-segment sampling switch. The high-segment sampling switch is connected to different voltages according to different operating states and comparator output results. This structure maintains common-mode voltage stability through split switching operation, without the need for an additional common-mode voltage circuit.

[0031] The high-segment sampling switch includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4. The source of the first PMOS transistor is connected to the high reference voltage VREFH, the drain is connected to the first output port CA_B, and the gate is connected to the first input port CA_UP. The source of the second PMOS transistor is connected to the high reference voltage VREFH, the drain is connected to the second output port CB_B, and the gate is connected to the second input port CB_UP. The source of the first NMOS transistor is connected to the low reference voltage VREFL, the drain is connected to the first output port CA_B, and the gate is connected to the third input port CA_DOWN. The source of the second NMOS transistor is connected to the low reference voltage VREFL, the drain is connected to the second output port CB_B, and the gate is connected to the fourth input port CB_DOWN. The source of the third NMOS transistor is connected to the fifth input port VIN, the drain is connected to the first output port CA_B, and the gate is connected to the sixth input port S_EN. The source of the fourth NMOS transistor is connected to the fifth input port VIN, the drain is connected to the second output port CB_B, and the gate is connected to the sixth input port S_EN. The sixth input port S_EN is the sampling control signal. When the sixth input port S_EN is high, the CDAC enters the sampling state. The base plate of the high-side capacitor is connected to the signal input terminal. The fifth input port VIN is the signal input port. The first input port CA_UP controls the pull-up operation of the first output port CA_B, and the second input port CB_UP controls the pull-up operation of the second output port CB_B. When the first input port CA_UP and the second input port CB_UP are low, the voltages of the first output port CA_B and the second output port CB_B are the high reference voltage VREFH. The third input port CA_DOWN controls the pull-down operation of the first output port CA_B, and the fourth input port CB_DOWN controls the pull-down operation of the second output port CB_B. When the first input port CA_DOWN and the second input port CB_DOWN are high, the voltages of the first output port CA_B and the second output port CB_B are the low reference voltage VREFL. Figure 2 The schematic diagram of the high-level sampling switch is shown, and its truth table is shown in Table 1:

[0032] Table 1 Truth Table of High-Segment Sampling Switch

[0033]

[0034] The mid-section capacitor array employs a simplified binary weighted structure. By introducing a common-mode voltage, during the conversion process, the voltage across the P / N terminals differs from the common-mode voltage. Symmetrical. In this implementation, the mid-section structure contains four sets of capacitor units configured strictly according to binary ratios. The mid-section DAC has four capacitors on one side: the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, and the tenth capacitor C10. The seventh capacitor C7 uses a single-unit capacitance (Cu), and the subsequent capacitors increase strictly according to binary ratios up to 8Cu for C10, i.e., C7=Cu, C8=2Cu, C9=4Cu, C10=8Cu. The top plate of each mid-section capacitor in the mid-section DAC is connected to the output port. Connect, and simultaneously connect the bridging capacitor. The top plate of the main CDAC and the top plate of the high-segment split capacitors form a unified charge-sharing node with the top plate of the high-segment split capacitors. The bridging capacitor is used to segment the main CDAC and generate a voltage division coefficient β for the capacitor voltage division of the low-segment DAC. This allows the capacitor array to be arranged in a non-binary manner, reducing the chip area. The bottom plate of each mid-segment capacitor is connected to the corresponding mid-segment sampling switch. The mid-segment sampling switch switches the capacitor bottom plate voltage according to different operating states and comparator output results. The common-mode voltage switching method of the mid-segment uses a fixed common-mode level. Its structure and control logic are simple, which can reduce the number of switches and traces and reduce parasitic effects. The characteristic of this mid-segment structure is its unique common-mode stabilization mechanism, which introduces an external common-mode voltage. With the help of a sophisticated switching control network, the common-mode level of the differential output signal is effectively maintained during capacitor switching.

[0035] The low-segment is a monotonic switching DAC structure, the core of which lies in the use of a precise binary weighted capacitor array. In this embodiment, the low-segment structure includes six capacitor units with capacitance values ​​progressively increasing in a binary ratio, from the first capacitor C1 (unit capacitance Cu) to the sixth capacitor C6 (32 Cu), doubling sequentially to form a precise weight distribution. A single-sided DAC includes the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6. The top plates of all the low-segment capacitors in the low-segment DAC are connected to a bridging capacitor. The base plate of each low-segment capacitor is connected to its corresponding low-segment switch. The low-segment switch is used to select whether to connect the capacitor base plate to the high reference voltage VREFH or the low reference voltage VREFL. The low-segment sampling switch is connected to different voltages according to different operating states and comparator results. The monotonic switching method of the low segment adopts a unidirectional capacitor switching strategy, which simplifies the control logic and reduces switching losses.

[0036] The capacitance configuration of the high-segment capacitors simultaneously satisfies two constraints: First, the total capacitance of each split unit strictly follows a binary proportional relationship; second, through precisely designed capacitance ratios, the voltage transition during the switch from the high segment to the middle segment ensures that it satisfies a binary weighting relationship, satisfying the following formula:

[0037] ;

[0038] Bridge capacitor Total capacitance of high and mid sections The voltage division relationship formed between them introduces an attenuation coefficient β, which satisfies the following equation:

[0039] ;

[0040] Cdum is a redundant capacitor used to implement coefficients that satisfy the binary relationship. Therefore, the capacitance value of the CDAC system no longer follows the traditional binary multiplication relationship, but is bridged by capacitors. The effective weight is determined by the series voltage divider effect of the total capacitance of the high and middle sections, and the bridging capacitor. The capacitance value is precisely designed, and through the voltage divider effect, the chip area can be significantly reduced.

[0041] The CDAC workflow with hybrid switching is as follows:

[0042] The hybrid CDAC circuit provided by this invention adopts a three-stage switching strategy, and its specific workflow is as follows: During the sampling stage, the top-plate switches of the high-stage capacitor and the middle-stage capacitor are closed to connect to the common-mode voltage. The base plates of the high-segment and mid-segment capacitors are connected to the input signal ports VINP and VINN, while the top plate of the low-segment capacitors is connected to the bridging capacitor. The baseplate of the low-segment capacitors is connected to the high reference voltage VREFH. After sampling, the high-segment DAC comparison begins. During the first comparison, the baseplate of capacitor a in all high-segment split capacitor units is connected to VREFH, the baseplate of capacitor b is connected to VREFL, and the baseplate of the middle-segment capacitors is connected to the common-mode voltage. The low-side capacitors remain unchanged. When the first comparison result is high, all the highest-order capacitors on the P side are connected to VREFH, and all the highest-order capacitors on the N side are connected to VREFL; when the first comparison result is low, all the highest-order capacitors on the P side are connected to VREFL, and all the highest-order capacitors on the N side are connected to VREFH, as shown below. Figure 3 As shown, all capacitors in the high segment are then compared sequentially.

[0043] After completing the high-segment DAC comparison, the mid-segment DAC comparison stage begins. During the first mid-segment capacitor comparison, all mid-segment capacitor base plates are connected to common-mode voltage. When the comparison result is high, the first middle capacitor base plate on the P side is connected to VREFH, and the first middle capacitor base plate on the N side is connected to VREFL; when the comparison result is low, the first middle capacitor base plate on the P side is connected to VREFL, and the first middle capacitor base plate on the N side is connected to VREFH, as shown below. Figure 4 As shown, then all capacitors in the middle section are compared sequentially.

[0044] After completing the mid-range DAC comparison, the low-range DAC comparison stage begins. The low-range DAC comparison uses a single-ended switching method: during the first low-range capacitor comparison, all low-range capacitor base plates are connected to VREFH. When the comparison result is high, the first low-range capacitor base plate on the N-side is connected to VREFL, while the P-side remains unchanged; when the comparison result is low, the first low-range capacitor base plate on the P-side is connected to VREFL, while the N-side remains unchanged. Figure 5 As shown, the comparison of all capacitors in the lower segment is then performed sequentially.

[0045] All the above comparisons are of the P-side voltage after the switch. and N-side voltage Compare them.

[0046] The hybrid CDAC circuit proposed in this invention employs a three-stage collaborative working mechanism, sequentially performing high-segment, mid-segment, and low-segment conversion operations after the sampling phase. The high-segment split DAC starts working first, with its positive and negative (P-side and N-side) split capacitor units using a differential complementary switching method. After entering the conversion phase, only one capacitor in the high-segment split capacitor needs to be switched after each comparator decision. Furthermore, due to the characteristics of the split DAC, no external common-mode voltage is required during conversion. When the conversion enters the mid-segment range, the system automatically switches to a common-mode voltage-based switching method. Both the P-side and N-side of the mid-segment use a common-mode voltage-based switching method. This switching method requires an external common-mode voltage. However, since the capacitance of the driving capacitor is relatively low at this point, the driving requirements for the common-mode voltage are not high. This type of DAC based on common-mode voltage is simpler to lay out than the split-type DAC in the higher segments, effectively reducing parasitic capacitance and improving linearity. Finally, the low-segment monotonic switching stage is entered. This process implements a single-sided switching strategy. After each comparator output decision, the system only performs a reference voltage switching operation on one side (P-side or N-side) of the capacitor array in the differential path, while the other side of the capacitor array remains unchanged. This operating method reduces the number of switching operations by 50% compared to traditional differential switching, while bringing a significant improvement in energy efficiency.

[0047] The entire conversion process achieves efficient and accurate analog-to-digital conversion through this segmented switching strategy. By adopting a segmented hybrid structure and switching strategy, different switching methods are used in the high, middle and low segments to optimize power consumption, wiring complexity and chip area.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A capacitor-to-analog converter circuit based on hybrid switching, characterized in that, The capacitor-to-analog converter circuit includes a three-segment CDAC architecture that works in concert: a high-segment split DAC structure, a mid-segment common-mode voltage switching structure, and a low-segment monotonic switching structure. The high-segment split DAC structure includes multiple sets of differentially configured split capacitor units, referred to as high-segment split capacitor units. Each set of split capacitor units contains two capacitors with equal capacitance values. The top plates of the two capacitors are connected together and connected to the output port. It is also connected to the bridging capacitor. The top plate and one end of the switch, and the bottom plate of the two capacitors are connected to the high-segment sampling switch circuit; The middle section, based on common-mode voltage switching, includes multiple sets of differentially configured capacitors, referred to as middle section capacitors. The top plate of each middle section capacitor set, along with the top plates of the capacitors in the upper section split capacitor unit and bridging capacitors, constitute the middle section. Connect to the top plate and to the output port. The base plate of each group of mid-section capacitors is connected to the corresponding mid-section sampling switch; The low-segment monotonic switching structure includes multiple sets of differentially configured capacitors, referred to as low-segment capacitors. The top plate of each set of low-segment capacitors is connected to a bridging capacitor. The base plate is connected to the base plate of each group of low-segment capacitors, and the low-segment sampling switch circuit is connected to the base plate of each group of low-segment capacitors.

2. The capacitor-to-analog converter circuit based on hybrid switching according to claim 1, characterized in that, The high-segment sampling switch includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The source of the first PMOS transistor is connected to the high reference voltage VREFH, the drain is connected to the first output port CA_B, and the gate is connected to the first input port CA_UP. The source of the second PMOS transistor is connected to the high reference voltage VREFH, the drain is connected to the second output port CB_B, and the gate is connected to the second input port CB_UP. The source of the first NMOS transistor is connected to the low reference voltage VREFL. The connections are as follows: the drain of the second NMOS transistor is connected to the first output port CA_B, and the gate is connected to the third input port CA_DOWN; the source of the second NMOS transistor is connected to the low reference voltage VREFL, the drain is connected to the second output port CB_B, and the gate is connected to the fourth input port CB_DOWN; the source of the third NMOS transistor is connected to the fifth input port VIN, the drain is connected to the first output port CA_B, and the gate is connected to the sixth input port S_EN; the source of the fourth NMOS transistor is connected to the fifth input port VIN, the drain is connected to the second output port CB_B, and the gate is connected to the sixth input port S_EN.

3. The capacitor-to-analog converter circuit based on hybrid switching according to claim 2, characterized in that, The sixth input port S_EN is the sampling control signal. When the sixth input port S_EN is high, the CDAC enters the sampling state. The base plate of the high-segment split capacitor is connected to the signal input terminal. The fifth input port VIN is the signal input port. The first input port CA_UP controls the pull-up operation of the first output port CA_B. The second input port CB_UP controls the pull-up operation of the second output port CB_B. When the first input port CA_UP and the second input port CB_UP are low, the voltage of the first output port CA_B and the second output port CB_B is the high reference voltage VREFH. The third input port CA_DOWN controls the pull-down operation of the first output port CA_B. The fourth input port CB_DOWN controls the pull-down operation of the second output port CB_B. When the first input port CA_DOWN and the second input port CB_DOWN are high, the voltage of the first output port CA_B and the second output port CB_B is the low reference voltage VREFL.

4. The capacitor-to-analog converter circuit based on hybrid switching according to claim 1, characterized in that, The working process of the capacitor-to-digital converter circuit is as follows: first, sampling is performed, and after sampling, high-segment DAC comparison, mid-segment DAC comparison and low-segment DAC comparison are performed in sequence.

5. The capacitor-to-analog converter circuit based on hybrid switching according to claim 4, characterized in that, During the sampling phase, the top-plate switches of the high-segment split capacitor and the middle-segment capacitor are closed to connect to the common-mode voltage. The base plates of the high-segment split capacitor and the middle-segment capacitor are connected to the input signal ports VINP and VINN, while the top plate of the low-segment capacitor is connected to the bridging capacitor. The base plate of the low-segment capacitors is connected to the high reference voltage VREFH.

6. The capacitor-to-analog converter circuit based on hybrid switching according to claim 5, characterized in that, During the high-segment DAC comparison phase, in the first comparison, the base plate of capacitor a in all high-segment split capacitor units is connected to VREFH, the base plate of capacitor b is connected to VREFL, and the base plate of capacitors in the middle segment is connected to the common-mode voltage. The low-segment capacitors remain unchanged. When the first comparison result is high, all the highest-order capacitors on the P side are connected to VREFH, and all the highest-order capacitors on the N side are connected to VREFL. When the first comparison result is low, all the highest-order capacitors on the P side are connected to VREFL, and all the highest-order capacitors on the N side are connected to VREFH. Then, all the capacitors in the high segment are compared in turn.

7. The capacitor-to-analog converter circuit based on hybrid switching according to claim 6, characterized in that, After completing the high-band DAC comparison, the mid-band DAC comparison stage begins. During the first mid-band capacitor comparison, all mid-band capacitor base plates are connected to common-mode voltage. When the comparison result is high, the first middle capacitor base plate on the P side is connected to VREFH, and the first middle capacitor base plate on the N side is connected to VREFL. When the comparison result is low, the first middle capacitor base plate on the P side is connected to VREFL, and the first middle capacitor base plate on the N side is connected to VREFH. Then, all the middle capacitors are compared in sequence.

8. The capacitor-to-analog converter circuit based on hybrid switching according to claim 7, characterized in that, After completing the comparison of the mid-section DAC, the low-section DAC comparison stage begins. The low-section DAC comparison uses a single-ended switching method. When comparing the first low-section capacitor, all low-section capacitor base plates are connected to VREFH. When the comparison result is high, the first low-section capacitor base plate on the N side is connected to VREFL, while the P side remains unchanged. When the comparison result is low, the first low-section capacitor base plate on the P side is connected to VREFL, while the N side remains unchanged. Then, the comparison of all low-section capacitors is completed in sequence.

9. The capacitor-to-analog converter circuit based on hybrid switching according to claim 1, characterized in that, Bridge capacitor Total capacitance of high and mid sections The voltage division relationship formed between them introduces an attenuation coefficient β, which satisfies: Where Cdum is a redundant capacitor used to ensure that the capacitance value satisfies the binary relationship.

10. The capacitor-to-analog converter circuit based on hybrid switching according to claim 1, characterized in that, The number of bits in the high-segment split capacitor, middle-segment capacitor, and low-segment capacitor is dynamically adjusted according to the target number of bits to optimize power consumption and area.

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