Memory cell, memory array and preparation method thereof, memory and electronic equipment

Abstract

The invention provides a memory cell, a memory array and a preparation method thereof, a memory and electronic equipment, relates to the technical field of semiconductors, and aims to solve the problem of how to improve the memory density of the memory. The memory cell comprises a first conductor structure, a first semiconductor layer, a grid electrode, a first electric structure and a first insulating layer, the first semiconductor layer is arranged on one side of the first conductor structure, is connected with the first conductor structure and extends along the vertical direction of the first conductor structure; the grid electrode is arranged on at least one side of the first semiconductor layer in a plane parallel to the first conductor structure; the first electric structure is at least partially arranged on the side, away from the first conductor structure, of the first semiconductor layer; the first insulating layer is arranged between the grid electrode and the first semiconductor layer and between the first electric structure and the first semiconductor layer; the first electrical structure, the first semiconductor layer, and the first insulating layer form a structure that stores charges. The storage unit is used for storing data.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory cell, a memory array, a method for preparing the same, a memory, and an electronic device. Background Art

[0002] In recent years, technologies like the Internet of Things and artificial intelligence have entered a golden age of rapid development. The implementation of these emerging technologies has ushered in an era of intelligent connectivity. They not only bring new and convenient experiences to people's lives, but also significantly improve production efficiency in industrial applications, thereby generating higher-quality and efficient economic benefits. The further application and integration of these emerging technologies require massive amounts of data, which places higher demands on the storage density of memory, one of the most critical components in modern information systems.

[0003] In existing technology, dynamic random access memory (DRAM) consists of a transistor and a capacitor. The transistor controls the capacitor's charge storage to store data. However, because the capacitor's capacitance must be large enough to ensure the accuracy of stored data, further miniaturization of the capacitor to increase memory density is difficult.

[0004] Therefore, how to improve the storage density of memory is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Embodiments of the present application provide a memory cell, a memory array, a method for manufacturing the same, a memory, and an electronic device to solve the problem of how to improve the storage density of the memory.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a storage unit, which includes a first conductor structure, a first semiconductor layer, a gate, a first electrical structure and a first insulating layer; the first semiconductor layer is arranged on one side of the first conductor structure, connected to the first conductor structure, and extends along a vertical direction of the first conductor structure; the gate is arranged on at least one side of the first semiconductor layer in a plane parallel to the first conductor structure; the first electrical structure is at least partially arranged on a side of the first semiconductor layer away from the first conductor structure; the first insulating layer is arranged between the gate and the first semiconductor layer, and between the first electrical structure and the first semiconductor layer; the first electrical structure, the first semiconductor layer and the first insulating layer form a structure for storing charge.

[0008] The first electrical structure, the first semiconductor layer, and the first insulating layer form a charge storage structure. Whether charge is stored in the structure, and the amount of stored charge, can be used to represent stored data. The first semiconductor layer extends perpendicular to the first conductor structure. The gate is disposed on at least one side of the first semiconductor layer in a plane parallel to the first conductor structure. The portion of the first semiconductor layer corresponding to the gate forms a channel. The gate can control the conduction state of the channel. In other words, the gate can control the conductive path between an end of the first semiconductor layer proximate to the first conductor structure and an end of the first semiconductor layer proximate to the first electrical structure. This allows the gate to control the charging or discharging of the charge storage structure, thereby enabling reading and writing of the memory cell.

[0009] The structure for storing charge utilizes a portion of the first semiconductor layer. At the same time, the first electrical structure is arranged on a side of the first semiconductor layer away from the first conductor structure, and the first insulating layer is arranged between the first electrical structure and the first semiconductor layer, that is, the first electrical structure, the first semiconductor layer and the first insulating layer are stacked, thereby reducing the occupied area in the stacking direction and improving the integration density of the storage unit.

[0010] In one possible implementation of the first aspect, the first electrical structure includes a first conductive layer, and the first conductive layer, the first semiconductor layer, and the first insulating layer form a capacitor. Thus, the first conductive layer and the first semiconductor layer form two opposing electrodes, with the first insulating layer disposed therebetween, thereby forming a capacitor for storing charge.

[0011] In one possible implementation of the first aspect, the memory cell further includes a second insulating layer disposed between the first semiconductor layer and the first conductive layer; and / or the memory cell further includes a third insulating layer disposed between the gate and the first semiconductor layer. In this manner, by disposing the second insulating layer between the first semiconductor layer and the first conductive layer and selecting a suitable dielectric material for the second insulating layer, the dielectric constant of the insulating material between the two electrodes of the capacitor can be increased, thereby increasing the capacitance of the capacitor and facilitating improved performance of the memory cell. By disposing the third insulating layer between the gate and the first semiconductor layer and selecting a suitable material for the third insulating layer, the gate's ability to control the portion of the first semiconductor layer corresponding to the gate can be enhanced.

[0012] In one possible implementation of the first aspect, one end of the first semiconductor layer extends into the first conductive layer. This increases the area of ​​the first semiconductor layer relative to the first conductive layer, thereby increasing the area of ​​the electrodes of the capacitor relative to each other, thereby increasing the capacitance of the capacitor and improving the performance and reliability of the memory cell.

[0013] In one possible implementation of the first aspect, the first electrical structure includes a second semiconductor layer, a first electrode, and a second electrode; the second semiconductor layer is disposed on a side of the first semiconductor layer away from the first conductor structure, and a portion of the first insulating layer is located between the first semiconductor layer and the second semiconductor layer; the first electrode and the second electrode are disposed on a side of the second semiconductor layer near the first conductor structure, respectively connected to the second semiconductor layer, and the first electrode and the second electrode are respectively located on either side of the first semiconductor layer in a direction parallel to the second semiconductor layer. Thus, a portion of the first semiconductor layer near the second semiconductor layer, the first insulating layer, the second semiconductor layer, the first electrode, and the second electrode form a storage transistor, wherein a portion of the first semiconductor layer near the second semiconductor layer serves as a gate, the first insulating layer serves as a gate dielectric layer, a portion of the second semiconductor layer opposite the first semiconductor layer serves as a channel, and the first electrode and the second electrode serve as the source and drain of the storage transistor, respectively. Thus, the conduction state of the storage transistor can be controlled by the first semiconductor layer, and the conduction state of the storage transistor represents stored data.

[0014] In one possible implementation of the first aspect, the memory cell further includes an electrode plate, the electrode plate being disposed on at least one side of the first semiconductor layer, a portion of the first insulating layer being disposed between the electrode plate and the first semiconductor layer, and the electrode plate being located between the gate and the second semiconductor layer. Thus, the portion of the first semiconductor layer corresponding to the electrode plate, the first insulating layer, and the electrode plate form a capacitor capable of storing charge. The charge stored in this capacitor enhances the ability of the portion of the first semiconductor layer near the second semiconductor layer to control the conduction state of the memory transistor, thereby improving the performance of the memory cell.

[0015] In one possible implementation of the first aspect, by increasing the dimension of the electrode plate in a direction perpendicular to the first conductor structure, for example, by increasing the dimension of the electrode plate in a direction perpendicular to the first conductor structure to be larger than the dimension of the gate electrode in the direction perpendicular to the first conductor structure, the capacitance of the capacitor formed by the first semiconductor layer and the electrode plate can be increased, thereby improving the performance of the memory cell.

[0016] In one possible implementation of the first aspect, the first semiconductor layer includes a bottom and sidewalls, the sidewalls extending perpendicularly to the first conductor structure, and the bottom connected to an end of the sidewall distal from the first conductor structure. The gate is disposed on at least one side of the sidewall. In this manner, the portion of the first conductor structure corresponding to the gate serves as the sidewall, thereby enhancing the gate's ability to control the first semiconductor layer.

[0017] In one possible implementation of the first aspect, the first insulating layer includes a first portion and a second portion, the first portion being located between a sidewall of the first semiconductor layer and the gate, the second portion being located between the first electrical structure and a bottom of the first semiconductor layer, and the first portion and the second portion being connected. The first insulating layer can be integrally provided, and thus the first insulating layer can be formed using the same process, thereby reducing process steps.

[0018] In one possible implementation of the first aspect, the sidewalls of the first semiconductor layer are cylindrical, and the gate and the first insulating layer are disposed around the sidewalls. The memory cell further includes a filler disposed at the bottom of the first semiconductor layer, away from the first electrical structure, and surrounded by the sidewalls of the first semiconductor layer. The provision of the filler increases the area of ​​the bottom of the first semiconductor layer, thereby increasing the charge storage capacity of the structure formed by the bottom of the first semiconductor layer, the first electrical structure, and the first insulating layer, thereby improving the performance and reliability of the memory cell.

[0019] In one possible implementation of the first aspect, the material of the first semiconductor layer includes an oxide semiconductor. Oxide semiconductors have lower leakage current than silicon. Therefore, for the same storage time, controlling the charge and discharge of the charge storage structure through a channel formed by the oxide semiconductor can reduce the charge storage capacity of the charge storage structure, thereby facilitating further miniaturization of the memory cell and increasing the density of the memory cell.

[0020] In a second aspect, the present application provides a memory array comprising a plurality of memory cells arranged in an array, wherein the memory cells are any of the memory cells described in the first aspect. The gates of the memory cells in each row are connected to a word line, and the first conductor structures of the memory cells in each column are connected to form a bit line. Because the memory array utilizes the memory cells described in the first aspect, the storage density of the memory array can be increased.

[0021] In one possible implementation of the second aspect, the memory array includes multiple sub-memory arrays, which are stacked vertically along the first conductive structure of the memory cells. Each sub-memory array includes multiple memory cells arranged in an array. In this manner, a three-dimensional memory array can be formed through the stacking, thereby increasing the storage density of the memory array.

[0022] In one possible implementation of the second aspect, the first electrical structure of the memory cell includes a first conductive layer. In two memory cells adjacently disposed in a direction perpendicular to the first conductive structure, the first conductive layer of one memory cell serves as the first conductive structure of the other memory cell. In this manner, when forming a memory array, the first conductive layer of one of two adjacent sub-memory arrays and the first conductive structure of the other memory cell can be formed simultaneously, thereby reducing process steps and improving production efficiency.

[0023] In one possible implementation of the second aspect, the first electrical structure of the memory cell includes a first conductive layer. Multiple memory cells in the same sub-memory array share the same first conductive layer, and the first conductive layer extends along the rows and columns in which the multiple memory cells are arranged. In this manner, the first conductive layer can be directly formed using a semiconductor process, eliminating the need for additional semiconductor processes to form multiple columns after depositing the material forming the first conductive layer, thereby simplifying the formation process.

[0024] In a third aspect, the present application provides a memory comprising a control circuit and a memory array as described in any one of the second aspects, wherein the control circuit is connected to the memory array. Since the memory array used has a high storage density, the memory also has a high storage density.

[0025] In one possible implementation of the third aspect, the control circuit further includes a read circuit and a first transistor, wherein the gate of the first transistor is connected to the bit line, and the first electrode of the first transistor is connected to the read circuit. Thus, when reading the memory cell, the voltage applied to the bit line by the memory cell can control the conduction state of the first transistor, so that the read circuit can obtain data stored in the memory cell based on the conduction state of the first transistor.

[0026] In one possible implementation of the third aspect, the control circuit further includes a write circuit and a second transistor, wherein a gate of the second transistor is configured to receive a control signal from the control circuit, a first electrode of the second transistor is connected to the write circuit, and a second electrode of the second transistor is connected to a bit line. When reading data, the second transistor can receive the control signal to disconnect the write circuit, thereby preventing stored charge in the memory cell from leaking from the write circuit via the bit line, thereby improving the accuracy of the read data.

[0027] In one possible implementation of the third aspect, the second transistor is an oxide semiconductor transistor. This can reduce or avoid the impact of leakage current of the second transistor on the electrical signal on the word line, that is, reduce or avoid the impact on the conduction state of the first transistor, and improve the accuracy of the read data.

[0028] In a fourth aspect, the present application provides a method for preparing a memory array, comprising forming a first electrical structure on a substrate; forming a first dielectric layer and a gate on a side of the first electrical structure away from the substrate, the gate being embedded in the first dielectric layer; forming a through-hole extending vertically through the gate along the substrate; sequentially forming a first insulating layer and a first semiconductor layer in the through-hole; and forming a first conductor structure on a side of the first dielectric layer away from the substrate, the first conductor structure being connected to the first semiconductor layer. Thus, the first conductor structure, the first semiconductor layer, the gate, the first electrical structure, and the first insulating layer can form a memory cell, and the first conductor structure, the first semiconductor layer, the gate, the first electrical structure, and the first insulating layer are stacked, thereby reducing the area occupied by the memory cells in the stacking direction of the memory array, thereby forming a memory array with a high storage density.

[0029] In a fifth aspect, the present application provides an electronic device comprising a printed circuit board and a memory as described in any one of the third aspects, wherein the memory is disposed on the printed circuit board. Since the memory used in the electronic device has a high storage density, the electronic device can also have a large storage capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A structural block diagram of an electronic device provided in an embodiment of the present application;

[0031] Figure 2 A structural block diagram of a memory provided in an embodiment of the present application;

[0032] Figure 3 A schematic structural diagram of a storage unit provided in an embodiment of the present application;

[0033] Figure 4 A schematic structural diagram of another storage unit provided in an embodiment of the present application;

[0034] Figure 5 For the Figure 3 Schematic diagram of the cross-section structure along line AA;

[0035] Figure 6 A schematic structural diagram of another storage unit provided in an embodiment of the present application;

[0036] Figure 7 For the Figure 6 Schematic diagram of the cross-sectional structure of the middle BB line;

[0037] Figure 8 For the Figure 3 Schematic diagram of another possible cross-sectional structure of line AA;

[0038] Figure 9 For the Figure 3 Another possible cross-sectional structure diagram of line AA;

[0039] Figure 10 A schematic structural diagram of another storage unit provided in an embodiment of the present application;

[0040] Figure 11 For the Figure 10 Schematic diagram of the cross-section structure of the CC line;

[0041] Figure 12 A circuit schematic diagram of a storage unit provided in an embodiment of the present application;

[0042] Figure 13 A schematic structural diagram of another storage unit provided in an embodiment of the present application;

[0043] Figure 14 A schematic structural diagram of another storage unit provided in an embodiment of the present application;

[0044] Figure 15 A schematic structural diagram of another storage unit provided in an embodiment of the present application;

[0045] Figure 16 A schematic structural diagram of another storage unit provided in an embodiment of the present application;

[0046] Figure 17 A schematic structural diagram of another storage unit provided in an embodiment of the present application;

[0047] Figure 18 A circuit schematic diagram of another memory cell provided in an embodiment of the present application;

[0048] Figure 19 A schematic structural diagram of another storage unit provided in an embodiment of the present application;

[0049] Figure 20 A circuit schematic diagram of another memory cell provided in an embodiment of the present application;

[0050] Figure 21 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0051] Figure 22 A schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0052] Figure 23 A schematic diagram of a partial circuit structure of a memory provided in an embodiment of the present application;

[0053] Figure 24 A flow chart of a method for preparing a memory array provided in an embodiment of the present application;

[0054] Figures 25 to 31This is a schematic diagram of the structure of each step in the preparation process of the storage array provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] Unless otherwise defined, the technical or scientific terms used in this application should have the usual meanings understood by those skilled in the art. The terms "first", "second", "third" and similar words used in this specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Thus, features defined as "first", "second", and "third" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, "multiple" means two or more.

[0056] The directional terms such as "left", "right", "up" and "down" are defined relative to the orientation of the device schematically placed in the accompanying drawings. It should be understood that these directional terms are relative concepts. They are used for relative descriptions and clarifications, and they may change accordingly according to changes in the orientation of the chip or semiconductor packaging structure.

[0057] Figure 1 The following is a schematic diagram of the structure of an electronic device 200 provided in an embodiment of the present application. The electronic device 200 can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The electronic device 200 may include a printed circuit board (PCB) 250, on which a bus 205 and a system on chip (SoC) 210 connected to the bus 205 may be provided.

[0058] The system on chip 210 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the system on chip 210 may include one or more processors, such as an application processor (AP) 211 for processing application data and a graphics processing unit (GPU) 212 for processing image data. The system on chip 210 may also include a first random access memory (RAM) 213 for caching high-speed data. The first random access memory 213 may be connected to the processor of the system on chip 210. The first random access memory 213 may be a static random access memory (SRAM) or an embedded flash memory (EFlash).

[0059] The application processor 211, image processing unit 212, and first random access memory 213 may be integrated into a single die or may be provided on multiple dies. For example, the application processor 211 and first random access memory 213 are each formed on a single die and then packaged together. For example, the application processor 211 may include multiple dies, which are also packaged together to form the application processor 211.

[0060] The electronic device 200 may further include a second random access memory 220 connected to the system-on-chip 210 via the bus 205. The second random access memory 220 may also be disposed on the printed circuit board 250. The second random access memory 220 may be a dynamic random access memory (DRAM). The second random access memory 220 may be used to store volatile data, such as temporary data generated by the system-on-chip 210. The storage capacity of the second random access memory 220 is generally greater than that of the first random access memory 213, but the read speed is generally slower than that of the first random access memory 213.

[0061] In addition, the electronic device 200 may further include a communication chip 230 and a power management chip 240 connected to the system on chip 210 via a bus 205. The communication chip 230 and the power management chip 240 may also be provided on a printed circuit board 250. The communication chip 230 may be used for processing the protocol stack, or for amplifying, filtering, and other processing of analog radio frequency signals, or for simultaneously implementing the above functions. The power management chip 240 may be used to power other chips. In one embodiment, the system on chip 210 and the second random access memory 220 may be packaged in a packaging structure, such as using a 2.5D (dimension) or 3D packaging, to obtain a faster data transmission rate between chips.

[0062] Figure 2 Schematic diagram of the structure of a memory 300 provided in an embodiment of the present application. In one embodiment, the memory 300 may be as follows Figure 1 The first random access memory 213 shown may also be the second random access memory 220. This application does not limit the application scenario of the memory 300.

[0063] The memory 300 includes a memory array 400 and a control circuit 310 , and the control circuit 310 is connected to the memory array 400 .

[0064] In some embodiments, the memory array 400 includes a plurality of memory cells 100 arranged in an array. For example, the memory cells 100 may be arranged in a three-dimensional array. The memory cell 100 may store 1 bit (bit) or multiple bits of data. The memory array 400 may further include signal lines such as word lines (WL) and bit lines (BL). Each memory cell 100 is connected to a corresponding signal line. One or more of the above signal lines may be used to select the memory cell 100 to be read or written in the memory array 400 by receiving a control level output by a controller, thereby implementing read and write operations on the memory cell 100.

[0065] The control circuit 310 may include one or more peripheral circuits including a decoder 320, a driver 330, a timing controller 340, a read circuit 370, a write circuit 380, a buffer 350, or an input / output driver 360. The decoder 320 is used to decode the address of the memory cell 100. The decoder 320 decodes the received address to determine the memory cell 100 to be accessed. The driver 330 controls the level of the signal line based on the decoding result generated by the decoder 320, thereby enabling access to the specified memory cell 100. The read circuit 370 is used to perform read operations on the memory cell 100. The read circuit 370 may include a sense amplifier that amplifies the electrical signal output by the memory cell 100. The write circuit 380 is used to perform write operations on the memory cell 100. The buffer 350 is used to cache read data, for example, using a FIFO (first-in, first-out) buffering mechanism. The timing controller 340 is used to control the timing of the buffer 350 and control the driver 330 to drive the signal lines in the memory array 400. The input / output driver 360 is used to drive transmission signals, such as received data signals and data signals to be transmitted, so that the data signals can be transmitted over long distances. The memory array 400, decoder 320, driver 330, timing controller 340, read circuit 370, write circuit 380, buffer 350, and input / output driver 360 can be integrated into a single die or integrated into multiple dies.

[0066] In order to improve the performance of the memory 300, such as storage density, the present embodiment proposes a memory unit 100. Figure 3 , Figure 3 1 is a schematic structural diagram of the storage unit 100 .

[0067] Memory cell 100 may be disposed on substrate 111 and include a first conductor structure 112, a first semiconductor layer 120, a gate 113, a first electrical structure 140, and a first insulating layer 130. First conductor structure 112 may extend in a plane parallel to substrate 111. First semiconductor layer 120 is disposed on one side of first conductor structure 112 and connected to the first conductor structure 112. First semiconductor layer 120 extends perpendicular to first conductor structure 112. Gate 113 is disposed on at least one side of first semiconductor layer 120 in a plane parallel to first conductor structure 112. First electrical structure 140 is at least partially disposed on a side of first semiconductor layer 120 facing away from first conductor structure 112. First insulating layer 130 is disposed between gate 113 and first semiconductor layer 120, and between first electrical structure 140 and first semiconductor layer 120. First electrical structure 140, first semiconductor layer 120, and first insulating layer 130 form a structure for storing charge.

[0068] Because the first electrical structure 140, the first semiconductor layer 120, and the first insulating layer 130 form a structure capable of storing charge, the stored data can be represented by whether the charge storage structure stores charge or the amount of charge stored, that is, the state of the stored charge. Furthermore, the first semiconductor layer 120 of the memory cell 100 extends perpendicular to the first conductor structure 112. In a plane parallel to the first conductor structure 112, the gate 113 is disposed on at least one side of the first semiconductor layer 120. Therefore, the gate 113 can be used to control the conductive path between an end of the first semiconductor layer 120 proximate to the first conductor structure 112 and an end of the first semiconductor layer 120 proximate to the first electrical structure 140. Thus, the gate 113 can be used to control the charging or discharging of the charge storage structure, changing the state of the charge stored in the structure and enabling reading and writing of the memory cell 100.

[0069] In addition, the charge storage structure utilizes a portion of the first semiconductor layer 120. Furthermore, the first electrical structure 140 is disposed on a side of the first semiconductor layer 120 away from the first conductor structure 112, and the first insulating layer 130 is disposed between the first electrical structure 140 and the first semiconductor layer 120. That is, the first semiconductor layer 120, the first insulating layer 130, and the first electrical structure 140 are stacked, thereby reducing the occupied area on the substrate 111 plane and improving the integration density of the memory cell 100.

[0070] For the convenience of further description, the following Figure 3 In the coordinate system, the Y direction is along the thickness direction of the substrate 111 , and the XZ plane is perpendicular to the Y direction, that is, the XZ plane is parallel to the plane where the substrate 111 is located.

[0071] The first semiconductor layer 120 extends along a direction perpendicular to the first conductor structure 112. Since the first conductor structure 112 is parallel to the substrate 111, the first semiconductor layer 120 extending along the direction perpendicular to the first conductor structure 112 is perpendicular to the substrate 111, that is, the first semiconductor layer 120 extends along the Y direction. It should be noted that, unless otherwise specified, the terms "perpendicular" or "along the Y direction" in this application refer to "approximately perpendicular" or "approximately along the Y direction," etc. This is not strictly limited in this application and may vary depending on the process technology node. For example, the first semiconductor layer 120 extending along the direction perpendicular to the first conductor structure 112 may be such that the angle between the direction of extension of the first conductor structure 112 and the direction perpendicular to the first conductor structure 112 varies within a certain angular range, such as ±10°, ±20°, or ±30°.

[0072] The first conductor structure 112 can be made of a conductive material such as a metal or a metal compound, for example, titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (WN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), tungsten (W), ruthenium (Ru), molybdenum (Mo), iridium (Ir), nickel (Ni), platinum (Pt), palladium (Pd), ruthenium oxide (RuO), iridium oxide (IrO), indium tin oxide (ITO), etc.

[0073] The first semiconductor layer 120 is connected to the first conductor structure 112. For example, the first semiconductor layer 120 and the first conductor structure 112 may be in direct contact. For example, the first semiconductor layer 120 and the first conductor structure 112 may be connected via other structures, for example, a film layer for forming an ohmic contact is provided between the first semiconductor layer 120 and the first conductor structure 112.

[0074] For example, please see Figure 3 The first semiconductor layer 120 may include a top portion 123, which may extend to the first conductor structure 112. That is, a portion of the first semiconductor layer 120 close to the first conductor structure 112 is surrounded by the first conductor structure 112. In this way, the contact area between the first semiconductor layer 120 and the first conductor structure 112 may be increased, thereby reducing resistance. For example, see Figure 4 The surface of the first conductor structure 112 in contact with the first semiconductor layer 120 is planar. The first semiconductor layer 120 is formed by deposition, and a portion of the deposited material is removed through photolithography and etching processes to form a portion extending into the first conductor structure 112. When the surface of the first conductor structure 112 in contact with the first semiconductor layer 120 is planar, a grinding process can be used to directly remove excess material from the top surface, thereby simplifying the process steps.

[0075] The first semiconductor layer 120 can be formed of a semiconductor material, such as silicon, germanium, or the like. For example, the first semiconductor layer 120 can be formed of an oxide semiconductor material, such as one or more of indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tungsten oxide (IWO), indium zinc oxide (IZO), indium strontium zinc oxide (ISZO), indium aluminum zinc oxide (IAZO), indium tin oxide (ITO), aluminum zinc oxide (AZO), and indium oxide (InO). Oxide semiconductors have lower leakage current than silicon. Therefore, for the same storage time, controlling the charge and discharge of the charge storage structure through the channel formed by the oxide semiconductor can reduce the charge storage capacity of the charge storage structure, which is conducive to further miniaturization of the memory cell and improving the density of the memory cell 100.

[0076] In some embodiments, see Figure 3The first semiconductor layer 120 may include a bottom 121 and a sidewall 122, the sidewall 122 extending along the Y direction, and the bottom 121 connected to an end of the sidewall 122 away from the first conductor structure 112. For example, see Figure 5 , Figure 5 It is along Figure 3 In the schematic diagram of the cross-sectional structure along line AA, the cross-sectional shape of the sidewall 122 of the first semiconductor layer 120 can be annular, for example, a circular ring, an elliptical ring, or a ring formed by a polygon, that is, the shape of the sidewall 122 can be barrel-shaped. The bottom 121 of the first semiconductor layer 120, the first electrical structure 140, and the first insulating layer 130 form a structure for storing charge. For example, the bottom 121 and the sidewall 122 can be integrally provided, whereby the bottom 121 and the sidewall 122 can be formed by the same process, for example, a chemical vapor deposition (CVD) process.

[0077] For example, see Figure 3 、 Figure 5 The memory cell 100 may further include a filler 150, which is disposed on a side of the bottom 121 of the first semiconductor layer 120 away from the first electrical structure 140 and surrounded by the sidewalls 122 of the first semiconductor layer 120. The filler 150 may be made of a dielectric material, such as SiO2, Si3N4, Al2O3, and combinations thereof. Providing the filler 150 increases the area of ​​the bottom 121 of the first semiconductor layer 120 facing the first electrical structure 140, thereby increasing the charge storage capacity of the structure formed by the bottom 121 of the first semiconductor layer 120, the first electrical structure 140, and the first insulating layer 130, thereby improving the performance and reliability of the memory cell 100.

[0078] In some embodiments, see Figures 6 and 7 , Figure 6 is a structural diagram of another storage unit 100 provided in an embodiment of the present application. Figure 7 It is along Figure 6 Schematic diagram of the cross-sectional structure along line BB. The cross-sectional shape of the first semiconductor layer 120 is circular, that is, at least a portion of the first semiconductor layer 120 is cylindrical, extending in the Y direction. The end of the first semiconductor layer 120 near the first electrical structure 140, the first electrical structure 140, and the first insulating layer 130 form a charge storage structure.

[0079] The first insulating layer 130 is disposed between the gate 113 and the first semiconductor layer 120. The gate 113, the first semiconductor layer 120, and the first insulating layer 130 form a first storage transistor. In a plane parallel to the substrate 111, the portion of the first semiconductor layer 120 corresponding to the gate 113 forms a channel. Along the Y direction, the portions of the first semiconductor layer 120 located on either side of the gate 113 form the transistor's source and drain, respectively. The gate 113 can thus control the channel in the first semiconductor layer 120, thereby controlling the conduction state of the first storage transistor.

[0080] In addition, the first insulating layer 130 is also disposed between the first semiconductor layer 120 and the first electrical structure 140. For example, the first insulating layer 130 may be disposed around the sidewall 122 of the first semiconductor layer 120. For example, the first insulating layer 130 may extend from between the gate 113 and the first semiconductor layer 120 to between the first semiconductor layer 120 and the first electrical structure 140. In other words, the first insulating layer 130 may include a first portion 131 and a second portion 132, wherein the first portion 131 is located between the sidewall 122 of the first semiconductor layer and the gate 113, and the second portion 132 is located between the first electrical structure 140 and the bottom of the first semiconductor layer 120, and the first portion 131 and the second portion 132 are connected. In this way, the first insulating layer 130 is disposed integrally, and therefore the first insulating layer 130 can be directly formed through a single deposition process, thereby reducing the number of process steps. For example, the first insulating layer 130 between the gate 113 and the first semiconductor layer 120 and the first insulating layer 130 between the first semiconductor layer 120 and the first electrical structure 140 may be two separate parts. These two parts may have different functions. For example, the first insulating layer 130 between the gate 113 and the first semiconductor layer 120 may serve as a gate dielectric layer, while the first insulating layer 130 between the first semiconductor layer 120 and the first electrical structure 140 may serve as a charge storage dielectric layer. Therefore, the materials of the two parts may be selected according to different functions to improve the performance of the memory cell 100.

[0081] The first insulating layer 130 may include a dielectric material, such as silicon oxide (SiO x ), silicon nitride (SiN x ) or high-k dielectric materials, high-k dielectric materials include but are not limited to one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), and titanium oxide (TiO2).

[0082] The gate 113 is disposed near the first semiconductor layer 120 on at least one side of the first semiconductor layer 120. That is, in a plane parallel to the first conductor structure 112, the gate 113 is disposed on at least one side of the first semiconductor layer 120. Along the Y direction, the gate 113 can be disposed between the first conductor structure 112 and the first electrical structure 140. For example, the gate 113 is disposed closer to the first conductor structure 112 than to the first electrical structure 140. In this way, the charge storage structure formed by the bottom 121 of the first semiconductor layer 120, the first electrical structure 140, and the first insulating layer 130 can be completely located on the side of the gate 113 near the first electrical structure 140, thereby ensuring the charge storage capability of the structure.

[0083] The configuration of the gate 113 may be determined according to the shape of the first semiconductor layer 120 .

[0084] For example, see Figure 5 or Figure 7 When the cross-section of the sidewall 122 of the first semiconductor layer 120 is annular or circular, in order to enhance the channel control capability of the gate 113 over the first semiconductor layer 120, the gate 113 may be disposed around the first semiconductor layer 120, that is, the gate 113 may be disposed around the sidewall 122 of the first semiconductor layer 120. For example, when the cross-section of the sidewall 122 of the first semiconductor layer 120 is annular, the gate 113 may also be annular and disposed around the first semiconductor layer 120.

[0085] For example, see Figure 8 , Figure 8 It is along Figure 3 In another possible cross-sectional structural diagram along line AA, the first semiconductor layer 120 includes two side walls 122, which are spaced apart along the X direction. For example, the two side walls 122 are parallel to each other, and in this cross section, both side walls 122 extend a certain dimension along the Z direction. In other words, the shape of the first semiconductor layer 120 is approximately U-shaped. In this case, the gate 113 may also include two parts, with the two side walls 122 being disposed between the two parts of the gate 113, and the two side walls 122 corresponding one-to-one to the two parts of the gate 113, so that the gate 113 can also control the on and off of the channel formed by the side walls 122. In this way, it can be considered that the gate 113 is disposed on both sides of the first semiconductor layer 120.

[0086] For example, see Figure 9 , Figure 9 It is along Figure 3 Another possible cross-sectional structure diagram of line AA, wherein the sidewall 122 of the first semiconductor layer 120 is arranged in the same manner as Figure 8 The same as in, Figure 9 and Figure 8 The difference lies in the arrangement of the gate 113. Figure 9 In the embodiment, the gate 113 may be disposed around the two sidewalls 122 , that is, the gate 113 is formed with a through hole 190 , and the two sidewalls 122 are disposed through the hole of the gate 113 .

[0087] For example, see Figures 10 and 11 , Figure 10 is a structural diagram of another storage unit 100 provided in an embodiment of the present application. Figure 11 It is along Figure 10 A schematic diagram of a possible cross-sectional structure of the CC line in FIG. The first semiconductor layer 120 includes only one sidewall 122. The sidewall 122 of the first semiconductor layer 120 is connected to the bottom 121 of the first semiconductor layer 120, and the sidewall 122 and the bottom 121 are generally approximately L-shaped. The gate 113 can be set on one side of the sidewall 122, for example, as shown in FIG. Figure 10 As shown, the gate 113 and the bottom 121 can be disposed on different sides of the sidewall 122. It is easy to understand that the gate 113 and the bottom 121 can also be disposed on the same side of the sidewall 122.

[0088] In some embodiments, see Figure 3 , the first electrical structure 140 may include a first conductive layer 141, and a first insulating layer 130 is provided between the first conductive layer 141 and the first semiconductor layer 120. The first conductive layer 141 may be made of any suitable material, for example, a metal material or an oxide material with good conductivity, such as tungsten (W), titanium nitride (TiN), indium tin oxide (ITO), aluminum zinc oxide (AZO), etc. Thus, a portion of the first semiconductor layer 120 close to the insulating layer and the first conductive layer 141 may be equivalent to two electrode plates arranged opposite to each other, and the first insulating layer 130 is sandwiched between a portion of the first semiconductor layer 120 close to the insulating layer and the first conductive layer 141, so that a portion of the first semiconductor layer 120 close to the insulating layer, the first conductive layer 141 and the first insulating layer 130 form a capacitor, which is a structure for storing charge.

[0089] As can be seen from the above, the gate 113, the first semiconductor layer 120, and the first insulating layer 130 can form a first memory transistor. In addition, a portion of the first semiconductor layer 120 close to the insulating layer, the first conductive layer 141, and the first insulating layer 130 form a capacitor, thereby forming a 1T1C memory cell 100. Figure 12 , Figure 12The circuit schematic diagram of the memory cell 100 is shown in FIG. The source or drain of the first storage transistor T1 is connected to an electrode of the capacitor C1. For example, when reading and writing the memory cell 100, by controlling the voltage applied to the gate 113, the conductive path between the first semiconductor layer 120 and the two ends of the first conductor structure 112 and the first conductive layer 141 can be controlled, thereby controlling the charging or discharging of the capacitor to achieve data reading and writing. For example, when performing a read operation on the memory cell 100, a voltage is applied to the gate 113, and the conductive path between the first semiconductor layer 120 and the two ends of the first conductive layer 141 is turned on. If there is charge stored in the capacitor, the capacitor can output a discharge signal to the first conductor structure 112 through the first semiconductor layer 120. If there is no charge stored in the capacitor, the capacitor will not output a discharge signal to the first conductor structure 112 through the first semiconductor layer 120. By sensing the discharge signal, the data stored in the memory cell 100 can be obtained. After reading the data, it is usually necessary to write it back. After writing back the data, the voltage applied to the gate can be canceled to cut off the conductive path between the first semiconductor layer 120 close to the first conductor structure 112 and the first conductive layer 141, so that the capacitor retains the charge and the memory cell retains the data.

[0090] For example, see Figure 13 The memory cell 100 may further include a second insulating layer 151, which is disposed between the first semiconductor layer 120 and the first conductive layer 141. A portion of the first semiconductor layer 120 close to the insulating layer, the first conductive layer 141, and the first insulating layer 130 form a capacitor. By providing the second insulating layer 151, the dielectric constant between the portion of the first conductive layer 141 close to the insulating layer and the first semiconductor layer 120 can be increased, thereby increasing the charge storage capacity of the capacitor, which is beneficial to improving the performance and reliability of the memory cell 100. For example, the material of the second insulating layer 151 can be silicon oxide (SiO x ), silicon nitride (SiN x ) or one or more dielectric materials such as aluminum oxide (Al2O3).

[0091] For example, see Figure 14Memory cell 100 may further include a third insulating layer 152 disposed between gate 113 and first semiconductor layer 120. Providing third insulating layer 152 enhances gate 113's ability to control the portion of first semiconductor layer 120 corresponding to gate 113. This enhances gate 113's ability to control the channel formed in first semiconductor layer 120, thereby increasing the degree to which the channel is turned off or on. Increasing the channel's conductivity reduces the time it takes for the first conductive structure 112 to charge the capacitor; increasing the channel's off-state duration increases the duration of charge retention in the capacitor, thereby reducing the refresh rate of memory cell 100. Consequently, the performance of memory cell 100 can be enhanced. Third insulating layer 152 may be made of the same material as second insulating layer 151.

[0092] For example, see Figure 15 The memory cell 100 may include both the second insulating layer 151 and the third insulating layer 152. For example, the second insulating layer 151 and the third insulating layer 152 may be the same film layer. In this way, the second insulating layer 151 and the third insulating layer 152 may be prepared simultaneously, such as by forming the film layer through the same deposition process. The film layer includes two parts, one of which is the second insulating layer 151 and the other is the third insulating layer 152. This reduces the number of process steps and improves production efficiency.

[0093] For example, see Figure 16 One end of the first semiconductor layer 120 may extend into the first conductive layer 141. Since the first insulating layer 130 is disposed between the first semiconductor layer 120 and the first conductive layer 141, the first semiconductor layer 120 may also partially extend into the first semiconductor layer 120. Consequently, a portion of the side surface of the first semiconductor layer 120 that extends into the first conductive layer 141 and is surrounded by the first conductive layer 141 also forms a portion of the capacitor electrode, increasing the area of ​​the capacitor electrode opposite thereto, thereby increasing the capacitance of the capacitor and improving the performance and reliability of the memory cell 100.

[0094] In some embodiments, see Figure 17 , the first electrical structure 140 may include a second semiconductor layer 144 , a first electrode 142 and a second electrode 143 .

[0095] The second semiconductor layer 144 is disposed on a side of the first semiconductor layer 120 away from the first conductor structure 112, with a portion of the first insulating layer located between the first and second semiconductor layers. The second semiconductor layer 144 may be disposed opposite the first conductor structure 112, with the first semiconductor layer 120 sandwiched between the second semiconductor layer 144 and the first conductor structure 112. The material used for the second semiconductor layer 144 may be the same as that used for the first semiconductor layer 120. For example, the material used for the second semiconductor layer 144 and the material used for the first semiconductor layer 120 may be the same, such as IGZO.

[0096] The first electrode 142 and the second electrode 143 are disposed on a side of the second semiconductor layer 144 near the first conductor structure 112 and are respectively connected to the second semiconductor layer 144. For example, the first electrode 142 and the second electrode 143 are both disposed in contact with the second semiconductor layer 144. In addition, along a direction parallel to the second semiconductor layer 144, that is, along a direction perpendicular to the direction Y, the first electrode 142 and the second electrode 143 are respectively located on either side of the first semiconductor layer 120. The material of the first electrode 142 and the second electrode 143 can be any suitable conductive material, such as tungsten (W). The material of the first electrode 142 and the second electrode 143 can be the same, so that the first electrode 142 and the second electrode 143 can be manufactured simultaneously.

[0097] Thus, a portion of the first semiconductor layer 120 close to the second semiconductor layer 144, the first insulating layer 130, the second semiconductor layer 144, the first electrode 142 and the second electrode 143 form a second storage transistor, wherein a portion of the first semiconductor layer 120 close to the first electrical structure 140 is the gate 113, the first insulating layer 130 is the gate dielectric layer, the portion of the second semiconductor layer 144 opposite to the first semiconductor layer 120 forms a channel, and the first electrode 142 and the second electrode 143 are the source and drain of the second storage transistor, respectively.

[0098] As can be seen from the foregoing, the gate 113, the first semiconductor layer 120, and the first insulating layer 130 can form a first storage transistor T1. A portion of the first semiconductor layer 120 in the first storage transistor T1 that is close to the first electrical structure 140 serves as the gate 113 of the second storage transistor, thereby forming a 2T0C memory cell 100. Figure 18 , Figure 18 1 is a circuit diagram of the memory cell 100. One of the source or drain of the first memory transistor T1 is connected to the gate of the second memory transistor T2. The second memory transistor T2 is a structure for storing charge.

[0099] For example, when the first storage transistor T1 is turned on, a portion of the first semiconductor layer 120 near the first electrical structure 140 serves as the gate 113 of the second storage transistor T2. Controlled by the voltage applied by the first conductor structure 112, the carrier concentration in the second semiconductor layer 144 changes, i.e., the concentration of the effective charge stored in the channel of the second storage transistor T2 changes, thereby affecting the conduction state of the second storage transistor T2. Subsequently, by controlling the voltage applied to the gate 113 of the first storage transistor T1, the gate 113 of the first storage transistor T1 is turned off, maintaining the conduction state of the channel of the second storage transistor T2, thereby enabling data writing.

[0100] When performing a read operation on the memory cell 100, a voltage is applied to the source of the second memory transistor T2, and the current of the drain of the second memory transistor T2 is sensed, thereby determining the conduction state of the channel of the second memory transistor T2, thereby obtaining the data stored in the memory cell 100.

[0101] For example, see Figure 19 , the second storage transistor T2 also includes an electrode plate 160. The electrode plate 160 is arranged on at least one side of the first semiconductor layer 120 in a direction parallel to the second semiconductor layer 144. A first insulating layer 130 is provided between the electrode plate 160 and the first semiconductor layer 120, and the electrode plate 160 is located between the gate 113 and the second semiconductor layer 144. Thus, the portion of the first semiconductor layer 120 corresponding to the electrode plate 160, the first insulating layer 130 and the electrode plate 160 form a capacitor that can store charge. The charge stored in the capacitor can enhance the control capability of the portion of the first semiconductor layer 120 close to the second semiconductor layer 144 over the conduction state of the second storage transistor T2. Thus, a 2T1C storage unit 100 is formed, and its circuit schematic diagram is shown in FIG. Figure 20 As shown, one of the source or drain of the first storage transistor T1 is connected to the gate of the second storage transistor T2, and a capacitor C2 is provided at the connection.

[0102] In order to increase the capacitance of the capacitor C2 formed by the portion of the first semiconductor layer 120 corresponding to the electrode plate 160, the first insulating layer 130, and the electrode plate 160, the size of the electrode plate 160 can be increased. For example, the size of the electrode plate 160 along the vertical direction of the first conductor structure 112 can be made larger than the size of the gate 113 along the vertical direction of the first conductor structure 112. This can increase the ability of the portion of the first semiconductor layer 120 corresponding to the second semiconductor layer 144 to retain charge, and increase the duration of the gate 113 of the second storage transistor T2 controlling the channel of the second storage transistor T2. This helps reduce the refresh frequency of the memory cell 100, improve the reliability of the memory cell 100, and enhance the performance of the memory. Based on the aforementioned memory cell 100, please refer to Figure 21 The memory array 400 provided in an embodiment of the present application includes a plurality of memory cells 100 arranged in an array, wherein the memory cells 100 are any of the aforementioned memory cells 100. The gate 113 of each row of memory cells 100 is connected to a word line. For example, the gate 113 extends in the Z direction to form a word line. The first conductor structure 112 of each column of memory cells 100 is connected to form a bit line. A memory cell 100 connected to both the word line and the bit line can be selected by selecting a word line and a bit line, thereby performing a write operation on the memory cell 100. For example, a high level is applied to the selected word line, that is, a high level is applied to the gate 113 connected to the word line, so that the channel of the write transistor of the memory cell 100 is turned on; a high level is applied to the selected bit line, that is, a high level is applied to the first conductor structure 112 connected to the bit line, so that the charge storage structure of the memory cell 100 is charged, thereby changing the amount of charge in the structure and implementing a data write operation.

[0103] In some embodiments, the memory array 400 may include multiple sub-memory arrays 400, each stacked vertically along the first conductive structure 112 of the memory cell 100. That is, the multiple sub-memory arrays 400 are stacked along the Y direction, and each sub-memory array 400 includes multiple memory cells 100 arranged in an array. In other words, the memory array 400 may be a three-dimensional memory array 400, where the multiple memory cells 100 included in the sub-memory arrays 400 are arranged in an array in the XZ plane. This improves the integration density of the memory array 400.

[0104] For example, see Figure 21 A dielectric layer 170 may be provided between the plurality of sub-memory arrays 400 to separate two adjacent sub-memory arrays 400 from each other and to make the two adjacent sub-memory arrays 400 independent of each other. The dielectric layer 170 may be made of any suitable dielectric material, such as silicon oxide (SiO x )wait.

[0105] For example, when the first electrical structure 140 of the memory cell 100 includes a first conductive layer 141, the multiple memory cells 100 in the memory array 400 share the same first conductive layer 141, and the first conductive layer 141 extends along the row direction and column direction of the multiple memory cells 100. For example, the memory array 400 includes multiple sub-memory arrays 400, and the multiple memory cells 100 in each sub-memory array 400 share the same first conductive layer 141, and the first conductive layer 141 extends along the row direction or column direction of the multiple memory cells 100. In this way, the first conductive layer 141 can be directly formed through a deposition process, simplifying the formation process.

[0106] For example, please see Figure 22 In the case where the first electrical structure 140 of the memory cell 100 includes a first conductive layer 141, the first conductive layer 141 of two adjacent memory cells 100 arranged in a direction perpendicular to the first conductive structure 112, one memory cell 100, serves as the first conductive structure 112 of the other memory cell 100. This avoids the need for a dielectric layer 170 between two adjacent sub-memory arrays 400, reduces process steps, and improves production efficiency. In this case, to independently perform read and write operations on each memory cell 100, multiple memory cells 100 in the same sub-memory array 400 that share the same first conductive layer 141 are arranged in a column direction. That is, the first conductive layer 141 extends along the X direction and corresponds to one memory cell 100 in the Z direction.

[0107] As previously mentioned, the memory 300 provided in this application includes a control circuit 310 and the aforementioned memory array 400. The first electrical structure 140 of the memory cell 100 in the memory array 400 includes a second semiconductor layer 144. The control circuit 310 is connected to the memory array 400. Figure 23 , Figure 23 It is a partial circuit structure diagram of the memory 300 provided in an embodiment of the present application.

[0108] In some embodiments, the control circuit 310 of the memory 300 may include a read circuit 370 and a first transistor 391. The gate of the first transistor 391 is connected to a bit line, and a first electrode of the first transistor 391 is connected to the read circuit 370. The first electrode may be the source or drain of the first transistor 391. Thus, when a read operation is performed on the memory cell 100, if a charge is stored in the capacitor C1 of the memory cell 100, the capacitor C1 may apply a voltage to the bit line. Since the gate of the first transistor 391 is connected to the bit line, the voltage applied by the capacitor C1 to the bit line turns on the first transistor 391 or affects the degree of conduction of the first transistor 391. Thus, the read circuit 370 can obtain the data stored in the memory cell 100 based on the conduction state of the first transistor 391. Accordingly, when no charge is stored in the capacitor C1 of the memory cell 100, the capacitor does not apply a voltage to the bit line, and thus does not affect the conduction state of the first transistor 391.

[0109] Exemplarily, the first transistor 391 may be an oxide semiconductor transistor. The leakage current of the transistor formed by the oxide semiconductor is small, and therefore, the influence of the leakage current on the conduction state of the first transistor 391 can be reduced or avoided, thereby improving the accuracy of the read data.

[0110] For example, each bit line in the memory array 400 may be provided with a corresponding first transistor 391, and the gate of the first transistor 391 is connected to the corresponding word line. Thus, the first transistor 391 can be directly connected to the word line, reducing the influence of the parasitic capacitance of the connection between the first transistor 391 and the word line.

[0111] For example, the second electrode of the first transistor 391 can be grounded via a resistor 393, and the second electrode of the first transistor 391 is the other of the source or the drain of the first transistor 391. In this way, the conduction state of the first transistor 391 can be determined by obtaining the potential of the first electrode of the first transistor 391 by the read circuit 370, thereby providing a new reading method.

[0112] In some embodiments, the control circuit 310 of the memory 300 may further include a write circuit 380 and a second transistor 392. The gate of the second transistor 392 is configured to receive a control signal from the control circuit 310. The first electrode of the second transistor 392 is connected to the write circuit 380, and the second electrode of the second transistor 392 is connected to the bit line. The first electrode of the second transistor 392 serves as the source or drain of the second transistor 392, and the second electrode of the second transistor 392 serves as the other of the drain or source of the second transistor 392. In this way, when reading data, the second transistor 392 receives the control signal to disconnect the write circuit 380, thereby preventing the stored charge of the memory cell 100 from leaking from the write circuit 380 via the bit line, thereby improving the accuracy of the read data.

[0113] Exemplarily, the second transistor 392 may be an oxide semiconductor transistor. The leakage current of the transistor formed by the oxide semiconductor is small. Therefore, the influence of the leakage current on the electrical signal on the word line can be reduced or avoided, that is, the influence on the conduction state of the first transistor 391 can be reduced or avoided, thereby improving the accuracy of the read data.

[0114] For example, the control signal received by the gate of the second transistor 392 may come from the timing controller 340 . During the time corresponding to reading data, the timing controller 340 sends a control signal to the gate of the second transistor 392 to disconnect the write circuit 380 .

[0115] For example, a second transistor 392 may be provided for each bit line in the memory array 400. Thus, the second transistor 392 may be directly connected to the word line, further reducing the number of connections between the word line and the second transistor 392, thereby further reducing the possibility of stored charge in the memory cell 100 leaking from the write circuit 380 via the bit line.

[0116] Finally, the present invention also provides a method for manufacturing a memory array 400. The materials of the components formed in the manufacturing method can refer to the materials of the corresponding components in the aforementioned memory cell 100, and will not be repeated here. Figure 24 , the preparation method comprises the following steps:

[0117] S100, see Figure 25 , a first electrical structure 140 is formed on the substrate 111 .

[0118] The first electrical structure 140 can be formed on the substrate 111 using any suitable semiconductor process. The first electrical structure 140 can be formed directly on a side surface of the substrate 111, or after forming another film layer on a side surface of the substrate 111, the first electrical structure 140 is formed on the film layer. For example, the film layer can be a buffer layer to prevent defects caused by lattice mismatch between the first electrical structure 140 and the substrate 111.

[0119] Illustratively, when the first electrical structure 140 includes a first conductive layer 141, a conductive material can be formed on one side surface of the substrate 111 by a suitable deposition process. For example, when the first conductive layer 141 is tungsten (W), a chemical vapor deposition (CVD) process can be used to form the conductive material. As can be seen from the foregoing, the first conductive layer 141 includes a variety of configurations, such as the first conductive layer 141 extending between multiple rows and columns of memory cells 100. For another example, the first conductive layer 141 is a plurality of columns, each column corresponding to a column of memory cells 100 and extending between the memory cells 100 in this column. Therefore, when the first conductive layer 141 is a plurality of columns, the conductive material can also be formed into a plurality of columns by photolithography and etching processes, thereby forming the first conductive layer 141.

[0120] For example, when the first electrical structure 140 includes a second semiconductor layer 144, a first electrode 142 and a second electrode 143, the second semiconductor layer 144 and the initial electrode layer can be formed by appropriate deposition, and the initial electrode layer can be formed into the first electrode 142 and the second electrode 143 by photolithography and etching processes.

[0121] For ease of description, this embodiment will be described below with the first electrical structure 140 including the first conductive layer 141. For the case where the first electrical structure 140 includes the second semiconductor layer 144, the first electrode 142, and the second electrode 143, those skilled in the art may modify the implementation accordingly.

[0122] S200, see Figures 26 to 28 A first dielectric layer 180 and a gate 113 are formed on a side of the first electrical structure 140 away from the substrate 111 , and the gate 113 is embedded in the first dielectric layer 180 .

[0123] In order to embed the gate 113 in the first dielectric layer 180 , multiple deposition processes and etching processes may be used.

[0124] For example, Figure 26 As shown, an initial first dielectric layer 181 may be formed on a side of the first electrical structure 140 away from the substrate 111. Figure 27 As shown, a groove is formed on the surface of the initial first dielectric layer 181 on the side away from the substrate 111 by photolithography and etching. Then, a gate 113 is formed in the groove by deposition. If the material deposited in the groove to form the gate 113 protrudes from the groove, the protruding portion of the material can be removed by chemical mechanical polishing (CMP) or other processes. Finally, as shown in FIG. Figure 28As shown, an initial second dielectric layer 182 is deposited on the initial first dielectric layer 181 and the surface of the gate 113 away from the substrate 111. The initial first dielectric layer 180 and the initial second dielectric layer 182 together form the first dielectric layer 180. The grooves may be arranged in multiple rows, each row corresponding to a row of memory cells 100 and extending between the memory cells 100 in the row. Thus, after the material forming the gate 113 is deposited in the grooves, word lines can be directly formed.

[0125] S300, see Figure 29 , forming a through hole 190 , and passing through the gate 113 along the vertical direction of the substrate 111 .

[0126] A photolithography process can be used to form a pattern on the side of the first dielectric layer 180 away from the substrate 111. This pattern exposes the area where the through-hole 190 is pre-formed. Then, the exposed area is etched to form the through-hole 190, which extends through the gate 113. For example, the formed through-holes 190 can be arranged in an array, that is, the formed through-holes 190 include multiple rows and multiple columns. For example, depending on whether a portion of the first semiconductor layer 120 extends into the first conductive layer 141, the etching can be stopped when the first conductive layer 141 is reached, or after a portion of the first conductive layer 141 has been etched.

[0127] S400, see Figure 30 , a first insulating layer 130 and a first semiconductor layer 120 are sequentially formed in the through hole 190 .

[0128] The first insulating layer 130 and the first semiconductor layer 120 may be formed using a deposition process. For example, the first insulating layer 130 is formed in the through hole 190 using a suitable deposition process, and then the first semiconductor layer 120 is formed on the surface of the first insulating layer 130 using a suitable deposition process. The first semiconductor layer 120 extends in the through hole 190 in a direction perpendicular to the substrate 111.

[0129] For example, the first insulating layer 130 and the first semiconductor layer 120 do not completely fill the through-hole 190. Therefore, dielectric material can continue to be deposited to fill the through-hole 190, thereby forming a filling body 150 in the through-hole 190. The filling body 150 is located on the side of the bottom 121 of the first semiconductor layer 120 away from the first electrical structure 140 and is surrounded by the sidewalls 122 of the first semiconductor layer 120. It is easy to understand that when the filling body 150 is formed, the dielectric material is also formed on the surface of the first semiconductor layer 120 away from the substrate 111, completely covering the first semiconductor layer 120. Therefore, at least a portion of the dielectric material outside the through-hole 190 can be removed to expose the first semiconductor layer 120. For example, a chemical mechanical polishing process can be used to remove this portion of the dielectric material.

[0130] For example, see Figure 31 In order to make the first semiconductor layers 120 of the memory cells 100 in the memory array 400 independent of each other, at least a portion of the first semiconductor layer 120 outside the through hole 190 may be removed by photolithography and etching processes.

[0131] S500, please continue to see Figure 3 A first conductor structure 112 is formed on a side of the first dielectric layer 180 away from the substrate 111 , and the first conductor structure 112 is connected to the first semiconductor layer 120 .

[0132] A conductive material forming the first conductor structure 112 is deposited on a side of the first dielectric layer 180 remote from the substrate 111 through a deposition process. The conductive material covers the surface of the first dielectric layer 180 remote from the substrate 111. To form the first conductor structure 112, photolithography and etching processes are also required to form the conductive material covering the first dielectric layer 180 into multiple columns, each corresponding to a column of through-holes 190. The columns extend between the multiple first semiconductor layers 120 formed in the through-holes 190, thereby forming the first conductor structure 112.

[0133] The above are only specific embodiments of the present application, but the scope of protection of the application is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A storage unit, characterized in that: include: a first conductor structure; a first semiconductor layer, disposed on one side of the first conductor structure, connected to the first conductor structure, and extending in a vertical direction of the first conductor structure; a gate, disposed on at least one side of the first semiconductor layer in a plane parallel to the first conductor structure; a first electrical structure, at least partially disposed on a side of the first semiconductor layer away from the first conductor structure; a first insulating layer, disposed between the gate and the first semiconductor layer, and between the first electrical structure and the first semiconductor layer; The first electrical structure, the first semiconductor layer, and the first insulating layer form a structure for storing charges.

2. The storage unit according to claim 1, wherein The first electrical structure includes a first conductive layer, wherein the first conductive layer, the first semiconductor layer, and the first insulating layer form a capacitor.

3. The storage unit according to claim 2, wherein The memory cell further includes a second insulating layer disposed between the first semiconductor layer and the first conductive layer; and / or, The memory cell further includes a third insulating layer disposed between the gate and the first semiconductor layer.

4. The storage unit according to claim 2 or 3, wherein: One end of the first semiconductor layer extends into the first conductive layer.

5. The storage unit according to claim 1, wherein The first electrical structure includes a second semiconductor layer, a first electrode, and a second electrode; The second semiconductor layer is arranged on a side of the first semiconductor layer away from the first conductor structure, and a portion of the first insulating layer is located between the first semiconductor layer and the second semiconductor layer; The first electrode and the second electrode are arranged on a side of the second semiconductor layer close to the first conductor structure, are respectively connected to the second semiconductor layer, and are respectively located on both sides of the first semiconductor layer along a direction parallel to the second semiconductor layer.

6. The storage unit according to claim 5, wherein It also includes an electrode plate, which is arranged at least on one side of the first semiconductor layer, with a portion of the first insulating layer arranged between the electrode plate and the first semiconductor layer, and the electrode plate is located between the gate and the second semiconductor layer.

7. The storage unit according to claim 6, wherein: A dimension of the electrode plate along a direction perpendicular to the first conductor structure is greater than a dimension of the gate along the direction perpendicular to the first conductor structure.

8. The storage unit according to any one of claims 1 to 7, wherein: The first semiconductor layer includes a bottom and a sidewall, the sidewall extends along a vertical direction of the first conductor structure, and the bottom is connected to an end of the sidewall away from the first conductor structure; the gate is arranged on at least one side of the sidewall.

9. The storage unit according to claim 8, wherein The first insulating layer includes a first portion and a second portion, the first portion is located between the sidewall of the first semiconductor layer and the gate, the second portion is located between the first electrical structure and the bottom of the first semiconductor layer, and the first portion and the second portion are connected.

10. The storage unit according to claim 8 or 9, characterized in that The side wall is cylindrical, and the gate and the first insulating layer are arranged around the side wall; The memory cell further includes a filling body, which is arranged on a side of the bottom of the first semiconductor layer away from the first electrical structure and is surrounded by a sidewall of the first semiconductor layer.

11. The storage unit according to any one of claims 1 to 10, wherein: The material of the first semiconductor layer includes an oxide semiconductor.

12. A storage array, characterized in that: The invention comprises a plurality of memory cells arranged in an array, wherein the memory cells are the memory cells according to any one of claims 1 to 11, the gates of the memory cells in each row are connected to a word line, and the first conductor structures of the memory cells in each column are connected to form a bit line.

13. The storage array according to claim 12, wherein: The memory array includes a plurality of sub-memory arrays, which are stacked along a vertical direction of the first conductor structure of the memory cell. Each of the sub-memory arrays includes a plurality of the memory cells arranged in an array.

14. The storage array according to claim 13, wherein: The first electrical structure of the memory cell includes a first conductive layer. Two memory cells are adjacently arranged in a vertical direction of the first conductive structure, wherein the first conductive layer of one memory cell serves as the first conductive structure of the other memory cell.

15. The storage array according to claim 13, wherein: The first electrical structure of the memory cell includes a first conductive layer. The multiple memory cells in the same sub-memory array share the same first conductive layer, and the first conductive layer extends along the row direction and column direction of the multiple memory cells.

16. A memory, characterized in that: include: A control circuit and the memory array according to any one of claims 12 to 15, wherein the control circuit is connected to the memory array.

17. The memory according to claim 16, wherein: The control circuit includes a read circuit and a first transistor, wherein a gate of the first transistor is connected to the bit line, and a first electrode of the first transistor is connected to the read circuit.

18. The memory according to claim 16 or 17, wherein: The control circuit includes a write circuit and a second transistor, a gate of the second transistor is configured to receive a control signal from the control circuit, a first electrode of the second transistor is connected to the write circuit, and a second electrode of the second transistor is connected to the bit line.

19. The memory according to claim 18, wherein The second transistor is an oxide semiconductor transistor.

20. A method for preparing a storage array, characterized in that: include: forming a first electrical structure on a substrate; forming a first dielectric layer and a gate on a side of the first electrical structure away from the substrate, wherein the gate is embedded in the first dielectric layer; forming a through hole along a vertical direction of the substrate, wherein the through hole penetrates the gate; forming a first insulating layer and a first semiconductor layer in sequence in the through hole; A first conductor structure is formed on a side of the first dielectric layer away from the substrate, and the first conductor structure is connected to the first semiconductor layer.

21. An electronic device, characterized in that: include: A printed circuit board and the memory according to any one of claims 16 to 19, wherein the memory is provided on the printed circuit board.

Images