Semiconductor device and data storage system including the same

Abstract

A semiconductor device and a data storage system including the same may include a first semiconductor structure including a first substrate, a first circuit element on the first substrate, a first circuit interconnect line on the first circuit element, and a first peripheral region insulating layer; a second semiconductor structure including a first region of a second substrate on the first semiconductor structure, a second circuit element on the first region of the second substrate, and a second circuit interconnect line on the second circuit element; a capacitor structure including a first capacitor electrode spaced apart from the first circuit interconnect line on a lower surface of the second substrate, a second region of the second substrate facing the first capacitor electrode, and a first through-via extending in the second substrate and electrically connected to the first capacitor electrode; and a third semiconductor structure including a third substrate on the second semiconductor structure and a memory cell on the third substrate.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices, and more particularly, to a data storage system including the semiconductor device. Background Art

[0002] In data storage systems requiring data storage, semiconductor devices capable of storing high-capacity data are required. Therefore, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, as one method for increasing the data storage capacity of semiconductor devices, semiconductor devices including memory cells arranged three-dimensionally rather than two-dimensionally have been proposed. Summary of the Invention

[0003] An aspect of the present disclosure is to provide a semiconductor device with improved integration.

[0004] Another aspect of the present disclosure is to provide a data storage system including a semiconductor device with improved integration.

[0005] According to an example embodiment of the present disclosure, a semiconductor device may include: a first semiconductor structure including a first substrate, a first circuit element on the first substrate, a first circuit interconnection line on the first circuit element, and a first peripheral region insulating layer on the first circuit interconnection line; a second semiconductor structure including a first region of a second substrate on the first semiconductor structure, a second circuit element on the first region of the second substrate, and a second circuit interconnection line on the second circuit element; a capacitor structure including a first capacitor electrode spaced apart from the first circuit interconnection line on the lower surface of the second substrate, a second region of the second substrate facing the first capacitor electrode, and a first through-via penetrating the second substrate (i.e., extending in the second substrate) and connected to the first capacitor electrode; and a third semiconductor structure including a third substrate on the second semiconductor structure and the capacitor structure and a memory cell on the third substrate.

[0006] A semiconductor device according to an example embodiment of the present disclosure may include: a first substrate; a first circuit element on the first substrate; a circuit interconnection line on the first circuit element; a passive element structure including a conductive layer spaced apart from the circuit interconnection line; a peripheral region insulating layer on the circuit interconnection line and the conductive layer; a second substrate on the peripheral region insulating layer; a first through-via penetrating the second substrate (i.e., extending in the second substrate) and connected to the conductive layer; and a second through-via penetrating the second substrate and connected to the circuit interconnection line.

[0007] A data storage system according to an example embodiment of the present disclosure may include: a semiconductor memory device, including a first semiconductor structure, the first semiconductor structure including a first substrate, a first circuit element on the first substrate, and a first circuit interconnection structure on the first circuit element; a second semiconductor structure including a second substrate on the first semiconductor structure, a second circuit element on the second substrate, and a second circuit interconnection structure on the second circuit element; a third semiconductor structure on the second semiconductor structure and including a memory cell; a passive element structure including a conductive layer on the lower surface of the second substrate and a through-path penetrating the second substrate (i.e., extending in the second substrate) and connected to the conductive layer; and input / output pads electrically connected to the first and second circuit elements; and a controller electrically connected to the semiconductor memory device through the input / output pads and configured to control the semiconductor memory device.

[0008] By stacking a second semiconductor structure including a second substrate on a first semiconductor structure including a first substrate and including a passive element structure including a conductive layer on a lower surface of the second substrate, a semiconductor device with improved integration and a data storage system including the same can be provided.

[0009] The advantages and effects of the present application are not limited to the foregoing and can be more easily understood in the course of describing specific exemplary embodiments of the present disclosure.

[0010] Various extensions can be made to the advantages and effects of the present application without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals (when used) designate corresponding elements throughout the several views, and in which:

[0012] Figure 1 is a schematic block diagram of a semiconductor device according to an example embodiment;

[0013] Figure 2 is a circuit diagram illustrating a charge pump circuit included in a voltage generator of a semiconductor device according to example embodiments;

[0014] Figure 3 is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0015] Figure 4A and Figure 4B is a schematic plan view of a semiconductor device according to an example embodiment;

[0016] Figure 5is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0017] Figures 6A to 6C is a schematic plan view of a semiconductor device according to an example embodiment;

[0018] Figure 7 is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0019] Figure 8 is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0020] 9A to 9I is a schematic cross-sectional view for describing a method of manufacturing a semiconductor device according to an example embodiment;

[0021] Figure 10 is a view schematically illustrating a data storage system including a semiconductor device according to example embodiments;

[0022] Figure 11 is a perspective view schematically illustrating a data storage system including a semiconductor device according to example embodiments; and

[0023] Figure 12 is a cross-sectional view schematically illustrating a semiconductor package according to example embodiments. DETAILED DESCRIPTION

[0024] Hereinafter, example embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0025] Figure 1 is a schematic block diagram of a semiconductor device according to example embodiments.

[0026] refer to Figure 1 , a semiconductor device 10 may include a memory cell array 20 and a peripheral circuit 30 operably coupled to the memory cell array 20. The semiconductor device 10 may be a memory device, and may be, for example, a nonvolatile memory such as a flash memory or a volatile memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like.

[0027] The memory cell array 20 may include a plurality of memory cells. The plurality of memory cells may be connected to a row decoder 33 via a plurality of word lines WL, and may be connected to a read / write circuit 35 via a bit line BL. In an example embodiment, a plurality of memory cells arranged along the same column are connected to the same word line WL, and a plurality of memory cells arranged along the same row may be connected to the same bit line BL. In some example embodiments, the memory cell array 20 may include a plurality of memory blocks, and each memory block may include a plurality of memory cells.

[0028] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor device 10, and may transmit and receive data DATA to and from devices outside the semiconductor device 10. The peripheral circuit 30 may include a row decoder 33, a read / write circuit 35, a control logic 37, and a voltage generator 38 configured to generate various voltages required for operation. According to example embodiments, the peripheral circuit 30 may further include various sub-circuits (not explicitly shown), such as an input / output circuit and an error correction circuit for correcting errors in the data DATA read from the memory cell array 20.

[0029] The control logic 37 may be coupled to the row decoder 33, the voltage generator 38, and the read / write circuit 35. The control logic 37 may control the overall operation of the semiconductor device 10. The control logic 37 may generate various internal control signals used within the semiconductor device 10 in response to the control signal CTRL. For example, when performing a memory operation such as a program operation or an erase operation, the control logic 37 may adjust the voltage levels supplied to the word lines WL and the bit lines BL.

[0030] The row decoder 33 may select some of the plurality of memory cells in response to the address ADDR and may select at least one word line WL. The row decoder 33 may transmit a voltage for performing a memory operation to the selected word line WL.

[0031] The read / write circuit 35 may be connected to the memory cell array 20 through the bit line BL. The read / write circuit 35 may include a write driver or a sense amplifier. Specifically, during a program operation, the read / write circuit 35 may operate as a write driver and apply a voltage to the bit line BL according to the data DATA to be stored in the memory cell array 20. Meanwhile, during a read operation, the read / write circuit 35 operates as a sense amplifier and may sense the data DATA stored in the memory cell array 20.

[0032] The voltage generator 38 may include a controller 52 , an oscillator 54 , and a charge pump circuit 56 .

[0033] The charge pump circuit 56 may include a plurality of charge pumps, and each of the plurality of charge pumps may include at least one switching element and at least one pumping capacitor. The output voltage of the charge pump circuit 56 may be used for the operation of the semiconductor device 10. For example, the row decoder 33 may use the output voltage of the charge pump circuit 56 to input a bias voltage to the word line WL to perform a program operation, an erase operation, a read operation, etc.

[0034] The controller 52 may control the operation of the oscillator 54. For example, the controller 52 may determine the frequency of the clock signal CLK output by the oscillator 54 to the charge pump circuit 56 based on at least one of process, voltage, and / or temperature (PVT) information of the semiconductor device 10 and a target level of a voltage to be output by the charge pump circuit 56. For example, when the charge pump circuit 56 includes a plurality of charge pumps, the selected charge pump that is actually operated among the plurality of charge pumps may be determined by the controller 52.

[0035] The oscillator 54 may output a clock signal CLK that turns on or off at least one switching element included in the charge pump circuit 56. The clock signal CLK output by the oscillator 54 may be determined in response to a control signal VGC from the controller 52. For example, the oscillator 54 may differently set the frequency and swing range (i.e., voltage amplitude) of the clock signal CLK according to the control signal VGC sent by the controller 52.

[0036] Figure 2 is a circuit diagram illustrating a charge pump circuit included in a voltage generator of a semiconductor device according to example embodiments.

[0037] refer to Figure 2 The charge pump circuit 56a may include a plurality of diodes DI, a plurality of pumping capacitors CP, and an output capacitor COUT. The plurality of diodes DI may be connected in series with each other cathode to anode, and the plurality of pumping capacitors CP may be connected to nodes between adjacent pairs of diodes DI. The first diode may receive a power supply voltage VCC having a predetermined level, and the last diode may transmit the output current IOUT to the output node. The output capacitor COUT may be connected between the output node and ground.

[0038] Each of the plurality of pumping capacitors CP can be charged or discharged by the clock signal CLK or a complementary clock signal CLKB, where the complementary clock signal CLKB is phase-shifted by an inverter INV to have a phase opposite to that of the clock signal CLK. For example, odd-numbered pumping capacitors CP can be charged or discharged by the clock signal CLK, and even-numbered pumping capacitors CP can be charged or discharged by the complementary clock signal CLKB.

[0039] Figure 3 is a schematic cross-sectional view of a semiconductor device according to example embodiments.

[0040] refer to Figure 3, the semiconductor device 10a may include first to third semiconductor structures S1, S2 and S3 and a passive element structure PE. The first to third semiconductor structures S1, S2 and S3 may be stacked sequentially in a vertical direction (i.e., a vertical direction perpendicular to the upper surface of the first semiconductor structure S1). The passive element structure PE may be disposed between the first semiconductor structure S1 and the second semiconductor structure S2. According to the explanation, the passive element structure PE may be described as being disposed across the first semiconductor structure S1 and the second semiconductor structure S2. In some example embodiments, the third semiconductor structure S3 may be disposed below the first semiconductor structure S1 and the second semiconductor structure S2.

[0041] The first and second semiconductor structures S1 and S2 and the passive element structure PE may include a peripheral circuit configured to drive a memory cell, and may be a structure in which Figure 1 The third semiconductor structure S3 may be a region of the peripheral circuit 30. Figure 1 The first semiconductor structure S1 may include a first substrate 201 , the second semiconductor structure S2 may include a second substrate 301 , and the third semiconductor structure S3 may include a third substrate 101 .

[0042] The passive element structure PE may include a passive element, such as at least one of a resistor, an inductor, or a capacitor. The passive element structure PE may include a conductive layer CL, and the conductive layer CL may be disposed under the second substrate 301. In some example embodiments, the passive element structure PE may further include a partial region of the second substrate 301. In some example embodiments, the passive element structure PE may include Figure 1 and Figure 2 In this case, the conductive layer CL may be a capacitor electrode of the pumping capacitor CP.

[0043] Figure 4A and Figure 4B is a schematic plan view of a semiconductor device according to example embodiments. Figure 4A Shown Figure 3 An example embodiment of a layout on the upper surface 301F of the second substrate 301, Figure 4B Shown Figure 3 An example embodiment of a layout on the lower surface 301B of the second substrate 301 is shown.

[0044] refer to Figure 4A In the semiconductor device 100 , the first to fourth circuit regions PS1 , PS2 , PS3 , and PS4 , the first through via region TS1 , and the second through via region TS2 may be disposed on the upper surface 301F of the second substrate 301 .

[0045] The first to fourth circuit regions PS1, PS2, PS3, and PS4 may be regions in which circuit elements performing different functions are arranged. However, in example embodiments, the number, relative sizes, and specific arrangements of the first to fourth circuit regions PS1, PS2, PS3, and PS4 may be variously changed.

[0046] The first through via regions TS1 may be spaced apart from each other. The first through via regions TS1 may be provided with a through via that penetrates the second substrate 301 and is connected to the conductive layer CL (see FIG. 1 ). Figure 3 ) of the first through via region. For example, the first through vias may be arranged in one or more rows in each first through via region TS1. The second through via region TS2 may be where a through via is provided that penetrates the second substrate 301 and is electrically connected to the first semiconductor structure S1 (see FIG. Figure 3 ) of a through-path of a circuit element. The term "connection" (or "connected . . . ," or similar terms such as "contacting" or "contacting . . . "), as may be used herein, is intended to refer to a physical and / or electrical connection between two or more elements, and may include other intervening elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In example embodiments, the number, size, and arrangement of the second through-path region TS2 relative to the first to fourth circuit regions PS1, PS2, PS3, and PS4 may be varied variously. For example, in some example embodiments, the circuit region may be further disposed outside the second through-path region TS2.

[0047] refer to Figure 4B In the semiconductor device 100 , the first through via region TS1 , the second through via region TS2 , and the conductive layer CL may be disposed on the lower surface 301B of the second substrate 301 .

[0048] Since the through via extends by penetrating the second substrate 301 , the first and second through via regions TS1 and TS2 may be provided to respectively correspond to the first and second through via regions TS1 and TS2 on the upper surface 301F of the second substrate 301 .

[0049] The conductive layer CL may be disposed overlapping the first through-via region TS1. The term "overlap" (or "overlapping" or similar terms), as used herein, is intended to generally refer to a first element intersecting at least a portion of a second element in the vertical direction (i.e., the Z direction), but does not require that the first and second elements be completely aligned with each other in the horizontal plane (i.e., the X and / or Y directions). The conductive layer CL, together with the through-vias in the first through-via region TS1, may form a passive element structure PE. In example embodiments, the passive element structure PE may be a capacitor structure, and the conductive layer CL may be an electrode of the capacitor. The conductive layer CL may be disposed in an area vertically overlapping the first to fourth circuit regions PS1, PS2, PS3, and PS4 on the upper surface 301F of the second substrate 301. In some embodiments, the conductive layer CL may be disposed in an area vertically overlapping some of the first to fourth circuit regions PS1, PS2, PS3, and PS4. The conductive layer CL may be arranged in a rectangular shape, but the shape of the conductive layer CL in plan view is not limited thereto. In some example embodiments, the conductive layer CL may have an elliptical shape, a polygonal shape, or a linear shape.

[0050] Figure 5 is a schematic cross-sectional view of a semiconductor device according to example embodiments. Figure 5 Shown along Figure 4A and Figure 4B The cross section is taken along the section line II'.

[0051] refer to Figure 5 , shows a cross section of the first semiconductor structure S1 and the second semiconductor structure S2 and the passive element structure PE of the semiconductor device 100 according to example embodiments. Figure 5 For the sake of clarity, the cross section of the third semiconductor structure S3 is omitted and thus will not be described here.

[0052] The first semiconductor structure S1 may include a first substrate 201, a first source / drain region 205 and a first device isolation layer 210 (for example, a shallow trench isolation (STI) structure) in the first substrate 201, a first circuit element 220 arranged on the first substrate 201, a first peripheral region insulating layer 290, a first circuit contact plug 270, a first circuit interconnect line 280 and a first bonding insulating layer 299.

[0053] The first substrate 201 may have an upper surface extending in the X and Y directions. An active region may be defined on the first substrate 201 by a first device isolation layer 210. A first source / drain region 205 including impurities may be provided in a portion of the active region. The first substrate 201 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. The first substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0054] The first circuit elements 220 may include planar transistors. Each first circuit element 220 may include a first circuit gate dielectric layer 222, a first spacer layer 224, and a first circuit gate electrode 225. First source / drain regions 205 may be disposed on both sides of the first circuit gate electrode 225 in the first substrate 201.

[0055] The first peripheral region insulating layer 290 may cover the first circuit element 220, the first circuit contact plug 270, and the first circuit interconnect line 280 on the first substrate 201. The term "covering" (or "covering..." or similar terms), as may be used herein, is intended to generally refer to an element, structure, or layer being directly on or over another element, structure, or layer, or having one or more other intervening elements, structures, or layers therebetween. The first peripheral region insulating layer 290 may include multiple insulating layers formed in different process operations. The first peripheral region insulating layer 290 may be formed of an insulating material.

[0056] A first circuit contact plug 270 and a first circuit interconnect line 280 may be included in a first circuit interconnect structure electrically connected to the first circuit element 220 and the first source / drain region 205. The first circuit contact plug 270 may have a cylindrical shape, and the first circuit interconnect line 280 may have a linear shape, but embodiments are not limited thereto. An electrical signal may be applied to the first circuit element 220 through the first circuit contact plug 270 and the first circuit interconnect line 280. The first circuit interconnect line 280 may include a first lower circuit interconnect line 282 and a second upper circuit interconnect line 284. The first circuit contact plug 270 may include a first lower circuit contact plug 272 connected to the first source / drain region 205 and the first circuit gate electrode 225, and a first upper circuit contact plug 274 connected to the first lower circuit interconnect line 282 and the second upper circuit interconnect line 284. The first lower circuit interconnect line 282 may be connected to the first lower circuit contact plug 272, and the first upper circuit interconnect line 284 may be connected to the first upper circuit contact plug 274.

[0057] The first circuit contact plug 270 and the first circuit interconnection line 280 may include a conductive material, and may include, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each component may further include a diffusion barrier. In example embodiments, the number of layers of the first circuit contact plug 270 and the first circuit interconnection line 280 may be varied.

[0058] A first bonding insulating layer 299 may be provided on the first peripheral region insulating layer 290. The first bonding insulating layer 299 may be a layer for bonding the first semiconductor structure S1 and the second semiconductor structure S2. The first bonding insulating layer 299 may include, for example, at least one of SiN, SiON, SiCN, SiOC, SiOCN, or SiO.

[0059] The second semiconductor structure S2 may include a first region of a second substrate 301, a second device isolation layer 310 in the first region of the second substrate 301, a second circuit element 320 disposed on the second substrate 301, a second peripheral region insulating layer 390, a second circuit contact plug 370, a second circuit interconnection line 380, a second through-via TSV2, and a via insulating layer 315. The first region of the second substrate 301 may include a well region 302 and a second source / drain region 305.

[0060] The second substrate 301 may have an upper surface extending in the X and Y directions. An active region may be defined on the second substrate 301 by a second device isolation layer 310. A well region 302 including impurities may be disposed in a portion of the active region of the second substrate 301, and a second source / drain region 305 including impurities may be disposed in the well region 302. The well region 302 may be arranged to surround at least the second circuit element 320 disposed on the first capacitor electrode 284P of the passive element structure PE. However, the arrangement of the well region 302 is not limited thereto. The term "surround" (or similar terms), as used herein, is intended to generally refer to an element, structure, or layer surrounding, enclosing, or encircling another element, structure, or layer on all sides, even though interruptions or gaps may exist. Thus, for example, a material layer having a void or gap therein may still "surround" another layer that it surrounds. The second substrate 301 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. The second substrate 301 may be provided as a bulk wafer or an epitaxial layer.

[0061] The second circuit elements 320 may include planar transistors. Each second circuit element 320 may include a second circuit gate dielectric layer 322, a second spacer layer 324, and a second circuit gate electrode 325. Second source / drain regions 305 may be disposed on both sides of the second circuit gate electrode 325 in the second substrate 301.

[0062] The second peripheral region insulating layer 390 may cover the second circuit element 320, the second circuit contact plug 370, and the second circuit interconnection line 380 on the second substrate 301. The second peripheral region insulating layer 390 may be formed of an insulating material. In some example embodiments, the second peripheral region insulating layer 390 may include a bonding insulating layer disposed at the uppermost portion.

[0063] A second circuit contact plug 370 and a second circuit interconnection line 380 may be included in a second circuit interconnect structure electrically connected to the second circuit element 320 and the second source / drain region 305. An electrical signal may be applied to the second circuit element 320 through the second circuit contact plug 370 and the second circuit interconnection line 380. The second circuit contact plug 370 may include a second lower circuit contact plug 372 connected to the second source / drain region 305 and the second circuit gate electrode 325, and a second upper circuit contact plug 374 connected to a second lower circuit interconnection line 382 and a second upper circuit interconnection line 384. The second circuit interconnection line 380 may include a second lower circuit interconnection line 382 connected to the second lower circuit contact plug 372, and a second upper circuit interconnection line 384 connected to the second upper circuit contact plug 374.

[0064] The second through-via TSV2 may electrically and physically connect the second circuit interconnection line 380 and the first circuit interconnection line 280 of the first semiconductor structure S1. The second through-via TSV2 may be electrically connected to the first circuit element 220. The second through-via TSV2 may extend into the first semiconductor structure S1 by penetrating the second substrate 301. The second through-via TSV2 may be electrically isolated from the second substrate 301 by the via insulating layer 315.

[0065] The second circuit contact plug 370, the second circuit interconnection line 380, and the second through-via TSV2 may include a conductive material, and may include, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each component may further include an anti-diffusion layer. In example embodiments, the number of layers of the second circuit contact plug 370 and the second circuit interconnection line 380 may be variously changed.

[0066] The via insulating layer 315 may include an insulating material such as silicon oxide or silicon nitride. In example embodiments, positions of upper and lower ends of the via insulating layer 315 and thicknesses thereof may be variously changed.

[0067] The passive element structure PE may include a first capacitor electrode 284P, a second capacitor electrode 309, and first and second capacitor dielectric regions 290P and 299P therebetween. The passive element structure PE may further include a first through via TSV1 connected to the first capacitor electrode 284P and the capacitor contact plug 360.

[0068] The first capacitor electrode 284P may correspond to Figure 4B The conductive layer CL in the first region of the second substrate 301 may be disposed below the lower surface of the second substrate 301. The first capacitor electrode 284P may be the conductive layer closest to the lower surface of the first region of the second substrate 301. No other conductive material may be interposed between the first capacitor electrode 284P and the second substrate 301. The first capacitor electrode 284P may be spaced apart from the first circuit interconnect structure. On the first peripheral region insulating layer 290, the first capacitor electrode 284P may be disposed at substantially the same level as the second upper circuit interconnect line 284 disposed in the uppermost portion of the first circuit interconnect lines 280. The first capacitor electrode 284P may be spaced apart from the second upper circuit interconnect line 284 in the horizontal direction. The first capacitor electrode 284P may be formed together with the second upper circuit interconnect line 284 and may therefore include the same material and have substantially the same thickness as the second upper circuit interconnect line 284. The entire lower surface of the first capacitor electrode 284P may be covered by the first peripheral region insulating layer 290.

[0069] The second capacitor electrode 309 may be a second region of the second substrate 301. The second region of the second substrate 301 may include a region of the second substrate 301 facing the first capacitor electrode 284P and may include a region on the lower surface of the well region 302. The second region of the second substrate 301 may further include a contact region 307 disposed in the second substrate 301 at a predetermined depth from the upper surface of the second substrate 301. The second capacitor electrode 309 may include impurities. For example, the contact region 307 may include impurities of the same conductivity type as other regions of the second capacitor electrode 309 but at a different concentration. In some example embodiments, an impurity region for blocking an electric field may be further disposed between the second capacitor electrode 309 and the well region 302.

[0070] The first capacitor dielectric region 290P and the second capacitor dielectric region 299P may be arranged in parallel with the first peripheral region insulating layer 290 and the bonding insulating layer 299, respectively. The first capacitor dielectric region 290P may be formed together with the first peripheral region insulating layer 290, and the second capacitor dielectric region 299P may be formed together with the bonding insulating layer 299. By way of explanation, the first capacitor dielectric region 290P and the second capacitor dielectric region 299P may be described as regions disposed between the first capacitor electrode 284P and the second capacitor electrode 309 in the first peripheral region insulating layer 290 and the bonding insulating layer 299, respectively.

[0071] The first through-via TSV1 can electrically and physically connect the second circuit interconnect structure and the first capacitor electrode 284P. The first through-via TSV1 can extend to the level of the first semiconductor structure S1 by penetrating the second substrate 301. The first through-via TSV1 can be electrically separated from the second substrate 301 by the through-via insulating layer 315. For example, the first through-via TSV1 can be connected to both ends of the first capacitor electrode 284P in one direction (e.g., the X direction). However, in example embodiments, the arrangement position, arrangement form, and number of the first through-via TSV1 can be changed differently. In each first through-via TSV1, in a horizontal direction parallel to the upper surface of the first substrate 201, the width of its upper surface can be greater than the width of its lower surface.

[0072] The capacitor contact plug 360 may be connected to the contact region 307 to apply an electrical signal to the second capacitor electrode 309. The first through-via TSV1 and the capacitor contact plug 360 may receive different voltages, so that the first capacitor electrode 284P and the second capacitor electrode 309 may receive different voltages. For example, the second capacitor electrode 309 may receive a ground voltage through the capacitor contact plug 360. The capacitor contact plug 360 may be provided at the same level as the second lower circuit contact plug 372.

[0073] The first through-via TSV1 and the capacitor contact plug 360 may be connected to the second lower circuit interconnection line 382 of the second semiconductor structure S2. The upper surface of the first through-via TSV1 and the upper surface of the capacitor contact plug 360 may be arranged at substantially the same level. The upper surface may be arranged at substantially the same level as the upper surface of the second lower circuit contact plug 372. However, in some example embodiments, the upper surface of the first through-via TSV1 may be arranged at a level different from the level of the upper surface of the second lower circuit contact plug 372. For example, the upper surface of the first through-via TSV1 may be arranged at the same level as the upper surface of the second lower circuit interconnection line 382. The upper surface of the first through-via TSV1 may be arranged at the same level as the upper surface of the second through-via TSV2. The first through-via TSV1 and the capacitor contact plug 360 may include a conductive material, and may include, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each component may further include a diffusion barrier.

[0074] As described above, the passive element structure PE of this example embodiment may be a capacitor structure including a capacitor, and may be a metal-oxide-semiconductor (MOS) capacitor in which the second capacitor electrode 309 is formed of a semiconductor material. In some example embodiments, the passive element structure PE may include a plurality of capacitors.

[0075] As reference Figures 4A to 5 As described above, in the semiconductor device 100, the first capacitor electrode 284P may be provided on the lower surface of the second substrate 301 and may be connected to the second circuit interconnection structure on the upper surface of the second substrate 301 through the first through via TSV1. Therefore, compared to a case where the first capacitor electrode 284P is provided on the upper surface of the second substrate 301, the areas of the first to fourth circuit regions PS1, PS2, PS3, and PS4 on the upper surface of the second substrate 301 may be increased, thereby improving integration.

[0076] Figures 6A to 6C is a schematic plan view of a semiconductor device according to example embodiments. Figures 6A to 6C Shown is the corresponding Figure 4B The area in area "A".

[0077] refer to Figure 6A In the semiconductor device 100a, the lower surface 301B of the second substrate 301 (see Figure 4B) may include a first conductive layer CL1 and a second conductive layer CL2 spaced apart from each other. The first conductive layer CL1 and the second conductive layer CL2 may include line patterns alternately arranged in the Y direction and extending in the X direction, and a connecting portion connecting the line patterns and extending in the Y direction. The connecting portion may overlap with the first through-via region TS1. For example, each of the first conductive layer CL1 and the second conductive layer CL2 may be an electrode of a capacitor. In example embodiments, the relative arrangement of the first conductive layer CL1 and the second conductive layer CL2 may vary.

[0078] refer to Figure 6B In the semiconductor device 100b, the lower surface 301B of the second substrate 301 (see Figure 4B The conductive layer CLb on the conductive layer CLb may have a shape in which a plurality of line patterns are connected at their ends and extend as a layer. Both ends of the conductive layer CLb may overlap with the first through-via region TS1. For example, the conductive layer CLb may form a resistor. In example embodiments, the arrangement shape of the conductive layer CLb may vary.

[0079] refer to Figure 6C In the semiconductor device 100c, the lower surface 301B of the second substrate 301 (see Figure 4B The conductive layer CLc on the first through-via region TS1 may be arranged to form concentric squares toward the center of the arrangement area. Both ends of the conductive layer CLc may overlap with the first through-via region TS1. For example, the conductive layer CLc may form an inductor. In example embodiments, the conductive layer CLc may be arranged to form concentric circles, and the arrangement shape of the conductive layer CLc may vary.

[0080] In an example embodiment, Figure 3 The passive component structure PE may include Figure 4B and Figures 6A to 6C At least one of the passive elements formed by the conductive layers CLa, CLb, or CLc of the example embodiment.

[0081] Figure 7 is a schematic cross-sectional view of a semiconductor device according to example embodiments.

[0082] refer to Figure 7 , in the semiconductor device 100d, reference Figure 5 The description can be equally applied to the first semiconductor structure S1 and the second semiconductor structure S2.

[0083] The third semiconductor structure S3 may include a source structure SS including a third substrate 101, gate electrodes 130 stacked on the source structure SS and included in a plurality of stepped regions GP, interlayer insulating layers 120 alternately stacked with the gate electrodes 130, channel structures CH arranged to penetrate the stacked structure of the gate electrodes 130, and cell contact plugs 170 connected to the gate electrodes 130 and extending vertically (i.e., in the Z direction). The third semiconductor structure S3 may further include a horizontal insulating layer 110 disposed below the gate electrode 130, a substrate insulating layer 121 disposed to penetrate the third substrate 101, a contact insulating layer 160 surrounding the cell contact plugs 170, studs 180 on the channel structures CH and the cell contact plugs 170, a cell interconnection line 185 on the studs 180, and first and second cell region insulating layers 192 and 194 covering the gate electrodes 130.

[0084] In this example embodiment, the semiconductor device 100 d may be a NAND flash memory device in which memory cells are arranged around the channel structure CH in the third semiconductor structure S3 .

[0085] The source structure SS may include a third substrate 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104 sequentially stacked in a vertical direction. However, in example embodiments, the number of conductive layers of the source structure SS may be variously changed.

[0086] The third substrate 101 may serve as at least a portion of a common source line. The third substrate 101 may have an upper surface extending in the X direction and the Y direction (i.e., in a horizontal plane). The third substrate 101 may include a conductive material. For example, the third substrate 101 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The third substrate 101 may further include impurities. The third substrate 101 may be provided as a bulk wafer or an epitaxial layer. In some example embodiments, the third substrate 101 may be provided as a polycrystalline semiconductor layer, such as a polysilicon layer or an epitaxial layer. The third substrate 101 may be bonded to the second peripheral region insulating layer 390, or may be formed on the second peripheral region insulating layer 390.

[0087] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be stacked in sequence and disposed on the upper surface of the third substrate 101. The first horizontal conductive layer 102 may not extend below the plurality of stepped regions GP, and the second horizontal conductive layer 104 may extend below the plurality of stepped regions GP. The first horizontal conductive layer 102 may function as part of a common source line and may function as a common source line, for example, together with the third substrate 101. The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may include a semiconductor material, and may include, for example, polysilicon.

[0088] The horizontal insulating layer 110 may be provided on the third substrate 101 below the plurality of stepped regions GP at the same level as the first horizontal conductive layer 102 (i.e., coplanar with the first horizontal conductive layer 102). The horizontal insulating layer 110 may include a plurality of insulating layers. The horizontal insulating layer 110 may be a layer remaining after a portion of the horizontal insulating layer 110 is replaced by the first horizontal conductive layer 102 during the manufacturing process of the semiconductor device 100d. The horizontal insulating layer 110 may include at least one of silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0089] The substrate insulating layer 121 may be provided to penetrate the third substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104. The substrate insulating layer 121 may include an insulating material, and may include, for example, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0090] The gate electrodes 130 may be stacked on the third substrate 101 and vertically spaced apart from each other to form a stack structure together with the interlayer insulating layer 120. The stack structure may include a lower stack structure and an upper stack structure vertically stacked. However, according to example embodiments, the stack structure may be formed of a single stack structure.

[0091] The gate electrodes 130 may include a lower gate electrode 130L forming the gate of a ground select transistor, memory gate electrodes 130M for a plurality of memory cells, and an upper gate electrode 130U forming the gate of a string select transistor. The number of memory gate electrodes 130M for a memory cell may be determined according to the capacity of the semiconductor device 100d. According to example embodiments, there may be one to four or more upper gate electrodes 130U and lower gate electrodes 130L, respectively, and the upper gate electrodes 130U and lower gate electrodes 130L may have the same or different structures as the memory gate electrode 130M. In example embodiments, the gate electrodes 130 may further include a gate electrode 130 disposed above the upper gate electrode 130U and / or below the lower gate electrode 130L and included in an erase transistor used in an erase operation utilizing a gate-induced drain leakage (GIDL) current phenomenon. In addition, a portion of the gate electrode 130, such as the memory gate electrode 130M adjacent to the upper gate electrode 130U or the lower gate electrode 130L, may be a dummy gate electrode.

[0092] The gate electrode 130 may extend to different lengths along the X direction to form a stepped structure in the plurality of stepped regions GP. The gate electrode 130 may have a shape in which a predetermined depth is removed from the upper portion of any one of the lower stacked structure and the upper stacked structure of the gate electrode 130 in the stepped region GP. The stepped regions GP may be arranged so as not to overlap each other in the Z direction. At least a portion of the gate electrode 130 of the upper stacked structure may extend horizontally on the stepped region GP of the lower stacked structure. In example embodiments, the arrangement form, arrangement order, and depth of the stepped regions GP may be varied.

[0093] The gate electrode 130 may form first and second step structures in each stepped region GP in an asymmetrical shape in the X direction. In the first step structure, the gate electrode 130 may be connected to the cell contact plug 170, and in the second step structure, the gate electrode 130 may form a dummy region or dummy structure that is not connected to the cell contact plug 170. In example embodiments, the specific shape of the step structure, the number of gate electrodes 130 included in each step structure, etc. are not limited to Figure 7 In some example embodiments, the gate electrode 130 may be arranged to have a stepped structure in the Y direction.

[0094] Due to the stepped structure, the lower gate electrode 130 may extend longer than the upper gate electrode 130, so that each gate electrode 130 may have a region in which the upper surface is exposed upward from the interlayer insulating layer 120 and the other gate electrodes 130. This region may be referred to as a pad region 130P. In each gate electrode 130, the pad region 130P may be a region including the end portion of the gate electrode 130 in the X direction. The gate electrodes 130 may be connected to the cell contact plugs 170 in the pad region 130P, respectively. The gate electrode 130 may include a region having an increased cross-sectional thickness in the pad region 130P.

[0095] The gate electrode 130 may include a metal material and may include, for example, tungsten (W). According to example embodiments, the gate electrode 130 may include polysilicon or a metal silicide material. In example embodiments, the gate electrode 130 may further include a diffusion barrier, and the diffusion barrier may include, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0096] The interlayer insulating layer 120 may be disposed between the gate electrodes 130 and may therefore be included in a stacked structure having the gate electrodes 130. Similar to the gate electrodes 130, the interlayer insulating layers 120 may be spaced apart from each other in a direction perpendicular to the upper surface of the third substrate 101 and may be arranged to extend in the X direction. In the stacked structure, a relatively thick upper interlayer insulating layer 125 may be disposed on the uppermost portions of the lower stacked structure and the upper stacked structure. However, in embodiments, the thickness and shape of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 may be varied differently. The interlayer insulating layer 120 and the upper interlayer insulating layer 125 may include an insulating material such as silicon oxide or silicon nitride.

[0097] The channel structures CH may be included in each memory cell string and may be arranged in rows and columns on the third substrate 101 to be spaced apart from each other. The channel structures CH may be arranged to form a grid pattern or a zigzag shape in one direction in the XY plane. The channel structures CH may have a pillar shape and may have inclined side surfaces that narrow as they extend vertically toward the third substrate 101 according to an aspect ratio.

[0098] The channel structure CH may include a first channel structure CH1 and a second channel structure CH2 stacked vertically. The channel structure CH may have a shape in which the first channel structure CH1 below and the second channel structure CH2 above are connected, and may have a curved portion due to a width difference in the connection area. However, according to example embodiments, the number of channel structures stacked in the Z direction may vary.

[0099] Each channel structure CH may include a channel layer and a channel dielectric layer disposed within a channel hole (i.e., an opening). The channel layer may be connected to the first horizontal conductive layer 102 at its lower portion. The channel layer may include a semiconductor material such as polycrystalline silicon or single crystal silicon. The channel dielectric layer may be disposed between the gate electrode 130 and the channel layer. The channel dielectric layer may include a tunneling layer, a charge storage layer, and a blocking layer stacked sequentially from the channel layer.

[0100] The cell contact plug 170 can be connected to the contact region 130P of the gate electrode 130. The cell contact plug 170 can penetrate at least a portion of the first and second cell region insulating layers 192 and 194 and can be connected to each upwardly exposed contact region 130P of the gate electrode 130. The term "exposed" (or "exposed," or similar terms) may be used herein to describe the relationship between elements in the manufacture of an integrated circuit device and / or to refer to an intermediate process description in the manufacture of an integrated circuit device, but may not require that a particular element be exposed in the completed device. Similarly, the term "unexposed" may be used to describe the relationship between elements in the manufacture of an integrated circuit device and / or to refer to an intermediate process description in the manufacture of an integrated circuit device, but may not require that a particular element be unexposed in the completed device. The cell contact plug 170 can penetrate the gate electrode 130 below the contact region 130P, can penetrate the second horizontal conductive layer 104, the horizontal insulating layer 110, and the third substrate 101, and can be connected to the second circuit interconnect line 380 in the second semiconductor structure S2. Although not specifically shown, the cell contact plug 170 may also have a bent portion between upper and lower portions thereof, similar to the bent portion between the first and second channel structures CH1 and CH2 .

[0101] The cell contact plug 170 may be spaced apart from the gate electrode 130 below the contact region 130P by the contact insulating layer 160. The cell contact plug 170 may be spaced apart from the third substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 by the substrate insulating layer 121. However, in some example embodiments, the cell contact plug 170 may be connected to the contact region 130P without penetrating the gate electrode 130. In some example embodiments, a through via extending into the second semiconductor structure S2 by penetrating the third substrate 101 may be further provided outside the gate electrode 130.

[0102] The cell contact plug 170 may include a conductive material, such as at least one of tungsten (W), copper (Cu), aluminum (Al), or alloys thereof. In some example embodiments, the cell contact plug 170 may include a barrier layer (not explicitly shown) extending along its side surface and bottom surface, and / or may have an air gap therein.

[0103] The contact insulating layer 160 may be arranged to surround the side surface of each cell contact plug 170 below the contact region 130P. The contact insulating layers 160 may be spaced apart from each other in the Z direction around each cell contact plug 170. The contact insulating layer 160 may be provided at substantially the same level as the gate electrode 130. The contact insulating layer 160 may include an insulating material and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0104] The pillar 180 and the cell interconnection line 185 may be included in the cell interconnection structure of the memory cell electrically connected to the third semiconductor structure S3. The pillar 180 may be connected to the channel structure CH and the cell contact plug 170, and may electrically connect the channel structure CH and the gate electrode 130 to the cell interconnection line 185. The pillar 180 may have a plug shape, and the cell interconnection line 185 may have a line shape. In example embodiments, the number of plugs and interconnection lines included in the cell interconnection structure may be varied. The pillar 180 and the cell interconnection line 185 may include metal, and may include, for example, tungsten (W), copper (Cu), and aluminum (Al).

[0105] The first and second cell region insulating layers 192 and 194 may be disposed to cover the lower and upper stack structures, respectively. Each of the first and second cell region insulating layers 192 and 194 may be formed of an insulating material or may be formed of a plurality of insulating layers.

[0106] Figure 8 is a schematic cross-sectional view of a semiconductor device according to example embodiments.

[0107] refer to Figure 8 In the semiconductor device 100 e , the second semiconductor structure S2 and the third semiconductor structure S3 may be bonded by a wafer bonding method.

[0108] refer to Figure 5The description can be equally applied to the first semiconductor structure S1 and the second semiconductor structure S2. However, the second semiconductor structure S2 can further include a second bonding path 395, a second bonding metal layer 398, and a second bonding insulation layer 399, which are included in the bonding structure. The second bonding path 395 can be arranged on the uppermost portion of the second circuit interconnect line 380 and can be electrically connected to the second circuit interconnect line 380. At least a portion of the second bonding metal layer 398 can be connected to the second bonding path 395 on the second bonding path 395. The second bonding metal layer 398 can be connected to the third bonding metal layer 198 of the third semiconductor structure S3. The second bonding metal layer 398 together with the third bonding metal layer 198 can provide an electrical connection path for bonding the second semiconductor structure S2 and the third semiconductor structure S3. The second bonding path 395 and the second bonding metal layer 398 can include a conductive material, such as copper (Cu). The second bonding insulation layer 399 can be arranged around the second bonding metal layer 398. The second bonding insulation layer 399 may also serve as a diffusion barrier for the second bonding metal layer 398 and may include, for example, at least one of SiN, SiON, SiCN, SiOC, SiOCN, or SiO.

[0109] When no other description is given, refer to Figure 7 The description of the third semiconductor structure S3 may be applied to the third semiconductor structure S3. The third semiconductor structure S3 may further include a third bonding via 195, a third bonding metal layer 198, and a third bonding insulating layer 199, which are included in the bonding structure. The third semiconductor structure S3 may further include a passivation layer 106 covering the upper surface of the third substrate 101.

[0110] The third bonding via 195 and the third bonding metal layer 198 may be disposed below the lowest portion of the cell interconnection line 185. The third bonding via 195 may connect the cell interconnection line 185 and the third bonding metal layer 198, and the third bonding metal layer 198 may be bonded to the second bonding metal layer 398 of the second semiconductor structure S2. The third bonding insulating layer 199 may be bonded and connected to the second bonding insulating layer 399 of the second semiconductor structure S2 by bonding. The third bonding via 195 and the third bonding metal layer 198 may include a conductive material, such as copper (Cu). The third bonding insulating layer 199 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, or SiOCN.

[0111] The second semiconductor structure S2 and the third semiconductor structure S3 may be bonded to each other by bonding the second bonding metal layer 398 and the third bonding metal layer 198 and bonding the second bonding insulating layer 399 and the third bonding insulating layer 199. The second semiconductor structure S2 and the third semiconductor structure S3 may be bonded by hybrid bonding including copper (Cu)-to-copper (Cu) bonding and dielectric-to-dielectric bonding.

[0112] In example embodiments, the third semiconductor structure S3 may not include the first horizontal conductive layer 102 and the second horizontal conductive layer 104 (see FIG. Figure 7 ). In a state where the channel layer is exposed through its upper end, the channel structure CH may be directly connected to the third substrate 101. However, in an embodiment, the electrical connection shape of the channel structure CH and the common source line may be variously changed, and the channel structure CH and the source structure SS may have the same Figure 7 The same structure as the embodiment of the present invention.

[0113] The passivation layer 106 may be disposed on the upper surface of the third substrate 101 and may protect the semiconductor device 100e. The passivation layer 106 may include at least one of insulating materials, and may include, for example, silicon oxide, silicon nitride, or silicon carbide.

[0114] 9A to 9I are schematic cross-sectional views illustrating intermediate processes in an exemplary method of fabricating a semiconductor device according to example embodiments. 9A to 9I Shows the manufacturing Figure 7 Embodiments of the method of semiconductor device, each of which shows a corresponding Figure 7 cross-section.

[0115] refer to Figure 9A , a first circuit element 220 , a first circuit interconnection structure, a first capacitor electrode 284P, and a first peripheral region insulating layer 290 may be formed on the first substrate 201 of the first semiconductor structure S1.

[0116] First, a first device isolation layer 210 may be formed in the first substrate 201, and a first circuit gate dielectric layer 222 and a first circuit gate electrode 225 may be sequentially formed on the first substrate 201. The first device isolation layer 210 may be formed, for example, by a shallow trench isolation (STI) process. The first circuit gate dielectric layer 222 and the first circuit gate electrode 225 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD), but the embodiment is not limited thereto. The first circuit gate dielectric layer 222 may be formed of silicon oxide, and the first circuit gate electrode 225 may be formed of at least one of polysilicon or a metal silicide layer, but the present disclosure is not limited thereto.

[0117] Next, a first spacer layer 224 may be formed on both sidewalls of the first circuit gate dielectric layer 222 and the first circuit gate electrode 225, and first source / drain regions 205 may be formed in the first substrate 201 on both sides of the first circuit gate electrode 225. According to example embodiments, the first spacer layer 224 may be formed of multiple layers. The first source / drain regions 205 may be formed by performing an ion implantation process (e.g., using the first circuit gate electrode 225 as an implantation mask).

[0118] The first circuit contact plug 270 in the first circuit interconnect structure can be formed by forming a portion of the first peripheral region insulating layer 290, then partially etching and removing the first peripheral region insulating layer 290, and filling the removed portion with a conductive material. The term "filled..." (or "fill" or similar terms), as used herein, is intended to broadly refer to completely filling a defined space (e.g., the removed portion of the first peripheral region insulating layer 290) or partially filling a defined space; that is, the defined space need not be completely filled, but can, for example, be partially filled or have gaps or other spaces throughout. The first circuit interconnect line 280 can be formed, for example, by depositing a conductive material and then patterning the conductive material. The first capacitor electrode 284P can be formed together with the second upper circuit interconnect line 284 and can be formed to be horizontally spaced apart from the second upper circuit interconnect line 284.

[0119] The first peripheral region insulating layer 290 may be formed of a plurality of insulating layers. The first peripheral region insulating layer 290 may be partially formed in each operation of forming the first circuit interconnection structure.

[0120] refer to Figure 9B , a first peripheral region insulating layer 290 may be further formed on the second upper circuit interconnection line 284 and the first capacitor electrode 284P, and a first bonding insulating layer 299 may be formed.

[0121] The first bonding insulating layer 299 may be used to bond with the second semiconductor structure S2 (see Figure 9C ) is bonded to a second substrate 301. The first bonding insulating layer 299 may be, for example, SiCN, but the present disclosure is not limited thereto. The first peripheral region insulating layer 290 on the first capacitor electrode 284P and the first bonding insulating layer 299 on the first capacitor electrode 284P may form a first capacitor dielectric region 290P and a second capacitor dielectric region 299P, respectively.

[0122] Through this operation, the first semiconductor structure S1 can be formed, and the passive element structure PE can be formed (see Figure 7 ) part.

[0123] refer to Figure 9CThe second substrate 301 of the second semiconductor structure S2 may be bonded to the first semiconductor structure S1 , and the second circuit element 320 , the second lower circuit contact plug 372 , and the capacitor contact plug 360 may be formed on the second substrate 301 .

[0124] Through the same process as the first semiconductor structure S1 described above, a second device isolation layer 310 can be formed in the second substrate 301. After the well region 302 is formed, a second circuit element 320 can be formed on the second substrate 301, and a second source / drain region 305 and a contact region 307 can be formed. The well region 302, the second source / drain region 305, and the contact region 307 can be formed by, for example, an ion implantation process.

[0125] By forming the second peripheral region insulating layer 390 (see Figure 9E ) and then partially etching and removing the second peripheral region insulating layer 390 and filling the removed portion with a conductive material to form a second lower circuit contact plug 372 and a capacitor contact plug 360. The capacitor contact plug 360 may be formed together with the second lower circuit contact plug 372.

[0126] refer to Figure 9D , a first through via TSV1 and a second through via TSV2 may be formed.

[0127] First, a penetrating second peripheral region insulating layer 390 (see FIG. Figure 9E ) and a second substrate 301 and a via hole exposing the second upper circuit interconnection line 284 and the first capacitor electrode 284P. A via insulating layer 315 may be formed in the via hole and the remaining portion of the via hole may be filled with a conductive material to form a first through via TSV1 and a second through via TSV2. The first through via TSV1 may contact the first capacitor electrode 284P, and the second through via TSV2 may contact the second upper circuit interconnection line 284. In some example embodiments, the first through via TSV1 and the second through via TSV2 may be formed in the second lower circuit interconnection line 382 (see Figure 9E ) is formed after.

[0128] By this operation, a passive element structure PE (see Figure 8 ).

[0129] refer to Figure 9E , a second circuit interconnection structure can be formed.

[0130] First, a second peripheral region insulating layer 390 may be further formed, and second circuit contact plugs 370 and second circuit interconnection lines 380 of the second circuit interconnection structure may be formed by the same process as in the first semiconductor structure S1 described above.

[0131] Through this operation, a second semiconductor structure S2 may be formed.

[0132] refer to Figure 9F , the third substrate 101 of the third semiconductor structure S3 can be bonded to the second semiconductor structure S2, a horizontal insulating layer 110 and a second horizontal conductive layer 104 can be formed, a substrate insulating layer 121 can be formed, sacrificial insulating layers 118 and interlayer insulating layers 120 can be alternately stacked, a stepped structure of the sacrificial insulating layers 118 and the interlayer insulating layers 120 can be formed, and a first vertical sacrificial layer 119a and a second vertical sacrificial layer 119b can be formed.

[0133] The third substrate 101 may be bonded to the third peripheral region insulating layer 390. In some example embodiments, the third substrate 101 may be formed of, for example, polysilicon and may be formed in a CVD process. A plurality of insulating layers of the horizontal insulating layer 110 may be sequentially stacked in the Z direction (i.e., vertically) on the third substrate 101. Some areas of the horizontal insulating layer 110 may be removed in the patterning process. The second horizontal conductive layer 104 may be formed on the horizontal insulating layer 110 and may be bent in the area where the horizontal insulating layer 110 has been removed and may contact the third substrate 101. The substrate insulating layer 121 may be formed to include a substrate to be provided. Figure 7 The cell contact plugs 170 penetrate (ie, extend through) the third substrate 101 , the horizontal insulating layer 110 , and the second horizontal conductive layer 104 in some areas of the region.

[0134] Next, sacrificial insulating layers 118 and interlayer insulating layers 120 may be alternately stacked to form a lower mold structure. The lower mold structure may be formed relative to the upper surface of the third substrate 101 at a position where the first channel structure CH1 (see FIG. 1 ) is provided. Figure 7 ) at a height of . A relatively thick upper interlayer insulating layer 125 may be formed on the interlayer insulating layer 120. The sacrificial insulating layer 118 may be formed of a material different from the interlayer insulating layer 120. Next, a stepped region GP may be formed by partially removing the sacrificial insulating layer 118 and the interlayer insulating layer 120 from the upper portion. The sacrificial insulating layer 118 may form a stepped structure in predetermined units, and the sacrificial insulating layer 118 in the uppermost portion of the sacrificial insulating layer 118 provided in the stepped region GP may be exposed upward.

[0135] Next, a first cell region insulating layer 192 covering the lower mold structure may be formed, and a first vertical sacrificial layer 119a penetrating the lower mold structure may be formed. The first vertical sacrificial layer 119a may be formed at a position corresponding to Figure 7The first vertical sacrificial layer 119a may include, for example, polysilicon, a carbon-based material, or a metal material.

[0136] Next, an upper mold structure may be formed on the lower mold structure in the same manner, and second vertical sacrificial layers 119b may be formed. The second vertical sacrificial layers 119b may be formed to be connected to the first vertical sacrificial layers 119a, respectively.

[0137] refer to Figure 9G , a channel structure CH and a cell contact hole OH may be formed.

[0138] First, the first vertical sacrificial layer 119a and the second vertical sacrificial layer 119b (see FIG. Figure 9F ) to form a hole-shaped channel hole and then deposit a channel layer, a channel dielectric layer, etc. to form a channel structure CH.

[0139] Next, the first vertical sacrificial layer 119a and the second vertical sacrificial layer 119b (see FIG. Figure 9F ) and further removing the second peripheral region insulating layer 390 exposed through the bottom surface thereof to form a cell contact hole OH. The second circuit interconnection line 380 may be exposed through the bottom surface of the cell contact hole OH.

[0140] refer to Figure 9H , a preliminary contact insulating layer 160P and a vertical sacrificial layer 191 may be formed in the cell contact hole OH, a first horizontal conductive layer 102 may be formed, and the sacrificial insulating layer 118 may be removed (see Figure 9G ).

[0141] First, the through-cell contact holes OH (see FIG. Figure 9G ) exposed portion. The tunnel portion can be formed by removing a predetermined length of the sacrificial insulating layer 118 around the cell contact hole OH. In one stepped region GP, ​​the tunnel portion can be formed to have a relatively short length in the sacrificial insulating layer 118 in the uppermost portion, and can be formed to have a relatively long length in the sacrificial insulating layer 118 disposed therebelow.

[0142] Next, an insulating material may be deposited in the cell contact hole OH and the tunnel portion to form a preliminary contact insulating layer 160P. The preliminary contact insulating layer 160P may be formed on the sidewalls of the cell contact hole OH and fill the tunnel portion. The preliminary contact insulating layer 160P may not completely fill the tunnel portion in the uppermost portion of the stepped region GP. A vertical sacrificial layer 191 may fill the cell contact hole OH and the tunnel portion in the uppermost portion thereof. The vertical sacrificial layer 191 may include a material different from that of the preliminary contact insulating layer 160P and may include, for example, polysilicon.

[0143] Next, an opening may be formed in an area (not shown) extending to the third substrate 101 by penetrating the sacrificial insulating layer 118 and the interlayer insulating layer 120. Next, the horizontal insulating layer 110 may be selectively removed through the opening, and a conductive material may be deposited in the area where the horizontal insulating layer 110 has been removed, thereby forming the first horizontal conductive layer 102.

[0144] Next, the sacrificial insulating layer 118 may be selectively removed relative to the interlayer insulating layer 120 , the second horizontal conductive layer 104 , and the preliminary contact insulating layer 160P using, for example, wet etching. As a result, a tunnel portion TL may be formed in the region where the sacrificial insulating layer 118 has been removed.

[0145] refer to Figure 9I , the gate electrode 130 and the cell contact plug 170 may be formed.

[0146] This can be done by using the tunnel section TL (see Figure 9H ) to form a gate electrode 130. The conductive material may include metal, polysilicon or metal silicide material.

[0147] Next, the vertical sacrificial layer 191 in the cell contact hole OH may be removed (see FIG. Figure 9H ). Vertical sacrificial layer 191 may be removed selectively with respect to interlayer insulating layer 120 and gate electrode 130. Portions of preliminary contact insulating layer 160P exposed after vertical sacrificial layer 191 has been removed may also be removed. In this case, all of preliminary contact insulating layer 160P may be removed from pad region 130P and may remain thereunder, thereby forming contact insulating layer 160.

[0148] The cell contact plug 170 may be formed by depositing a conductive material in the cell contact hole OH. The cell contact plug 170 may be formed to have a horizontally extending portion horizontally extending from the pad region 130P and thus may be physically and electrically connected to the gate electrode 130 .

[0149] Next, refer to Figure 7 , pillars 180 and cell interconnection lines 185 connected to the cell contact plugs 170 and upper ends of the channel structures CH may be formed, thereby forming a third semiconductor structure S3 and manufacturing the semiconductor device 100 d.

[0150] Figure 10 is a block diagram schematically illustrating a data storage system including a semiconductor device according to example embodiments.

[0151] refer to Figure 10, the data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or more semiconductor devices 1100, or may be an electronic device including a storage device. For example, the data storage system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device, which includes one or more semiconductor devices 1100.

[0152] The semiconductor device 1100 may be a nonvolatile memory device, for example, the semiconductor device 1100 may be a nonvolatile memory device as described above. Figure 7 and Figure 8 The NAND flash memory device described herein may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an example embodiment, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including one or more bit lines BL, a common source line CSL, a word line WL, first and second upper gate lines UL1 and UL2, first and second lower gate lines LL1 and LL2, and a memory cell string CSTR between the bit lines BL and the common source line CSL.

[0153] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a corresponding one of the bit lines BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. According to example embodiments, the number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be variously changed.

[0154] In example embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0155] In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 or the upper erase control transistor UT2 may be used for an erase operation for deleting data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0156] The common source line CSL, the first and second lower gate lines LL1 and LL2, the word line WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connection interconnection line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection interconnection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0157] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 through one or more input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 through one or more input / output connection interconnection lines 1135 extending from the first structure 1100F to the second structure 1100S.

[0158] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface (I / F) 1230 . According to example embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , in which case the controller 1200 may control the plurality of semiconductor devices 1100 .

[0159] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include a controller interface 1221 configured to handle communications with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be recorded in memory cell transistors MCT of semiconductor device 1100, and data to be read from memory cell transistors MCT of semiconductor device 1100 can be transmitted via controller interface 1221. Host interface 1230 can provide communication functionality between data storage system 1000 and an external host. Upon receiving a control command from an external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0160] Figure 11 is a perspective view schematically illustrating a data storage system including a semiconductor device according to example embodiments.

[0161] refer to Figure 11 , a data storage system 2000 according to an example embodiment of the present disclosure may include a main board 2001, a controller 2002 provided on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through an interconnection pattern 2005 formed on the main board 2001.

[0162] The mainboard 2001 may include a connector 2006 including a plurality of pins for connecting to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an example embodiment, the data storage system 2000 may communicate with the external host through any one of interfaces such as a universal serial bus (USB), a peripheral component interconnect fast (PCI-Express), a serial advanced technology attachment (SATA), and M-Phy for universal flash storage (UFS). In an example embodiment, the data storage system 2000 may operate with power supplied from the external host through the connector 2006. The data storage system 2000 may further include a power management integrated circuit (PMIC) configured to distribute the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0163] The controller 2002 may record data in or read data from the semiconductor package 2003 and may increase the operating speed of the data storage system 2000 .

[0164] DRAM 2004 can be a buffer memory to mitigate the speed difference between semiconductor package 2003, which serves as a data storage space, and an external host. DRAM 2004 included in data storage system 2000 can also operate as a high-speed cache memory and can provide space for temporarily storing data during control operations of semiconductor package 2003. When data storage system 2000 includes DRAM 2004, controller 2002 can further include a DRAM controller for controlling DRAM 2004 in addition to a NAND controller for controlling semiconductor package 2003.

[0165] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a mold layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0166] The package substrate 2100 may be a printed circuit board including package pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Figure 10 Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include the above reference Figure 7 or Figure 8 A semiconductor device is described.

[0167] In example embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input / output pads 2210 of the package and the package upper pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire method and may be electrically connected to the package upper pads 2130 of the package substrate 2100. According to example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including through-silicon vias (TSVs) instead of the bonding wire type connection structure 2400.

[0168] In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on an additional interposer substrate different from the main board 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other through interconnection lines formed on the interposer substrate.

[0169] Figure 12 is a cross-sectional view schematically illustrating a semiconductor package according to example embodiments. Figure 12 Shown Figure 11 An example embodiment of a semiconductor package 2003 is shown, and conceptually illustrates a Figure 11 The semiconductor packaging in 2003 Figure 11 The cutting line II-II' is the area to be cut.

[0170] refer to Figure 12 In the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body 2120, a package upper pad 2130 (see FIG. 1 ) provided on the upper surface of the package substrate body 2120, and a package upper pad 2130 (see FIG. 1 ). Figure 11 ), lower pads 2125 provided on or exposed through the lower surface of the package substrate body 2120, and internal interconnection lines 2135 electrically connecting the upper pads 2130 and the lower pads 2125 within the package substrate body 2120. The lower pads 2125 may be electrically connected to the conductive connectors 2800, such as Figure 11 An interconnect pattern 2005 is shown on a main board 2001 of a data storage system 2000 .

[0171] Each semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010 in a vertical direction. The first structure 3100 may include a peripheral circuit region including a peripheral interconnection line 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line WL electrically connected to the gate stack structure 3210 (see FIG. 2 ). Figure 10 ) of the contact plug 3235. As mentioned above Figure 7 and Figure 8As described above, in each semiconductor chip 2200 , the first structure 3100 may include first and second semiconductor structures S1 and S2 and a passive element structure PE. The first capacitor electrode 284P of the passive element structure PE may be disposed under the second substrate 301 and connected to a first through via TSV1 penetrating the second substrate 301 .

[0172] Each semiconductor chip 2200 may include a through-interconnection line 3245 electrically connected to the peripheral interconnection line 3110 of the first structure 3100 and extending into the second structure 3200. The through-interconnection line 3245 may be disposed outside the gate stack structure 3210 and may be further disposed to penetrate the gate stack structure 3210. Each semiconductor chip 2200 may further include an input / output pad 2210 (see FIG. 2 ) electrically connected to the peripheral interconnection line 3110 of the first structure 3100. Figure 11 ).

[0173] The present disclosure is not limited to the above-described embodiments and drawings, but is defined by the appended claims. Therefore, without departing from the scope of the present disclosure as defined by the appended claims, a person of ordinary skill in the art may make various substitutions, modifications, changes, or combinations of the embodiments, and such substitutions, modifications, changes, or combinations of the embodiments should be construed as being included within the scope of the present disclosure.

[0174] CROSS-REFERENCE TO RELATED APPLICATIONS

[0175] This application claims the benefit of priority from Korean Patent Application No. 10-2024-0049465 filed on April 12, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device comprising: A first semiconductor structure includes a first substrate, a first circuit element on the first substrate, a first circuit interconnection line on the first circuit element, and a first peripheral region insulating layer on the first circuit interconnection line; a second semiconductor structure comprising a first region of a second substrate on the first semiconductor structure, a second circuit element on the first region of an upper surface of the second substrate, and a second circuit interconnection line on the second circuit element; a capacitor structure comprising a first capacitor electrode, a second region of the second substrate facing the first capacitor electrode, and a first through-via extending in the second substrate and electrically connected to the first capacitor electrode, the first capacitor electrode being spaced apart from the first circuit interconnection line on a lower surface of the second substrate, the lower surface of the second substrate being opposite to the upper surface of the second substrate in a vertical direction perpendicular to the lower surface of the second substrate; as well as The third semiconductor structure includes a third substrate on the second semiconductor structure and the capacitor structure, and a memory cell on the third substrate. 2 . The semiconductor device according to claim 1 , wherein the capacitor structure further comprises a capacitor contact plug on the second region of the second substrate and electrically connected to the second region of the second substrate. 3 . The semiconductor device according to claim 2 , wherein the first through via and the capacitor contact plug are configured to receive different voltages. 4 . The semiconductor device of claim 1 , wherein the capacitor structure further comprises a capacitor dielectric region between the first capacitor electrode and the second region of the second substrate. 5 . The semiconductor device according to claim 1 , wherein the first through via at least partially overlaps the first capacitor electrode in a plan view. 6 . The semiconductor device according to claim 1 , wherein the first capacitor electrode overlaps with at least a portion of the second circuit element in a plan view. 7 . The semiconductor device according to claim 1 , wherein the first peripheral region insulating layer is on the entire lower surface of the first capacitor electrode. 8 . The semiconductor device according to claim 1 , wherein the first through via includes a plurality of through vias electrically connected to respective opposite ends of the first capacitor electrode in a horizontal direction parallel to the lower surface of the second substrate. 9 . The semiconductor device according to claim 1 , wherein the second semiconductor structure further comprises a second through via extending in the second substrate, connected to the first circuit interconnection line, and electrically connected to the first circuit element.

10. The semiconductor device according to claim 1, wherein the first semiconductor structure further comprises a first bonding insulating layer on the first peripheral region insulating layer, and The first through via further extends in the first joining insulating layer. 11 . The semiconductor device of claim 1 , wherein the first capacitor electrode comprises a same material as at least an uppermost portion of the first circuit interconnection line. 12 . The semiconductor device according to claim 1 , wherein the first region of the second substrate includes source / drain regions of the second circuit element and a well region extending around the source / drain regions.

13. The semiconductor device according to claim 1, wherein the third semiconductor structure further comprises: gate electrodes stacked on the third substrate and spaced apart from each other in the vertical direction; as well as A channel structure extends in the gate electrode in the vertical direction.

14. A semiconductor device comprising: First substrate: a first circuit element on the first substrate; circuit interconnects on the first circuit element; a passive component structure comprising a conductive layer spaced apart from the circuit interconnection line in a vertical direction perpendicular to the upper surface of the first substrate; a peripheral region insulating layer on the circuit interconnects and the conductive layer; a second substrate on the peripheral region insulating layer; a first through via extending in the second substrate and electrically connected to the conductive layer; as well as A second through via penetrates the second substrate and is electrically connected to the circuit interconnection line. 15 . The semiconductor device according to claim 14 , wherein the peripheral region insulating layer is on the entire lower surface of the conductive layer. 16 . The semiconductor device of claim 14 , wherein the passive component structure comprises at least one of a resistor, an inductor, or a capacitor.

17. The semiconductor device according to claim 14, wherein An upper surface of the first through via is coplanar with an upper surface of the second through via relative to an upper surface of the second substrate.

18. The semiconductor device according to claim 14, further comprising: a second circuit element on the second substrate, wherein the conductive layer at least partially vertically overlaps at least one of the second circuit elements.

19. A data storage system comprising: Semiconductor memory devices, including: a first semiconductor structure comprising a first substrate, a first circuit element on the first substrate, and a first circuit interconnect structure on the first circuit element; a second semiconductor structure comprising a second substrate on the first semiconductor structure, a second circuit element on an upper surface of the second substrate, and a second circuit interconnect structure on the second circuit element; a third semiconductor structure on the second semiconductor structure and comprising a memory cell; a passive component structure including a conductive layer on a lower surface of the second substrate opposite to the upper surface of the second substrate and a through via extending in the second substrate and electrically connected to the conductive layer; and an input / output pad electrically connected to the first circuit element and the second circuit element; and A controller is electrically connected to the semiconductor memory device through the input / output pads and is configured to control the semiconductor memory device.

20. The data storage system of claim 19, wherein the conductive layer is spaced apart from the first circuit interconnect structure in a vertical direction perpendicular to the lower surface of the second substrate.

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