Semiconductor structure, memory system and manufacturing method of semiconductor structure

Abstract

The embodiment of the invention provides a semiconductor structure, a memory system and a manufacturing method of the semiconductor structure. The semiconductor structure comprises a stacked structure; the grid line isolation structure penetrates through the stacking structure and comprises a first isolation part and a second isolation part which are arranged in the first direction, and the first isolation part and the second isolation part extend in the first direction; the insulation structure penetrates through the stacking structure and is connected between the first isolation part and the second isolation part; wherein the first direction intersects with the stacking direction of the stacking structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a memory system, and a method for manufacturing the semiconductor structure. Background Art

[0002] To improve the integration density of semiconductor structures, the number of stacked layers in the semiconductor structure is gradually increasing. However, a high number of stacked layers increases the risk of the semiconductor structure toppling, thereby reducing the stability of the semiconductor structure and making it difficult to achieve the expected yield. Summary of the Invention

[0003] The present application provides a semiconductor structure, a memory system, and a method for manufacturing a semiconductor structure that can at least partially solve the above-mentioned problems or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor structure. The semiconductor structure includes: a stacked structure; a gate line isolation structure extending through the stacked structure and including a first isolation portion and a second isolation portion arranged along a first direction, both of which extend along the first direction; and an insulation structure extending through the stacked structure and connected between the first isolation portion and the second isolation portion; wherein the first direction intersects the stacking direction of the stacked structure.

[0005] In an exemplary embodiment, a size of the insulating structure is larger than a size of the first isolation portion and larger than a size of the second isolation portion in a second direction, and the first direction, the second direction, and the stacking direction intersect each other.

[0006] In an exemplary embodiment, the semiconductor structure further includes a filling structure penetrating the insulating structure and having a spacing distance from the first isolation portion and the second isolation portion in the first direction, respectively.

[0007] In an exemplary embodiment, the material filling the structure includes, from outside to inside, one of the following: silicon oxide and polysilicon; silicon oxide, silicon nitride, and polysilicon; silicon oxide; silicon oxide, polysilicon, and silicon oxide.

[0008] In an exemplary embodiment, the first isolation portion, the second isolation portion, and the filling structure are made of the same material.

[0009] In an exemplary embodiment, the material of the insulating structure includes silicon oxide.

[0010] In an exemplary embodiment, on a plane perpendicular to the stacking direction, the stacking structure is divided into a storage area and a connection area along a first direction, and a plurality of insulating structures are arranged at intervals along the first direction within the storage area.

[0011] In an exemplary embodiment, in the first direction, a dimension between adjacent insulating structures is greater than or equal to 5 μm, and a dimension of the insulating structure is greater than or equal to 500 nm.

[0012] In an exemplary embodiment, multiple dielectric layers intermittently cover the end surfaces of the first isolation part and the second isolation part in the stacking direction; wherein, in the second direction, the size of the dielectric layer is larger than the size of the first isolation part and larger than the size of the second isolation part, and the first direction, the second direction and the stacking direction intersect with each other.

[0013] In an exemplary embodiment, in the first direction, a size of adjacent dielectric layers is greater than or equal to 300 nm, and a size of the dielectric layer is greater than or equal to 150 nm.

[0014] In an exemplary embodiment, the material of the plurality of dielectric layers includes silicon oxide.

[0015] In an exemplary embodiment, the stacked structure is divided into memory blocks by gate line isolation structures and insulating structures adjacent in the second direction, and a dielectric layer connects adjacent memory blocks.

[0016] In an exemplary embodiment, sidewalls of the first isolation portion and the second isolation portion are both planar.

[0017] In an exemplary embodiment, the semiconductor structure further includes: a channel structure extending in the insulating structure along the stacking direction.

[0018] In a second aspect, some embodiments of the present application provide a memory system comprising: a memory including a semiconductor structure as described in any of the above embodiments; and a controller coupled to the memory and configured to control the memory to store data.

[0019] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor structure. The method includes: forming a first slit portion, a first trench, and a second slit portion that penetrate an initial stacked structure, wherein the initial stacked structure includes alternating first and second dielectric layers, the first slit portion, the first trench, and the second slit portion are spaced apart along a first direction, and both the first and second slit portions extend along the first direction; replacing a portion of each second dielectric layer around the first trench with a plurality of third dielectric layers; and forming a first isolation portion and a second isolation portion in the first and second slit portions, respectively; wherein the first direction intersects with a stacking direction of the initial stacked structure.

[0020] In an exemplary embodiment, before replacing a portion of each second dielectric layer at the periphery of the first trench with a plurality of third dielectric layers, the manufacturing method further includes: forming a sacrificial material layer in the first gap portion and the second gap portion; wherein replacing a portion of each second dielectric layer at the periphery of the first trench with a plurality of third dielectric layers includes: removing a portion of each second dielectric layer at the periphery of the first trench to the sacrificial material layer and forming a plurality of first gaps; and forming a plurality of third dielectric layers in the plurality of first gaps.

[0021] In an exemplary embodiment, after replacing a portion of each second dielectric layer on the periphery of the first trench with a plurality of third dielectric layers, the manufacturing method further includes: forming an initial fourth dielectric layer on one side of the initial stacking structure and the sacrificial material layer in the stacking direction; and removing a portion of the initial fourth dielectric layer so that the retained plurality of fourth dielectric layers are intermittently located on one side of the sacrificial material layer, and the size of each retained fourth dielectric layer in the second direction is larger than the size of the sacrificial material layer in the second direction; wherein the first direction, the second direction, and the stacking direction intersect with each other.

[0022] In an exemplary embodiment, before forming the first isolation portion and the second isolation portion in the first slit portion and the second slit portion, respectively, the manufacturing method further includes: removing the sacrificial material layer and exposing the first slit portion and the second slit portion; using the first slit portion and the second slit portion, removing at least a portion of each second dielectric layer to form a plurality of second gaps; and forming a plurality of gate layers in the plurality of second gaps.

[0023] In an exemplary embodiment, on a plane perpendicular to the stacking direction, the initial stacking structure is divided into a storage area and a connection area along a first direction, the first gap portion is located in the storage area, and the second gap portion is located in the storage area and the connection area; wherein, using the first gap portion and the second gap portion to remove at least a portion of each second dielectric layer to form a plurality of second gaps includes: using the second gap portion to remove a portion of each second dielectric layer located in the connection area; and using the first gap portion and the second gap portion to remove each second dielectric layer located in the storage area to form a plurality of second gaps.

[0024] In an exemplary embodiment, after replacing a portion of each second dielectric layer around the first trench with a plurality of third dielectric layers, the manufacturing method further includes: forming a filling structure in the first trench.

[0025] In an exemplary embodiment, the filling structure, the first isolation portion, and the second isolation portion are formed in the same thin film deposition process. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0027] Figure 1 is a three-dimensional schematic diagram of a semiconductor structure according to an embodiment of the present application;

[0028] Figures 2A to 2C is a schematic structural diagram of a semiconductor structure according to another embodiment of the present application;

[0029] Figure 3 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application;

[0030] Figures 4A to 18 This is a schematic structural diagram of a semiconductor structure during the manufacturing process according to an embodiment of the present application;

[0031] Figure 19 is a block diagram of a system having a memory system according to an embodiment of the present application; and

[0032] Figure 20A and Figure 20B is a schematic diagram of a memory system according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] It should be noted that in this specification, the terms "first," "second," "third," etc., are used solely to distinguish one feature from another and do not limit the features, and in particular do not indicate any order of precedence. Therefore, without departing from the teachings of this application, the first dielectric layer discussed in this application may also be referred to as the second dielectric layer, and vice versa.

[0035] In the accompanying drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The accompanying drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximations, not degrees, and are intended to account for the inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0036] It should also be understood that expressions such as "comprises," "including," "having," "includes," and / or "comprising" are open rather than closed expressions in this specification, indicating the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplary" is intended to refer to an example or illustration.

[0037] Unless otherwise defined, all words used herein (including engineering terms and scientific and technological terms) have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that, unless otherwise specified in this application, words defined in commonly used dictionaries should be interpreted as having the same meaning as they do in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0038] It should be noted that, unless there is a conflict, the embodiments and features of the embodiments in this application may be combined with each other. In addition, unless explicitly limited or inconsistent with the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but may be performed in any order or in parallel.

[0039] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0040] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0041] Some embodiments of the present application provide a semiconductor structure. Figure 1 100 is a perspective schematic diagram of a semiconductor structure according to an embodiment of the present invention. In order to more clearly illustrate the internal structure of the semiconductor structure 100, Figure 1 Part of the semiconductor structure 100 is removed to expose the internal structure of the semiconductor structure 100 .

[0042] It should be noted that the D1, D2, and D3 directions in the various figures illustrate the spatial relationships between components in the semiconductor structure. For example, the D3 direction is the stacking direction of the stacked structure (or initial stacked structure), and the D1 and D2 directions are two directions that intersect (e.g., are perpendicular to) each other on a plane that intersects (e.g., is perpendicular to) the stacking direction. For example, the D1 direction is the extension direction of the first isolation portion or the second isolation portion. The same concept will be used throughout this application to describe the spatial relationships between components in the semiconductor structure.

[0043] like Figure 1 As shown, semiconductor structure 100 includes a stacked structure 111, a gate line isolation structure 112, and an insulating structure 113. Gate line isolation structure 112 extends through stacked structure 111 and includes a first isolation portion 1121 and a second isolation portion 1122 arranged along direction D1. First isolation portion 1121 and second isolation portion 1122 both extend along direction D1. Insulation structure 113 extends through stacked structure 111 and connects first isolation portion 1121 and second isolation portion 1122.

[0044] According to the semiconductor structure 100 provided in the above embodiment, the first isolation portion 1121 and the second isolation portion 1122 arranged along the D1 direction both extend along the D1 direction and penetrate the stacked structure 111. The insulating structure 113 penetrates the stacked structure 111 and connects between the first isolation portion 1121 and the second isolation portion 1122, thereby helping to optimize structural stress, alleviate the problem of semiconductor structure tipping, and improve the stability and yield of the semiconductor structure 100. Furthermore, the insulating structure 113 and the gate line isolation structure 112 can also electrically isolate the stacked structure 111 located on either side thereof.

[0045] In some embodiments, the stacked structure 111 may include a first stacked portion 1111 and a second stacked portion 1112. As viewed in the direction D3, the first stacked portion 1111 at least partially surrounds the second stacked portion 1112. The first stacked portion 1111 may include alternating first dielectric layers 1113 and gate layers 1114 along the direction D3. The second stacked portion 1112 may include alternating first dielectric layers 1113 and second dielectric layers 1115 along the direction D3. For example, each first dielectric layer 1113 in the first stacked portion 1111 and the second stacked portion 1112 may extend continuously laterally in a plane perpendicular to the direction D3 and may be a unitary structure. Each gate layer 1114 and each second dielectric layer 1115 may be connected in a one-to-one correspondence and extend laterally in a plane perpendicular to the direction D3.

[0046] In some embodiments, the material of the first dielectric layer 1113 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO xN y ) or any other suitable insulating material. For example, the material of the first dielectric layer 1113 may be silicon oxide (SiO2). The material of the gate layer 1114 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), polycrystalline silicon (poly-Si), amorphous silicon (α-Si), tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru) or any other suitable conductive material. The material of the second dielectric layer 1115 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. The material of the second dielectric layer 1115 may be different from the material of the first dielectric layer 1113. For example, the material of the second dielectric layer 1115 may be silicon nitride (Si3N4).

[0047] In some embodiments, on a plane perpendicular to the D3 direction, the stacked structure 111 can be divided along the D1 direction into a storage area 101 and a connection area 102. For example, the first stacked portion 1111 is located within the storage area 101 and a portion of the connection area 102, and the second stacked portion 1112 is located within the connection area 102. The first stacked portion 1111 within the connection area 102 can be located on both sides of the second stacked portion 1112 along the D2 direction.

[0048] In some other embodiments, the stack structure may include alternately stacked first dielectric layers and gate layers along the D3 direction, and the stack structure in the connection region may have a stepped structure (not shown).

[0049] In some embodiments, the gate line isolation structure 112 extends within the storage region 101 and the connection region 102 and is separated into a first isolation portion 1121 and a second isolation portion 1122 by the insulation structure 113. For example, the first stacking portion 1111 within the connection region 102 may contact the second isolation portion 1122.

[0050] In some embodiments, the material of the portion of the gate line isolation structure 112 that contacts the first stack portion 1111 includes silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating materials.

[0051] In some embodiments, the first isolation portion 1121 and the second isolation portion 1122 in the gate line isolation structure 112 can be made of the same material. For example, the materials of the first isolation portion 1121 and the second isolation portion 1122 can include silicon oxide (SiO2) and polycrystalline silicon (poly-Si) from the outside to the inside. The gate line isolation structure 112 having such a material combination helps improve stress distribution. For another example, the first isolation portion 1121 and the second isolation portion 1122 can be made of a single material, which is not specifically limited in this application.

[0052] In some embodiments, the stacked structure 111 is divided into memory blocks 103 by gate line isolation structures 112 and insulation structures 113 adjacent to each other in the direction D1.

[0053] In some embodiments, the sidewalls of the first isolation portion 1121 and the second isolation portion 1122 are both planar.

[0054] In some embodiments, in the direction D2, the dimension l3 of the insulating structure 113 is larger than the dimension l1 of the first isolation portion 1121, and the dimension l3 of the insulating structure 113 is larger than the dimension l2 of the second isolation portion 1122. The insulating structure 113 extends into the stacked structure 111 in the direction D2, further improving the stability and yield of the semiconductor structure 100.

[0055] In some embodiments, the material of the insulating structure 113 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the insulating structure 113 is made of a single material (eg, silicon oxide (SiO 2 )).

[0056] In some embodiments, the semiconductor structure 100 may further include a semiconductor layer 114. The semiconductor layer 114 may be located on one side of the stacked structure 111 in the D3 direction and extend laterally along the D1 and D2 directions. The material of the semiconductor layer 114 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art. For example, the material of the semiconductor layer 114 may be silicon (Si).

[0057] In some embodiments, the semiconductor structure 100 may further include a channel structure 115. The channel structure 115 may be substantially columnar and extend along the D3 direction. On a plane perpendicular to the D3 direction, multiple channel structures 115 are arranged in an array along the D1 and D2 directions. For example, within the storage area 101, some channel structures 115 extend through the first stack portion 1111, while some channel structures 115 extend through the insulating structure 113. For example, the channel structure 115 may extend along the D3 direction into the semiconductor layer 114.

[0058] In some embodiments, the semiconductor structure 100 may further include an insulating layer 118. The insulating layer 118 may be located on a side of the stacked structure 111 facing away from the semiconductor layer 114 in the D3 direction and may extend laterally along the D1 direction and the D2 direction. For example, the insulating layer 118 may cover the surface of the channel structure 115 and the stacked structure 111. For another example, the first isolation portion 1121 and the second isolation portion 1122 may penetrate the insulating layer 118. The material of the insulating layer 118 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. It should be noted that, when the insulating layer 118 contacts the first dielectric layer 1113 in the stacked structure 111 and the two are made of the same material, there is no obvious interface between the two.

[0059] Figures 2A to 2C This is a schematic diagram of the structure of a semiconductor structure according to another embodiment of the present invention. Figure 2A is a schematic top view of the semiconductor structure 200 . Figure 2B yes Figure 2A A partially enlarged schematic diagram of area A is shown. Figure 2C It is along Figure 2B The cross-sectional schematic diagrams taken along lines BB', CC', and DD' are shown. For the purpose of brevity, the same contents as those in the previous embodiment will not be repeated in this application.

[0060] like Figures 2A to 2C As shown, semiconductor structure 200 includes a stacked structure 211, a gate line isolation structure 212, and an insulating structure 213. Gate line isolation structure 212 extends through stacked structure 211 and includes a first isolation portion 2121 and a second isolation portion 2122 arranged along direction D1. First isolation portion 2121 and second isolation portion 2122 both extend along direction D1. Insulation structure 213 extends through stacked structure 211 and connects first isolation portion 2121 and second isolation portion 2122.

[0061] In some embodiments, the stack structure 211 may include a first stack portion 2111 and a second stack portion 2112. As viewed from the D3 direction, the first stack portion 2111 at least partially surrounds the second stack portion 2112. The first stack portion 2111 may include alternating first dielectric layers 2113 and gate layers 2114 along the D3 direction. The second stack portion 2112 may include alternating first dielectric layers 2113 and second dielectric layers 2115 along the D3 direction.

[0062] In some embodiments, the gate layer 2114 may include a metal layer 21141, an adhesion layer 21142, and a gate barrier layer 21143. The adhesion layer 21142 surrounds the metal layer 21141, and the gate barrier layer 21143 surrounds the adhesion layer 21142. The material of the metal layer 21141 may include one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), or any other suitable metal material. The material of the adhesion layer 21142 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other suitable material. The material of the gate barrier layer 21143 may include one or more of aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O3), hafnium oxide (HfO2), or any other suitable high-k dielectric constant material.

[0063] In some embodiments, the semiconductor structure 200 may further include a filling structure 216. The filling structure 216 extends through the insulating structure 213 and is spaced apart from the first isolation portion 2121 and the second isolation portion 2122 in the D1 direction. For example, in a plane perpendicular to the D3 direction, the filling structure 216 is approximately located in the middle of the insulating structure 213. In other words, the insulating structure 213 may surround the outer periphery of the filling structure 216.

[0064] In some embodiments, the material (or material combination) of the filling structure 216 includes one of the following from the outside to the inside: silicon oxide (SiO2) and polysilicon (poly-Si); silicon oxide (SiO2), silicon nitride (Si3N4) and polysilicon (poly-Si); silicon oxide (SiO2); silicon oxide (SiO2), polysilicon (poly-Si) and silicon oxide (SiO2). For example, Figure 2C It is shown that the material of the filling structure 216 includes silicon oxide (SiO2) and polysilicon (poly-Si) from the outside to the inside. It should be noted that when the material of the insulating structure 213 and the material of the filling structure 216 are the same, for example, both are a single material (for example, silicon oxide (SiO2)), there is no obvious interface between the two. Figure 1 An insulating structure 113 is shown.

[0065] In some embodiments, the first isolation portion 2121, the second isolation portion 2122, and the filling structure 216 in the gate line isolation structure 212 can be made of the same material. For example, the materials of the first isolation portion 2121, the second isolation portion 2122, and the filling structure 216 can all include silicon oxide (SiO2) and polycrystalline silicon (poly-Si) from the outside to the inside. The gate line isolation structure 212 having the above material combination helps improve stress distribution. In addition, the first isolation portion 2121, the second isolation portion 2122, and the filling structure 216, which are made of the same material, can be formed in the same process, which helps improve manufacturing efficiency and save manufacturing costs.

[0066] In some embodiments, on a plane perpendicular to the D3 direction, the stacked structure 211 is divided into a storage area 201 and a connection area 202 along the D1 direction. For example, along the D1 direction, the connection area 202 is located between two storage areas 201. Multiple insulating structures 213 may be arranged at intervals along the D1 direction within the storage area 201. Generally speaking, on a plane perpendicular to the D3 direction, the area of ​​the storage area 201 is larger than the area of ​​the connection area 202. Providing multiple insulating structures 213 within the storage area 201 helps to improve the stability of the stacked structure 211 within the storage area 201, thereby improving the stability and yield of the semiconductor structure 200. In other embodiments, multiple insulating structures may be arranged at intervals along the D1 direction within the connection area (not shown), and this application does not impose specific limitations.

[0067] In some embodiments, as Figure 2B As shown, in the direction D1 , a dimension l4 between adjacent insulating structures 213 is greater than or equal to 5 μm, and a dimension l5 of the insulating structure 213 is greater than or equal to 500 nm.

[0068] In some embodiments, the semiconductor structure 200 may further include a plurality of dielectric layers 217 (hereinafter referred to as fourth dielectric layers 217). The plurality of fourth dielectric layers 217 may intermittently cover the end surfaces of the first isolation portion 2121 and the second isolation portion 2122 in the D3 direction. In the D2 direction, the dimension l6 of the fourth dielectric layer 217 is larger than the dimension l1 of the first isolation portion 2121 (refer to FIG. Figure 1 ), and is larger than the size l2 of the second isolation portion 2122 (reference Figure 1 For example, in a plane perpendicular to the D3 direction, the fourth dielectric layer 217 may be substantially rectangular. In this embodiment, the fourth dielectric layer 217 spans the gate line isolation structure 212 in the D2 direction, which can further improve the stability and yield of the semiconductor structure 200.

[0069] In some embodiments, the material of the fourth dielectric layer 217 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiOx N y ) or any other suitable insulating material. For example, the material of the fourth dielectric layer 217 can be silicon oxide (SiO2). When the material of the insulating layer 218 and the material of the fourth dielectric layer 217 are both silicon oxide (SiO2), there is no obvious interface between the two.

[0070] In some embodiments, as Figure 2B As shown, in the direction D1, a dimension 17 of adjacent fourth dielectric layers 217 may be greater than or equal to 300 nm, and a dimension 18 of the fourth dielectric layer 217 may be greater than or equal to 150 nm.

[0071] In some embodiments, the stacked structure 211 is divided into memory blocks 203 by gate line isolation structures 212 and insulation structures 213 adjacent to each other in the D1 direction. The fourth dielectric layer 217 connects adjacent memory blocks 203. For example, the fourth dielectric layer 217 extends to adjacent memory blocks 203 in the D2 direction, thereby improving the stability of the adjacent memory blocks 203 and thereby improving the stability and yield of the semiconductor structure 200.

[0072] In some embodiments, as Figure 2C As shown, in the semiconductor structure 200, the channel structure 215 may include a charge blocking layer 2151, a charge trapping layer 2152, a tunneling layer 2153, and a channel layer 2154, which are arranged in sequence from the outside to the inside. The materials of the charge blocking layer 2151, the charge trapping layer 2152, and the tunneling layer 2153 may include silicon oxide (SiO2), silicon nitride (Si3N4), and silicon oxide (SiO2) in sequence. The material of the channel layer 2154 may include amorphous silicon (α-Si), polycrystalline silicon (poly-Si), or any other suitable semiconductor material. The charge blocking layer 2151, the charge trapping layer 2152, and the tunneling layer 2153 may be referred to as storage functional layers. For example, the channel layer 2154 may protrude from the first stack portion 2111 and extend into the semiconductor layer 214. The storage functional layer may surround the portion of the channel layer 2154 that passes through the first stack portion 2111. When the material of the channel layer 2154 is the same as that of the semiconductor layer 214 , there is no obvious interface between the two.

[0073] In some embodiments, the portion of the channel structure 215 surrounded by a gate layer 2114 and a portion of the gate layer 2114 constitute a memory cell. Multiple memory cells are arranged in series along the extension direction of the channel structure 215 (e.g., direction D3) to form a memory cell string and share the channel layer 2154.

[0074] Some embodiments of the present application provide a method for manufacturing a semiconductor structure. Figure 3FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application. Figure 3 As shown, a method 300 for manufacturing a semiconductor structure (hereinafter referred to as manufacturing method 300 ) may include the following steps.

[0075] S310, forming a first slit portion, a first groove and a second slit portion that penetrate the initial stacking structure, wherein the initial stacking structure includes a first dielectric layer and a second dielectric layer alternately stacked, the first slit portion, the first groove and the second slit portion are arranged at intervals along the first direction, and the first slit portion and the second slit portion both extend along the first direction.

[0076] S320 , replacing a portion of each second dielectric layer around the first trench with a plurality of third dielectric layers.

[0077] S330 , forming a first isolation portion and a second isolation portion in the first slit portion and the second slit portion, respectively.

[0078] According to the manufacturing method provided in the embodiment of the present application, by reasonably setting the position and arrangement of the first gap portion, the first groove and the second gap portion, a portion of each second dielectric layer on the periphery of the first groove is replaced with multiple third dielectric layers to form an insulating structure, which helps to improve the dumping problem in the manufacturing process and improve the structural stability and yield.

[0079] Figures 4A to 18 This is a schematic diagram of the structure of a semiconductor structure in the manufacturing process according to an embodiment of the present application. For example, Figures 4A to 18 Can be used to form Figures 2A to 2C The semiconductor structure 200 is shown. Figures 4A to 18 The manufacturing method 300 including steps S310 to S330 is exemplarily described.

[0080] S310

[0081] Figure 4A and Figure 4B The intermediate structure 400a after forming the first slit portion 431, the second slit portion 432 and the first trench 433 is shown. Figure 4A is a schematic top view of the intermediate structure 400a. Figure 4B It is along Figure 4A Schematic cross-sectional views taken along line BB', line CC', and line DD' are shown.

[0082] like Figure 4A and Figure 4BAs shown, an etching process (e.g., dry etching and / or wet etching) can be used to form a first slit portion 431, a second slit portion 432, and a first trench 433 that penetrate the initial stacked structure 411'. The initial stacked structure 411' includes alternating first dielectric layers 4113 and second dielectric layers 4115. The first slit portion 431, the first trench 433, and the second slit portion 432 are arranged at intervals along the D1 direction, and both the first slit portion 431 and the second slit portion 432 extend along the D1 direction.

[0083] In some embodiments, in the D2 direction, the sizes of the first slit portion 431, the first groove 433, and the second slit portion 432 may be substantially equal. In the D1 direction, the size of the first slit portion 431 may be larger than the size of the first groove 433, and the size of the second slit portion 432 may be larger than the size of the first groove 433.

[0084] In some embodiments, the sidewalls of the first slit portion 431 and the second slit portion 432 are both planar.

[0085] In some embodiments, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof may be used to alternately form the first dielectric layer 4113 and the second dielectric layer 4115 to form an initial stacked structure 411'. For example, on a plane perpendicular to the D3 direction, the initial stacked structure 411' may be divided into a storage area 401 and a connection area 402 along the D1 direction. Each layer of the first dielectric layer 4113 and each layer of the second dielectric layer 4115 may extend continuously laterally within the storage area 401 and the connection area 402. For example, the material of the first dielectric layer 4113 may include silicon oxide (SiO2), and the material of the second dielectric layer 4115 may include silicon nitride (Si3N4).

[0086] In some embodiments, the initial stacked structure 411' may be formed on the surface of the substrate 434. For example, the substrate 434 may include a semiconductor substrate. The material of the semiconductor substrate may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). For another example, the semiconductor substrate may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. In some examples, the substrate 434 may be a composite layer structure. In other examples, the substrate 434 may be composed of a single material. For example, the substrate 434 may play a supporting role during the manufacturing process and may be at least partially removed in subsequent processes.

[0087] In some embodiments, after forming the initial stacked structure 411' and before forming the first slit portion 431, the second slit portion 432, and the first trench 433, a channel structure 415 can be formed that penetrates the initial stacked structure 411' and extends into the substrate 434. For example, there can be multiple channel structures 415. On a plane perpendicular to the z-direction, the multiple channel structures 415 are arranged in an array along the D1 direction and the D2 direction within the storage area 401.

[0088] In some embodiments, after forming the channel structure 415 and before forming the first slit portion 431, the second slit portion 432, and the first trench 433, an insulating layer 418 covering the initial stacked structure 411' and the channel structure 415 may be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, the insulating layer 418 may extend laterally within the storage region 401 and the connection region 402. If the manufacturing method 300 includes the step of forming the insulating layer 418, the first slit portion 431, the second slit portion 432, and the first trench 433 may penetrate the insulating layer 418.

[0089] S320

[0090] Figure 5 The intermediate structure 400 b is shown after forming a first sacrificial material layer 435 . Figure 6 The intermediate structure 400 c is shown after forming a first mask layer 436 . Figure 7 The intermediate structure 400 d is shown after removing the first sacrificial material layer 435 in the first trench 433 . Figure 8 The intermediate structure 400e is shown after a plurality of first gaps 437 are formed. Figure 9 The intermediate structure 400 f is shown after forming a plurality of third dielectric layers 438 .

[0091] like Figure 4A 、 Figure 4B as well as Figure 9 As shown, a portion of each second dielectric layer 4115 around the first trench 433 is replaced with a plurality of third dielectric layers 438. The plurality of third dielectric layers 438 and the second dielectric layers 4115 located between adjacent third dielectric layers 438 form an insulating structure 413 (structure within the dashed box). The insulating structure 413 may penetrate the initial stacked structure 411'.

[0092] In some embodiments, the material of the third dielectric layer 438 may be different from the material of the second dielectric layer 4115. For example, when the material of the second dielectric layer 4115 is silicon nitride (Si3N4), the material of the third dielectric layer 438 may include silicon oxide (SiO2). For example, the first dielectric layer 4113 and the third dielectric layer 438 may be made of the same material (e.g., silicon oxide (SiO2)). It should be noted that Figure 9 The interface between the first dielectric layer 4113 and the third dielectric layer 438 is shown to illustrate the spatial relationship between the two. When the material of the first dielectric layer 4113 and the third dielectric layer 438 is the same, there is no obvious interface between the two. In other embodiments, the third dielectric layer 438 can be made of one or more of any other suitable insulating materials, which is not limited in this application.

[0093] The following combination Figures 4A to 9 Step S320 is described with an example.

[0094] In some embodiments, as Figure 4A 、 Figure 4B as well as Figure 5 As shown, after forming the first slit portion 431, the second slit portion 432, and the first trench 433, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a first sacrificial material layer 435 in the first slit portion 431, the second slit portion 432, and the first trench 433. The material of the first sacrificial material layer 435 may include polycrystalline silicon (poly-Si), carbon (C), or any other suitable easily removable material. Subsequently, an initial first mask layer 436' covering the insulating layer 418 may be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, the initial first mask layer 436' may extend laterally along the D2 direction and the D3 direction. The material of the initial first mask layer 436' may be different from the material of the first sacrificial material layer 435. For example, the material of the initial first mask layer 436' may include silicon oxide (SiO2).

[0095] In some embodiments, as Figure 5 and Figure 6 As shown, a portion of the initial first mask layer 436′ can be removed using a photolithography and etching (e.g., dry etching) process to form an opening exposing the first sacrificial material layer 435 in the first trench 433, and the initial first mask layer 436′ is converted into a first mask layer 436. The first mask layer 436 covers the insulating layer 418 and the first sacrificial material layer 435 in the first slit portion 431 and the second slit portion 432.

[0096] In some embodiments, as Figure 6 and Figure 7As shown, an etching process (e.g., wet etching) can be used to remove the first sacrificial material layer 435 in the first trench 433. The first mask layer 436 can function as a mask to protect the first sacrificial material layer 435 in the first slit portion 431 and the second slit portion 432 from being removed. After the above-described process, the first sacrificial material layer 435 can be formed only in the first slit portion 431 and the second slit portion 432. Optionally, after removing the first sacrificial material layer 435 in the first trench 433, the first mask layer 436 can be removed (not shown).

[0097] In some embodiments, as Figure 7 and Figure 8 As shown, an etching process (e.g., wet etching) can be used to remove a portion of each second dielectric layer 4115 around the first trench 433 to the first sacrificial material layer 435, thereby forming a plurality of first gaps 437. For example, when the materials of the first dielectric layer 4113 and the second dielectric layer 4115 are different, the etching material (e.g., etchant) isotropically removes a portion of each second dielectric layer 4115 to the first sacrificial material layer 435 through the first trench 433, while retaining each first dielectric layer 4113 around the first trench 433. For example, as described above, the first slit portion 431, the first groove 433 and the second slit portion 432 are arranged at intervals along the D1 direction. In the process of isotropically removing a portion of each second dielectric layer 4115, the first sacrificial material layer 435 in the first slit portion 431 and the second slit portion 432 can serve as an etching stop layer, thereby multiple first gaps 437 can expose the first sacrificial material layer 435 in the first slit portion 431 and the second slit portion 432, and the size of each first gap 437 in the D2 direction can be larger than the size of the first slit portion 431 in the D2 direction, and can be larger than the size of the second slit portion 432 in the D2 direction.

[0098] In some embodiments, as Figure 8 and Figure 9 As shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a plurality of third dielectric layers 438 in the plurality of first gaps 437 and to form an insulating structure 413. The size of the insulating structure 413 in the D2 direction can be larger than the size of the first slit portion 431 in the D2 direction, and can also be larger than the size of the second slit portion 432 in the D2 direction.

[0099] In some embodiments, as Figure 9As shown, during the process of forming the plurality of third dielectric layers 438, a film layer made of the same material as the third dielectric layers 438 may be formed on the inner wall of the first trench 433, and a portion of the first trench 433 may remain unfilled. In other embodiments, the first trench 433 may be completely filled with a film layer made of the same material as the third dielectric layers 438, so that the first trench 433 is filled.

[0100] In some embodiments, during the process of forming multiple third dielectric layers 438, a film layer made of the same material as the third dielectric layer 438 can be formed on one side of the initial stacked structure 411' and the first sacrificial material layer 435 in the D3 direction (for example, the surface of the first mask layer 436). This film layer can be called an initial fourth dielectric layer 417'.

[0101] In some embodiments, the manufacturing method 300 may further include the following steps: removing a portion of the initial fourth dielectric layer so that the retained multiple fourth dielectric layers are discontinuously located on one side of the sacrificial material layer, and the size of each retained fourth dielectric layer in the second direction is larger than the size of the sacrificial material layer in the second direction; removing the sacrificial material layer and exposing the first slit portion and the second slit portion; using the first slit portion and the second slit portion, removing at least a portion of each second dielectric layer to form a plurality of second gaps; and forming a plurality of gate layers in the plurality of second gaps.

[0102] Figures 10A to 17 The intermediate structures in the process of executing the above steps are shown. Figure 10A and Figure 10B The intermediate structure 400 g is shown after forming a plurality of fourth dielectric layers 417 within the connection region 402 . Figure 11A and Figure 11B The intermediate structure 400h is shown after removing the first sacrificial material layer 435 within the connection region 402 . Figure 12 The intermediate structure 400i is shown after forming the second gap 440 within the connection region 402. Figure 13 The intermediate structure 400 j is shown after forming a second sacrificial material layer 441 . Figure 14A and Figure 14B The intermediate structure 400 k is shown after forming a plurality of fourth dielectric layers 417 within the memory region 401 . Figure 15A and Figure 15B The intermediate structure 4001 is shown after the first sacrificial material layer 435 within the storage region 401 has been removed.

[0103] Figure 16 The intermediate structure 400m is shown after forming the second gap 440 within the storage area 401.

[0104] Figure 17The intermediate structure 400 n is shown after removal of the second sacrificial material layer 441 .

[0105] In some embodiments, as Figure 9 、 Figure 10A as well as Figure 10B As shown, an etching (e.g., dry etching) process can be used to remove a portion of the initial fourth dielectric layer 417' in the connection area 402, retaining the initial fourth dielectric layer 417' in the storage area 401, and the initial fourth dielectric layer 417' that is not removed in the connection area 402 can serve as multiple fourth dielectric layers 417 in the connection area 402. The multiple fourth dielectric layers 417 in the connection area 402 can be intermittently located on one side (e.g., the surface) of the first sacrificial material layer 435 in the second slit portion 432. For example, a pattern design can be used to make the size l6 of each retained fourth dielectric layer 417 in the D2 direction larger than the size l2 of the first sacrificial material layer 435 in the D2 direction. It should be noted that Figure 10A and Figure 10B Only the second slit portion 432 is shown as being located within the connection region 402. In other embodiments, both the first slit portion and the second slit portion may be located within the connection region, such that the plurality of fourth dielectric layers within the connection region may be discontinuously located on one side (e.g., a surface) of the first sacrificial material layer in the first slit portion and / or the second slit portion.

[0106] In some embodiments, as Figures 10A to 11B As shown, after forming the plurality of fourth dielectric layers 417 in the connection region 402, an etching process (e.g., wet etching) may be used to remove the first sacrificial material layer 435 in the second slit portion 432 in the connection region 402, thereby exposing the second slit portion 432 in the connection region 402. Because the plurality of fourth dielectric layers 417 in the connection region 402 are intermittently arranged, during the process of removing the first sacrificial material layer 435 in the connection region 402, the first sacrificial material layer 435 not covered by the plurality of fourth dielectric layers 417 may come into contact with the etching material (e.g., etchant) and thereby be removed, and the plurality of fourth dielectric layers 417 in the connection region 402 may remain.

[0107] In some embodiments, as Figure 11A 、 Figure 11B as well as Figure 12 As shown, after removing the first sacrificial material layer 435 in the second gap portion 432 in the connection area 402, an etching (for example, wet etching) process can be used to utilize the second gap portion 432 in the connection area 402 to remove a portion of each second dielectric layer 4115 located on both sides of the second gap portion 432, thereby forming a plurality of second gaps 440 in the connection area 402.

[0108] In some embodiments, as Figure 12 and Figure 13 As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form a second sacrificial material layer 441 in the plurality of second gaps 440 in the connection area 402 and in the second slit portion 432 in the connection area 402. The material of the second sacrificial material layer 441 may include polycrystalline silicon (poly-Si), carbon (C) or any other suitable easily removable material. For example, the material of the second sacrificial material layer 441 is spin-on carbon (SOC). For example, in the process of forming the second sacrificial material layer 441, the second sacrificial material layer 441 may be formed in the first trench 433. For another example, in the process of forming the second sacrificial material layer 441, a film layer of the same material as the second sacrificial material layer 441 may be formed on the side of the initial stacked structure 411' facing away from the substrate 434 in the D3 direction.

[0109] In some embodiments, as Figure 13 As shown, after forming the second sacrificial material layer 441, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form an initial second mask layer 442' on the side of the initial stacked structure 411' that is away from the substrate 434 in the direction D3. The material of the initial second mask layer 442' may be different from that of the first sacrificial material layer 435. For example, the material of the initial second mask layer 442' may include silicon oxynitride (SiO x N y The initial fourth dielectric layer 417 ′ in the storage region 401 may be located on a side of the initial second mask layer 442 ′ facing the substrate 434 .

[0110] In some embodiments, as Figure 13 、 Figure 14A as well as Figure 14BAs shown, after forming the second sacrificial material layer 441, an etching process (e.g., dry etching) can be used to remove the initial second mask layer 442' in the storage area 401, the initial fourth dielectric layer 417' in the storage area 401, the film layer made of the same material as the second sacrificial material layer 441 between the initial second mask layer 442' in the storage area 401 and the initial fourth dielectric layer 417' in the storage area 401, and a portion of the composite film formed by the first mask layer 436 in the storage area 401, while retaining the composite film layer in the connection area 402. The initial fourth dielectric layer 417' in the composite film layer that is not removed in the storage area 401 can serve as the multiple fourth dielectric layers 417 in the storage area 401. The multiple fourth dielectric layers 417 in the storage area 401 can be intermittently located on one side (e.g., the surface) of the first sacrificial material layer 435 in the first slit portion 431 and the second slit portion 432. For example, patterning can be performed to ensure that the dimension l6 of each fourth dielectric layer 417 retained in the storage region 401 in the D2 direction is larger than the dimensions l1 and l2 of the first sacrificial material layer 435 in the D2 direction. For example, the composite film layer not removed in the storage region 401 can also be located on a side (e.g., a surface) of the insulating structure 413 facing away from the substrate 434 in the D3 direction.

[0111] In some embodiments, as Figures 14A to 15B As shown, after forming the plurality of fourth dielectric layers 417 in the storage area 401, an etching process (e.g., wet etching) can be used to remove the first sacrificial material layer 435 in the first slit portion 431 and the second slit portion 432 in the storage area 401, thereby exposing the first slit portion 431 and the second slit portion 432 in the storage area 401. Because the plurality of fourth dielectric layers 417 in the storage area 401 are intermittently arranged, during the process of removing the first sacrificial material layer 435 in the storage area 401, the first sacrificial material layer 435 not covered by the plurality of fourth dielectric layers 417 may come into contact with the etching material (e.g., etchant) and thereby be removed, and the plurality of fourth dielectric layers 417 in the storage area 401 may remain.

[0112] In some embodiments, as Figure 15A 、 Figure 15B as well as Figure 16 As shown, after removing the first sacrificial material layer 435 in the first slit portion 431 and the second slit portion 432 in the storage area 401, an etching process (e.g., wet etching) can be used to remove each second dielectric layer 4115 in the storage area 401 using the first slit portion 431 and the second slit portion 432 in the storage area 401, thereby forming a plurality of second gaps 440 in the storage area 401. Optionally, after forming the plurality of second gaps 440 in the storage area 401, the second mask layer 442 in the storage area 401 and the connection area 402 can be removed.

[0113] In some embodiments, as Figure 16 and Figure 17 As shown, an etching (e.g., wet etching) process can be used to remove the second sacrificial material layer 441 in the second slit portion 432 in the connection area 402. For example, during the above removal process, the second sacrificial material layer 441 in the first groove 433 can be removed. After the above process, the second gaps in the storage area 401 and the connection area 402 are connected to each other, and the first slit portion 431, the second slit portion 432, and the first groove 433 are exposed. The multiple fourth dielectric layers 417 span the first slit portion 431 and the second slit portion 432 in the D2 direction, which can reinforce the initial stacking structure 411' and prevent the initial stacking structure 411' from collapsing when the multiple second gaps 440 are present.

[0114] It should be noted that although the above describes in detail an example in which multiple fourth dielectric layers 417 and multiple second gaps 440 are first formed in the connection region 402, and then multiple fourth dielectric layers 417 and multiple second gaps 440 are formed in the storage region 401, in other embodiments, multiple fourth dielectric layers and multiple second gaps may be formed in the storage region first, and then multiple fourth dielectric layers and multiple second gaps may be formed in the connection region. In still other embodiments, multiple fourth dielectric layers in the storage region and the connection region may be formed in the same etching process, and multiple second gaps may be formed in the same etching process. This application does not specifically limit the above embodiments.

[0115] S330

[0116] Figure 18 The intermediate structure 400 o is shown after forming the first isolation portion 4121 and the second isolation portion 4122 .

[0117] like Figure 17 and Figure 18 As shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form a first isolation portion 4121 and a second isolation portion 4122 in the first slit portion 431 and the second slit portion 432, respectively. For example, silicon oxide (SiO2) and polysilicon (poly-Si) may be sequentially formed in the first slit portion 431 and the second slit portion 432, respectively.

[0118] In some embodiments, as Figure 17 and Figure 18 As shown, before forming the first isolation portion 4121 and the second isolation portion 4122 , the manufacturing method 300 may further include forming a plurality of gate layers 4114 in the plurality of second gaps 440 . Thus, the initial stacked structure 411 ′ is converted into the stacked structure 411 .

[0119] In some embodiments, as Figure 17 and Figure 18 As shown, the manufacturing method 300 may further include the step of forming a filling structure 416 in the first trench 433. The filling structure 416 may be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, the following materials (or material combinations) may be formed in the first trench 433: silicon oxide (SiO2) and polycrystalline silicon (poly-Si); silicon nitride (Si3N4) and polycrystalline silicon (poly-Si); silicon oxide (SiO2); silicon oxide (SiO2), polycrystalline silicon (poly-Si), and silicon oxide (SiO2) to form the filling structure 416.

[0120] In some embodiments, the filling structure 416, the first isolation portion 4121, and the second isolation portion 4122 can be formed in the same thin film process. For example, silicon oxide (SiO2) can be formed on the inner walls of the first trench 433, the first slit portion 431, and the second slit portion 432 using the same thin film deposition process. Subsequently, polysilicon (poly-Si) can be formed inside the silicon oxide (SiO2) in the first trench 433, the first slit portion 431, and the second slit portion 432 using a thin film deposition process. In this embodiment, the filling structure 416, the first isolation portion 4121, and the second isolation portion 4122 can be made of the same material.

[0121] In some embodiments, the manufacturing method 300 may further include the step of forming a semiconductor layer. Figure 18 As shown, a portion of the substrate 434 may be removed and a portion of the channel structure 415 protruding from the stack structure 411 may be removed to expose the channel layer 4154. Next, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form a semiconductor layer 214 connected to (e.g., in contact with) the channel layer 4154 on a side of the stack structure 411 facing away from the insulating layer 418 (see FIG. Figure 2C ).

[0122] The method for manufacturing a semiconductor structure provided by the above embodiment helps to improve the tipping problem during the manufacturing process and improves structural stability and yield.

[0123] An embodiment of the present application also provides a memory system. Figure 19 FIG. 1 is a block diagram of a system having a memory system according to an embodiment of the present application. Figure 20A and Figure 20B is a schematic diagram of a memory system according to an embodiment of the present application.

[0124] like Figure 19As shown, the system 11 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has the memory system 12 located therein). Figure 19 As shown, system 11 may include a host 18 and a memory system 12 having one or more memories 14 and a controller 16. Host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). Host 18 may be configured to send or receive data to or from memory 14.

[0125] The memory 14 may include the semiconductor structure described in any embodiment of the present application, for example, Figure 1 The semiconductor structure 100 and Figures 2A to 2CA semiconductor structure 200 is shown. According to some embodiments, a controller 16 is coupled to the memory 14 and the host 18 and is configured to control the memory 14. The controller 16 can manage data stored in the memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. The controller 16 can be configured to control operations of the memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the memory 14, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some embodiments, the controller 16 is further configured to process error correction code (ECC) associated with data read from or written to the memory 14. Any other appropriate functions may also be performed by the controller 16, such as formatting the memory 14. The controller 16 may communicate with an external device (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 may communicate with the external device via at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-Express, PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, and the like.

[0126] The controller 16 and the one or more memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of final electronic products. Figure 20AIn one example shown in FIG, the controller 16 and the single memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 22 may further include a memory card that connects the memory card 22 to a host (e.g., Figure 19 The host 18 in the memory card connector 24 is coupled. Figure 20B In another example shown in FIG, the controller 16 and the plurality of memories 14 may be integrated into an SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Figure 19 In some embodiments, the SSD 26 has a storage capacity and / or an operating speed that is higher than that of the memory card 22.

[0127] The above description is merely an embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the technical concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, characterized in that include: stacked structure; a gate line isolation structure, which passes through the stacked structure and includes a first isolation portion and a second isolation portion arranged along a first direction, wherein the first isolation portion and the second isolation portion both extend along the first direction; as well as an insulating structure, passing through the stacked structure and connected between the first isolation portion and the second isolation portion; The first direction intersects with the stacking direction of the stacking structure.

2. The semiconductor structure according to claim 1, wherein In a second direction, a size of the insulating structure is larger than a size of the first isolation portion and larger than a size of the second isolation portion, and the first direction, the second direction, and the stacking direction intersect with each other.

3. The semiconductor structure according to claim 1 or 2, further comprising: The filling structure penetrates the insulating structure and has a spacing distance from the first isolation portion and the second isolation portion in the first direction.

4. The semiconductor structure according to claim 3, wherein: The material of the filling structure includes one of the following from the outside to the inside: silicon oxide and polysilicon; Silicon oxide, silicon nitride and polysilicon; silicon oxide; silicon oxide, polysilicon and silicon oxide.

5. The conductor structure according to claim 4, wherein: The first isolation portion, the second isolation portion, and the filling structure are made of the same material.

6. The semiconductor structure according to claim 1 or 4, wherein: The material of the insulating structure includes silicon oxide.

7. The semiconductor structure according to claim 1 or 2, wherein: On a plane perpendicular to the stacking direction, the stacking structure is divided into a storage area and a connection area along the first direction, and a plurality of the insulating structures are arranged at intervals along the first direction in the storage area.

8. The semiconductor structure according to claim 7, wherein: In the first direction, a dimension between adjacent insulating structures is greater than or equal to 5 μm, and a dimension of the insulating structure is greater than or equal to 500 nm.

9. The semiconductor structure of claim 1 , further comprising: a plurality of dielectric layers intermittently covering end surfaces of the first isolation portion and the second isolation portion in the stacking direction; In the second direction, the size of the dielectric layer is larger than the size of the first isolation portion and larger than the size of the second isolation portion, and the first direction, the second direction and the stacking direction intersect with each other.

10. The semiconductor structure according to claim 9, wherein In the first direction, a size of adjacent dielectric layers is greater than or equal to 300 nm, and a size of the dielectric layer is greater than or equal to 150 nm.

11. The semiconductor structure according to claim 9, wherein The material of the plurality of dielectric layers includes silicon oxide.

12. The semiconductor structure according to claim 9, wherein The stacked structure is divided into memory blocks by the gate line isolation structures and the insulation structures adjacent to each other in the second direction, and the dielectric layer connects the adjacent memory blocks.

13. The semiconductor structure according to claim 1, wherein Side walls of the first isolation portion and the second isolation portion are both planar.

14. The semiconductor structure of claim 2, further comprising: A channel structure extends in the insulating structure along the stacking direction.

15. A memory system, characterized in that: include: A memory comprising the semiconductor structure according to any one of claims 1 to 14; as well as The controller is coupled to the memory and is used to control the memory to store data.

16. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first slit portion, a first trench, and a second slit portion penetrating an initial stacked structure, wherein the initial stacked structure includes alternately stacked first dielectric layers and second dielectric layers, the first slit portion, the first trench, and the second slit portion are spaced apart along a first direction, and both the first slit portion and the second slit portion extend along the first direction; and replacing a portion of each of the second dielectric layers around the first trench with a plurality of third dielectric layers; and forming a first isolation portion and a second isolation portion in the first slit portion and the second slit portion, respectively; The first direction intersects with the stacking direction of the initial stacking structure.

17. The manufacturing method according to claim 16, wherein: Before replacing a portion of each of the second dielectric layers around the first trench with a plurality of third dielectric layers, the manufacturing method further includes: forming a sacrificial material layer in the first slit portion and the second slit portion; The step of replacing a portion of each of the second dielectric layers around the first trench with a plurality of third dielectric layers includes: removing a portion of each of the second dielectric layers at the periphery of the first trench down to the sacrificial material layer, and forming a plurality of first gaps; and The plurality of third dielectric layers are formed in the plurality of first gaps.

18. The manufacturing method according to claim 17, wherein: After replacing a portion of each of the second dielectric layers around the first trench with a plurality of third dielectric layers, the manufacturing method further includes: forming an initial fourth dielectric layer on one side of the initial stacked structure and the sacrificial material layer in the stacking direction; and removing a portion of the initial fourth dielectric layer so that a plurality of remaining fourth dielectric layers are intermittently located on one side of the sacrificial material layer, and a size of each of the remaining fourth dielectric layers in the second direction is larger than a size of the sacrificial material layer in the second direction; The first direction, the second direction and the stacking direction intersect with each other.

19. The manufacturing method according to claim 18, before forming the first isolation portion and the second isolation portion in the first slit portion and the second slit portion, respectively, the manufacturing method further comprises: removing the sacrificial material layer and exposing the first slit portion and the second slit portion; Using the first slit portion and the second slit portion, removing at least a portion of each of the second dielectric layers to form a plurality of second gaps; as well as A plurality of gate layers are formed in the plurality of second gaps.

20. The manufacturing method according to claim 19, wherein: On a plane perpendicular to the stacking direction, the initial stacking structure is divided into a storage area and a connection area along the first direction, the first gap portion is located in the storage area, and the second gap portion is located in the storage area and the connection area; Wherein, using the first slit portion and the second slit portion to remove at least a portion of each of the second dielectric layers to form a plurality of second gaps includes: using the second slit portion to remove a portion of each of the second dielectric layers located in the connection region; and The first slit portions and the second slit portions are used to remove each of the second dielectric layers in the storage area to form a plurality of second gaps.

21. The manufacturing method according to claim 18, after replacing a portion of each of the second dielectric layers around the first trench with a plurality of third dielectric layers, the manufacturing method further comprises: A filling structure is formed in the first trench.

22. The manufacturing method according to claim 21, wherein: The filling structure, the first isolation portion, and the second isolation portion are formed in a same thin film deposition process.

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