Nonvolatile two-terminal memory cell and related product thereof

Abstract

The invention discloses a nonvolatile two-terminal memory cell and a related product thereof. The nonvolatile two-end storage unit comprises N conversion layers, and N is a positive integer greater than 2; n + 1 electrode layers, wherein the electrode layers and the conversion layers are alternately stacked; and the selective conduction device is provided with voltage output ports in one-to-one correspondence with the electrode layers, and the voltage output ports are connected to the electrode layers. According to the scheme of the embodiment of the invention, multiple layers of resistance state switchable structures can be integrated in one storage unit through the multiple conversion layers and the multiple electrode layers which are alternately stacked, and multiple resistance state combinations are formed under the independent control of the selective conduction device; therefore, the low resistance state, the high resistance state and the intermediate resistance state between the low resistance state and the high resistance state of the whole nonvolatile two-end storage unit are achieved, more conductance is covered, and the requirement for complex convolution operation in the field of artificial intelligence is met.

Description

Technical Field

[0001] The present application generally relates to the field of semiconductor technology. More specifically, the present application relates to a non-volatile two-terminal memory cell, a memory array, a storage-computation-in-one device, and a convolution operation method. Background Art

[0002] Resistive Random Access Memory (RRAM) is a non-volatile memory cell that stores data by changing the resistance state of the memory cell. When a positive voltage is applied to its electrode layer, a conductive path is formed in the resistive switching layer, and the RRAM is in a low-resistance state. Subsequently, when a negative voltage is applied to the electrode layer, the state of the conductive path formed in the resistive switching layer changes, and the RRAM switches from a low-resistance state to a high-resistance state.

[0003] RRAM is currently widely used in consumer electronics, the Internet of Things (IoT), industrial electronics, automotive electronics, data centers, and artificial intelligence (AI), thanks to its advantages such as fast erase and write speeds, strong durability, low power consumption, high storage density, fast read and write speeds, and compatibility with CMOS processes. In AI, RRAM storage and analog computing can be used to perform the computationally intensive multiplication and addition operations typically found in convolution operations.

[0004] However, the traditional RRAM has only two resistance states, high resistance and low resistance, and can only achieve two conductivities. When used for convolution operations, it can only provide two weight values. The implemented convolution operations are relatively simple and cannot adapt to more complex convolution operations.

[0005] In view of this, there is an urgent need to provide a non-volatile two-terminal storage solution to realize multi-resistance RRAM, thereby meeting the needs of complex convolution operations in the field of artificial intelligence. Summary of the Invention

[0006] In order to at least solve one or more of the technical problems mentioned above, the present application proposes a non-volatile two-terminal storage solution in multiple aspects.

[0007] In a first aspect, the present application provides a non-volatile two-terminal memory cell comprising: N conversion layers, where N is a positive integer greater than 2; N+1 electrode layers, the electrode layers and the conversion layers being stacked alternately; and a selective conduction device having voltage output ports corresponding one-to-one to the electrode layers, the voltage output ports being connected to each electrode layer.

[0008] In some embodiments, the non-volatile two-terminal memory cell is configured such that if two adjacent electrode layers of the conversion layer receive a first driving voltage, the resistance state mark of the conversion layer is set to a low resistance state mark; if two adjacent electrode layers of the conversion layer receive a second driving voltage, the resistance state mark of the conversion layer is set to a high resistance state mark.

[0009] In some embodiments, the non-volatile two-terminal memory cell is configured such that: if the resistance state markers of all the switching layers are high resistance state markers, the conductance represented by the non-volatile two-terminal memory cell is the first conductance. If the resistance state markers of all the switching layers are low resistance state markers, the conductance represented by the non-volatile two-terminal memory cell is the second conductance. If there are both low resistance state markers and high resistance state markers among the N switching layers, the conductance represented by the non-volatile two-terminal memory cell is the third conductance. Rmin < Rmid < Rmax, and the magnitude of the third conductance is negatively correlated with the number of high resistance state markers.

[0010] In some embodiments, the non-volatile two-terminal memory cell includes a bottom electrode layer, a top electrode layer, and an intermediate electrode layer. Among them, the bottom electrode layer is the electrode layer located at the bottom in the stacking direction of the non-volatile two-terminal memory cell, the top electrode layer is the electrode layer located at the top in the stacking direction of the non-volatile two-terminal memory cell, the intermediate electrode layer is the electrode layer located between the bottom electrode layer and the top electrode layer, and the intermediate electrode layer is multiplexed by a plurality of adjacent switching layers.

[0011] In some embodiments, the electrode layer includes a stacked memory cell electrode layer and a conductive metal layer.

[0012] In some embodiments, the bottom electrode layer includes a conductive metal layer and a memory cell electrode layer arranged in sequence along the stacking direction; the intermediate electrode layer includes a memory cell electrode layer, a conductive metal layer, and a memory cell electrode layer arranged in sequence along the stacking direction; the top electrode layer includes a memory cell electrode layer and a conductive metal layer arranged in sequence along the stacking direction.

[0013] In some embodiments, the number of selective conduction devices is one and the selective conduction device has a plurality of voltage output ports, where the plurality of voltage output ports are connected to the electrode layers in one-to-one correspondence.

[0014] In some embodiments, the number of selective conduction devices is N + 1 and each selective conduction device has one voltage output port, where each selective conduction device is connected to the electrode layers in one-to-one correspondence through the voltage output port it has.

[0015] In some embodiments, the areas of the N + 1 electrode layers have a monotonic change characteristic in the stacking direction.

[0016] In some embodiments, the voltage output port is connected to the electrode layer through a metal wire, where one end of the metal wire is connected to the voltage output port and the other end is connected to the surface of the electrode layer exposed in the stacking direction.

[0017] In some embodiments, the non-volatile two-terminal memory cell satisfies one or more of the following conditions: the thickness of each conversion layer is the same or the thickness of at least part of the conversion layer is different; the material of each conversion layer is the same or the material of at least part of the conversion layer is different; the thickness of each electrode layer is the same or the thickness of at least part of the electrode layer is different; the material of each electrode layer is the same or the material of at least part of the electrode layer is different.

[0018] In a second aspect, the present application provides a memory array comprising: a word line; a bit line; and at least two non-volatile two-terminal memory cells as described in any one of the first aspects, wherein the non-volatile two-terminal memory cells comprise: a bottom electrode layer, a top electrode layer, and an intermediate electrode layer, the bottom electrode layer being the electrode layer located at the bottom in the stacking direction of the non-volatile two-terminal memory cell, the top electrode layer being the electrode layer located at the top in the stacking direction of the non-volatile two-terminal memory cell, and the intermediate electrode layer being the electrode layer located between the bottom electrode layer and the top electrode layer; the bottom electrode layer being connected to one of the word line and the bit line, the top electrode layer being connected to the other of the word line and the bit line, and the intermediate electrode layer being connected to the word line or the bit line.

[0019] In some embodiments, the storage array is configured as follows: in response to the selective conduction device connected to two adjacent electrode layers of the conversion layer being turned on and the two adjacent electrode layers of the conversion layer receiving a first driving voltage, the resistance state mark of the conversion layer is set to a low resistance state mark; in response to the selective conduction device connected to two adjacent electrode layers of the conversion layer being turned on and the two adjacent electrode layers of the conversion layer receiving a second driving voltage, the resistance state mark of the conversion layer is set to a high resistance state mark.

[0020] In some embodiments, the memory array is configured to: in response to the selective conduction device connected to the bottom electrode layer and the selective conduction device connected to the top electrode layer being turned on, the selective conduction device connected to the middle electrode layer being turned off, and the top electrode layer and the bottom electrode layer receiving a third driving voltage, read the conductance represented by the non-volatile two-terminal memory cell.

[0021] In a third aspect, the present application provides a storage-computing integrated device, which includes a storage array as described in any one of the second aspects.

[0022] In some embodiments, the memory array is configured to: in response to each nonvolatile two-terminal memory cell in the memory array completing a write operation, the memory array stores the conductance represented by each nonvolatile two-terminal memory cell as a first matrix for a matrix multiplication operation.

[0023] In some embodiments, a write operation of a non-volatile two-terminal memory cell includes: in response to a selective conduction device connected to two adjacent electrode layers of the conversion layer being turned on, determining a resistance state mark of the conversion layer according to a driving voltage received by the two adjacent electrode layers of the conversion layer; and determining the conductance represented by the non-volatile two-terminal memory cell based on the resistance state mark of each conversion layer in the non-volatile two-terminal memory cell.

[0024] In some embodiments, the memory array is configured to: in response to each non-volatile two-terminal memory cell being in a read operation state, receive the applied voltage on the word line as an input of the second matrix; obtain the matrix multiplication result of the first matrix and the second matrix by reading the drive current on the bit line; wherein the read operation state satisfies the following conditions: the selective conduction device connected to the bottom electrode layer and the selective conduction device connected to the top electrode layer are both turned on, and the selective conduction device connected to the middle electrode layer is turned off.

[0025] In some embodiments, the drive current on the bit line is equal to the sum of the product of the applied voltage on the word line and the conductance characterized by the non-volatile two-terminal memory cell.

[0026] In some embodiments, the matrix multiplication operation includes: a convolution operation; the storage array stores the conductance represented by each non-volatile two-terminal storage cell as a first matrix of the matrix multiplication operation includes: the storage array stores the conductance represented by each non-volatile two-terminal storage cell as a weight matrix required for the convolution operation.

[0027] In a fourth aspect, the present application provides a convolution operation method, which is applied to a storage-computing integrated device such as any one of the third aspects, the method comprising: adjusting the applied voltage on each word line to input the input data of the convolution operation into the storage array; reading the driving current on each bit line to obtain the convolution operation result; wherein the convolution operation result is the product of the input data and the weight matrix stored in the storage array.

[0028] In some embodiments, the weight matrix includes: the conductance represented by each non-volatile two-terminal memory cell in the memory array; reading the driving current on each bit line to obtain a convolution operation result includes: calculating the product of the applied voltage of each word line and the conductance represented by the non-volatile two-terminal memory cell connected to the word line to obtain the current output by each non-volatile two-terminal memory cell to the bit line; calculating the sum of the currents output by the non-volatile two-terminal memory cells connected to each bit line to obtain the driving current on each bit line; and obtaining the convolution operation result based on the driving current on each bit line.

[0029] In some embodiments, adjusting the applied voltage on each word line to input the input data of the convolution operation into the memory array includes: turning on the bottom electrode layer and the top electrode layer in each non-volatile two-terminal memory cell; turning off the middle electrode layer in each non-volatile two-terminal memory cell; and adjusting the applied voltage on the word line to input the input data of the convolution operation.

[0030] In some embodiments, before adjusting the applied voltage on each word line to input the input data of the convolution operation into the storage array, it also includes: controlling each non-volatile two-terminal storage unit to perform a write operation by adjusting the applied voltage on the word line and / or the applied voltage on the bit line to store the weight matrix required for the convolution operation into the storage array.

[0031] In some embodiments, by adjusting the applied voltage on the word line and / or the applied voltage on the bit line, each non-volatile two-terminal memory cell is controlled to perform a write operation to store the weight matrix required for the convolution operation into the storage array, including: turning on the selective conduction device connected to the two adjacent electrode layers of the conversion layer; by adjusting the applied voltage on the word line and / or the applied voltage on the bit line, the driving voltage received by the two adjacent electrode layers of the conversion layer is controlled to determine the resistance state mark of the conversion layer; based on the resistance state mark of each conversion layer in the non-volatile two-terminal memory cell, the conductance represented by the non-volatile two-terminal memory cell is determined to store it as the weight value of the weight matrix required for the convolution operation into the storage array.

[0032] Through the non-volatile two-terminal memory cell provided above, the embodiments of the present application integrate a multi-layer resistance-switchable structure within a single memory cell by alternately stacking multiple conversion layers and multiple electrode layers. Because each electrode layer is connected to the selective conduction device via the voltage output port of the selective conduction device, the voltage received by each electrode layer can be independently controlled, thereby achieving independent control of the conductive path of each conversion layer, that is, achieving independent control of the resistance state of each conversion layer. Furthermore, through the combination of the resistance states of different conversion layers, the entire non-volatile two-terminal memory cell can be realized in a low resistance state, a high resistance state, and an intermediate resistance state between the two. This can cover a wider range of conductivities and meet the needs of complex convolution operations in the field of artificial intelligence. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other objects, features and advantages of the exemplary embodiments of the present application will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0034] Figure 1 An exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present application is shown;

[0035] Figure 2 illustrative structural diagrams of non-volatile two-terminal memory cells according to other embodiments of the present application are shown;

[0036] Figure 3 illustrative structural diagrams of non-volatile two-terminal memory cells according to yet other embodiments of the present application;

[0037] Figure 4 Schematic diagram showing an equivalent circuit of a non-volatile two-terminal memory cell according to some embodiments of the present application;

[0038] Figure 5 An exemplary structural diagram of a storage array according to some embodiments of the present application is shown;

[0039] Figure 6 A schematic diagram showing a storage and computing integrated device according to some embodiments of the present application is shown;

[0040] Figure 7 A schematic diagram showing a storage and computing integrated device according to some embodiments of the present application is shown;

[0041] Figure 8 An exemplary flow chart of a convolution operation method according to some embodiments of the present application is shown;

[0042] Figure 9 An exemplary flow chart showing a method for calculating a convolution operation result according to some embodiments of the present application is shown;

[0043] Figure 10 An exemplary flow chart of a convolution operation method according to some embodiments of the present application is shown;

[0044] Figure 11 An exemplary flow chart of a weight matrix storage method according to some embodiments of the present application is shown. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0046] It should be understood that the terms "include" and "comprising" used in the description and claims of this application indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0047] It should also be understood that the terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this specification and claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" as used in this specification and claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0048] As used in this specification and claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0049] The specific implementation of the present application will be described in detail below with reference to the accompanying drawings.

[0050] Example application scenarios

[0051] Convolutional Neural Networks (CNNs) are deep learning models used in computer vision. Their applications have made significant progress in image recognition, object detection, image generation, and other fields. For example, convolution operations perform weighted processing on pixels in an image. Because RRAM combines storage and computation, the computationally intensive multiplication and addition operations involved in convolution can be simulated using RRAM.

[0052] However, existing RRAM only has two resistance states: high resistance and low resistance. The resistance value of the convolution kernel in the convolution operation can be only high or low. The convolution kernel combination is single, and the implemented convolution operation is relatively simple.

[0053] Exemplary application scenarios

[0054] In view of this, an embodiment of the present application provides a non-volatile two-terminal storage solution, which realizes multiple resistance states through alternating stacked conversion layers and electrode layers and under the control of a selective conduction device, thereby adapting to more complex convolution operations.

[0055] Figure 1 An exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present application is shown. Figure 1As shown, the non-volatile two-terminal storage unit includes: N conversion layers 12 and N+1 electrode layers 11, wherein N is an integer greater than 2, and these conversion layers 12 and electrode layers 11 are alternately stacked, so that each conversion layer 12 is provided with an electrode layer 11 adjacent to it above and below, and the conversion layer 12 and its two adjacent electrode layers 11 constitute a storage sub-unit.

[0056] The nonvolatile two-terminal memory cell further includes a selective conduction device 13 having voltage output ports corresponding one-to-one with the electrode layers 11, with each voltage output port connected to one electrode layer 11, thereby ensuring a one-to-one correspondence between the voltage output ports and the electrode layers 11. Furthermore, the electrode layers 11 and the voltage output ports of the selective conduction device 13 can be electrically connected via metal wiring.

[0057] As an example, the selective conduction device 13 can be a selector, which is a switching tube used in semiconductor devices. Its main function is to select a signal from multiple input signals for output, thereby controlling the driving voltage received by the electrode layer in each storage sub-unit, and then realizing the resistance state control of the current storage sub-unit.

[0058] As another example, the selective conduction device 13 can also be a multiplexer (MUX), which is a combinational logic circuit that can select a signal output from multiple input signals according to different channel selection control signals, thereby controlling the driving voltage received by the electrode layer in each storage sub-unit, and further realizing the resistance state control of the current storage sub-unit.

[0059] The above description of the selective conduction device is only an example. In actual application, other devices with selective conduction function are also applicable to this application.

[0060] In this embodiment, the number of selective conduction devices 13 can be one or more. As an example, the number of selective conduction devices 13 is N+1, and each selective conduction device 13 has one voltage output port. Each selective conduction device 13 is connected to the electrode layer 11 via its voltage output port in a one-to-one correspondence, i.e., each voltage output port is independently controlled by its own control module. As another example, the number of selective conduction devices 13 is one, and the selective conduction device 13 has multiple voltage output ports. The multiple voltage output ports are connected to the electrode layer 11 in a one-to-one correspondence, i.e., each voltage output port is uniformly controlled by a single control module.

[0061] In a non-volatile two-terminal memory cell, adjacent memory sub-cells can share an electrode layer 11, that is, a reused electrode layer 11 exists in the non-volatile two-terminal memory cell. Based on the position of the electrode layer 11 in the non-volatile two-terminal memory cell, the N+1 electrode layers 11 can be classified into the following three categories: bottom electrode layer, top electrode layer, and middle electrode layer. The bottom electrode layer is the electrode layer at the bottom of the non-volatile two-terminal memory cell in the stacking direction, the top electrode layer is the electrode layer at the top of the non-volatile two-terminal memory cell in the stacking direction, and the middle electrode layer is the electrode layer located between the bottom electrode layer and the top electrode layer. The middle electrode layer is reused by multiple adjacent conversion layers.

[0062] Through the electrode layer reuse design, the number of electrode layers in the non-volatile two-terminal memory cell can be reduced, thereby reducing the number of required voltage output ports and reducing the stacking height of the non-volatile two-terminal memory cell, which is beneficial to reducing the workload of the selective conduction device and miniaturizing the non-volatile two-terminal memory cell.

[0063] Furthermore, in some embodiments, the electrode layer 11 may be a single material structure layer or a composite structure layer. For example, the electrode layer 11 may have a composite structure including a stacked storage unit electrode layer 112 and a conductive metal layer 111 . Figure 2 illustrative structural diagrams of non-volatile two-terminal storage cells according to other embodiments of the present application are shown. Figure 3 FIG. 4 shows an exemplary structural diagram of a non-volatile two-terminal storage unit according to some other embodiments of the present application, such as Figure 2 and Figure 3 As shown, the bottom electrode layer includes a conductive metal layer 111 and a storage unit electrode layer 112 arranged in sequence along the stacking direction. The composition of the top electrode layer is consistent with that of the bottom electrode layer, and the difference lies in the arrangement direction of the conductive metal layer 111 and the storage unit electrode layer 112. The top electrode layer includes the storage unit electrode layer 112 and the conductive metal layer 111 arranged in sequence along the stacking direction, and the middle electrode layer includes the storage unit electrode layer 112, the conductive metal layer 111 and the storage unit electrode layer 112 arranged in sequence along the stacking direction.

[0064] Furthermore, to facilitate the fabrication of metal wiring connecting the electrode layers and the voltage output port via a metal through-hole process, the non-volatile two-terminal memory cell in some embodiments designs the electrode layer area: the areas of the N+1 electrode layers vary monotonically in the stacking direction, thereby ensuring that each electrode layer has an exposed surface in the stacking direction for fabricating metal wiring. Specifically, the voltage output port is connected to the electrode layer via a metal wiring, wherein one end of the metal wiring is connected to the voltage output port, and the other end is connected to the exposed surface of the electrode layer in the stacking direction.

[0065] It should be noted that the monotonic change here includes monotonic increase and monotonic decrease. If the monotonic change characteristic is monotonic decrease, then the non-volatile storage unit at both ends is as follows: Figure 1-Figure 3 As shown, the metal connection is formed on the upper surface of the electrode layer, and the voltage output port is connected to the upper surface of the electrode layer through the metal connection; if the monotonic change characteristic is a monotonically increasing characteristic, then conversely, the metal connection is formed on the lower surface of the electrode layer.

[0066] It should be further explained that if the electrode layer is a single material structure layer, such as Figure 1 As shown, the area of ​​the electrode layer has a monotonic variation characteristic in the stacking direction; if the electrode layer is a composite structure layer, then part of the structural layer in the composite structure may have a monotonic variation characteristic in the stacking direction, such as Figure 2 As shown, all the conductive metal layers and part of the memory cell electrode layers may have monotonically varying characteristics in the stacking direction, or, as shown in FIG. Figure 3 As shown, only the conductive metal layer has a monotonically changing characteristic in the stacking direction, so that the metal wiring is formed on the exposed surface of the conductive metal layer.

[0067] It should also be noted that in the above-mentioned monotonic change characteristics, the amplitude of each increase or decrease can be fixed or variable, that is, the area difference between each two adjacent electrode layers can be the same or different, and no excessive restrictions are imposed here.

[0068] In addition to the area of ​​the electrode layer, the thickness and material of the electrode layer can also be designed to meet actual needs. Similar to the electrode layer, the size and material of the conversion layer can also be adjusted according to actual conditions. In some embodiments, the non-volatile two-terminal storage unit meets one or more of the following conditions: the thickness of each conversion layer is the same or the thickness of at least some of the conversion layers is different, the material of each conversion layer is the same or the material of at least some of the conversion layers is different, the thickness of each electrode layer is the same or the thickness of at least some of the electrode layers is different, and the material of each electrode layer is the same or the material of at least some of the electrode layers is different.

[0069] The following describes the principle of realizing multiple resistance states of the non-volatile two-terminal memory cell shown in the embodiment of the present application. The non-volatile two-terminal memory cell can achieve its overall resistance state adjustment by adjusting the resistance state combination of multiple storage sub-units.

[0070] First, the resistance state control process of the storage sub-unit is explained. Taking one of the conversion layers as an example, if the two adjacent electrode layers of the conversion layer receive a first driving voltage, the resistance state mark of the conversion layer is set to a low resistance state mark, and correspondingly, the current storage sub-unit is in a low resistance state; if the two adjacent electrode layers of the conversion layer receive a second driving voltage, the resistance state mark of the conversion layer is set to a high resistance state mark, and correspondingly, the current storage sub-unit is in a high resistance state.

[0071] It should be noted that the first driving voltage here is the write-1 driving voltage Vprogram, which is used to control the memory sub-unit to perform the write-1 operation. The write-1 operation is also called the program operation or the set operation. The second driving voltage here is the write-0 driving voltage Vearse, which is used to control the memory sub-unit to perform the write-0 operation. The write-0 operation is also called the erase operation or the reset operation.

[0072] The resistance state combinations of multiple memory sub-units are described below. For the convenience of understanding, the low resistance state label is defined as label number 1 corresponding to the write-1 operation, and the high resistance state label is defined as label number 0 corresponding to the write-0 operation. In the non-volatile two-terminal memory cell, if the resistance state labels of all conversion layers are high resistance state labels, the conductance represented by the non-volatile two-terminal memory cell is the first conductance; if the resistance state labels of all conversion layers are low resistance state labels, the conductance represented by the non-volatile two-terminal memory cell is the second conductance; if both low resistance state labels and high resistance state labels exist in N conversion layers, the conductance represented by the non-volatile two-terminal memory cell is the third conductance, where the first conductance is The second conductance is The third conductance is Rmin < Rmid < Rmax, and the magnitude of the third conductance is negatively correlated with the number of high resistance state labels.

[0073] It can be understood that when the resistance state labels of all conversion layers are high resistance state labels, the conductance represented by the non-volatile two-terminal memory cell is the smallest, the resistance value is the largest, and it presents a high resistance state; when the resistance state labels of all conversion layers are low resistance state labels, the conductance represented by the non-volatile two-terminal memory cell is the largest, the resistance value is the smallest, and it presents a low resistance state; when both low resistance state labels and high resistance state labels exist in N conversion layers, the conductance represented by the non-volatile two-terminal memory cell is in the middle, and the resistance value is also in the middle, presenting an intermediate resistance state between the high resistance state and the low resistance state.

[0074] Assuming that a non-volatile two-terminal memory cell has four conversion layers, corresponding to four storage sub-units, the resistance state of the non-volatile two-terminal memory cell can be determined based on the tag coding sequence composed of the resistance state tags of the conversion layers. When the tag coding sequence corresponding to the four conversion layers is 0000, it means that the four storage sub-units are all in a high-resistance state. At this time, the non-volatile two-terminal memory cell is equivalent to four high-resistance resistors connected in series. Therefore, the non-volatile two-terminal memory cell is in a high-resistance state; when the tag coding sequence corresponding to the four conversion layers is 1111, it means that the four storage sub-units are all in a low-resistance state. At this time, the non-volatile two-terminal memory cell is equivalent to four low-resistance resistors connected in series. Therefore, the non-volatile two-terminal memory cell is in a low-resistance state; when the tag coding sequence corresponding to the four conversion layers is other sequences, for example: 0001, 0010 , 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, indicating that there are both low-resistance states and high-resistance states in the four storage sub-units. At this time, the non-volatile two-terminal storage unit is equivalent to a number of low-resistance resistors and a number of high-resistance resistors connected in series, presenting an intermediate resistance state between the high-resistance state and the low-resistance state, and the resistance of the intermediate resistance state is positively correlated with the number of high-resistance resistors, that is, the more the number of mark codes 0 in the mark coding sequence, the higher the resistance value and the lower the conductance of the non-volatile two-terminal storage unit.

[0075] It should be noted that the conductance of the non-volatile two-terminal memory cell is related to the number of high-resistance state marks, but has nothing to do with the position of the high-resistance state marks in the sequence.

[0076] It can be understood that in a non-volatile two-terminal memory cell, a single memory sub-cell still only has two resistance states, high and low. However, through the design of alternating stacked conversion layers and electrode layers and the control of the driving voltage by the selective conduction device, multiple memory sub-cells can be combined to present a specific resistance state combination, thereby achieving an intermediate resistance state.

[0077] In order to understand the multi-resistance switching process of non-volatile two-terminal storage cells, Figure 4 Schematic diagram showing an equivalent circuit of a non-volatile two-terminal memory cell according to some embodiments of the present application. Figure 4 The non-volatile two-terminal memory cell shown has five conversion layers and six electrode layers, which is equivalent to five memory sub-cells connected in series. Figure 4 R1, R2, R3, R4 and R5 represent five storage subunits, S0, S1, S2, S3, S4 and S5 represent selective conduction devices connected to six electrode layers. Figure 4 The read and write operations of the non-volatile storage units at both ends are described as follows:

[0078] When a non-volatile two-terminal memory cell performs a write operation, the selective conduction device connected to the electrode layer of the target memory sub-cell is first turned on. For example, when the target memory sub-cell is R2, S1 and S2 are first turned on, and then a write 1 drive voltage Vprogram or a write 0 drive voltage Vearse is applied to the S1-R2-S2 path to perform a write 1 operation or a write 0 operation on R2. The same applies to the write operations of R1, R3, R4 and R5.

[0079] When the non-volatile two-terminal memory cell performs a read operation, the selective conduction device connecting the bottom electrode layer and the top electrode layer is turned on, that is, Figure 4 S0 and S5 in the circuit, and close the selective conduction device connected to the middle electrode layer, that is, Figure 4 S1, S2, S3 and S4 in the circuit, and then apply a third driving voltage to the path of S0-R1-R2-R3-R4-R5-S5, where the third driving voltage is the read voltage Vread, so as to read the resistance state / conductance currently stored in the non-volatile two-terminal memory cell.

[0080] Based on the non-volatile two-terminal memory cell shown in any of the above embodiments, some embodiments of the present application provide the following Figure 5 The storage array shown, Figure 5 An exemplary structural diagram of a storage array according to some embodiments of the present application is shown. Figure 5 As shown, the memory array includes: a word line (WL), a bit line (BL) and at least two non-volatile two-terminal memory cells 10, wherein the structure of the non-volatile two-terminal memory cell 10 has been described in detail in the previous embodiment and will not be repeated here.

[0081] In a memory array, a bottom electrode layer in a non-volatile two-terminal memory cell is connected to one of a word line and a bit line, a top electrode layer is connected to the other of the word line and the bit line, and a middle electrode layer is connected to the word line or the bit line. Specifically, the bottom electrode layer, the top electrode layer, and the middle electrode layer are connected to a voltage output port of a selective conduction device via metal wiring, and a voltage input port of the selective conduction device is connected to a word line or a bit line. The bottom electrode layer is the electrode layer at the bottom of the non-volatile two-terminal memory cell in the stacking direction, the top electrode layer is the electrode layer at the top of the non-volatile two-terminal memory cell in the stacking direction, and the middle electrode layer is the electrode layer located between the bottom and top electrode layers.

[0082] When the selective conduction device connected to the electrode layer of the storage sub-unit is turned on, the storage sub-unit can receive a corresponding driving voltage from the word line and / or bit line, and perform a write 1 operation, a write 0 operation or a read operation in response to the driving voltage. Specifically, the storage array is configured as follows: in response to the selective conduction device connected to the two adjacent electrode layers of the conversion layer being turned on, and the two adjacent electrode layers of the conversion layer receiving a first driving voltage, where the first driving voltage is a write 1 driving voltage Vprogram, the resistance state mark of the conversion layer is set to a low resistance state mark, and the storage sub-unit where the conversion layer is located performs a write 1 operation; in response to the selective conduction device connected to the two adjacent electrode layers of the conversion layer being turned on, and the two adjacent electrode layers of the conversion layer receiving a second driving voltage, where the second driving voltage is a write 0 driving voltage Vearse, the resistance state mark of the conversion layer is set to a high resistance state mark, and the storage sub-unit where the conversion layer is located performs a write 0 operation; in response to the selective conduction device connected to the bottom electrode layer and the selective conduction device connected to the top electrode layer being turned on, the selective conduction device connected to the middle electrode layer being turned off, and the top electrode layer and the bottom electrode layer receiving a third driving voltage, the non-volatile two-terminal storage cell performs a read operation, thereby reading the conductance represented by the non-volatile two-terminal storage cell.

[0083] Based on the above-mentioned storage array, some embodiments of the present application provide a storage and computing integrated device, which includes the storage array in any of the above embodiments. Figure 6 A schematic diagram of a storage and computing integrated device according to some embodiments of the present application is shown. Figure 6 As shown, the storage and calculation simulation results of the storage and calculation integrated device are determined based on the current on the bit line. Specifically, Figure 6 Where G1 and G2 represent the conductance of the non-volatile two-terminal memory cells at different locations in the memory array. When voltages V1 and V2 are applied to the word line, the current I flowing through the bit line where the non-volatile two-terminal memory cell is located is I=I1+I2=V1×G1+V2×G2. The above-mentioned multiplication followed by accumulation operation can be approximated to the multiplication-addition operation in the matrix multiplication operation. The conductance of the non-volatile two-terminal memory cell can be set by performing write-1 operations and write-0 operations.

[0084] When the storage-computing integrated device is used to perform a matrix multiplication operation, in response to each non-volatile two-terminal storage cell in the storage array completing a write operation, the storage array stores the conductance represented by each non-volatile two-terminal storage cell as a first matrix for the matrix multiplication operation.

[0085] Furthermore, the values ​​of the matrix elements in the first matrix are the conductance represented by each non-volatile two-terminal memory cell in the memory array. When a write operation is performed, the non-volatile two-terminal memory cell is turned on in response to the selective conduction device connected to the two adjacent electrode layers of the conversion layer, and the resistance state mark of the conversion layer is determined according to the driving voltage received by the two adjacent electrode layers of the conversion layer. Then, the conductance represented by the non-volatile two-terminal memory cell is determined based on the resistance state mark of each conversion layer in the non-volatile two-terminal memory cell.

[0086] It should be noted that the resistance state combinations of the storage sub-units in the non-volatile two-terminal storage unit are limited, and the numerical range covered by the actual conductance of the non-volatile two-terminal storage unit is limited. In order to enable the storage array of the storage and computing integrated device to be used for general matrix operations, a mapping relationship can be formed between the actual conductance of the non-volatile two-terminal storage unit and the matrix to be calculated, and the matrix element values ​​in the matrix to be calculated are used as the conductance represented by the non-volatile two-terminal storage unit to adapt to matrix multiplication operations in various numerical ranges.

[0087] The above describes the process of the storage and computing integrated device realizing the storage function. The following describes the process of the storage and computing integrated device realizing the simulation computing function.

[0088] When the storage and computing integrated device is used to perform matrix multiplication operations, in response to each non-volatile two-terminal memory cell being in a read operation state, the applied voltage on the word line is received as the second matrix as input, and then the matrix multiplication result of the first matrix and the second matrix is ​​obtained by reading the driving current on the bit line, wherein each non-volatile two-terminal memory cell satisfies the following conditions when it is in the read operation state: the selective conduction device connected to the bottom electrode layer and the selective conduction device connected to the top electrode layer are both turned on, and the selective conduction device connected to the middle electrode layer is turned off.

[0089] according to Figure 6 As shown in the schematic diagram of the storage and computing integrated device, it can be understood that the driving current on the bit line is equal to the sum of the products of the applied voltage on the word line and the conductance represented by the non-volatile two-terminal storage cells. Figure 7 A schematic diagram of a storage and computing integrated device according to some embodiments of the present application is shown. Figure 7 As shown, assuming that the memory array includes four non-volatile two-terminal memory cells, these four non-volatile two-terminal memory cells are integrated between two word lines and two bit lines, and the characterized conductances are G1, G2, G3 and G4 respectively, the driving voltages on the two word lines are V3 and V4 respectively, and the driving currents output by the two bit lines are I3 and I4 respectively, the first matrix can be expressed as The second matrix can be expressed as [V3V4], and the calculation of I3 and I4 is equivalent to the multiplication of the first matrix and the second matrix: Among them, I3=V3×G3+V4×G5, I4=V3×G4+V4×G6.

[0090] Furthermore, the aforementioned matrix multiplication operation may include a convolution operation. In the convolution operation of computer image processing technology, an image f(x, y) is convolved with a specially designed convolution kernel g(x, y) to perform a certain weighted processing on the pixels in the current image. The image f(x, y) can be understood as a matrix to be operated on, and the convolution kernel g(x, y) can be understood as another matrix to be operated on, also known as a weight matrix. When the storage-computing device is used for a convolution operation, the storage array stores the conductance represented by each non-volatile two-terminal storage unit as the weight matrix required for the convolution operation. That is, the first matrix described above is the weight matrix.

[0091] It should be noted that convolution operations can not only be applied in computer image processing technology, but also in other technologies such as digital signal processing. The above description is only an example provided by this embodiment. The storage and computing device in this embodiment is also applicable to convolution operations in other application fields besides computer image processing.

[0092] In some embodiments, a storage array can take into account both storage and simulation computing functions. In other embodiments, multiple storage arrays responsible for different functions can be set up in the storage and computing device. For example, the storage and computing device includes at least two storage arrays, one of which is responsible for storing the weight matrix as a storage sub-array, and the other is responsible for convolution operations as a computing sub-array.

[0093] The following combination Figure 8 The convolution operation method of the storage and computing device shown above is explained. Figure 8 An exemplary flow chart of a convolution operation method 800 according to some embodiments of the present application is shown. Figure 8 As shown, in step S801, the applied voltage on each word line is adjusted to input the input data of the convolution operation into the memory array;

[0094] In step S802 , the driving current on each bit line is read to obtain a convolution operation result.

[0095] The result of the convolution operation is the product of the input data and the weight matrix stored in the storage array.

[0096] by Figure 7 Taking the storage and computing device shown as an example, step S801 can input the second matrix [V3V4] into the storage array by adjusting V3 and V4, and use it as input data for convolution operation. Then, step S802 is executed to read I3 and I4 to obtain the input data and the weight matrix pre-stored in the storage array. The convolution operation result.

[0097] When executing step S801, it is necessary to adjust the selective conduction device in the non-volatile two-terminal memory cell to switch the non-volatile two-terminal memory cell to a read operation state so as to read the conductance of the non-volatile two-terminal memory cell in the memory array for use in a convolution operation. Specifically, the process includes turning on the bottom electrode layer and the top electrode layer in each non-volatile two-terminal memory cell and turning off the middle electrode layer in each non-volatile two-terminal memory cell. After adjusting the selective conduction device, the voltage applied to the word line is adjusted to input input data for the convolution operation.

[0098] In this embodiment, the calculation process of the driving current on the bit line is the convolution operation process of the input data and the weight matrix. Figure 9 An exemplary flow chart of a convolution operation result calculation method 900 of some embodiments of the present application is shown, namely Figure 8 The specific execution process of step S802.

[0099] like Figure 9 As shown, in step S901, the product of the applied voltage of each word line and the conductance represented by the non-volatile two-terminal memory cell connected to the word line is calculated to obtain the current outputted to the bit line by each non-volatile two-terminal memory cell;

[0100] In step S902, the sum of the currents output by the non-volatile storage cells at both ends connected to each bit line is calculated to obtain the driving current on each bit line;

[0101] In step S903 , a convolution operation result is obtained based on the driving current on each bit line.

[0102] Still Figure 7 Taking the integrated storage and computing device shown as an example, for a nonvolatile two-terminal memory cell with a conductance of G3, the applied voltage received on its word line is V3, and the current output by this nonvolatile two-terminal memory cell to the bit line is V3×G3. For a nonvolatile two-terminal memory cell with a conductance of G5, the applied voltage received on its word line is V4, and the current output by this nonvolatile two-terminal memory cell to the bit line is V4×G5. If a nonvolatile two-terminal memory cell with a conductance of G3 and a nonvolatile two-terminal memory cell with a conductance of G5 are connected to the same bit line, the sum of the currents on this bit line is V3×G3+V4×G5, i.e., the drive current I3 on ​​this bit line. The drive current I4 on the other bit line can be calculated using the same method, thereby forming the final convolution operation result: [I3I4].

[0103] During the above-mentioned convolution operation, a pre-stored weight matrix needs to be used. Therefore, in some embodiments, before the storage-computing integrated device performs simulation calculations, the weight matrix needs to be pre-stored in the storage-computing integrated device.

[0104] Figure 10 An exemplary flow chart of a convolution operation method 1000 according to some embodiments of the present application is shown. Figure 10 As shown, in step S1001, by adjusting the voltage applied on the word line and / or the voltage applied on the bit line, each non-volatile two-terminal storage unit is controlled to perform a write operation to store the weight matrix required for the convolution operation into the storage array;

[0105] In step S1002 , the voltage applied to each word line is adjusted to input the input data of the convolution operation into the memory array;

[0106] In step S1003 , the driving current on each bit line is read to obtain a convolution operation result.

[0107] It should be noted that the specific contents of the above-mentioned steps S1002 and S1003 are consistent with those of steps S801 and S802 in the previous embodiment, and will not be further elaborated here.

[0108] In this embodiment, when executing step S1001, the selective conduction device in the non-volatile two-terminal memory cell needs to be adjusted to switch the non-volatile two-terminal memory cell to a write operation state, and perform a write-1 operation or a write-0 operation on the memory sub-unit, so that the non-volatile two-terminal memory cells at different positions in the memory array exhibit different resistance states, representing different conductances.

[0109] It should be noted that the process of adjusting the weight matrix stored in the storage array can be understood as the process of adjusting the conductance / resistance state of each non-volatile two-terminal storage unit in the storage array, and the process of adjusting the conductance / resistance state of each non-volatile two-terminal storage unit in the storage array can be understood as the process of adjusting the resistance state of each storage sub-unit in each non-volatile two-terminal storage unit. Therefore, step S1001 can be divided into sub-steps of switching the resistance state of each storage sub-unit, and the specific process is as follows.

[0110] Figure 11 An exemplary flow chart of a weight matrix storage method 1100 according to some embodiments of the present application is shown. Figure 11 As shown, in step S1101, the selective conduction devices connected to two adjacent electrode layers of the conversion layer are turned on;

[0111] In step S1102, by adjusting the voltage applied on the word line and / or the voltage applied on the bit line, the driving voltage received by two adjacent electrode layers of the conversion layer is controlled to determine the resistance state mark of the conversion layer;

[0112] In step S1103 , the conductance represented by the nonvolatile two-terminal memory cell is determined based on the resistance state flag of each conversion layer in the nonvolatile two-terminal memory cell, and is stored in a memory array as a weight value of a weight matrix required for a convolution operation.

[0113] by Figure 4 Taking the non-volatile two-terminal memory cell shown as an example, when adjusting R2, S1 and S2 are first turned on, and then the applied voltage on the S1-R2-S2 path is controlled by adjusting the applied voltage on the word line and / or the applied voltage on the bit line. When the applied voltage is the write 1 drive voltage Vprogram, the resistance state of the conversion layer in R2 is marked as 1, indicating that R2 is in a low resistance state. When the applied voltage is the write 0 drive voltage Vearse, the resistance state of the conversion layer in R2 is marked as 0, indicating that R2 is in a high resistance state. The write operation of R1, R3, R4 and R5 is the same.

[0114] After the resistance state of each storage sub-unit in the non-volatile two-terminal storage unit is adjusted, the resistance state of the entire non-volatile two-terminal storage unit can be determined based on the combination of resistance state marks, thereby determining the conductance it represents, and storing it in the storage array as the weight value of the weight matrix required for the convolution operation.

[0115] The resistance state flags of the storage subunits in the non-volatile two-terminal memory cell can form different combinations, so that the non-volatile two-terminal memory cell not only has high and low resistance states, but also can present an intermediate resistance state between the high resistance state and the low resistance state. Furthermore, according to the number of high resistance state flags in multiple storage subunits, the intermediate resistance state can be divided into multiple intermediate resistance states representing different conductivities, thereby realizing a multi-resistance state non-volatile two-terminal memory solution to adapt to complex convolution operations.

[0116] In summary, the embodiments of the present application provide a non-volatile two-terminal memory cell that integrates multiple memory sub-cells with variable resistance states within a single memory cell by alternately stacking multiple conversion layers and multiple electrode layers. Because the driving voltage received by the electrode layer of each memory sub-cell can be independently controlled by a selective conduction device, multiple resistance state combinations of the conversion layers can be achieved. This allows the non-volatile two-terminal memory cell containing multiple conversion layers to have not only a low resistance state and a high resistance state, but also an intermediate resistance state between the two, thereby realizing a multi-conductance non-volatile two-terminal memory cell that can meet the needs of complex convolution operations in the field of artificial intelligence.

[0117] Based on the above-mentioned non-volatile two-terminal storage cell, the present application also provides a storage array, which integrates the above-mentioned multi-conductance non-volatile two-terminal storage cell between the word line and the bit line, so that multiple conductivities can be stored in the storage array through a write operation, and the conductance data can be read through a read operation to realize multi-value storage.

[0118] Based on the above-mentioned storage array, the present application also provides a storage and computing integrated device, which uses the storage array for storage and analog calculations, stores array data with multiple matrix elements into the storage array through the write operation of the non-volatile two-terminal unit, and completes the matrix multiplication operation in the storage array through the read operation, the adjustment of the word line drive voltage and the reading operation of the bit line drive current, thereby deepening the application adaptability of the non-volatile two-terminal storage unit in the convolution operation.

[0119] Although multiple embodiments of the present application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art can conceive of many changes, modifications, and alternatives without departing from the thought and spirit of the present application. It should be understood that in the process of practicing the present application, various alternatives to the embodiments of the present application described herein can be adopted. The accompanying claims are intended to define the scope of protection of the present application and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A non-volatile two-terminal memory cell, characterized in that: include: N conversion layers (12), wherein N is a positive integer greater than 2; N+1 electrode layers (11), the electrode layers (11) and the conversion layers (12) being stacked alternately; and The selective conduction device (13) has voltage output ports corresponding one to one with the electrode layers (11), and the voltage output port is connected to each of the electrode layers (11).

2. The non-volatile two-terminal memory cell according to claim 1, wherein: The non-volatile two-terminal memory cell is configured as: If two adjacent electrode layers of the conversion layer receive the first driving voltage, the resistance state flag of the conversion layer is set to a low resistance state flag; If two adjacent electrode layers of the conversion layer receive the second driving voltage, the resistance state flag of the conversion layer is set to a high resistance state flag.

3. The non-volatile two-terminal memory cell according to claim 2, wherein: The non-volatile two-terminal memory cell is configured as: If the resistance state marks of all conversion layers are the high resistance state marks, the conductance represented by the non-volatile two-terminal memory cell is the first conductance If the resistance state marks of all conversion layers are the low resistance state marks, the conductance represented by the non-volatile two-terminal memory cell is the second conductance If both the low-resistance state mark and the high-resistance state mark exist simultaneously in the N conversion layers, the conductance represented by the non-volatile two-terminal storage cell is the third conductance Rmin < Rmid < Rmax, and the magnitude of the third conductance is negatively correlated with the number of high-resistance state marks.

4. The non-volatile two-terminal memory cell according to claim 1, wherein: The non-volatile two-terminal memory cell includes: a bottom electrode layer, a top electrode layer and an intermediate electrode layer, wherein the bottom electrode layer is the electrode layer located at the bottom in the stacking direction of the non-volatile two-terminal memory cell, the top electrode layer is the electrode layer located at the top in the stacking direction of the non-volatile two-terminal memory cell, and the intermediate electrode layer is the electrode layer located between the bottom electrode layer and the top electrode layer, and the intermediate electrode layer is reused by multiple conversion layers adjacent to it.

5. The non-volatile two-terminal memory cell according to claim 4, wherein: The electrode layer (11) comprises a stacked storage unit electrode layer (112) and a conductive metal layer (111).

6. The non-volatile two-terminal memory cell according to claim 5, wherein: The bottom electrode layer comprises: a conductive metal layer (111) and a storage unit electrode layer (112) sequentially arranged along the stacking direction; the middle electrode layer comprises: a storage unit electrode layer (112), a conductive metal layer (111), and a storage unit electrode layer (112) sequentially arranged along the stacking direction; and the top electrode layer comprises: a storage unit electrode layer (112) and a conductive metal layer (111) sequentially arranged along the stacking direction.

7. The non-volatile two-terminal memory cell according to claim 1, wherein: The number of the selective conduction device (13) is one and the selective conduction device (13) has a plurality of voltage output ports, wherein the plurality of voltage output ports are connected to the electrode layer (11) in a one-to-one correspondence.

8. The non-volatile two-terminal memory cell according to claim 1, wherein: The number of the selective conduction devices (13) is N+1 and each selective conduction device (13) has a voltage output port, wherein each selective conduction device (13) is connected to the electrode layer (11) in a one-to-one correspondence via the voltage output port it has.

9. The nonvolatile two-terminal memory cell according to claim 1, wherein: The areas of the N+1 electrode layers (11) have a monotonically varying characteristic in the stacking direction.

10. The non-volatile two-terminal memory cell according to claim 9, wherein: The voltage output port is connected to the electrode layer (11) via a metal wire, wherein one end of the metal wire is connected to the voltage output port, and the other end is connected to the surface of the electrode layer exposed in the stacking direction.

11. The non-volatile two-terminal memory cell according to claim 1, wherein: The non-volatile two-terminal storage unit satisfies one or more of the following conditions: The thickness of each conversion layer (12) is the same or the thickness of at least some of the conversion layers (12) are different; The materials of each conversion layer (12) are the same or the materials of at least some of the conversion layers (12) are different; The thickness of each electrode layer (11) is the same, or the thickness of at least some of the electrode layers (11) is different; The material of each electrode layer (11) is the same, or the materials of at least some of the electrode layers (11) are different.

12. A storage array, characterized in that: include: word line; bit lines; At least two non-volatile two-terminal memory cells (10) according to any one of claims 1 to 11, wherein the non-volatile two-terminal memory cells (10) comprise: a bottom electrode layer, a top electrode layer, and an intermediate electrode layer, wherein the bottom electrode layer is an electrode layer located at the bottom in a stacking direction of the non-volatile two-terminal memory cell, the top electrode layer is an electrode layer located at the top in a stacking direction of the non-volatile two-terminal memory cell, and the intermediate electrode layer is an electrode layer located between the bottom electrode layer and the top electrode layer; The bottom electrode layer is connected to one of the word line and the bit line, the top electrode layer is connected to the other of the word line and the bit line, and the middle electrode layer is connected to the word line or the bit line.

13. The storage array according to claim 12, wherein: The storage array is configured as follows: In response to the selective conduction devices connected to two adjacent electrode layers of the conversion layer being turned on and the two adjacent electrode layers of the conversion layer receiving a first driving voltage, the resistance state flag of the conversion layer is set to a low resistance state flag; In response to the selective conduction devices connected to two adjacent electrode layers of the conversion layer being turned on and the two adjacent electrode layers of the conversion layer receiving the second driving voltage, the resistance state flag of the conversion layer is set to a high resistance state flag.

14. The storage array according to claim 12, wherein: The storage array is configured as follows: In response to the selective conduction device connected to the bottom electrode layer and the selective conduction device connected to the top electrode layer being turned on, the selective conduction device connected to the middle electrode layer being turned off, and the top electrode layer and the bottom electrode layer receiving a third driving voltage, the conductance represented by the non-volatile two-terminal memory cell is read.

15. A storage and computing integrated device, characterized in that: The integrated storage and computing device includes the storage array as described in any one of claims 12-14.

16. The storage and computing integrated device according to claim 15, characterized in that: The storage array is configured as follows: In response to each nonvolatile two-terminal memory cell in the memory array completing a write operation, the memory array stores the conductance represented by each nonvolatile two-terminal memory cell as a first matrix for a matrix multiplication operation.

17. The storage and computing integrated device according to claim 16, characterized in that: The write operation of the non-volatile two-terminal storage unit includes: In response to the selective conduction devices connected to two adjacent electrode layers of the conversion layer being turned on, determining the resistance state mark of the conversion layer according to the driving voltages received by the two adjacent electrode layers of the conversion layer; The conductance represented by the nonvolatile two-terminal memory cell is determined based on the resistance state signature of each switching layer in the nonvolatile two-terminal memory cell.

18. The storage and computing integrated device according to claim 16, characterized in that: The storage array is configured as follows: In response to each nonvolatile two-terminal memory cell being in a read operation state, receiving the voltage applied on the word line as an input of the second matrix; Obtaining a matrix multiplication result of the first matrix and the second matrix by reading a driving current on the bit line; The read operation state satisfies the following conditions: the selective conduction device connected to the bottom electrode layer and the selective conduction device connected to the top electrode layer are both turned on, and the selective conduction device connected to the middle electrode layer is turned off.

19. The storage and computing integrated device according to claim 18, characterized in that: The driving current on the bit line is equal to the sum of the products of the applied voltage on the word line and the conductance represented by the non-volatile two-terminal memory cell.

20. The storage and computing integrated device according to claim 16, characterized in that: The matrix multiplication operation includes: a convolution operation; The storage array stores the conductance represented by each non-volatile two-terminal storage unit as a first matrix for the matrix multiplication operation, including: the storage array stores the conductance represented by each non-volatile two-terminal storage unit as a weight matrix required for the convolution operation.

21. A convolution operation method, characterized in that: Applied to the storage-computing integrated device according to any one of claims 15 to 20, the method comprising: adjusting the applied voltage on each word line to input the input data of the convolution operation into the memory array; Read the driving current on each bit line to obtain the convolution operation result; The convolution operation result is the product of the input data and the weight matrix stored in the storage array.

22. The convolution operation method according to claim 21, characterized in that: The weight matrix includes: the conductance represented by each non-volatile two-terminal storage unit in the storage array; reading the driving current on each bit line to obtain the convolution operation result includes: Calculating the product of the applied voltage of each word line and the conductance of the non-volatile two-terminal memory cell connected to the word line to obtain the current outputted to the bit line by each non-volatile two-terminal memory cell; Calculate the sum of the currents output by the non-volatile storage units at both ends connected to each bit line to obtain the driving current on each bit line; The convolution operation result is obtained based on the driving current on each bit line.

23. The convolution operation method according to claim 21, wherein: Adjusting the applied voltage on each word line to input the input data of the convolution operation into the memory array includes: turning on the bottom electrode layer and the top electrode layer in each nonvolatile two-terminal memory cell; closing the middle electrode layer in each nonvolatile two-terminal memory cell; The voltage applied to the word line is adjusted to input the input data of the convolution operation.

24. The convolution operation method according to claim 21, wherein: Before adjusting the voltage applied to each word line to input the input data of the convolution operation into the memory array, the method further includes: By adjusting the voltage applied to the word line and / or the voltage applied to the bit line, each non-volatile two-terminal memory cell is controlled to perform a write operation, so as to store the weight matrix required for the convolution operation in the memory array.

25. The convolution operation method according to claim 24, characterized in that: Controlling each non-volatile two-terminal storage unit to perform a write operation by adjusting the voltage applied to the word line and / or the voltage applied to the bit line to store the weight matrix required for the convolution operation in the storage array includes: Turning on the selective conduction device connected to two electrode layers adjacent to the conversion layer; By adjusting the voltage applied to the word line and / or the voltage applied to the bit line, the driving voltage received by two adjacent electrode layers of the conversion layer is controlled to determine the resistance state mark of the conversion layer; The conductance represented by the nonvolatile two-terminal memory cell is determined based on the resistance state mark of each conversion layer in the nonvolatile two-terminal memory cell, so as to be stored in the memory array as a weight value of a weight matrix required for a convolution operation.

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