Semiconductor device structure and forming method thereof

Abstract

The invention discloses a semiconductor device structure and a forming method thereof. The forming method comprises the following steps: forming a sacrificial gate stack on a part of a fin-shaped structure; removing the exposed part of the fin-shaped structure to expose a part of the substrate and the surface of the semiconductor layer of the fin-shaped structure; depositing a first semiconductor material on the exposed portion of the substrate; depositing a dielectric layer; performing an etching process to trim at least a portion of the suspension of the sidewall portion of the dielectric layer; removing a sidewall portion of the dielectric layer; and forming a second semiconductor material on the bottom of the dielectric layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device structure, and more particularly to a structure and method for reducing the concentration of fluorine residues in a dielectric layer. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have enabled each generation of integrated circuits to feature smaller and more complex circuits than the previous one. Throughout the evolution of integrated circuits, functional density (i.e., the number of interconnect devices per unit chip area) has generally increased as geometry (i.e., the smallest component or circuit that can be produced by the fabrication process) has decreased. Process geometry reduction generally increases production capacity and reduces associated costs. However, this reduction in geometry also increases the complexity of processing and manufacturing integrated circuits.

[0003] Therefore, there is a need for improved methods of processing and manufacturing integrated circuits. Summary of the Invention

[0004] In some embodiments, a method for forming a semiconductor device structure includes forming a sacrificial gate stack on a portion of a fin structure; removing an exposed portion of the fin structure to expose a portion of a substrate and a surface of a semiconductor layer of the fin structure; depositing a first semiconductor material on the exposed portion of the substrate; depositing a dielectric layer, wherein the dielectric layer includes a bottom portion located on the first semiconductor material and the dielectric layer includes a sidewall portion located on the surface of the semiconductor layer; performing an etching process to trim at least a portion of the overhang of the sidewall portion of the dielectric layer; removing the sidewall portion of the dielectric layer; and forming a second semiconductor material on the bottom of the dielectric layer.

[0005] In some embodiments, a method for forming a semiconductor device structure includes forming a fin structure from a substrate, wherein the fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers; forming a sacrificial gate stack on the fin structure; depositing a gate spacer on the sacrificial gate stack; removing a portion of the fin structure to expose a portion of the substrate; recessing the second semiconductor layer to form a plurality of voids; forming a plurality of dielectric spacers in the voids; depositing a first semiconductor material on the exposed portion of the substrate; depositing a dielectric layer, wherein the dielectric layer includes a sidewall portion contacting the gate spacers, the first semiconductor layer, and the dielectric spacers, and the dielectric layer includes a bottom portion contacting the first semiconductor material, and wherein a first thickness of a first portion of the sidewall portion near the bottom portion is less than a second thickness of a second portion of the sidewall portion above the first portion; performing a nitrogen trifluoride plasma etching process to reduce the second thickness of the second portion of the sidewall portion; performing an ammonia plasma post-treatment process to remove at least a portion of a plurality of fluorine residues from the dielectric layer left by the nitrogen trifluoride plasma etching process; removing the sidewall portion of the dielectric layer; and forming a second semiconductor material on the bottom portion of the dielectric layer.

[0006] In some embodiments, a semiconductor device structure includes a buried epitaxial layer on a substrate; a dielectric layer on the buried epitaxial layer; a source / drain region on the dielectric layer; a first nanostructured channel adjacent to the source / drain region; a first dielectric spacer contacting the first nanostructured channel; a gate dielectric layer on the first nanostructured channel; and a gate layer on the gate dielectric layer, wherein a center-to-corner thickness ratio of the dielectric layer is between about 0.75 and about 1.33, and wherein a fluorine residue concentration in the dielectric layer is about 0.9 atomic % or less. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 5 are perspective views of various stages in the fabrication of a semiconductor device structure in some embodiments.

[0008] Figures 6 to 19 In some embodiments, the various stages of manufacturing a semiconductor device structure are along Figure 5 Sectional view along section line AA.

[0009] The description of the accompanying drawings is as follows:

[0010] AA: Section Line

[0011] E: Etching process

[0012] PT: post-processing

[0013] T1, T2, T3, T4: thickness

[0014] 100: Semiconductor device structure

[0015] 101: Substrate

[0016] 104: Semiconductor layer stacking

[0017] 106: First semiconductor layer

[0018] 108: Second semiconductor layer

[0019] 112: Fin-like structure

[0020] 114,151: Grooves

[0021] 116: Ibe

[0022] 118: Insulation material

[0023] 120: Quarantine

[0024] 130: Sacrificial gate structure

[0025] 132: Sacrificial gate dielectric layer

[0026] 133: Oxide layer

[0027] 134: Sacrificial gate layer

[0028] 135: Nitride layer

[0029] 136,154: Mask layer

[0030] 138: First gate spacer

[0031] 139: Second gate spacer

[0032] 144: Dielectric spacer

[0033] 150: First semiconductor material

[0034] 152: Dielectric layer

[0035] 153a: Part 1

[0036] 153b: Part 2

[0037] 156: Second semiconductor material

[0038] 158,160: Semiconductor material layer

[0039] 162: Contact etch stop layer

[0040] 164: Interlayer dielectric layer

[0041] 170: Gate dielectric layer

[0042] 172: Gate layer

[0043] 174: Gate structure DETAILED DESCRIPTION

[0044] The following detailed description is accompanied by accompanying drawings to facilitate an understanding of various aspects of the present invention. It should be noted that the various structures are for illustrative purposes only and are not drawn to scale, as is common practice in the industry. In practice, the dimensions of the various structures may be arbitrarily increased or decreased for clarity.

[0045] The following provides different embodiments or examples for implementing different structures of the embodiments of the present invention. The specific components and arrangements are provided to simplify the present disclosure and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes the two being in direct contact, or the two being separated by additional components rather than in direct contact. The same reference numerals may be repeatedly used in various embodiments of the present invention for simplicity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same corresponding relationship.

[0046] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," or similar terms are used to describe the relationship of one element or structure to another element or structure in the drawings. These spatially relative terms encompass various orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is rotated 90 degrees or otherwise, the spatially relative adjectives used will be interpreted based on that orientation.

[0047] Embodiments of the present invention provide a semiconductor device structure having a dielectric layer disposed between two semiconductor materials in source / drain regions. An etching process is performed on the dielectric layer to prevent sidewall merging, followed by a post-treatment process to remove fluorine residues left by the etching process, thereby preventing leakage current.

[0048] Although the embodiments of the present invention are described using nanostructured channel field effect transistors such as all-around gate field effect transistors (e.g., horizontal all-around gate field effect transistors or vertical all-around gate field effect transistors), some embodiments of the present invention can be used in other processes and / or other devices such as planar field effect transistors, fin field effect transistors, or other suitable devices. It should be readily understood by those skilled in the art that other adjustments are also within the scope of the embodiments of the present invention. In the example of a all-around gate transistor structure, the all-around gate transistor structure can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the structure, including double patterning or multiple patterning processes. Generally speaking, double patterning or multiple patterning processes combine photolithography and self-alignment processes, and the pattern spacing produced is smaller than the pattern spacing obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and the sacrificial layer is patterned using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the all-around gate structure.

[0049] Figures 1 to 19 is an exemplary process for manufacturing the semiconductor device structure 100 in an embodiment of the present invention. Figures 1 to 19 Additional steps may be provided before, during, or after the processes shown, and additional embodiments of the method may replace or omit some of the steps described below. The order of the steps / processes is not limited to this and may be interchangeable.

[0050] Figures 1 to 5 1 is a perspective view of various stages of fabricating a semiconductor device structure 100 in some embodiments. Figure 1As shown, semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of substrate 101. Substrate 101 can be a semiconductor substrate. Substrate 101 can include a crystalline semiconductor material such as, but not limited to, silicon, germanium, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, or indium phosphide. In some embodiments, substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) between two silicon layers to enhance performance. In one embodiment, the insulating layer is an oxygen-containing layer.

[0051] The substrate 101 may include various regions doped with dopants (e.g., p-type or n-type dopants). Depending on the circuit design, the dopant may be phosphorus for n-type field effect transistors or boron for p-type field effect transistors.

[0052] The semiconductor layer stack 104 includes semiconductor layers composed of alternating different materials to facilitate the formation of a nanostructured channel in a multi-gate device (e.g., a nanostructured channel field-effect transistor). In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first and second semiconductor layers 106, 108. The first and second semiconductor layers 106, 108 are composed of semiconductor materials having different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be composed of silicon, and the second semiconductor layer 108 may be composed of silicon germanium. In some examples, the first semiconductor layer 106 may be composed of silicon germanium, and the second semiconductor layer 108 may be composed of silicon. In some other embodiments, the first semiconductor layer 106 or the second semiconductor layer 108 may be or include other materials such as germanium, silicon carbide, germanium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, gallium arsenide phosphide, aluminum indium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, or any combination thereof.

[0053] The first semiconductor layer 106 and the second semiconductor layer 108 may be formed by any suitable deposition process such as epitaxy. For example, the epitaxial growth method of the semiconductor layer stack 104 may be molecular beam epitaxy, metal organic chemical vapor deposition, and / or other suitable epitaxial growth processes.

[0054] The first semiconductor layer 106 or a portion thereof may form a nanostructured channel of the semiconductor device structure 100 during subsequent fabrication stages. The term "nanostructured" as used herein refers to a material portion having nanometer or even micrometer dimensions. Thus, the term may refer to elongated material portions having circular and substantially circular cross-sections, as well as bundle- or rod-shaped material portions (which may be cylindrical or have a substantially rectangular cross-section). A gate may surround the nanostructured channel of the semiconductor device structure 100. The semiconductor device structure 100 may include a nanostructured transistor. The nanostructured transistor may be considered a nanosheet transistor, a nanowire transistor, a fully wrapped gate transistor, a multi-bridge channel transistor, or any transistor having a gate surrounding a channel. Methods for defining the channel of the semiconductor device structure 100 using the first semiconductor layer 106 are described below.

[0055] The thickness of each first semiconductor layer 106 may be between about 5 nm and about 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, the thickness of each second semiconductor layer 108 may be between about 2 nm and about 50 nm. The three first semiconductor layers 106 and the three second semiconductor layers 108 are arranged in an alternating manner. Figure 1 , which is provided for illustrative purposes only and does not limit the present invention beyond the scope of the claims. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in semiconductor layer stack 104, and the number of layers depends on the desired number of channels in semiconductor device structure 100. In some embodiments, semiconductor layer stack 104 includes two first semiconductor layers 106. In some embodiments, semiconductor layer stack 104 includes three first semiconductor layers 106. In some embodiments, semiconductor layer stack 104 includes four first semiconductor layers 106.

[0056] like Figure 2As shown, fin structures 112 are formed from the semiconductor layer stack 104. Each of the fin structures 112 includes an upper portion comprising a first semiconductor layer 106 and a second semiconductor layer 108, and a well 116 formed from the substrate 101. The fin structures 112 may be formed by patterning a hard mask layer (not shown) on the semiconductor layer stack 104 using multiple patterning steps including photolithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching, and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form mask cells comprising the photoresist layer. In some embodiments, the method of patterning the photoresist layer to form the mask cells may employ an electron beam lithography process. The etching process passes through the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101 to form trenches 114 in unprotected areas, thereby retaining a plurality of extended fin structures 112. The trench 114 extends along the X direction. The trench 114 may be etched by dry etching (eg, reactive ion etching), wet etching, and / or a combination thereof.

[0057] like Figure 3 As shown, after the fin structure 112 is formed, an insulating material 118 may be formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is buried in the insulating material 118. A planarization step such as chemical mechanical polishing and / or etch-back is then performed to expose the upper surface of the fin structure 112. The insulating material 118 may be composed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, fluorosilicate glass, a low dielectric constant dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as low-pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition.

[0058] like Figure 4 As shown, the insulating material 118 is recessed to form an isolation region 120. The recessing of the insulating material 118 can expose portions of the fin structures 112, such as the semiconductor layer stack 104. The recessing of the insulating material 118 can expose the trenches 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The upper surface of the insulating material 118 can be flush with or lower than the surface of the second semiconductor layer 108 contacting the well 116 (formed from the substrate 101). In some embodiments, the isolation region 120 is a shallow trench isolation region.

[0059] like Figure 5As shown, one or more sacrificial gate structures 130 (only one is shown in the figure) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. The sacrificial gate structures 130 may each include a sacrificial gate dielectric layer 132, a sacrificial gate layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate layer 134, and the mask layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. Although there is one sacrificial gate structure 130 shown in the figure, some embodiments may have two or more sacrificial gate structures 130 arranged along the X direction. In some embodiments, three sacrificial gate structures 130 are arranged along the X direction, as shown in FIG. Figures 11 to 16 shown.

[0060] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The portion of the fin structure 112 covered by the sacrificial gate layer 134 of the sacrificial gate structure 130 may serve as a channel region for the semiconductor device structure 100.

[0061] Figures 6 to 19 In some embodiments, the various stages of manufacturing the semiconductor device structure 100 are as follows Figure 5 The side section view of the section line AA. Figure 6 As shown, a first gate spacer 138 is deposited on the exposed surface of the semiconductor device structure 100. For example, the first gate spacer 138 is deposited on the fin structure 112, the isolation region 120, and the sacrificial gate structure 130. The first gate spacer 138 can be composed of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, and / or combinations thereof. The first gate spacer 138 can be formed by any suitable process. In some embodiments, the first gate spacer 138 is a compliant layer formed by a compliant process such as atomic layer deposition.

[0062] like Figure 7 As shown, a second gate spacer 139 is deposited on the first gate spacer 138. The second gate spacer 139 may include any suitable dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbonitride, or silicon oxycarbide. The thickness of the second gate spacer 139 may be from about 0.5 nm to about 5 nm. The second gate spacer 139 may be formed by any suitable process. In some embodiments, the second gate spacer 139 is deposited by chemical vapor deposition, plasma-assisted chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition.

[0063] like Figure 8 As shown, the horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed. In some embodiments, the method for removing the horizontal portions of the first gate spacer 138 and the second gate spacer 139 may be an anisotropic etching process. The anisotropic etching process may be a selective etching process that does not substantially affect the mask layer 136, the semiconductor layer stack 104, and the isolation region 120.

[0064] like Figure 9 As shown, the portion of the fin structure 112 not covered by the sacrificial gate structure 130, the first gate spacer 138, and the second gate spacer 139 is recessed to a level higher than, flush with, or lower than the upper surface of the isolation region 120. The method for recessing the portion of the fin structure 112 may be an etching process. The etching process may be dry etching (such as reactive ion etching, neutral beam etching, or the like) or wet etching (such as using tetramethylammonium hydroxide, ammonium hydroxide, or any suitable etchant). The well portion 116 is exposed on both sides of the sacrificial gate structure 130, as shown in FIG. Figure 9 shown.

[0065] like Figure 10 As shown, edge portions of each of the second semiconductor layers 108 of the semiconductor layer stack 104 are horizontally removed along the X-direction. Removing the edge portions of the second semiconductor layer 108 may form a cavity. In some embodiments, the method for removing portions of the second semiconductor layer 108 may be a selective wet etching process. In an example where the second semiconductor layer 108 is composed of silicon germanium and the first semiconductor layer 106 is composed of silicon, a wet etchant may be used to selectively etch the second semiconductor layer 108. The wet etchant may be, but is not limited to, ammonium hydroxide, tetramethylammonium hydroxide, ethylenediaminecatechol, or potassium hydroxide solution.

[0066] After removing the edge portions of the second semiconductor layer 108, a dielectric layer may be deposited in the cavity to form dielectric spacers 144. The dielectric spacers 144 may be composed of a low-k dielectric material such as silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, or silicon nitride. The dielectric spacers 144 may be formed by first forming a compliant dielectric layer using a compliant deposition process such as atomic layer deposition, followed by anisotropic etching to remove portions of the compliant dielectric layer outside the dielectric spacers 144. The first semiconductor layer 106 may protect the dielectric spacers 144 during the anisotropic etching process. The remaining second semiconductor layer 108 between the dielectric spacers 144 may be capped along the X-direction.

[0067] like Figure 11As shown, trenches 151 are formed between adjacent semiconductor layer stacks and between adjacent sacrificial gate structures 130. As described above, in some embodiments, the mask layer 136 includes an oxide layer 133 and a nitride layer 135. A first semiconductor material 150 is formed on the exposed well portion 116 at the bottom of the trench 151. In some embodiments, the first semiconductor material 150 includes undoped silicon or undoped silicon germanium. The first semiconductor material 150 can be initially epitaxially formed on a semiconductor surface, such as on the exposed well portion 116 and the first semiconductor layer 106. The first semiconductor material 150 can be a buried epitaxial layer. A subsequent etching process is performed to remove the portion of the first semiconductor material 150 on the first semiconductor layer 106. The first semiconductor material 150 formed on the exposed well portion 116 can form a concave upper surface as a result of the etching process. In some embodiments, the thickness of the first semiconductor material 150 along the Z direction is approximately 5 nm to approximately 50 nm.

[0068] Then as Figure 11 As shown, a dielectric layer 152 is formed on the semiconductor device structure 100. The method for forming the dielectric layer 152 may define the deposition portion of the deposition-etch profile selective process. In some embodiments, the dielectric layer 152 may be formed immediately after the aluminum oxide removal process. The dielectric layer 152 is formed within the trenches 151 and over the sacrificial gate structure 130, the first gate spacer 138, and the second gate spacer 139. The dielectric layer 152 may include any suitable dielectric material. The dielectric layer 152 may be formed by any suitable process. In some embodiments, the dielectric layer 152 is formed by chemical vapor deposition. The portion of the dielectric layer 152 formed on the vertical surfaces may have a first thickness T1, and the portion of the dielectric layer 152 formed on the horizontal surfaces may have a second thickness T2, with the second thickness T2 being substantially greater than the first thickness T1. In some embodiments, the sidewall portion of the dielectric layer 152 is located on the vertical surface within each trench 151, while the bottom of the dielectric layer 152 is located on the first semiconductor material 150. For example, the sidewall portion of the dielectric layer 152 may be formed on vertical surfaces of the dielectric spacer 144, the first semiconductor layer 106, the first gate spacer 138, and the second gate spacer 139, as shown in FIG. Figure 11As shown. In some embodiments, the sidewall portion of the dielectric layer 152 has a thickness T1, and the bottom of the dielectric layer 152 has a thickness T2, and the thickness T2 is substantially greater than the thickness T1. In some embodiments, the width of the trench 151 in the X direction is about 22nm to about 26nm, and the thickness T1 may be greater than about 5nm and less than about 10nm. If the thickness T1 is greater than 10nm, the dielectric layer 152 may be connected to the top of the trench 151. In other words, the dielectric layer 152 may seal the trench 151 and form a cavity therein. The bottom of the dielectric layer 152 may serve as an isolation layer to prevent leakage current from passing through the portion of the well 116 below the bottom-most second semiconductor layer 108. Therefore, if the thickness T2 is less than about 3nm, the bottom of the dielectric layer 152 may be too thin to fully serve as an isolation layer. In some embodiments, the sidewall portion of the dielectric layer 152 defines an overhang at or near the top of the trench 151, wherein the second portion 153b of the sidewall portion extends into the trench 151 in the X direction and substantially exceeds the first portion 153a of the sidewall portion. In some embodiments, the first portion 153a may conform more closely to the vertical surface of the trench 151 than the second portion 153b. In other words, the thickness T1 of the first portion 153a of the sidewall portion closer to the bottom is less than the thickness T3 of the second portion 153b of the sidewall portion above the first portion 153a. In some embodiments, the second portion 153b of the sidewall portion is defined at the top of the trench 151 and contacts the second gate spacer 139. As smaller process nodes are developed to reduce geometric dimensions, individual overhangs on both sides of the same trench 151 may merge, connecting the dielectric layer 152 to the top or near the top of the trench 151, as described above. Therefore, it is necessary to reduce the size of the overhang. In some embodiments, a solution is to perform an etching process ( Figure 12 ) to trim at least a portion of the overhang to reduce the thickness T3.

[0069] like Figure 12As shown, an etching process E is performed. The etching process reduces the thickness of the overhang from thickness T3 to thickness T4. In some embodiments, after the nitrogen trifluoride plasma etching process, the second portion 153b of the sidewall portion does not extend into the trench and substantially extends beyond the first portion 153a. In some embodiments, the etching process may include nitrogen trifluoride plasma etching. In some embodiments, the nitrogen trifluoride flow rate of the nitrogen trifluoride plasma etching is between about 10 SCCM (standard cubic centimeters per minute) and about 150 SCCM, such as between about 40 SCCM and about 100 SCCM, such as about 70 SCCM. In some embodiments, the RF power of the nitrogen trifluoride plasma etching is between about 50 watts and about 150 watts, such as between about 70 watts and about 120 watts, such as about 90 watts (13.56 MHz). In some embodiments, the temperature of nitrogen trifluoride plasma etching is about 20°C or higher, such as between about 100°C and about 600°C, such as between about 300°C and about 500°C, such as between about 425°C and about 475°C. In some embodiments, the pressure of nitrogen trifluoride plasma etching is about 0.1 torr or greater, such as between about 0.1 torr and about 10 torr, such as between about 1 torr and about 3 torr, such as between about 1.62 torr and about 1.98 torr. In some embodiments, the processing time of nitrogen trifluoride plasma etching is about 5 seconds to about 120 seconds, such as between about 30 seconds and about 90 seconds. Although the etching process can be trimmed to remove the suspended portion as needed, fluorine residues may remain in the dielectric layer 152 to cause a leakage current path. Therefore, it is necessary to remove the fluorine residues remaining in the dielectric layer 152. In some embodiments, the solution is to perform a post-processing process ( Figure 12 ).

[0070] like Figure 12As shown, a post-treatment process PT is performed. In some embodiments, the post-treatment process is an ammonia plasma treatment. In some embodiments, the ammonia flow rate of the ammonia plasma treatment is between about 0.1 SLM (standard liters per minute) and about 1.0 SLM, such as between about 0.2 SLM and about 0.6 SLM, such as about 0.4 SLM. In some embodiments, the RF power of the ammonia plasma treatment is between about 100 watts and about 350 watts, such as between about 180 watts and about 280 watts, such as about 230 watts (13.56 MHz). In some embodiments, the temperature of the ammonia plasma treatment is about 20°C or higher, such as between about 100°C and about 600°C, such as between about 300°C and about 500°C, such as between about 425°C and about 475°C. In some embodiments, the pressure of the ammonia plasma treatment is about 0.1 Torr or greater, such as between about 0.1 Torr and about 10 Torr, such as between about 1 Torr and about 7 Torr, such as between about 3 Torr and about 5 Torr, such as between about 3.6 Torr and about 4.4 Torr. In some embodiments, the treatment time of the ammonia plasma treatment is about 10 seconds to about 60 seconds, such as about 30 seconds to about 60 seconds. The post-treatment process can remove at least a portion of the fluorine residue remaining in the dielectric layer 152. In some embodiments, the post-treatment process can reduce the concentration of fluorine residues in the dielectric layer 152 to meet a critical value (such as a fluorine residue concentration of about 0.9 atomic % or less). In some embodiments, the critical value can be between about 0.5 atomic % and about 1.5 atomic %. In some embodiments, the critical value is set to a level that can avoid leakage current paths. In some embodiments, the critical value is set to a level that can avoid merging of sidewall portions and avoid leakage current without substantially increasing the fluorine concentration in the bottom of the dielectric layer 152. The concentration after post-treatment can be significantly lower than the concentration of fluorine residues after the etching process (which can be as high as 3 atomic % or higher). In some embodiments, performing an ammonia plasma etching process may increase the fluorine concentration in the bottom portion of dielectric layer 152 from a first concentration below a critical value to a second concentration above the critical value. For example, in some embodiments, performing an ammonia plasma etching process increases the fluorine concentration in the bottom portion of dielectric layer 152 from a first concentration of approximately 0.9 atomic % or less to a second concentration greater than 0.9 atomic %. In some embodiments, performing an ammonia plasma post-treatment process reduces the fluorine concentration in the bottom portion from a second concentration above the critical value to a third concentration below the critical value. For example, in some embodiments, performing an ammonia plasma post-treatment process reduces the fluorine concentration in the bottom portion from the second concentration to a third concentration, such as approximately 0.9 atomic % or less. In some embodiments, the second concentration may be at least two times greater than the first concentration and / or the third concentration, such as at least three times greater. In some embodiments, the first and second concentrations may be substantially the same.In some embodiments, the third concentration may be slightly higher than the first concentration, such as 1.5 times higher or slightly lower, which is less than a level that induces leakage current paths, as described above.

[0071] like Figure 13 As shown, a mask layer 154 is formed on the dielectric layer 152 and partially fills the trench 151. The mask layer 154 may be a bottom anti-reflective coating. The method of forming the mask layer 154 may be to first form a layer to completely fill the trench 151 and form the layer on the sacrificial gate structure 130, and then recess the layer to form the mask layer 154. In some embodiments, the method of recessing the mask layer 154 may be a selective etching process that does not substantially affect the dielectric layer 152. The selective etching process may be dry etching, wet etching, or a combination thereof. In some embodiments, the selective etching process is wet etching. The mask layer 154 contacts a first portion 153a of the sidewall portion of the dielectric layer 152 in the trench 151 and exposes a second portion 153b of the sidewall portion of the dielectric layer 152 in the trench 151. In some embodiments, the height of the upper surface of the mask layer 154 in the trench 151 may be between the upper surface and the lower surface of the sacrificial gate layer 134, as shown in FIG. Figure 13 As shown in FIG. In some embodiments, the upper surface of the mask layer 154 in the trench 151 is lower than the lower surface of the sacrificial gate layer 134, for example, lower than the topmost first semiconductor layer 106, and between the upper and lower surfaces of the second first semiconductor layer 106 from the bottom. Subsequent processing will remove the sidewall portion of the dielectric layer 152, while preserving the bottom of the dielectric layer 152. Therefore, the mask layer 154 can protect the bottom of the dielectric layer 152 during the subsequent removal of the second portion 153b of the sidewall portion and the subsequent recessing of the first portion 153a of the sidewall portion of the dielectric layer 152.

[0072] like Figure 14 As shown, the sidewall portion of the dielectric layer 152 in each trench 151, the exposed second portion 153b thereof, and the portion of the dielectric layer 152 on the sacrificial gate structure 130, the first gate spacer 138, and the second gate spacer 139 are removed. The method for removing the portion of the dielectric layer 152 can be a selective etching process such as dry etching, wet etching, or a combination thereof. The selective etching process removes the sidewall portion of the dielectric layer 152, the exposed second portion 153b thereof, but does not substantially affect the mask layer 154, the first gate spacer 138, the second gate spacer 139, and the mask layer 136. The remaining first portion 153a of the sidewall portion of the dielectric layer 152 is located in the trench 151, and its upper surface is substantially coplanar with the upper surface of the mask layer 154, as shown in FIG. Figure 14 shown.

[0073] like Figure 15As shown, the mask layer 154 and the first portion 153a of the sidewall portion of the dielectric layer 152 are removed. The mask layer 154 and the sidewall portion of the dielectric layer 152 can be removed by any suitable process. In some embodiments, a selective etching process first recesses the first portion 153a of the sidewall portion of the dielectric layer 152, with the upper surface of the recessed dielectric layer 152 being substantially lower than the upper surface of the mask layer 154. The selective etching process recesses the dielectric layer 152 without substantially affecting the mask layer 136, the first gate spacer 138, the second gate spacer 139, and the mask layer 154. In some embodiments, the upper surface of the recessed dielectric layer 152 is at a height between the upper and lower surfaces of the bottommost first semiconductor layer 106. In some embodiments, the selective etching process for recessing the first portion 153a of the sidewall portion of the dielectric layer 152 and the selective etching process for removing the exposed second portion 153b of the sidewall portion of the dielectric layer 152 are the same selective etching process. In other words, a single selective etching process may be performed to remove the sidewall portion of the dielectric layer 152 , thereby exposing the second portion 153 b and recessing the first portion 153 a of the sidewall portion of the dielectric layer 152 .

[0074] The mask layer 154 is then removed. The method for removing the mask layer 154 can be a selective process. In some embodiments, the method for removing the mask layer 154 can be a stripping process such as using a solvent or oxygen plasma. The selective process for removing the mask layer 154 does not substantially affect the mask layer 136, the first gate spacer 138, the second gate spacer 139, the first semiconductor layer 106, the dielectric spacer 144, and the dielectric layer 152. After removing the mask layer 154, the dielectric layer 152 includes a sidewall portion (which is a first portion of the recess of the sidewall portion) and a bottom. As described above, the upper surface of the sidewall portion of the dielectric layer 152 can be at a height between the upper surface and the lower surface of the bottommost first semiconductor layer 106.

[0075] An etching process is then performed to remove the sidewall portions of dielectric layer 152 while preserving the bottom portion of dielectric layer 152. As described above, the sidewall portions of dielectric layer 152 have a thickness T1 that is substantially less than the thickness T2 of the bottom portion of dielectric layer 152. Thus, the etching process completely removes the sidewall portions of dielectric layer 152 and reduces the thickness T2 of the bottom portion of dielectric layer 152. In some embodiments, after removing the sidewall portions of dielectric layer 152, the thickness T2 of the bottom portion of dielectric layer 152 is approximately 5 nm to approximately 8 nm. The etching process can be any suitable etching process, such as a dry etching process, a wet etching process, or a combination thereof.

[0076] After the etching process to remove the sidewall portion of the dielectric layer 152, the dielectric layer 152 (eg, the remaining bottom portion) is located on the first semiconductor material 150, as shown in FIG. Figure 15As shown. An annealing process may then be performed on the dielectric layer 152 as appropriate after the implantation process to reduce the wet etching rate of the dielectric layer 152. In some embodiments, the implantation process includes implanting dopants into the dielectric layer 152. For example, the dielectric layer 152 includes silicon nitride, and the dopants may include silicon, fluorine, boron, or any suitable dopants. Dopant gases such as silicon-containing gases, fluorine-containing gases, or boron-containing gases may be used during the implantation process. The implantation energy of the implantation process may be from about 0.2 keV to about 5 keV, the implantation temperature may be from about -60°C to about 450°C, the implantation tilt angle may be from about 0 degrees to about 15 degrees, and the substrate rotation angle may be from about 0 degrees to about 360 degrees. The dopant concentration may be from about 5x 10 20 cm -3 to about 1x 10 21 cm -3 As mentioned above, the implantation process reduces the wet etching rate of the dielectric layer 152. Therefore, if the dopant concentration of the dielectric layer 152 is less than about 5x 10 20 cm -3 , the wet etching rate of the dielectric layer 152 is not reduced, and the subsequent wet etching process will substantially reduce the thickness of the dielectric layer 152. On the other hand, if the dopant concentration of the dielectric layer 152 is greater than about 1×10 21 cm -3 , which may negatively affect the quality of the subsequently formed second semiconductor material 156 . In some embodiments, the dopant concentration of the dielectric layer 152 increases as it moves away from the first semiconductor material 150 .

[0077] In some embodiments, dielectric layer 152 has a first silicon concentration before the implantation process. The first silicon concentration is substantially uniform throughout dielectric layer 152. In embodiments where the dopant is silicon, dielectric layer 152 has a second silicon concentration after the implantation process, and the second silicon concentration is substantially greater than the first silicon concentration. In some embodiments where the dopant is boron or fluorine, dielectric layer 152 is substantially free of dopants before the implantation process. The dopant concentration profile after the implantation process increases from the bottom surface of dielectric layer 152 toward the top surface of dielectric layer 152.

[0078] In some embodiments, exposed layers such as the first gate spacer 138, the second gate spacer 139, the first semiconductor layer 106, and the dielectric spacer 144 may also be doped with dopants from the implantation process. Thus, in some embodiments, the first gate spacer 138, the second gate spacer 139, the first semiconductor layer 106, and the dielectric spacer 144 include dopants located at corresponding surfaces exposed in the trench 151. In some embodiments, the dopant is silicon, and the silicon concentration is substantially higher at or near the corresponding surfaces of the first gate spacer 138, the second gate spacer 139, the first semiconductor layer 106, and the dielectric spacer 144 exposed in the trench, while the silicon concentration is lower in other areas of the first gate spacer 138, the second gate spacer 139, the first semiconductor layer 106, and the dielectric spacer 144. In other words, the dopant concentrations of the first gate spacer 138, the second gate spacer 139, the first semiconductor layer 106, and the dielectric spacer 144 decrease as they move away from the trench 151. In some embodiments, the dopants diffuse through the dielectric layer 152 into the first semiconductor material 150. As a result, the first semiconductor material 150 may include dopants near the interface between the first semiconductor material 150 and the dielectric layer 152.

[0079] After the implantation process, an annealing process may be optionally performed to drive out hydrogen and densify the dielectric layer 152. The annealing process may be any suitable annealing process. In some embodiments, the annealing process may be flash lamp annealing, laser spike annealing, or rapid thermal annealing. For flash lamp annealing or laser spike annealing, the annealing temperature may be approximately 1050° C. to approximately 1200° C. For rapid thermal annealing, the annealing temperature may be approximately 600° C. to approximately 1000° C. For flash lamp annealing or laser spike annealing, the dwell time of the annealing process may be approximately 0.1 milliseconds to approximately 40 milliseconds. For rapid thermal annealing, the dwell time of the annealing process may be approximately 1 second to approximately 20 seconds. The chamber pressure during the annealing process may be approximately 1 Torr to approximately 760 Torr.

[0080] Implantation process and annealing process Figure 15 The wet etch rate of the dielectric layer 152 is shown to be reduced. In some embodiments, the wet etch rate can be improved by about 75%. Figure 15 The implantation process and annealing process are performed before the step of forming the dielectric layer 152. In other words, the implantation process and annealing process are performed after the sidewall portion of the dielectric layer 152 is removed. For example, if Figure 15 The step of depositing the dielectric layer 152 shown is followed by an implantation process and an annealing process. The dopants in the dielectric layer 152 may make it difficult to remove the sidewall portion of the dielectric layer 152 .

[0081] After the implantation and annealing processes, a wet cleaning process may be optionally performed to remove native oxide and other contaminants from the semiconductor device structure 100. The wet cleaning process may utilize any suitable solution, such as deionized water, SC1 (deionized water, ammonium hydroxide, and / or hydrogen peroxide), SC2 (deionized water, hydrogen chloride, and / or hydrogen peroxide), ozonated deionized water, SPM (sulfuric acid and / or hydrogen peroxide), SOM (sulfuric acid and / or ozone), SPOM, phosphoric acid, diluted hydrofluoric acid, hydrofluoric acid, hydrofluoric acid and ethylene glycol, hydrofluoric acid and nitric acid, ammonium hydroxide, or tetramethylammonium hydroxide. The wet cleaning process does not substantially affect the dielectric layer 152 because the implantation and annealing processes reduce the wet etch rate. Without the implantation and annealing processes, the subsequent wet cleaning process may reduce the thickness of the dielectric layer 152, potentially causing leakage current. In some embodiments, if the implantation process and the annealing process are not performed on the dielectric layer 152, the wet cleaning process can reduce the thickness of the dielectric layer 152 by 1 nm or more. In some embodiments, the thickness T2 of the bottom of the dielectric layer 152 after the wet cleaning process can be about 2 nm to about 5 nm, such as between about 3 nm and about 4 nm. In some embodiments, the thickness T2 of the bottom of the dielectric layer 152 after the wet cleaning process has a thickness difference between the center and the corners (such as the deviation between the center and the corners) of about 0.5 nm or less. In some embodiments, the center-to-corner thickness ratio of the dielectric layer 152 is between about 0.75 and about 1.33. Such a center-to-corner thickness ratio close to 1 cannot be achieved by deposition alone, but can be achieved by the deposition-etch-post-treatment process disclosed herein. The center-to-corner thickness ratio can be between about 0.75 and about 1.33 to significantly improve performance. This is based on ensuring that the overall thickness of the dielectric layer 152 is sufficient to prevent leakage current, but not so thick that the dielectric layer 152 is too close to the first semiconductor layer 106 and negatively impacts the quality of the second semiconductor material 156. In some embodiments, the center thickness (at the vertical center of the trench 151) and the corner thickness (adjacent to the sidewall portion) of the dielectric layer 152 after the wet clean process are both between about 3 nm and about 4 nm. In some embodiments, the lower surface of the dielectric layer 152 can be flush with the lower surface of the dielectric spacer 144, and the thickness T2 of the dielectric layer 152 can be between about 50% and about 80% of the thickness of the dielectric spacer 144. If the thickness T2 of the dielectric layer 152 is less than about 50% of the thickness of the dielectric spacer 144, the dielectric layer 152 may be too thin to prevent leakage current. On the other hand, if the thickness T2 of the dielectric layer 152 is greater than about 80% of the thickness of the dielectric spacers 144, the quality of the second semiconductor material 156 may be negatively affected due to the dielectric layer 152 being too close to the first semiconductor layer 106. In some embodiments, the wet cleaning process may cause variations in the thickness of the dielectric layer 152. For example, the edge portion of the dielectric layer 152 adjacent to the dielectric spacers 144 may be thinner than the center portion of the dielectric layer 152.In some embodiments, the thickness of the edge portion of the dielectric layer 152 may be about 1.5 nm to about 2.5 nm, while the thickness of the central portion of the dielectric layer 152 may be about 3 nm to about 4 nm.

[0082] In some embodiments, the distance along the Z direction from the lower surface of the bottommost first semiconductor layer 106 to the upper surface of the topmost first semiconductor layer 106 may be approximately 30 nm to approximately 60 nm, and the distance from the upper surface of the topmost first semiconductor layer 106 to the upper surface of the nitride layer 135 may be approximately 120 nm to approximately 150 nm.

[0083] like Figure 16 As shown, a second semiconductor material 156 is formed in the trench 151 and can be epitaxially grown from the first semiconductor layer 106. In some embodiments, one or more additional semiconductor material layers 158 and 160 can be formed between the second semiconductor material 156 and the first semiconductor layer 106. In some embodiments, the semiconductor material layer 158 is formed on and in contact with the first semiconductor layer 106. In some embodiments, the semiconductor material layer 160 is formed on and in contact with the semiconductor material layer 158, such that the semiconductor material layer 160 is located between the semiconductor material layer 158 and the second semiconductor material 156. In some embodiments, the semiconductor material layers 158 and 160 can be composed of silicon, silicon phosphide, silicon carbide, silicon arsenide, silicon antimonide, or silicon carbon phosphide for n-type channel field effect transistors, or silicon, silicon germanium, or germanium for p-type channel field effect transistors. For p-type field effect transistors, p-type dopants such as boron can be included in the semiconductor material layers 158 and 160. For an n-type channel field effect transistor, n-type dopants such as phosphorus or arsenic may be included in the semiconductor material layers 158 and 160. In some embodiments, the dopant concentration of the semiconductor material layers 158 and 160 may be about 1 x 10 19 cm -3 About 2 x 10 21 cm -3 In some embodiments, the semiconductor material layers 158 and 160 may be formed by epitaxial growth methods such as chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. Figure 16In some embodiments shown, the semiconductor material layer 160 is a continuous layer over the semiconductor material layer 158 and the dielectric spacers 144. In some embodiments, the semiconductor material layer 158 is selectively formed over a semiconductor material, such as the first semiconductor layer 106, and not over a dielectric material, such as the dielectric layer 152 and the dielectric spacers 144. In some embodiments, the semiconductor material layer 158 includes crystal planes that correspond to crystal planes of the material used in the first semiconductor layer 106. The second semiconductor material 156 can be grown vertically and horizontally to form crystal planes that correspond to crystal planes of the material used in the first semiconductor layer 106. The second semiconductor material 156 can be a source / drain region. In embodiments of the present invention, the source region and the drain region are interchangeable and have substantially the same structure. Furthermore, the source / drain regions can be considered as a source or a drain, either independently or together, depending on the context. The second semiconductor material 156 can be composed of one or more layers of silicon, silicon phosphide, silicon carbide, or silicon carbon phosphide for n-type channel field-effect transistors, or one or more layers of silicon, silicon germanium, or germanium for p-type channel field-effect transistors. For p-type channel field-effect transistors, a p-type dopant such as boron can also be included in the second semiconductor material 156. The second semiconductor material 156 can be formed by epitaxial growth methods such as chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy.

[0084] like Figure 17 As shown, a contact etch stop layer 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The contact etch stop layer 162 covers the second gate spacer 139, the isolation region 120, and the second semiconductor material 156. The contact etch stop layer 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, the like, or a combination thereof, and may be formed by chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or any other suitable deposition technique. Figure 17 In some embodiments shown, the contact etch stop layer 162 is a single layer. In some embodiments, the contact etch stop layer 162 includes two or more layers. An interlayer dielectric layer 164 is then formed on the contact etch stop layer 162. The material used for the interlayer dielectric layer 164 may include a compound containing silicon, oxygen, carbon, and / or hydrogen, such as silicon oxide, silicon hydroxide, or silicon oxycarbide. Organic materials such as polymers may also be used for the interlayer dielectric layer 164. The deposition method of the interlayer dielectric layer 164 may be a plasma-assisted chemical vapor deposition process or other suitable deposition technology. In some embodiments, after the interlayer dielectric layer 164 is formed, the semiconductor device structure 100 may be subjected to a thermal process to anneal the interlayer dielectric layer 164.

[0085] After forming the interlayer dielectric layer 164, a planarization step such as chemical mechanical polishing may be performed on the semiconductor device structure 100 until the sacrificial gate layer 134 is exposed. Figure 17 shown.

[0086] like Figure 18 As shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. Removal of the sacrificial gate structure 130 and the second semiconductor layer 108 forms openings between the first gate spacers 138 and between the first semiconductor layer 106. The interlayer dielectric layer 164 protects the second semiconductor material 156 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate layer 134 can be removed first using a suitable process such as dry etching, wet etching, or a combination thereof, followed by removal of the sacrificial gate dielectric layer 132 using any suitable process such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as tetramethylammonium hydroxide solution can be used to selectively remove the sacrificial gate layer 134 without removing the first gate spacers 138, the interlayer dielectric layer 164, and the contact etch stop layer 162.

[0087] A selective wet etching process may be used to remove the second semiconductor layer 108. In the case where the second semiconductor layer 108 is composed of silicon germanium and the first semiconductor layer 106 is composed of silicon, the chemistry used in the selective wet etching process can remove the silicon germanium without substantially affecting the silicon and the dielectric material of the first gate spacer 138 and the dielectric spacer 144. In one embodiment, the wet etchant used to remove the second semiconductor layer 108 may be, but is not limited to, hydrofluoric acid, nitric acid, hydrochloric acid, or phosphoric acid.

[0088] like Figure 19As shown, after forming the nanostructured channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate layer 172 can be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (not shown) is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric materials such as silicon oxide, silicon nitride, a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. High-k dielectric materials include hafnium oxide, hafnium silicon oxide, tantalum hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide alloy, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed by chemical vapor deposition, atomic layer deposition, or any other suitable deposition technique. The gate layer 172 may include one or more layers of a conductive material such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, titanium aluminum, titanium aluminum nitride, tantalum carbonitride, tantalum carbide, tantalum silicon nitride, a metal alloy, other suitable materials, and / or any combination thereof. The gate layer 172 may be formed by chemical vapor deposition, atomic layer deposition, electroplating, or any other suitable deposition technique. The gate layer 172 may also be deposited on the upper surface of the interlayer dielectric layer 164. After the gate dielectric layer 170 and the gate layer 172 are formed on the interlayer dielectric layer 164, portions of the gate dielectric layer 170 and the gate layer 172 may be removed by chemical mechanical polishing until the upper surface of the interlayer dielectric layer 164 is exposed.

[0089] It should be understood that subsequent processing may be performed on the semiconductor device structure 100 to form conductive contacts in the interlayer dielectric layer 164 to electrically connect to the second semiconductor material 156, and to form conductive contacts to electrically connect to the gate layer 172. Interconnect structures may be formed on the semiconductor device structure 100 to provide an electrical path to devices formed on the substrate 101.

[0090] A semiconductor device structure provided by an embodiment of the present invention includes a dielectric layer 152 disposed between a first semiconductor material 150 and a second semiconductor material 156. Sidewall portions of the dielectric layer 152 may define an overhang at or near the top of a trench 151, wherein a second portion 153b of the sidewall portion extends into the trench 151 in the X-direction and substantially extends beyond the first portion 153a of the sidewall portion. As geometric dimensions shrink with advancements to smaller and smaller process nodes, individual overhangs on opposite sides of the same trench 151 may merge, resulting in the dielectric layer 152 connecting at or near the top of the trench 151. To trim and remove at least a portion of the overhang, an etching process, as described herein, may be performed. Although the etching process may be used to trim the overhang as needed, fluorine residue may remain in the dielectric layer 152, potentially inducing leakage current paths. To remove the fluorine residue, a post-treatment process, as described herein, may be performed. This prevents sidewall merging without substantially increasing the fluorine concentration at the bottom of the dielectric layer 152, thereby preventing leakage current.

[0091] In some embodiments, a method for forming a semiconductor device structure includes forming a sacrificial gate stack on a portion of a fin structure; removing an exposed portion of the fin structure to expose a portion of a substrate and a surface of a semiconductor layer of the fin structure; depositing a first semiconductor material on the exposed portion of the substrate; depositing a dielectric layer, wherein the dielectric layer includes a bottom portion located on the first semiconductor material and the dielectric layer includes a sidewall portion located on the surface of the semiconductor layer; performing an etching process to trim at least a portion of the overhang of the sidewall portion of the dielectric layer; removing the sidewall portion of the dielectric layer; and forming a second semiconductor material on the bottom of the dielectric layer.

[0092] In some embodiments, the method further includes performing a post-treatment process to remove at least a portion of fluorine residues from the dielectric layer left by the etching process, wherein the post-treatment process is an ammonia plasma treatment.

[0093] In some embodiments, the ammonia plasma treatment has an ammonia flow rate of about 0.1 SLM to about 1.0 SLM, and a 13.56 MHz RF power of about 100 watts to about 350 watts.

[0094] In some embodiments, the ammonia plasma treatment is performed at a temperature between about 100° C. and about 600° C., and at a pressure between about 0.1 torr and about 10 torr.

[0095] In some embodiments, the ammonia plasma treatment time is between about 10 seconds and about 60 seconds.

[0096] In some embodiments, the etching process is a nitrogen trifluoride plasma etching process.

[0097] In some embodiments, the nitrogen trifluoride flow rate of the nitrogen trifluoride plasma etching process is between about 10 SCCM and about 150 SCCM, and the 13.56 MHz RF power is between about 50 watts and about 150 watts.

[0098] In some embodiments, the temperature of the nitrogen trifluoride plasma etch is between about 100° C. and about 600° C., the pressure is between about 0.1 torr and about 10 torr, and the processing time is between about 5 seconds and about 120 seconds.

[0099] In some embodiments, the bottom thickness of the dielectric layer is between about 3 nm and about 4 nm, and the difference in thickness between the center and the corners is about 0.5 nm or less.

[0100] In some embodiments, the post-treatment process reduces the concentration of fluorine residues in the dielectric layer to about 0.9 atomic % or less.

[0101] In some embodiments, a method for forming a semiconductor device structure includes forming a fin structure from a substrate, wherein the fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers; forming a sacrificial gate stack on the fin structure; depositing a gate spacer on the sacrificial gate stack; removing a portion of the fin structure to expose a portion of the substrate; recessing the second semiconductor layer to form a plurality of voids; forming a plurality of dielectric spacers in the voids; depositing a first semiconductor material on the exposed portion of the substrate; depositing a dielectric layer, wherein the dielectric layer includes a sidewall portion contacting the gate spacers, the first semiconductor layer, and the dielectric spacers, and the dielectric layer includes a bottom portion contacting the first semiconductor material, and wherein a first thickness of a first portion of the sidewall portion near the bottom portion is less than a second thickness of a second portion of the sidewall portion above the first portion; performing a nitrogen trifluoride plasma etching process to reduce the second thickness of the second portion of the sidewall portion; performing an ammonia plasma post-treatment process to remove at least a portion of a plurality of fluorine residues from the dielectric layer left by the nitrogen trifluoride plasma etching process; removing the sidewall portion of the dielectric layer; and forming a second semiconductor material on the bottom portion of the dielectric layer.

[0102] In some embodiments, removing the portion of the fin structure to expose the portion of the substrate defines a trench, and wherein the second portion of the sidewall portion is defined at a top of the trench and contacts the gate spacer.

[0103] In some embodiments, before performing the nitrogen trifluoride plasma etching process, the second portion of the sidewall portion extends into the trench and substantially extends beyond the first portion, and after performing the nitrogen trifluoride plasma etching process, the second portion of the sidewall portion does not extend into the trench and substantially extends beyond the first portion.

[0104] In some embodiments, the step of performing a nitrogen trifluoride plasma etching process increases the fluorine concentration in the bottom of the dielectric layer from a first concentration of about 0.9 atomic % or less to a second concentration greater than 0.9 atomic %, and the step of performing an ammonia plasma post-treatment process reduces the fluorine concentration in the bottom from the second concentration to a third concentration of about 0.9 atomic % or less.

[0105] In some embodiments, a semiconductor device structure includes a buried epitaxial layer on a substrate; a dielectric layer on the buried epitaxial layer; a source / drain region on the dielectric layer; a first nanostructured channel adjacent to the source / drain region; a first dielectric spacer contacting the first nanostructured channel; a gate dielectric layer on the first nanostructured channel; and a gate layer on the gate dielectric layer, wherein a center-to-corner thickness ratio of the dielectric layer is between about 0.75 and about 1.33, and wherein a fluorine residue concentration in the dielectric layer is about 0.9 atomic % or less.

[0106] In some embodiments, the thickness of the dielectric layer is between about 3 nm and about 4 nm, and the difference in thickness between the center and the corners of the dielectric layer is about 0.5 nm or less.

[0107] In some embodiments, the thickness of the dielectric layer is about 50% to about 80% of the thickness of the first dielectric spacer, and the upper surface of the dielectric layer is lower than the lower surface of the first nanostructure channel.

[0108] In some embodiments, a lower surface of the dielectric layer is flush with a lower surface of the first dielectric spacer.

[0109] In some embodiments, the semiconductor device structure further includes a second nanostructure channel to contact the source / drain regions, wherein the second nanostructure channel is located on the first nanostructure channel, and a first dielectric spacer is located between the first nanostructure channel and the second nanostructure channel.

[0110] In some embodiments, the semiconductor device structure further includes a contact etch stop layer on the source / drain regions, and an interlayer dielectric layer on the contact etch stop layer.

[0111] The features of the above-described embodiments will facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that the present invention can be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present invention and that changes, substitutions, or modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device structure, comprising: forming a sacrificial gate stack on a portion of a fin structure; removing an exposed portion of the fin structure to expose a portion of the substrate and a surface of a semiconductor layer of the fin structure; depositing a first semiconductor material on the exposed portion of the substrate; Depositing a dielectric layer, wherein the dielectric layer includes a bottom portion located on the first semiconductor material and a sidewall portion located on a surface of the semiconductor layer; performing an etching process to trim at least a portion of an overhang of the sidewall portion of the dielectric layer; removing the sidewall portion of the dielectric layer; as well as A second semiconductor material is formed on the bottom of the dielectric layer.

2. The method for forming a semiconductor device structure according to claim 1, further comprising performing a post-treatment process to remove at least a portion of fluorine residues from the dielectric layer left by the etching process, wherein the post-treatment process is an ammonia plasma treatment.

3. The method for forming a semiconductor device structure according to claim 2, wherein an ammonia flow rate of the ammonia plasma treatment is between about 0.1 SLM and about 1.0 SLM, and a 13.56 MHz RF power is between about 100 W and about 350 W. 4 . The method for forming a semiconductor device structure according to claim 2 , wherein the temperature of the ammonia plasma treatment is between about 100° C. and about 600° C., and the pressure is between about 0.1 Torr and about 10 Torr.

5. A method for forming a semiconductor device structure, comprising: forming a fin structure from a substrate, wherein the fin structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers; forming a sacrificial gate stack on the fin structure; depositing a gate spacer on the sacrificial gate stack; removing a portion of the fin structure to expose a portion of the substrate; recessing the plurality of second semiconductor layers to form a plurality of cavities; forming a plurality of dielectric spacers in the plurality of cavities; depositing a first semiconductor material on the exposed portion of the substrate; Depositing a dielectric layer, wherein the dielectric layer includes a sidewall portion contacting the gate spacer, the plurality of first semiconductor layers, and the plurality of dielectric spacers, and the dielectric layer includes a bottom portion contacting the first semiconductor material, and wherein a first thickness of a first portion of the sidewall portion near the bottom portion is less than a second thickness of a second portion of the sidewall portion above the first portion; performing a nitrogen trifluoride plasma etching process to reduce the second thickness of the second portion of the sidewall portion; performing an ammonia plasma post-treatment process to remove at least a portion of a plurality of fluorine residues from the dielectric layer left by the nitrogen trifluoride plasma etching process; removing the sidewall portion of the dielectric layer; as well as A second semiconductor material is formed on the bottom of the dielectric layer.

6. The method for forming a semiconductor device structure as claimed in claim 5, wherein the step of removing the portion of the fin structure to expose the portion of the substrate defines a trench, and wherein the second portion of the sidewall portion is defined at a top of the trench and contacts the gate spacer.

7. The method for forming a semiconductor device structure as claimed in claim 6 , wherein before performing the nitrogen trifluoride plasma etching process, the second portion of the sidewall portion extends into the trench and substantially exceeds the first portion, and wherein after performing the nitrogen trifluoride plasma etching process, the second portion of the sidewall portion does not extend into the trench and substantially exceeds the first portion.

8. A semiconductor device structure comprising: a buried epitaxial layer located on a substrate; a dielectric layer located on the buried epitaxial layer; a source / drain region located on the dielectric layer; a first nanostructure channel adjacent to the source / drain region; a first dielectric spacer contacting the first nanostructure channel; a gate dielectric layer located on the first nanostructure channel; and a gate layer located on the gate dielectric layer, wherein a thickness ratio of the center to the corners of the dielectric layer is between about 0.75 and about 1.33, and The residual fluorine concentration in the dielectric layer is about 0.9 atomic % or less. 9 . The semiconductor device structure of claim 8 , wherein the thickness of the dielectric layer is between about 3 nm and about 4 nm, and a thickness difference between a center and a corner of the dielectric layer is about 0.5 nm or less. 10 . The semiconductor device structure of claim 8 , wherein a thickness of the dielectric layer is about 50% to about 80% of a thickness of the first dielectric spacer, and an upper surface of the dielectric layer is lower than a lower surface of the first nanostructure channel.

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